Page 1
December 1998
ADC14061
Self-Calibrating 14-Bit, 2.5 MSPS, 390 mW A/D Converter
ADC14061 Self-Calibrating 14-Bit, 2.5 MSPS, 390 mW A/D Converter
General Description
The ADC14061 is a self-calibrating 14-bit, 2.5 Megasample
per secondanalog to digital converter. It operates on a single
+5V supply, consuming just 390mW (typ).
The ADC14061 provides an easy and affordable upgrade
from 12 bit converters. The ADC14061 may also be used to
replace many hybrid converters with a resultant saving of
space, power and cost.
The ADC14061 operates with excellent dynamic performance at input frequencies up to
calibration feature of the ADC14061 can be used to get more
consistent and repeatable results over the entire operating
temperature range. On-command self-calibration reduces
many of the effects of temperature-induced drift, resulting in
more repeatable conversions.
The Power Down feature reduces power consumption to
less than 2mW.
TheADC14061 comes in a TQFP and is designed to operate
over the commercial temperature range of 0˚C to +70˚C.
1
⁄2the clock frequency.The
Connection Diagram
Features
n Single +5V Operation
n Auto-Calibration
n Power Down Mode
n TTL/CMOS Input/Output compatible
Key Specifications
n Resolution 14 Bits
n Conversion Rate 2.5 Msps (min)
n DNL 0.3 LSB (typ)
n SNR (f
n ENOB 12.8 Bits (typ)
n Supply Voltage +5V
n Power Consumption 390mW (typ)
= 500 kHz) 80 dB (typ)
IN
±
Applications
n Instrumentation
n PC-Based Data Acquisition
n Data Communications
n Blood Analyzers
n Sonar/Radar
%
5
DS100103-1
Ordering Information
Commercial
(0˚C ≤ TA ≤ +70˚C)
ADC14061CCVT VEG52A 52 Pin Thin Quad Flat Pack
© 1998 National Semiconductor Corporation DS100103 www.national.com
Package
Page 2
Block Diagram
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DS100103-2
Page 3
Pin Descriptions and Equivalent Circuits
Pin
Symbol Equivalent Circuit
No.
Analog I/O
1V
4V
48 V
47 V
50 V
49
+
IN
−
IN
REF+IN
REF−IN
REF+OUT
REF−OUT
Description
Non-Inverting analog signal Input. With a 2.0V reference voltage and a
2.0V common mode voltage, V
1.0 volt to 3.0 Volts.
, the input signal voltage range is from
CM
Inverting analog signal Input. With a 2.0V reference voltage and a 2.0V
common mode voltage, VCM, the input signal voltage range is from 1.0 Volt
to 3.0 Volts. The input signal should be balanced for best performance.
Positive reference input. This pin should be bypassed to AGND with a 0.1
µF monolithic capacitor. V
1.8V and a maximum of 2.2V. The full-scale input voltage is equal to
minus V
V
REF+IN
REF−IN
REF
.
+ minus V
should be a minimum of
REF− IN
Negative reference input. In most applications this pin should be connected
to AGND and the full reference voltage applied to V
application requires that V
bypassed to AGND with a 0.1 µF monolithic capacitor. V
should be a minimum of 1.8V and a maximum of 2.2V. The
V
REF− IN
full-scale input voltage is equal to V
be offset from AGND, this pin should be
REF−IN
minus V
REF+IN
REF+IN
REF−IN
.Ifthe
REF+IN
.
minus
Output of the high impedance positive reference buffer. With a 2.0V
reference input, and with a V
voltage. This pin should be bypassed to AGND with a 0.1 µF monolithic
of 2.0V, this pin will have a 3.0V output
CM
capacitor in parallel with a 10 µF capacitor.
The output of the negative reference buffer. With a 2.0V reference and a
of 2.0V, this pin will have a 1.0V output voltage. This pin should be
V
CM
bypassed to AGND with a 0.1 µF monolithic capacitor in parallel with a 10
µF capacitor.
52 V
REF (MID)
51 V
Output of the reference mid-point, nominally equal to 0.4 VA(2.0V). This
pin should be bypassed to AGND with a 0.1 µF monolithic capacitor. This
voltage is derived from V
.
CM
Input to the common mode buffer, nominally equal to 40%of the supply
CM
voltage (2.0V). This pin should be bypassed to AGND with a 0.1 µF
monolithic capacitor. Best performance is obtained if this pin is driven with
a low impedance source of 2.0V.
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Pin Descriptions and Equivalent Circuits (Continued)
Digital I/O
Digital clock input. The range of frequencies for this input is 300 kHz to 2.5
10 Clock
11 CAL
40 RESET
18 RD
44 PD
MHz. The clock frequency should not be changed or interrupted during
conversion or while reading data output.
CAL is a level-sensitive digital input that, when pulsed high for at least two
clock cycles, puts the ADC into the CALIBRATE mode. Calibration should
be performed upon ADC power-up (after asserting a reset) and each time
the temperature changes by more than 50˚C since the ADC14061 was last
calibrated. See Section 2.3 for more information.
RESET is a level-sensitive digital input that, when pulsed high for at least 2
CLOCK cycles, results in the resetting of the ADC. This reset pulse must
be applied after ADC power-up, before calibration.
RD is the (READ) digital input that, when low, enables the output data
buffers. When this input pin is high, the output data bus is in a high
impedance state.
PD is the Power Down input that, when low, puts the converter into the
power down mode. When this pin is high, the converter is in the active
mode.
17 EOC
23-32
35-38
Analog Power
6, 7,
45
5, 8,
46
D00-13
V
A
AGND
EOC is a digital output that, when low, indicates the availability of new
conversion results at the data output pins.
Digital data outputs that make up the 14-bit TRI-STATE conversion results.
D00 is the LSB, while D13 is the MSB (SIGN bit) of the two’s complement
output word.
Positive analog supply pins. These pins should be connected to a clean,
quiet +5V source and bypassed to AGND with 0.1 µF monolithic capacitors
in parallel with 10 µF capacitors, both located within 1 cm of these power
pins.
The ground return for the analog supply. AGND and DGND should be
connected together directly beneath the ADC14061 package. See Section
5 (Layout and grounding) for more details).
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Pin Descriptions and Equivalent Circuits (Continued)
Digital Power
Positive digital supply pin. This pin should be connected to the same clean,
20 V
12,13
14,19,
41,42,
DGND
43
34 V
D
33 DGND I/O
NC
2, 3,
9, 15,
16,
NC
21,
22, 39
D
I/O
quiet +5V source as is V
capacitor in parallel with a 10µF capacitor, both located within 1 cm of the
power pin.
The ground return for the digital supply. AGND and DGND should be
connected together directly beneath the ADC14061 package. See Section
5 (Layout and Grounding) for more details.
Positive digital supply pin for the ADC14061’s output drivers. This pin
should be connected to a +3V to +5V source and bypassed to DGND I/O
with a 0.1 µF monolithic capacitor. If the supply for this pin is different from
the supply used for V
capacitor. All bypass capacitors should be located within 1 cm of the
and VD, it should also be bypassed with a 10 µF
A
supply pin.
The ground return for the digital supply for the ADC14061’s output drivers.
This pin should be connected to the system digital ground, but not be
connected in close proximity to the ADC14061’s DGND or AGND pins. See
Section 5.0 (Layout and Grounding) for more details.
All pins marked NC (no connect) should be left floating. Do not connect the
NC pins to ground, power supplies, or any other potential or signal. These
pins are used for test in the manufacturing process.
and bypassed to DGND with a 0.1 µF monolithic
A
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Page 6
Absolute Maximum Ratings (Note 1)
If Military/Aerospace specified devices are required,
please contact the National Semiconductor Sales Office/
Distributors for availability and specifications.
Supply Voltage (V
A,VD,VD
Voltage on Any I/O Pin −0.3V to V
Input Current at Any Pin (Note 3)
Package Input Current (Note 3)
Power Dissipation at T
ESD Susceptibility (Note 5)
Human Body Model 1500V
Machine Model 200V
Soldering Temp., Infrared, 10 sec. (Note 6) 300˚C
I/O) 6.5V
=
25˚C (Note 4)
A
+
+0.3V
±
25mA
±
50mA
Storage Temperature −65˚C to +150˚C
Operating Ratings(Notes 1, 2)
Operating Temperature
Range
V
A,VD
V
I/O 2.7V to V
D
V
− IN 1.0V to 3.0V
REF
V
− IN AGND to 0.1V
REF
Digital Inputs −0.05V to V
|V
| ≤100 mV
A−VD
|AGND - DGND | 0V to 100 mV
≤ +70˚C
0˚C ≤ T
A
+4.75V to +5.25V
+ 0.05V
D
D
Converter Electrical Characteristics
The following specifications apply for AGND=DGND=DGND I/O=0V, V
PD=+5V, V
limits apply for T
Symbol Parameter Conditions
REF+ IN
A
=
+2.0V, V
=
T
=
to T
MAX
AGND, f
: all other limits T
REF− IN
=
T
J
MIN
CLK
=
2.5 MHz, C
=
A
T
J
+
=
V
=
L
=
25˚C(Notes 7, 8, 9)
A
50 pF/pin. After Auto-Cal
=
V
D
Typical
(Note 10)
=
+5.0V, V
I/O=3.0V or 5.0V,
D
@
Temperature. Boldface
Limits
(Note 11)
Units
Static Converter Characteristics
Resolution with No
Missing Codes
INL Integral Non Linearity
DNL Differential Non Linearity
Full-Scale Error
Zero Offset Error +0.1
±
±
±
0.75
0.3
0.4
14 Bits(min)
±
2.5 LSB(max)
±
1.0 LSB(max)
±
2.8
±
0.6
%
FS(max)
%
FS(max)
Reference and Analog Input Characteristics
V
IN
C
IN
V
REF
Input Voltage Range
(V
IN+−VIN−
)
Input Capacitance V
Reference Voltage
Range [( V
(V
REF−IN
)−
REF+IN
)] (Note 14)
Reference Input
Resistance
=
V
REF
=
1.0V + 0.7Vrms
IN
V
REF+IN−VREF+IN
− 2.0
(CLK
LOW)
(CLK
HIGH)
12 pF
28 pF
2.00
3.5 KΩ
1.8
2.2
1.8
2.2
V(min)
V(max)
V(min)
V(max)
Dynamic Converter Characteristics
BW Full Power Bandwidth 8 MHz
SNR Signal-to-Noise Ratio f
SINAD
Signal-to-Noise &
Distortion
ENOB Effective Number of Bits f
THD
SFDR
IMD
Total Harmonic
Distortion
Spurious Free Dynamic
Range
Intermodulation
Distortion
=
IN
=
f
IN
=
IN
=
f
IN
=
f
IN
f
IN1
f
IN2
500 kHz, V
500 kHz, V
500 kHz, V
500 kHz, V
500 kHz, V
=
95 kHz
=
105 kHz
=
1.9V
IN
P-P
=
1.9V
IN
P-P
=
1.9V
IN
P-P
=
1.9V
IN
P-P
=
1.9V
IN
P-P
80 dB
79 dB
12.8 Bits
−88 dB
90 dB
−97 dB
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Page 7
DC and Logic Electrical Characteristics
The following specifications apply for AGND=DGND=DGND I/O=0V, V
PD=+5V, V
Boldface limits apply for T
Symbol Parameter Conditions
CLOCK, RD, PD Digital Input Characteristics
V
IN(1)
V
IN(0)
I
IN(1)
I
IN(0)
C
IN
CAL, RESET Digital Input Characteristics
V
IN(1)
V
IN(0)
I
IN(1)
I
IN(0)
C
IN
D00 - D13 Digital Output Characteristics
V
OUT(1)
V
OUT(1)
V
OUT(0)
I
OZ
+I
SC
−I
SC
Power Supply Characteristics
I
A
I
D
I/O
I
D
PSRR
=
+2.0V, V
REF+
Logical ″1″ Input Voltage V
Logical ″0″ Input Voltage V
Logical ″1″ Input Current V
Logical ″0″ Input Current V
REF IN
=
A
T
J
=
AGND, f
=
T
=
2.5 MHz, RS=25Ω,C
CLK
to T
MIN
: all other limits T
MAX
+
=
5.25V 2.0 V(min)
+
=
4.75V 0.8 V(max)
=
5.0V 5 µA
IN
=
0V −5 µA
IN
A
VINInput Capacitance 5 pF
+
Logical ″1″ Input Voltage V
Logical ″0″ Input Voltage V
Logical ″1″ Input Current V
Logical ″0″ Input Current V
=
5.25V 3.5 V(min)
+
=
4.75V 1.0 V(max)
=
5.0V 5 µA
IN
=
0V −5 µA
IN
Input Capacitance 5 pF
Logical ″1″ Output
Voltage
Logical ″1″ Output
Voltage
Logical ″0″ Output
Voltage
TRI-STATE Output
Current
Output Short Circuit
Source Current
Output Short Circuit Sink
Current
V
I/O=4.75V, I
D
V
I/O=2.7V, I
D
I/O=5.25V, I
V
D
V
I/O=3.3V, I
D
=
3V or 5V 100 nA
V
OUT
=
V
0V −100 nA
OUT
=
V
0V, V
OUT
=
V
OUT
I/O=3V 12 mA
V
D
=
−360 µA 4.5 V(min)
OUT
=
−360 mA 2.5 V(min)
OUT
=
1.6 mA 0.4 V(max)
OUT
=
1.6 µA 0.4 V(max)
OUT
I/O=3V −10 mA
D
Analog Supply Current PD=VDI/O 70 85 mA(max)
Digital Supply Current PD=VDI/O 7 8 mA(max)
Output Bus Supply
Current
Total Power
Consumption
Power Supply Rejection
Ratio
PD=VDI/O 1 2 mA(max)
PD=V
I/O 390 475 mW(max)
D
PD=DGND
250 mV
1
⁄2LSB Error
DC to 10 MHz riding on V
PP
+
=
=
V
A
=
50 pF/pin. After Auto-Cal
L
=
=
T
25˚C(Notes 7, 8, 9)
J
A
=
V
+5.0V, V
D
Typical
(Note 10)
<
2mW
I/O=3.0V or 5.0V,
D
@
Temperature.
Limits
(Note 11)
Units
54 dB
AC Electrical Characteristics
The following specifications apply for AGND=DGND=DGND I/O=0V, V
PD=+5V, V
Boldface limits apply for T
Symbol Parameter Conditions
f
CLK
t
CONV
t
EOCL
REF
=
+
+2.0V, V
REF IN
=
A
T
=
=
J
AGND, f
to T
T
MIN
=
2.5 MHz, RS=25Ω,C
CLK
: all other limits T
MAX
A
Conversion Clock (CLOCK)
Frequency
Conversion Clock Duty Cycle
Conversion Latency 13 Clock Cycles
Falling edge of CLK to falling
edge of EOC
+
=
=
V
A
=
50 pF/pin. After Auto-Cal
L
=
=
T
25˚C(Notes 7, 8, 9)
J
Typical
(Note 10)
300 kHz(min)
1/(4f
V
D
=
+5.0V, V
I/O=3.0V or 5.0V,
D
@
Temperature.
Limits
(Note 11)
Units
(Limits)
3 2.5 MHz(max)
45
55
CLK
)
90
130
%
(min)
%
(max)
ns(min)
ns(max)
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Page 8
AC Electrical Characteristics (Continued)
+
=
=
The following specifications apply for AGND=DGND=DGND I/O=0V, V
PD=+5V, V
Boldface limits apply for T
REF
=
+
+2.0V, V
REF IN
=
A
T
J
=
AGND, f
=
T
MIN
to T
CLK
MAX
=
2.5 MHz, RS=25Ω,C
: all other limits T
A
=
L
=
=
T
25˚C(Notes 7, 8, 9)
J
Symbol Parameter Conditions
t
DATA_VALID
t
ON
t
OFF
t
CAL
Note 1: Absolute Maximum Ratings indicate limits beyond which damage to the device may occur. Operating Ratings indicate conditions for which the device is functional, but do not guarantee specific performance limits. For guaranteed specifications and test conditions, see the Electrical Characteristics. The guaranteed specifications apply only for the test conditions listed. Some performance characteristics may degrade when the device is not operated under the listed test conditions.
Note 2: All voltages are measured with respect to GND=AGND=DGND I/O=0V, unless otherwise specified.
Note 3: When the input voltage at any pin exceeds the power supplies (that is, V
The 50 mA maximum package input current rating limits the number of pins that can safely exceed the power supplies with an input current of 25 mA to two.
Note 4: The absolute maximum junction temperature (T
junction-to-ambient thermal resistance (θ
is 70˚C/W, so PDMAX = 1,785 mW at 25˚C and 1,142 mW at the maximum operating ambient temperature of 70˚C. Note that the power dissipation of this
TQFP, θ
JA
device under normal operation will typically be about 410 mW (390 mW quiescent power + 20 mW due to 1 TTL load on each digital output. The values for maximum
power dissipation listed above will be reached only when the ADC14061 is operated in a severe fault condition (e.g. when input or output pins are driven beyond the
power supply voltages, or the power supply polarity is reversed). Obviously, such conditions should always be avoided.
Note 5: Human body model is 100 pF capacitor discharged through a 1.5kΩ resistor. Machine model is 220 pF discharged through ZERO Ω.
Note 6: See AN450, ″Surface Mounting Methods and Their Effect on Product Reliability″, or the section entitled ″Surface Mount″ found in any post 1986 National
Semiconductor Linear Data Book, for other methods of soldering surface mount devices.
Note 7: The inputs are protected as shown below. Input voltage magnitudes up to 5V above V
is limited per Note 3. However, errors in the A/D conversion can occur if the input goes above V
, the full-cale input voltage must be ≤4.85VDCto ensure accurate conversions
V
DC
Falling edge of CLOCK to Data
Valid
RD low to data valid on D00
-D13
RD high to D00 -D13 in
TRI-STATE
Calibration Time 110 ms
<
AGND or V
IN
max) for this device is 150˚C. The maximum allowable power dissipation is dictated by TJmax, the
), and the ambient temperature (TA), and can be calculated using the formula PDMAX=(TJmax - TA)/θJA. In the 52-pin
JA
J
>
VAor VD), the current at that pin should be limited to 25 mA.
IN
or to 5V below GND will not damage this device, provided current
A
or below GND by more than 100 mV.As an example, if VAis 4.75
A
=
V
V
D
Typical
(Note 10)
1/(8f
CLK
+5.0V, V
)
A
50 pF/pin. After Auto-Cal
I/O=3.0V or 5.0V,
D
@
Temperature.
Limits
(Note 11)
38
95
23 33 ns(max)
25 33 ns(max)
Units
(Limits)
ns(min)
ns(max)
DS100103-12
DS100103-11
ESD Protection Scheme for Digital Input pins
Note 8: To guarantee accuracy, it is required that V
Note 9: With the test condition for V
Note 10: Typical figures are at T
Note 11: Tested limits are guaranteed to Nationsl’s AOQL (Average Outgoing Quality Level).
Note 12: Integral Non Linearity is defined as the deviation of the analog value, expressed in LSBs, from the straight line that passes through positive full-scale and
negative full-scale.
Note 13: Timing specifications are tested at the TTL logic levels, V
to 1.4V.
Note 14: Optimum SNR performance will be obtained by keeping the reference input in the 1.8V to 2.2V range. The LM4041CIM3-ADJ (SOT-23 package), the
LM4041CIZ-ADJ (TO-92 package), or the LM4041CIM-ADJ (SO-8 package) bandgap voltage reference is recommended for this application.
REF
=
=
T
A
J
and VDbe connected together and to the same power supply with separate bypass capacitors at each V+pin.
A
=
+−V
(V
REF
25˚C, and represent most likely parametric norms.
−) given as +2.0V, the 14-bit LSB is 122 µV.
REF
IL
ESD Protection Scheme for Analog Input and Digital
Output pins
=
0.4V for a falling edge and V
=
2.4V for a rising edge. TRI-STATE output voltage is forced
IH
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Page 9
AC Electrical Characteristics (Continued)
FIGURE 1. Transfer Characteristics
DS100103-13
FIGURE 2. Errors removed by Auto-Cal cycle
DS100103-14
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Page 10
Typical Performance Characteristics
INL vs Temperature
DS100103-25
INL vs V
and Temperature
REF
DS100103-35
SINAD & ENOB vs Temperature
DNL vs Temperature
DS100103-26
DNL vs V
REF
DS100103-34
SINAD & ENOB vs Clock Duty
Cycle
SNR vs Temperature
DS100103-27
THD vs Temperaure
DS100103-28
SFDR vs Temperature
DS100103-29
IMD
DS100103-32
Spectral Response
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DS100103-30
DS100103-33
DS100103-31
Page 11
Specification Definitions
APERTURE JITTER is the variation in aperture delay from
sample to sample. Aperture jitter shows up as input noise.
APERTURE DELAY is the time from the sampling edge of
the clock to when the input signal is acquired or held for conversion.
OFFSET ERROR is the difference between the ideal MSB
transition to the actual transition point. The MSB transition
should occur when V
+=VIN−.
IN
DIFFERENTIAL NON-LINEARITY (DNL) is the measure of
the maximum deviation from the ideal step size of 1 LSB.
EFFECTIVE NUMBER OF BITS (ENOB, or EFFECTIVE
BITS) is another method of specifying Signal-to-Noise and
Distortion Ratio, or SINAD. ENOB is defined as (SINAD
−1.76) / 6.02.
FULL SCALE ERROR is the difference between the input
voltage [(V
full scale and V
(V
REF−IN
+)−(VIN−)] just causing a transition to positive
IN
− 1.5 LSB, where V
REF
).
REF
is(V
REF+IN
)−
FULL POWER BANDWIDTH is a measure of the frequency
at which the reconstructed output fundamental drops 3 dB
below its low frequency value for a full scale input. The test
is performed with f
of f
. The input frequency at which the output is −3 dB
CLK
relative to the low frequency input signal is the full power
equal to 100 kHz plus integral multiples
IN
bandwidth.
INTERMODULATION DISTORTION (IMD) is the creation of
additional spectral components as a result of two sinusoidal
frequencies being applied to the ADC input at the same time.
It is defined as the ratio of the power in the intermodulation
products to the total power in the original frequencies. IMD is
usually expressed in dB.
Timing Diagrams
INTEGRAL NON-LINEARITY (INL) is a measure of the de-
viation of each individual code from a line drawn from negative full scale (
1
⁄2LSB below the first code transition) through
positive full scale (the last code transition). The deviation of
any given code from this straight line is measured from the
center of that code value.
PIPELINE DELAY (LATENCY) is the number of clock cycles
between initiation of conversion and the availability of that
same conversion result at the output. New data is available
at every clock cycle, but the data lags the conversion by the
pipeline delay.
SIGNAL TO NOISE RATIO (SNR) is the ratio, expressed in
dB, of the rms value of the input signal to the rms value of the
sum of all other spectral components below one-half the
sampling frequency, not including harmonics or dc.
SIGNAL TO NOISE PLUS DISTORTION (S/(N+D) or SINAD)) Is the ratio, expressed in dB, of the rms value of the
input signal to the rms value of all of the other spectral components below half the clock frequency, including harmonics
but excluding dc.
SPURIOUS FREE DYNAMIC RANGE (SFDR) is the difference, expressed in dB, between the rms values of the input
signal and the peak spurious signal, where a spurious signal
is any signal present in the output spectrum that is not
present at the input.
TOTAL HARMONIC DISTORTION (THD) is the ratio, expressed in dB or dBc, of the rms total of the first nine harmonic components, to the rms value of the input signal.
TIMING DIAGRAM 1. Output Timing
DS100103-15
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Page 12
Timing Diagrams (Continued)
DS100103-16
TIMING DIAGRAM 2. Reset and Calibration
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Page 13
Functional Description
Operating on a single +5V supply, the ADC14061 uses a
pipelined architecture and has error correction circuitry and a
calibration mode to help ensure maximum performance at all
times.
Balanced analog signals with a peak-to-peak voltage equal
to the input reference voltage, V
the common mode input voltage, V
(13 bits plus sign). Neglecting offsets, positive input signal
voltages (V
data and negative input signal voltages (V
+−VIN−>0) produce positive digital output
IN
produce negative output data. The input signal can be digi-
, and centered around
REF
, are digitized to 14 bits
CM
+−VIN−<0)
IN
tized at any clock rate between 300 Ksps and 2.5 Msps.
Input voltages below the negative full scale value will cause
the output word to take on the negative full scale value of
10,0000,0000,0000. Input voltage above the positive full
scale value will cause the output word to take on the positive
full scale value of 01,1111,1111,1111.
The output word rate is the same as the clock frequency.The
analog input voltage is acquired at the falling edge of the
clock and the digital data for that sample is delayed by the
pipeline for 13 clock cycles plus t
put is undefined if the chip is being reset or is in the calibra-
DATA_VALID
. The digital out-
tion mode. The output signal may be inhibited by the RD pin
while the converter is in one of these modes.
The RD pin must be low to enable the digital outputs. A logic
low on the power down (PD) pin reduces the converter
power consumption to less than two milliwatts.
Applications Information
1.0 OPERATING CONDITIONS
We recommend that the following conditions be observed for
operation of the ADC14061:
4.75V ≤ V
5.25V ≤ V
3.0V ≤ V
0.3MHz ≤ f
V
CM
V
REF IN
V
REF IN
1.1 The Analog Inputs
TheADC14061 has two analog signal inputs, V
These two pins form a balanced signal input. There are two
reference pins, V
fully differential input reference.
1.2 Reference Inputs
V
REF+IN
effective reference voltage, V
these two voltages:
The operational voltage range of V
+3.0 Volts. The operational voltage range of V
ground to 1.0V. For best performance, the difference between V
REF+IN
of 1.8V to 2.2V. Reducing the reference voltage below 1.8V
will decrease the signal-to-noise ratio (SNR) of the
ADC14061. Increasing the reference voltage (and, consequently, the input signal swing) above 2.2V will increase
THD.
≤ 5.25V
A
≤ 5.25V
D
I/O ≤ VD
D
≤ 2.5 MHz
CLK
=
2.0V (forced)
+=2.0V
−=AGND
REF+IN
and V
. These pins form a
REF−IN
should always be more positive than V
, is the difference between
REF
=
V
REF
and V
)−(V
(V
REF+IN
REF−IN
REF−IN
REF+IN
should remain within the range
).
is +1.8 Volts to
+ and VIN−.
IN
REF−IN
REF−IN
. The
V
REF (MID)
V
CM
this pin with 0.1µF capacitor to ground. Do not load this pin.
is the reference mid-point and is derived from
. This point is brought out only to be by passed. By pass
It is very important that all grounds associated with the reference voltage make connection to the analog ground plane at
a single point to minimize the effects of noise currents in the
gound path.
1.3 Signal Inputs
The signal inputs are V
is defined as
Figure 3
indicates the relationship between the input voltage
and the reference voltages.
+ and VIN−. The signal input, VIN,
IN
=
V
IN
+)−(VIN−).
(V
IN
Figure 4
shows the expected in-
put signal range.
FIGURE 3. Typical Input to Reference Relationaship.
DS100103-18
FIGURE 4. Expected Input Signal Range.
The ADC14061 performs best with a balanced input centered around V
is
V
+orVIN− should be less than the reference voltage and
IN
each signal input pin should be centered on the V
The two V
out of phase from each other. As a simple check to ensure
. The peak-to-peak voltage swing at either
CM
-centered input signals should be exactly 180˚
CM
this, be certain that the average voltage at the ADC iinput
pins is equal to V
impedance less than 100 Ohms.
. Drive the analog inputs with a source
CM
DS100103-17
CM
voltage.
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Page 14
Applications Information (Continued)
The sign bit of the output word will be a logic low when V
is greater than V
bit of the output word will be a logic high.
− . When VIN+ is less than VIN−, the sign
IN
For single ended operation, one of the analog inputs should
be connected to V
duced by about 12dB with a single ended input as compared
. However, SNR and SINAD are re-
CM
with differential inputs.
An input voltage of V
preted as mid-scale and will thus be converted to
=
+)−(VIN−)=0 will be inter-
(V
IN
IN
00,0000,0000,0000, plus any offset error.
The V
+ and the VIN− inputs of the ADC14061 consist of an
IN
analog switch followed by a switched-capacitor amplifier.
The capacitance seen at the analog input pins changes with
the clock level, appearing as 12 pF when the clock is low,
and 28 pF when the clock is high. It is recommended that the
ADC14061 be driven with a low impedance source of 100
Ohms or less.
Asimple application circuit is shown in
Figure 6
and
Here we use two LM6172 dual amplifiers to provide a balanced input to the ADC14061. Note that better noise performance is achieved when V
well-bypassed resistive divider. The resulting offset and off-
voltage is forced with a
REF+IN
set drift is minimal.
Since a dynamic capacitance is more difficult to drive than is
a fixed capacitance, choose driving amplifiers carefully. The
CLC427, CLC440, LM6152, LM6154, LM6172, LM6181 and
LM6182 are excellent amplifiers for driving the ADC14061.
1.4 V
Analog Inputs
CM
input of the ADC14061 is internally biased to 40
The V
CM
of the V
supply with on-chip resistors, as shown in
A
The V
pin must be bypassed to prevent any power supply
CM
noise from modulating this voltage. Modulation of the V
potential will result in the introduction of noise into the input
signal. The advantage of simply bypassing V
driving it) is the circuit simplicity.On the other hand, if the V
supply can vary for any reason, VCMwill also vary at a rate
and amplitude related to the RC filter created by the bypass
capacitor and the internal divider resistors. However, performance of this approach will be adequate for many
applications.
DS100103-21
FIGURE 5. VCMinput to the ADC14061 VCMis set to
40%of V
improved when V
By forcing V
lems mentioned above. One such approach is to buffer the
2.0 Volt reference voltage to drive the V
a constant potential as shown in
with on-chip resistors. Performance is
A
to a fixed potential, you can avoid the prob-
CM
is driven with a stable, low
CM
impedance source
CM
Figure 6
input, holding it at
and
Figure 8
reference voltage is different from the desired V
sired V
another stable source.
voltage may be derived from the reference or from
CM
Figure 7
Figure 5
CM
, that de-
CM
IN
CM
(without
.Ifthe
Note that the buffer used for this purpose should be a slow,
low noise amplifier. The LMC660, LMC662, LMC272 and
+
LMC7101 are good choices for driving the V
ADC14061.
CM
pin of the
2.0 DIGITAL INPUTS
Digital Inputs consist of CLOCK, RESET, CAL, RD and PD.
2.1 The CLOCK signal drives an internal phase delay loop to
create timing for theADC. Drive the clock input with a stable,
low phase jitter clock signal in the range of 300 kHz to 2.5
MHz. The trace carrying the clock signal should be as short
as possible. This trace should not cross any other signal line,
analog or digital, not even at 90˚.
The CLOCK signal also drives the internal state machine. If
the clock is interrupted, the data within the pipeline could become corrupted.
A 100 Ohm damping resistor should be placed in series with
the CLOCK pin to prevent signal undershoot at that input.
2.2 The RESET input is level sensitive and must be pulsed
.
high for at least two clock cycles to reset the ADC after
power-up and before calibration (See Timing Diagram 2).
2.3 The CAL input is level sensitive and must be pulsed high
for at least two clock cycles to begin ADC calibration (See
Timing Diagram 2). Reset the ADC14061 before calibrating.
Re-calibrate after the temperature has changed by more
than 50˚C since the last calibration was performed and after
return from power down.
During calibration, use the same clock frequency that will be
used for conversions to avoid excessive offset errors.
%
Calibration takes 272,800 clock cycles. Irrelevant data may
appear at the data outputs during RESET or CAL and for 13
.
clock cycles thereafter.Calibration should not be started until
the reference outputs have settled (100mS with 1µF capacitors on these outputs) after power up or coming out of the
power down mode.
2.4 RD pin is used to READ the conversion data. When the
A
RD pin is low, the output buffers go into the active state.
When the RD input is high, the output buffers are in the high
impedance state.
2.5 The PD pin, when low, holds the ADC14061 in a
power-down mode where power consumption is typically
less than 2mW to conserve power when the converter is not
being used. The ADC14061 will begin normal operation
within t
CLOCK input is present. Power dissipation during shut-down
after this pin is brought high, provided a valid
WU
is not affected by the clock frequency, or by whether there is
a clock signal present. The data in the pipeline is corrupted
while in the power down mode. The ADC14061 should be reset and calibrated upon returning to normal operation after a
power down.
3.0 OUTPUTS
The ADC14061 has four analog outputs: V
V
REF−OUT,VREF (MID)
EOC (End of Conversion) and 14 Data Output pins.
and VCM.There are 15 digital outputs:
REF+OUT
,
3.1 The reference output voltages are made available only
for the purpose of bypassing with capacitors. These pins
should not be loaded with more than 10 µADC. These output
voltages are described as
=
V
CM
=
V
CM
=
(V
REF
REF+IN
=
(V
REF+OUT+VREF−OUT
+1⁄2V
−1⁄2V
)−(V
REF
REF
REF
+ IN)
)/2.
where V
V
REF (MID)
V
REF+OUT
V
REF−OUT
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Page 15
Applications Information (Continued)
To avoid signal clipping and distortion, V
exceed 3.3V, V
V
should be held in the range of 1.8V to 2.2V.
CM
REF−OUT
should not be below 750 mV and
REF+OUT
3.2 The /EOC output goes low to indicate the presence of
valid data at the output data lines. Valid data is present the
entire time that this signal is low except during reset. Corrupt
or irrelevant data may appear at the data outputs when the
RESET pin or the CAL pin is high.
3.3 The Data Outputs are TTL/CMOS compatible. The output data format is two’s complement. Validdata is present at
these outputs while the EOC pin is low. While the t
and the t
DATA_VALID
timing, a simple way to capture a valid output is to latch the
time provide information about output
data on the rising edge of the CLOCK (pin 10).
Also helpful in minimizing noise due to output switching is to
minimize the load currents at the digital outputs. This can be
done by connecting buffers between the ADC outputs and
any other circuitry. Only one input should be connected to
each output pin. Additionally, inserting series resistors of 47
or 56 Ohms at the digital outputs, close to the ADC pins, will
isolate the outputs from other circuitry and limit output currents. (See
Figure 6
).
should not
time
EOCL
4.0 POWER SUPPLY CONSIDERATIONS
Each power supply pin should be bypassed with a parallel
combination of a 10 µF capacitor and a 0.1 µF ceramic chip
capacitor.The chip capacitors should be within
1
⁄2centimeter
of the power pins. Leadless chip capacitors are preferred because they provide low lead inductance.
While a single 5V source is used for the analog and digital
supplies of the ADC14061, these supply pins should be well
isolated from each other to prevent any digital noise from being coupled to the analog power pins. Supply isolation with
ferrite beads is shown in
Figure 6
and
Figure 8
.
As is the case with all high-speed converters, the ADC14061
is sensitive to power supply noise. Accordingly, the noise on
the analog supply pin should be kept below 100 mV
.
P-P
No pin should ever have a voltage on it that is in excess of
the supply voltages, not even at power up.
The V
I/O provides power for the output drivers and may be
D
operated from a supply in the range of 3.0V to the V
(nominal 5V). This can simplify interfacing to 3.0 Volt devices
and systems. Powering V
power consumption and noise generation due to output
switching. DO NOT operate the V
than V
or VA.
D
I/O from 3 Volts will also reduce
D
I/O at a voltage higher
D
supply
D
FIGURE 6. Simple application circuit with single-ended to differential buffer.
DS100103-19
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Page 16
Applications Information (Continued)
FIGURE 7. Differential drive circuit of
Figure 6
DS100103-20
. All 5k resistors are 0.1%. Tolerance of the other resistors is not
critical.
FIGURE 8. Driving the signal inputs with a transformer.
www.national.com 16
DS100103-22
Page 17
Applications Information (Continued)
5.0 LAYOUT AND GROUNDING
Proper grounding and proper routing of all signals are essential to ensure accurate conversion. Separate analog and
digital ground planes that are connected beneath the
ADC14061 are required to achieve specified performance.
The analog and digital grounds may be in the same layer,but
should be separated from each other and should never overlap each other. Separation should be at least
possible.
The ground return for the digital supply (DGND I/O ) carries
the ground current for the output drivers. This output current
can exhibit high transients that could add noise to the conversion process. To prevent this from happening, the DGND
I/O pin should NOT be connected in close proximity to any of
the ADC14061’s ground pins.
Capacitive coupling between the typically noisy digital
ground plane and the sensitive analog circuitry can lead to
poor performance that may seem impossible to isolate and
remedy. The solution is to keep the analog circuitry separated from the digital circuitry and from the digital ground
plane.
Digital circuits create substantial supply and ground current
transients. The logic noise thus generated could have significant impact upon system noise performance. The best logic
family to use in systems with A/D converters is one which
employs non-saturating transistor designs, or has low noise
characteristics, such as the 74LS, 74HC(T) and 74AC(T)Q
families. The worst noise generators are logic families that
draw the largest supply current transients during clock or signal edges, like the 74F and the 74AC(T) families.
Since digital switching transients are composed largely of
high frequency components, total ground plane copper
weight will have little effect upon the logic-generated noise.
This is because of the skin effect. Totalsurface area is more
important than is total ground plane volume.
An effective way to control ground noise is by connecting the
analog and digital ground planes together beneath the ADC
with a copper trace that is very narrow compared with the
1
⁄8inch, where
rest of the ground plane. A typical width is 3/16 inch (4 to 5
mm).This narrowing beneath the converter provides a fairly
high impedance to the high frequency components of the
digital switching currents, directing them away from the analog pins. The relatively lower frequency analog ground currents see a relatively low impedance across this narrow
ground connection.
Generally,analog and digital lines should cross each other at
90 degrees to avoid getting digital noise into the analog path.
To maximize accuracy in high speed, high resolution systems, however, avoid crossing analog and digital lines altogether. It is important to keep any clock lines isolated from
ALL other lines, including other digital lines. Even the generally accepted 90 degree crossing should be avoided as even
a little coupling can cause problems at high frequencies.
This is because other lines can introduce phase noise (jitter)
into the clock line, which can lead to degradation of SNR.
Best performance at high frequencies and at high resolution
is obtained with a straight signal path. That is, the signal path
through all components should form a straight line wherever
possible.
Be especially careful with the layout of inductors. Mutual inductance can change the characteristics of the circuit in
which they are used. Inductors should not be placed side by
side, even with just a small part of their bodies beside each
other.
The analog input should be isolated from noisy signal traces
to avoid coupling of spurious signals into the input. Any external component (e.g., a filter capacitor) connected between the converter’s input and ground should be connected
to a very clean point in the analog ground plane.
Figure 9
gives an example of a suitable layout. All analog circuitry (input amplifiers, filters, reference components, etc.)
should be placed on or over the analog ground plane. All
digital circuitry and I/O lines should be placed over the digital
ground plane.
All ground connections should have a low inductance path to
ground.
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Page 18
Applications Information (Continued)
FIGURE 9. Example at a suitable layout.
6.0 DYNAMIC PERFORMANCE
The ADC14061 can achieve impressive dynamic performance. To achieve the best dynamic performance with the
ADC14061, the clock source driving the CLK input must be
free of jitter. For best ac performance, isolate the ADC clock
from any digital circuitry with buffers, as with the clock tree
shown in
As mentioned in section 5.0, it is good practice to keep the
ADC clock line as short as possible and to keep it well away
from any other signals. Other signals can introduce phase
noise (jitter) into the clock signal, which can lead to increased distortion. Even lines with 90˚ crossings have capacitive coupling, so try to avoid even these 90˚ crossings of
the clock line.
Figure 10
.
DS100103-24
FIGURE 10. Isolating the ADC clock from other
circuitry with a clock tree.
DS100103-23
7.0 COMMON APPLICATION PITFALLS
Driving the inputs (analog or digital) beyond the power
supply rails. For proper operation, all inputs should not go
more than 100 mV beyond the supply rails (more than 100
mV below the ground pins or 100 mV above the supply pins).
Exceeding these limits on even a transient basis may cause
faulty or erratic operation. It is not uncommon for high speed
digital circuits (e.g., 74F and 74AC devices) to exhibit undershoot that goes more than a volt below ground. A resistor of
about 50 to 100Ω in series with the offending digital input will
eliminate the problem.
Do not allow input voltages to exceed the supply voltage during power up.
Be careful not to overdrive the inputs of the ADC14061 with
a device that is powered from supplies outside the range of
theADC14061 supply. Such practice may lead to conversion
inaccuracies and even to device damage.
Attempting to drive a high capacitance digital data bus.
The more capacitance the output drivers must charge for
each conversion, the more instantaneous digital current
flows through V
current spikes can couple into the analog circuitry of the
I/O and DGND I/O. These large charging
D
ADC14061, degrading dynamic performance. Adequate bypassing and maintaining separate analog and digital ground
planes will reduce this problem. The digital data outputs
should be buffered (with 74ACQ541, for example). Dynamic
performance can also be improved by adding series resistors at each digital output, close to the ADC14061, which reduces the energy coupled back into the converter output
pins by limiting the output current. A reasonable value for
these resistors is 47Ω.
Using an inadequate amplifier to drive the analog input.
As explained in Section 1.3, the capacitance seen at the in-
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Page 19
Applications Information (Continued)
put alternates between 12 pF and 28 pF,depending upon the
phase of the clock. This dynamic loaad is more difficult to
drive than is a fixed capacitance.
If the amplifier exhibits overshoot, ringing, or any evidence of
instability, even at a very low level, it will degrade performance. Amplifiers that have been used sucessfully to dirve
the analog inputs of the ADC14061 include the CLC427,
CLC440, LM6152, LM6154, LM6181 and the LM6182. A
small series reistor at each amplifier output and a capacitor
across the analog inputs (as shown in
prove performance.
Operating with the reference pins outside of the specified range. As mentioned in section 1.2, V
the range of
Figure 7
REF
) will often im-
should be in
1.8V ≤ V
with V
lead to signal distortion.
≤ 1.0V. Operating outside of these limits could
REF−IN
REF
≤ 2.2V
Using a clock source with excessive jitter, using excessively long clock signal trace, or having other signals
coupled to the clock signal trace. This will cause the sam-
pling interval to vary, causing excessive output noise and a
reduction in SNR performance.
Connecting pins marked ″NC″ to any potential. Some of
these pins are used for factory testing. They should all be left
floating. Connecting them to ground, power supply, or some
other voltage could result in a non-functional device.
www.national.com19
Page 20
Physical Dimensions inches (millimeters) unless otherwise noted
52-Lead Thin Quad Flat Pack
Ordering Information Package ADC14061CCVT
NS Package Number VEG52A
ADC14061 Self-Calibrating 14-Bit, 2.5 MSPS, 390 mW A/D Converter
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the body, or (b) support or sustain life, and whose failure to perform when properly used in accordance
with instructions for use provided in the labeling, can
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Tel: 1-800-272-9959
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