Rainbow Electronics ADC12L080 User Manual

October 2004

ADC12L080 12-Bit, 80 MSPS, 450 MHz Bandwidth A/D Converter with Internal Reference

General Description

The ADC12L080 is a monolithic CMOS analog-to-digital converter capable of converting analog input signals into 12-bit digital words at 80 Megasamples per second (MSPS). This converter uses a differential, pipeline architecture with digital error correction and an on-chip sample-and-hold circuit to minimize die size and power consumption while providing excellent dynamic performance. The ADC12L080 can be operated with either the internal or an external reference. Operating on a single 3.3V power supply, this device consumes just 425 mW at 80 MSPS, including the reference current. The Power Down feature reduces power consumption to just 50 mW.

The differential inputs provide a full scale input swing equal

to ternal reference input is converted on-chip to a differential reference for use by the processing circuitry. Output data format may be selected as either offset binary or two’s complement.

This device is available in the 32-lead LQFP package and operates over the industrial temperature range of −40˚C to +85˚C.

. The buffered, high impedance, single-ended ex-

REF

Features

n Single supply operation n Low power consumption n Power down mode n Internal or external reference n Selectable Offset Binary or 2’s Complement data format n Pin-compatible with ADC12010, ADC12020, ADC12040,

ADC12L063, ADC12L066

Key Specifications

n Full Power Bandwidth 450 MHz n DNL n SNR (f n SFDR (f n Power Consumption, 80 MHz

— Operating 425 mW (typ) — Power Down 50 mW (typ)

= 10 MHz) 66 dB (typ)

= 10 MHz) 80 dB (typ)

0.4 LSB (typ)

Applications

n Ultrasound and Imaging n Instrumentation n Cellular Base Stations/Communication Receivers n Sonar/Radar n xDSL n Wireless Local Loops n Data Acquisition Systems n DSP Front Ends

Connection Diagram

20061001

TRI-STATE®is a registered trademark of National Semiconductor Corporation.

Ordering Information

ADC12L080

Block Diagram

Industrial (−40˚C ≤ TA≤ +85˚C) Package

ADC12L080CIVY 32 Pin LQFP

ADC12L080EVAL Evaluation Board

www.national.com 2

20061002

Pin Descriptions and Equivalent Circuits

Pin No. Symbol Equivalent Circuit Description

ANALOG I/O

ADC12L080

31 V

32 V

REF

−

Differential analog signal Input pins. With a 1.0V reference voltage the full-scale differential input signal level is 2.0 V

P-P

with each input pin centered on a common mode voltage,

. The VIN- pin may be connected to VCMfor single-ended

operation, but a differential input signal is required for best performance.

Reference input. This pin should be connected to VAto use the internal 1.0V reference. If it is desired to use an external reference voltage, this pin should be bypassed to AGND with a 0.1 µF low ESL capacitor. Specified operation is with a

of 1.0V, but the device will function well with a V

REF

range indicated in the Electrical Tables.

These pins are high impedance reference bypass pins only. Connect a 0.1 µF capacitor from each of these pins to AGND. Connect a 1.0 µF capacitor from V

to VRN. DO NOT LOAD

these pins.

30 V

DIGITAL I/O

10 CLK

11 OF

8PD

Digital clock input. The range of frequencies for this input is 10 MHz to 80 MHz with guaranteed performance at 80 MHz. The input is sampled on the rising edge of this input.

Output format selection. When this pin is LOW, the output format is offset binary. When this pin is HIGH the output format is two’s complement. This pin may be changed asynchronously, but such a change will result in errors for one or two conversions.

PD is the Power Down input pin. When high, this input puts the converter into the power down mode. When this pin is low, the converter is in the active mode.

www.national.com3

Pin Descriptions and Equivalent Circuits (Continued)

Pin No. Symbol Equivalent Circuit Description

ADC12L080

14–19,

22–27

D0–D11

Digital data output pins that make up the 12-bit conversion results. D0 is the LSB, while D11 is the MSB of the output word.

ANALOG POWER

Positive analog supply pins. These pins should be connected

5, 6, 29 V

to a quiet +3.3V source and bypassed to AGND with 0.1 µF low ESL capacitors located within 1 cm of these power pins, and with a 10 µF capacitor.

4, 7, 28 AGND The ground return for the analog supply.

DIGITAL POWER

Positive digital supply pin. This pin should be connected to

13 V

the same quiet +3.3V source as is V DGND with a 0.1 µF monolithic capacitor in parallel with a 10 µF capacitor, both located within 1 cm of the power pin.

9, 12 DGND The ground return for the digital supply.

Positive digital supply pin for the ADC12L080’s output drivers. This pin should be connected to a voltage source in the range indicated in the Operating Ratings table and be bypassed to DR GND with a 0.1 µF capacitor. If the supply for this pin is

21 V

different from the supply used for V bypassed with a 10 µF capacitor. The voltage at this pin should never exceed the voltage on V 300 mV. All bypass capacitors should be located within 1 cm of the supply pin.

The ground return for the digital supply for the ADC12L080’s output drivers. This pin should be connected to the system

20 DR GND

digital ground, but not be connected in close proximity to the ADC12L080’s DGND or AGND pins. See Section 6.0 (Layout and Grounding) for more details.

and bypassed to

and VD, it should also be

by more than

www.national.com 4

ADC12L080

Absolute Maximum Ratings

(Notes 1, 2)

If Military/Aerospace specified devices are required, please contact the National Semiconductor Sales Office/ Distributors for availability and specifications.

A,VD,VDR

| ≤ 100 mV

A–VD

DR–VD

Voltage on Any Pin −0.3V to V

Input Current at Any Pin (Note 3)

Package Input Current (Note 3)

Package Dissipation at T

= 25˚C See (Note 4)

ESD Susceptibility

Human Body Model (Note 5) 2500V

4.2V

≤ 300 mV

or (V

+ 0.3V)

25 mA

50 mA

Operating Ratings (Notes 1, 2)

Operating Temperature −40˚C ≤ T

Supply Voltage (V

Output Driver Supply (V

REF

) +3.0V to +3.60V

A,VD

) +2.4V to V

CLK, PD, OF −0.05V to V

Input −0V to (VA− 0.5V)

0.5V to (VA-1.5V)

|AGND–DGND| 0V

≤ +85˚C

0.8V to 1.5V

+ 0.05V

Package Thermal Resistances

Package θ

32-Lead LQFP 79˚C / W

J-A

Machine Model (Note 5) 250V

Soldering Temperature,

Infrared, 10 sec. (Note 6) 235˚C

Storage Temperature −65˚C to +150˚C

Converter Electrical Characteristics

Unless otherwise specified, the following specifications apply for AGND = DGND = DR GND = 0V, VA=VD= +3.3V, VDR= +2.5V, PD = 0V, V

Boldface limits apply for T

= +1.0V external, VCM= 1.65V, R

REF

J=TMIN

to T

: all other limits TJ= 25˚C (Notes 7, 8, 9, 10)

MAX

Symbol Parameter Conditions

STATIC CONVERTER CHARACTERISTICS

Resolution with No Missing Codes 12 Bits

INL Integral Non Linearity Best Fit Method

DNL Differential Non Linearity No missing codes

Positive Error −0.15

GE Gain Error

Negative Error +0.4

Offset Error (V

+=VIN−)

Under Range Output Code 0 0

Over Range Output Code 4095 4095

REFERENCE AND ANALOG INPUT CHARACTERISTICS

REF

Common Mode Input Voltage 1.65

VINInput Capacitance (each pin to GND)

VIN= 1.0 Vdc +1V

Reference Voltage (Note 12) 1.0

P-P

100Ω,f

= 80 MHz, tr=tf= 2 ns, fIN= 70 MHz, CL= 15 pF/pin.

CLK

Typical

(Note 10)

1.2

0.4

+0.2

Limits

(Note 10)

(Limits)

4.0 LSB (max)

-3.3 LSB (min)

1.5 LSB (max)

-1.0 LSB (min)

+5.7

-2

-3.7

+1.7

-0.6

%FS (max)

%FS (min)

%FS (max)

%FS (min)

%FS (max)

0.5 V (min)

2.0 V (max)

(CLK LOW) 8 pF

(CLK HIGH) 7 pF

0.8 V (min)

1.5 V (max)

Units

www.national.com5

DC and Logic Electrical Characteristics

Unless otherwise specified, the following specifications apply for AGND = DGND = DR GND = 0V, VA=VD= +3.3V, VDR= +2.5V, PD = 0V, V

Boldface limits apply for T

ADC12L080

= +1.0V external, VCM= 1.65V, R

REF

J=TMIN

to T

: all other limits TJ= 25˚C (Notes 7, 8, 9, 10)

MAX

Symbol Parameter Conditions

DYNAMIC CONVERTER CHARACTERISTICS

BW Full Power Bandwidth -0.5 dBFS Input, Output at −3 dB 450 MHz

= 10 MHz, Differential VIN= −0.5 dBFS 66 64 dB (min)

= 40 MHz, Differential VIN= −0.5 dBFS 65 dB

SNR Signal-to-Noise Ratio

SINAD Signal-to-Noise & Distortion

ENOB Effective Number of Bits

THD Total Harmonic Distortion

2nd Harm

3rd Harm

Second Harmonic Distortion

Third Harmonic Distortion

SFDR Spurious Free Dynamic Range

IMD Intermodulation Distortion

= 70 MHz, Differential VIN= −0.5 dBFS 65 63 dB (min)

= 150 MHz, Differential VIN= −0.5 dBFS 63 dB

= 10 MHz, Differential VIN= −0.5 dBFS 66 63 dB (min)

= 40 MHz, Differential VIN= −0.5 dBFS 64.5 dB

= 70 MHz, Differential VIN= −0.5 dBFS 64 62.7 dB (min)

= 150 MHz, Differential VIN= −0.5 dBFS 62 dB

= 10 MHz, Differential VIN= −0.5 dBFS 10.7 10.2 Bits (min)

= 40 MHz, Differential VIN= 0.5 dBFS 10.4 Bits

= 70 MHz, Differential VIN= −0.5 dBFS 10.3 10.1 Bits (min)

= 150 MHz, Differential VIN= −0.5 dBFS 10.0 Bits

= 10 MHz, Differential VIN= −0.5 dBFS −77 -66 dB (max)

= 40 MHz, Differential VIN= −0.5 dBFS -74 dB

= 70 MHz, Differential VIN= −0.5 dBFS -71 -65 dB (max)

= 150 MHz, Differential VIN= −0.5 dBFS -70 dB

= 10 MHz, Differential VIN= −0.5 dBFS −80 -68 dB (max)

= 40 MHz, Differential VIN= −0.5 dBFS -80 dB

= 70 MHz, Differential VIN= −0.5 dBFS -80 -65.5 dB (max)

= 150 MHz, Differential VIN= −0.5 dBFS -79 dB

= 10 MHz, Differential VIN= −0.5 dBFS −84 -69 dB (max)

= 40 MHz, Differential VIN= −0.5 dBFS -81 dB

= 70 MHz, Differential VIN= −0.5 dBFS -79 -66 dB (max)

= 150 MHz, Differential VIN= −0.5 dBFS -78 dB

= 10 MHz, Differential VIN= −0.5 dBFS 80 68 dB (min)

= 40 MHz, Differential VIN= −0.5 dBFS 77 dB

= 70 MHz, Differential VIN= −0.5 dBFS 74 -65.5 dB (min)

= 150 MHz, Differential VIN= −0.5 dBFS 73 dB

1 = 19.6MHz, fIN2 = 20.5 MHz,

each = -6.0 dBFS

CLK, PD, OF DIGITAL INPUT CHARACTERISTICS

IN(1)

IN(0)

Logical “1” Input Voltage VD= 3.3V 2.0 V (min)

IN(1)

Logical “0” Input Voltage VD= 3.3V 0.8 V (max)

IN(0)

Logical “1” Input Current VIN+, VIN− = 3.3V 10 µA

Logical “0” Input Current VIN+, VIN− = 0V −10 µA

Digital Input Capacitance 5 pF

D0–D11 DIGITAL OUTPUT CHARACTERISTICS

−I

Logical “1” Output Voltage I

OUT(1)

Logical “0” Output Voltage I

OUT(0)

Output Short Circuit Source

Current

Output Short Circuit Sink Current V

= −0.5 mA

OUT

= 1.6 mA 0.4 V (max)

OUT

= 0V −20 mA

OUT

= 2.5V 20 mA

OUT

100Ω,f

= 80 MHz, tr=tf= 2 ns, fIN= 70 MHz, CL= 15 pF/pin.

CLK

Typical

(Note 10)

Limits

(Note 10)

66 dBFS

−

0.18

Units

(Limits)

V (min)

www.national.com 6

DC and Logic Electrical Characteristics (Continued)

Unless otherwise specified, the following specifications apply for AGND = DGND = DR GND = 0V, VA=VD= +3.3V, VDR= +2.5V, PD = 0V, V

Boldface limits apply for T

= +1.0V external, VCM= 1.65V, R

REF

J=TMIN

to T

MAX

: all other limits TJ= 25˚C (Notes 7, 8, 9, 10)

Symbol Parameter Conditions

POWER SUPPLY CHARACTERISTICS

Analog Supply Current

Digital Supply Current

Digital Output Supply Current

Total Power Consumption

PSRR1 Power Supply Rejection Ratio

PD Pin = DGND PD Pin = V

PD Pin = DGND, f PD Pin = V

PD Pin = DGND, C PD Pin = V

Rejection of Full-Scale Gain Error change with V

100Ω,f

= 3.0V vs. 3.6V

= 80 MHz, tr=tf= 2 ns, fIN= 70 MHz, CL= 15 pF/pin.

CLK

= 0, (Note 13)

= 0 pF (Note 14)

Typical

(Note 10)

120

Limits

(Note 10)

168 mA (max)

11.5 mA (max)

425

590 mW (max)

41 dB

(Limits)

AC Electrical Characteristics

Unless otherwise specified, the following specifications apply for AGND = DGND = DR GND = 0V, VA=VD= +3.3V, VDR= +2.5V, PD = 0V, V

Boldface limits apply for T

= +1.0V external, VCM= 1.65V, R

REF

J=TMIN

to T

: all other limits TJ= 25˚C (Notes 7, 8, 9, 10, 11)

MAX

Symbol Parameter Conditions

Maximum Clock Frequency 80 MHz (min)

Minimum Clock Frequency 10 MHz

Clock Duty Cycle

CONV

Note 1: Absolute Maximum Ratings indicate limits beyond which damage to the device may occur. Operating Ratings indicate conditions for which the device is functional, but do not guarantee specific performance limits. For guaranteed specifications and test conditions, see the Electrical Characteristics. The guaranteed specifications apply only for the test conditions listed. Some performance characteristics may degrade when the device is not operated under the listed test conditions.

Note 2: All voltages are measured with respect to GND = AGND = DGND = 0V, unless otherwise specified.

Note 3: When the input voltage at any pin exceeds the power supplies (that is, V

25 mA. The 50 mA maximum package input current rating limits the number of pins that can safely exceed the power supplies with an input current of 25 mA to two.

Note 4: The absolute maximum junction temperature (T junction-to-ambient thermal resistance (θ for maximum power dissipation will be reached only when the device is operated in a severe fault condition (e.g. when input or output pins are driven beyond the power supply voltages, or the power supply polarity is reversed). Obviously, such conditions should always be avoided.

Note 5: Human body model is 100 pF capacitor discharged through a 1.5 kΩ resistor. Machine model is 220 pF discharged through 0Ω.

Note 6: The 235˚C reflow temperature refers to infrared reflow. For Vapor Phase Reflow (VPR), the following Conditions apply: Maintain the temperature at the top

of the package body above 183˚C for a minimum 60 seconds. The temperature measured on the package body must not exceed 220˚C. Only one excursion above 183˚C is allowed per reflow cycle.

Note 7: The inputs are protected as shown below. Input voltages above V However, errors in the A/D conversion can occur if the input goes above V voltage must be ≤3.4V to ensure accurate conversions.

Clock High Time 5.5 ns (min)

Clock Low Time 5.5 ns (min)

Conversion Latency 6

Data Output Delay after Rising CLK Edge

Aperture Delay 2 ns

Aperture Jitter 0.7 ps rms

Power Down Mode Exit Cycle

), and the ambient temperature, (TA), and can be calculated using the formula PDMAX=(TJmax - TA)/θJA. The values

0.1 µF on pins 30, 31, 32, and 1.0 µF from pin 30 to 31

max) for this device is 150˚C. The maximum allowable power dissipation is dictated by TJmax, the

100Ω,f

= 80 MHz, tr=tf= 2 ns, fIN= 70 MHz, CL= 15 pF/pin.

CLK

Typical

(Note 10)

Limits

(Note 10)

60 40

Units

(Limits)

% (max)

% (min)

Clock

Cycles

= 2.5V 5.2 8.3 ns (max)

= 3.3V 4.8 7.5 ns (max)

1µs

AGND, or V

or below GND will not damage this device, provided current is limited per (Note 3).

or below GND by more than 100 mV. As an example, if VAis 3.3V, the full-scale input

VA,VDor VDR), the current at that pin should be limited to

ADC12L080

Units

mA mA

www.national.com7

+ 16 hidden pages