Page 1
December 2003
ADC12L066
12-Bit, 66 MSPS, 450 MHz Bandwidth A/D Converter with
Internal Sample-and-Hold
ADC12L066 12-Bit, 66 MSPS, 450 MHz Bandwidth A/D Converter with Internal Sample-and-Hold
General Description
The ADC12L066 is a monolithic CMOS analog-to-digital converter capable of converting analog input signals into 12-bit
digital words at 66 Megasamples per second (MSPS), minimum, with typical operation possible up to 80 MSPS. This
converter uses a differential, pipeline architecture with digital
error correction and an on-chip sample-and-hold circuit to
minimize die size and power consumption while providing
excellent dynamic performance. A unique sample-and-hold
stage yields a full-power bandwidth of 450 MHz. Operating
on a single 3.3V power supply, this device consumes just
357 mW at 66 MSPS, including the reference current. The
Power Down feature reduces power consumption to just
50 mW.
The differential inputs provide a full scale input swing equal
±
V
to
of the differential input is recommended for optimum performance. For ease of use, the buffered, high impedance,
single-ended reference input is converted on-chip to a differential reference for use by the processing circuitry. Output
data format is 12-bit offset binary.
This device is available in the 32-lead LQFP package and
will operate over the industrial temperature range of −40˚C to
+85˚C. An evaluation board is available to facilitate the
evaluation process.
with the possibility of a single-ended input. Full use
REF
Features
n Single supply operation
n Low power consumption
n Power down mode
n On-chip reference buffer
Key Specifications
n Resolution 12 Bits
n Conversion Rate 66 MSPS
n Full Power Bandwidth 450 MHz
n DNL
n SNR (f
n SFDR (f
n Data Latency 6 Clock Cycles
n Supply Voltage +3.3V
n Power Consumption, 66 MHz 357 mW (typ)
= 10 MHz) 66 dB (typ)
IN
= 10 MHz) 80 dB (typ)
IN
±
0.4 LSB (typ)
±
300 mV
Applications
n Ultrasound and Imaging
n Instrumentation
n Cellular Base Stations/Communications Receivers
n Sonar/Radar
n xDSL
n Wireless Local Loops
n Data Acquisition Systems
n DSP Front Ends
Connection Diagram
20032801
TRI-STATE®is a registered trademark of National Semiconductor Corporation.
© 2003 National Semiconductor Corporation DS200328 www.national.com
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Ordering Information
ADC12L066
Block Diagram
Industrial (−40˚C ≤ TA≤ +85˚C) Package
ADC12L066CIVY 32 Pin LQFP
ADC12L066CIVYX 32 Pin LQFP Tape and Reel
ADC12L066EVAL Evaluation Board
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20032802
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Pin Descriptions and Equivalent Circuits
Pin No. Symbol Equivalent Circuit Description
ANALOG I/O
ADC12L066
2V
3V
1V
31 V
32 V
IN
IN
REF
RP
RM
+
−
Analog signal Input pins. With a 1.0V reference voltage the
differential input signal level is 2.0 V
connected to V
for single-ended operation, but a differential
CM
. The VIN- pin may be
P-P
input signal is required for best performance.
Reference input. This pin should be bypassed to AGND with
a 0.1 µF monolithic capacitor. V
is 1.0V nominal and
REF
should be between 0.8V and 1.5V.
These pins are high impedance reference bypass pins.
Connect a 0.1 µF capacitor from each of these pins to AGND.
DO NOT LOAD these pins.
30 V
RN
DIGITAL I/O
10 CLK
11 OE
8PD
Digital clock input. The range of frequencies for this input is
1 MHz to 80 MHz (typical) with guaranteed performance at 66
MHz. The input is sampled on the rising edge of this input.
OE is the output enable pin that, when low, enables the
TRI-STATE®data output pins. When this pin is high, the
outputs are in a high impedance state.
PD is the Power Down input pin. When high, this input puts
the converter into the power down mode. When this pin is
low, the converter is in the active mode.
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Pin Descriptions and Equivalent Circuits (Continued)
Pin No. Symbol Equivalent Circuit Description
ADC12L066
14–19,
22–27
D0–D11
Digital data output pins that make up the 12-bit conversion
results. D0 is the LSB, while D11 is the MSB of the offset
binary output word.
ANALOG POWER
Positive analog supply pins. These pins should be connected
5, 6, 29 V
A
to a quiet +3.3V source and bypassed to AGND with 0.1 µF
monolithic capacitors located within 1 cm of these power pins,
and with a 10 µF capacitor.
4, 7, 28 AGND The ground return for the analog supply.
DIGITAL POWER
Positive digital supply pin. This pin should be connected to
13 V
D
the same quiet +3.3V source as is V
DGND with a 0.1 µF monolithic capacitor in parallel with a 10
µF capacitor, both located within 1 cm of the power pin.
9, 12 DGND The ground return for the digital supply.
Positive digital supply pin for the ADC12L066’s output drivers.
This pin should be connected to a voltage source of +1.8V to
and bypassed to DR GND with a 0.1 µF monolithic
V
D
21 V
DR
capacitor. If the supply for this pin is different from the supply
used for V
and VD, it should also be bypassed with a 10 µF
A
tantalum capacitor. The voltage at this pin should never
exceed the voltage on V
by more than 300 mV. All bypass
D
capacitors should be located within 1 cm of the supply pin.
The ground return for the digital supply for the ADC12L066’s
output drivers. This pin should be connected to the system
20 DR GND
digital ground, but not be connected in close proximity to the
ADC12L066’s DGND or AGND pins. See Section 5.0 (Layout
and Grounding) for more details.
and bypassed to
A
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Page 5
ADC12L066
Absolute Maximum Ratings (Notes 1,
2)
If Military/Aerospace specified devices are required,
please contact the National Semiconductor Sales Office/
Distributors for availability and specifications.
or V
A
+0.3V)
±
25 mA
±
50 mA
4.2V
D
V
A,VD,VDR
|V
| ≤ 100 mV
A–VD
Voltage on Any Pin −0.3V to (V
Input Current at Any Pin (Note 3)
Package Input Current (Note 3)
Package Dissipation at T
= 25˚C See (Note 4)
A
Operating Ratings (Notes 1, 2)
Operating Temperature −40˚C ≤ T
Supply Voltage (V
Output Driver Supply (V
V
Input 0.8V to 1.5V
REF
CLK, PD, OE
V
Input −0V to (VA− 0.5V)
IN
V
CM
|AGND–DGND| ≤100 mV
) +3.0V to +3.60V
A,VD
) +1.8V to V
DR
−0.05V to (VD+ 0.05V)
0.5V to (VA-1.5V)
ESD Susceptibility
Human Body Model (Note 5) 2500V
Machine Model (Note 5) 250V
Soldering Temperature,
Infrared, 10 sec. (Note 6) 235˚C
Storage Temperature −65˚C to +150˚C
Converter Electrical Characteristics
Unless otherwise specified, the following specifications apply for AGND = DGND = DR GND = 0V, VA=VD= +3.3V,
= +2.5V, PD = 0V, V
V
DR
=T
MIN
to T
: all other limits TJ= 25˚C (Notes 7, 8, 9, 10)
MAX
Symbol Parameter Conditions
STATIC CONVERTER CHARACTERISTICS
Resolution with No Missing Codes 12 Bits
INL Integral Non Linearity (Note 11)
DNL Differential Non Linearity
GE Gain Error
Offset Error (V
Under Range Output Code 0 0
Over Range Output Code 4095 4095
REFERENCE AND ANALOG INPUT CHARACTERISTICS
V
CM
C
IN
V
REF
Common Mode Input Voltage 1.0
VINInput Capacitance (each pin to
GND)
Reference Voltage (Note 13) 1.0
Reference Input Resistance 100 MΩ (min)
= +1.0V, VCM= 1.0V, f
REF
= 66 MHz, tr=tf= 2 ns, CL= 15 pF/pin. Boldface limits apply for T
CLK
Typical
(Note 10)
Positive Error −0.15
Negative Error +0.4
+=VIN−) +0.2
IN
VIN+ 1.0 Vdc
+1V
P-P
(CLK LOW) 8 pF
(CLK HIGH) 7 pF
Limits
(Note 10)
±
1.2
±
0.4
+2.7 LSB (max)
−3 LSB (min)
+1 LSB (max)
−0.95 LSB (min)
±
3 %FS (max)
+4 %FS (max)
−5 %FS (min)
±
1.3 %FS (max)
0.5 V (min)
1.5 V (max)
0.8 V (min)
1.5 V (max)
≤ +85˚C
A
Units
(Limits)
D
J
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Page 6
Converter Electrical Characteristics (Continued)
Unless otherwise specified, the following specifications apply for AGND = DGND = DR GND = 0V, VA=VD= +3.3V,
= +2.5V, PD = 0V, V
V
DR
ADC12L066
=T
MIN
to T
: all other limits TJ= 25˚C (Notes 7, 8, 9, 10)
MAX
Symbol Parameter Conditions
DYNAMIC CONVERTER CHARACTERISTICS
BW Full Power Bandwidth 0 dBFS Input, Output at −3 dB 450 MHz
SNR Signal-to-Noise Ratio
= +1.0V, VCM= 1.0V, f
REF
= 66 MHz, tr=tf= 2 ns, CL= 15 pF/pin. Boldface limits apply for T
CLK
= 10 MHz, VIN=
f
IN
−0.5 dBFS
= 25 MHz, VIN=
f
IN
−0.5 dBFS
= 150 MHz, V
f
IN
= −6 dBFS
f
= 240 Hz, VIN=
IN
−6 dBFS
Typical
(Note 10)
85˚C
25˚C 65 dB (min)
66
−40˚C 64.6 dB (min)
65 dB
85˚C
IN
25˚C 54 dB (min)
55
−40˚C 51 dB (min)
52 dB
Limits
(Note 10)
64.6 dB (min)
52 dB (min)
J
Units
(Limits)
SINAD Signal-to-Noise & Distortion
ENOB Effective Number of Bits
= 10 MHz, VIN=
f
IN
−0.5 dBFS
= 25 MHz, VIN=
f
IN
−0.5 dBFS
= 150 MHz, V
f
IN
= −6 dBFS
f
= 240 Hz, VIN=
IN
−6 dBFS
= 10 MHz, VIN=
f
IN
−0.5 dBFS
= 25 MHz, VIN=
f
IN
−0.5 dBFS
= 150 MHz, V
f
IN
= −6 dBFS
f
= 240 Hz, VIN=
IN
−6 dBFS
85˚C
25˚C 64.8 dB (min)
66
64.3 dB (min)
−40˚C 63 dB (min)
64 dB
IN
25˚C 53.9 dB (min)
55
85˚C
51.8 dB (min)
−40˚C 50 dB (min)
51 dB
85˚C
25˚C 10.5 Bits (min)
10.7
10.3
−40˚C 10.2
10.3 Bits
IN
25˚C 8.6 Bits (min)
8.8
85˚C
8.3
−40˚C 8.0
8.2 Bits
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Converter Electrical Characteristics (Continued)
Unless otherwise specified, the following specifications apply for AGND = DGND = DR GND = 0V, VA=VD= +3.3V,
= +2.5V, PD = 0V, V
V
DR
=T
MIN
to T
: all other limits TJ= 25˚C (Notes 7, 8, 9, 10)
MAX
Symbol Parameter Conditions
2nd
Harm
Second Harmonic Distortion
= +1.0V, VCM= 1.0V, f
REF
= 66 MHz, tr=tf= 2 ns, CL= 15 pF/pin. Boldface limits apply for T
CLK
= 10 MHz, VIN=
f
IN
−0.5 dBFS
= 25 MHz, VIN=
f
IN
−0.5 dBFS
= 150 MHz, V
f
IN
= −6 dBFS
f
= 240 Hz, VIN=
IN
−6 dBFS
Typical
(Note 10)
85˚C
25˚C −73 dB (max)
−80
−40˚C −68 dB (max)
−80 dB
85˚C
IN
25˚C −66 dB (max)
−81
−40˚C −56 dB (max)
−61 dB
Limits
(Note 10)
−73 dB(max)
−66 dB(max)
ADC12L066
J
Units
(Limits)
3rd
Harm
Third Harmonic Distortion
THD Total Harmonic Distortion
= 10 MHz, VIN=
f
IN
−0.5 dBFS
= 25 MHz, VIN=
f
IN
−0.5 dBFS
= 150 MHz, V
f
IN
= −6 dBFS
f
= 240 Hz, VIN=
IN
−6 dBFS
= 10 MHz, VIN=
f
IN
−0.5 dBFS
= 25 MHz, VIN=
f
IN
−0.5 dBFS
= 150 MHz, V
f
IN
= −6 dBFS
f
= 240 Hz, VIN=
IN
−6 dBFS
85˚C
25˚C −74 dB (max)
−84
−74 dB(max)
−40˚C −71 dB (max)
−79 dB
IN
25˚C −68 dB (max)
−78
85˚C
−68 dB(max)
−40˚C −64 dB (max)
−78 dB
85˚C
25˚C −72 dB (max)
−77
−72 dB(max)
−40˚C −66 dB (max)
−71 dB
IN
25˚C −63 dB (max)
−69
85˚C
−63 dB(max)
−40˚C −53 dB (max)
−57 dB
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Converter Electrical Characteristics (Continued)
Unless otherwise specified, the following specifications apply for AGND = DGND = DR GND = 0V, VA=VD= +3.3V,
= +2.5V, PD = 0V, V
V
DR
ADC12L066
=T
MIN
to T
: all other limits TJ= 25˚C (Notes 7, 8, 9, 10)
MAX
Symbol Parameter Conditions
SFDR Spurious Free Dynamic Range
= +1.0V, VCM= 1.0V, f
REF
= 66 MHz, tr=tf= 2 ns, CL= 15 pF/pin. Boldface limits apply for T
CLK
Typical
= 10 MHz, VIN=
f
IN
−0.5 dBFS
= 25 MHz, VIN=
f
IN
−0.5 dBFS
= 150 MHz, V
f
IN
= −6 dBFS
f
= 240 Hz, VIN=
IN
−6 dBFS
(Note 10)
85˚C
25˚C 73 dB (min)
80
−40˚C 68
73 dB
85˚C
IN
25˚C 66 dB (min)
74
−40˚C 56
61 dB
(Note 10)
DC and Logic Electrical Characteristics
Unless otherwise specified, the following specifications apply for AGND = DGND = DR GND = 0V, VA=VD= +3.3V,
= +2.5V, PD = 0V, V
V
DR
=T
to T
MIN
: all other limits TJ= 25˚C (Notes 7, 8, 9, 10)
MAX
Symbol Parameter Conditions
CLK, PD, OE DIGITAL INPUT CHARACTERISTICS
V
V
I
IN(1)
I
IN(0)
C
IN(1)
IN(0)
IN
Logical “1” Input Voltage VD= 3.3V 2.0 V (min)
Logical “0” Input Voltage VD= 3.3V 0.8 V (max)
Logical “1” Input Current V
Logical “0” Input Current V
Digital Input Capacitance 5 pF
D0–D11 DIGITAL OUTPUT CHARACTERISTICS
V
V
I
OZ
+I
−I
OUT(1)
OUT(0)
SC
SC
Logical “1” Output Voltage I
Logical “0” Output Voltage I
TRI-STATE Output Current
Output Short Circuit Source
Current
Output Short Circuit Sink Current V
POWER SUPPLY CHARACTERISTICS
I
A
I
D
I
DR
Analog Supply Current
Digital Supply Current
Digital Output Supply Current
Total Power Consumption
PSRR1 Power Supply Rejection
= +1.0V, VCM= 1.0V, f
REF
= 66 MHz, tr=tf= 2 ns, CL= 15 pF/pin. Boldface limits apply for T
CLK
Typical
(Note 10)
+
−
,V
IN
IN
OUT
OUT
V
OUT
V
OUT
V
OUT
OUT
PD Pin = DGND, V
PD Pin = V
PD Pin = DGND
PD Pin = V
PD Pin = DGND, (Note 14)
PD Pin = V
PD Pin = DGND, C
PD Pin = V
Rejection of Full-Scale Error with
V
A
= 3.3V 10 µA
IN
+
−
,V
= 0V −10 µA
IN
= −0.5 mA
= 1.6 mA 0.4 V (max)
= 3.3V 100 nA
= 0V −100 nA
= 0V −20 mA
= 2.5V 20 mA
= 1.0V
REF
DR
103
4
5.3
DR
DR
DR
= 3.0V vs. 3.6V
= 0 pF (Note 15)
L
2
<
1
0
357
50
58 dB
Limits
(Limits)
73
66
Limits
(Note 10)
V
−
DR
0.18
139 mA (max)
6.2 mA (max)
479 mW (max)
J
Units
J
Units
(Limits)
V (min)
mA
mA
mA
mA
mW
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Page 9
AC Electrical Characteristics
Unless otherwise specified, the following specifications apply for AGND = DGND = DR GND = 0V, VA=VD= +3.3V,
= +2.5V, PD = 0V, V
V
DR
=TJ=T
MIN
to T
: all other limits TA=TJ= 25˚C (Notes 7, 8, 9, 10, 12)
MAX
Symbol Parameter Conditions
1 Maximum Clock Frequency 80 66 MHz (min)
f
CLK
f
2 Minimum Clock Frequency 1 MHz
CLK
DC Clock Duty Cycle
t
CH
t
CL
t
CONV
t
OD
t
AD
t
AJ
t
DIS
t
EN
t
PD
Note 1: Absolute Maximum Ratings indicate limits beyond which damage to the device may occur. Operating Ratings indicate conditions for which the device is
functional, but do not guarantee specific performance limits. For guaranteed specifications and test conditions, see the Electrical Characteristics. The guaranteed
specifications apply only for the test conditions listed. Some performance characteristics may degrade when the device is not operated under the listed test
conditions.
Note 2: All voltages are measured with respect to GND = AGND = DGND = 0V, unless otherwise specified.
Note 3: When the input voltage at any pin exceeds the power supplies (that is, V
25 mA. The 50 mA maximum package input current rating limits the number of pins that can safely exceed the power supplies with an input current of 25 mA to two.
Note 4: The absolute maximum junction temperature (T
junction-to-ambient thermal resistance (θ
LQFP, θ
this device under normal operation will typically be about 612 mW (357 typical power consumption + 255 mW output loading with 250 MHz input). The values for
maximum power dissipation listed above will be reached only when the device is operated in a severe fault condition (e.g. when input or output pins are driven
beyond the power supply voltages, or the power supply polarity is reversed). Obviously, such conditions should always be avoided.
Note 5: Human body model is 100 pF capacitor discharged through a 1.5 kΩ resistor. Machine model is 220 pF discharged through 0Ω.
Note 6: The 235˚C reflow temperature refers to infrared reflow. For Vapor Phase Reflow (VPR), the following Conditions apply: Maintain the temperature at the top
of the package body above 183˚C for a minimum 60 seconds. The temperature measured on the package body must not exceed 220˚C. Only one excursion above
183˚C is allowed per reflow cycle.
Note 7: The inputs are protected as shown below. Input voltages above V
However, errors in the A/D conversion can occur if the input goes above V
voltage must be ≤3.4V to ensure accurate conversions.
Clock High Time 6.5 ns (min)
Clock Low Time 6.5 ns (min)
Conversion Latency 6
Data Output Delay after Rising CLK
Edge
Aperture Delay 2 ns
Aperture Jitter 1.2 ps rms
Data outputs into TRI-STATE Mode 10 ns
Data Outputs Active after TRI-STATE 10 ns
Power Down Mode Exit Cycle 0.1 µF on pins 30, 31, 32 300 ns
is 79˚C/W, so PDMAX = 1,582 mW at 25˚C and 823 mW at the maximum operating ambient temperature of 85˚C. Note that the power consumption of
JA
= +1.0V, VCM= 1.0V, f
REF
= 66 MHz, tr=tf= 2 ns, CL= 15 pF/pin. Boldface limits apply for T
CLK
Typical
(Note 10)
Limits
(Note 10)
40
60
= 2.5V 7.5 11 ns (max)
V
DR
V
= 3.3V 6.7 10.5 ns (max)
DR
<
AGND, or V
IN
max) for this device is 150˚C. The maximum allowable power dissipation is dictated by TJmax, the
), and the ambient temperature, (TA), and can be calculated using the formula PDMAX-(TJmax - TA)/θJA. In the 32-pin
JA
J
or below GND will not damage this device, provided current is limited per (Note 3).
A
or below GND by more than 100 mV. As an example, if VAis 3.3V, the full-scale input
A
>
VA,VDor VDR), the current at that pin should be limited to
IN
Units
(Limits)
% (min)
% (max)
Clock
Cycles
ADC12L066
A
20032807
Note 8: To guarantee accuracy, it is required that |VA–VD| ≤ 100 mV and separate bypass capacitors are used at each power supply pin.
Note 9: With the test condition for V
Note 10: Typical figures are at T
Level).
Note 11: Integral Non Linearity is defined as the deviation of the analog value, expressed in LSBs, from the straight line that passes through positive and negative
full-scale.
Note 12: Timing specifications are tested at TTL logic levels, V
Note 13: Optimum dynamic performance will be obtained by keeping the reference input in the 0.8V to 1.5V range. The LM4051CIM3-ADJ or the LM4051CIM3-1.2
bandgap voltage reference is recommended for this application.
Note 14: I
V
DR
voltage, C
Note 15: Power consumption excludes output driver power. See (Note 14).
is the current consumed by the switching of the output drivers and is primarily determined by load capacitance on the output pins, the supply voltage,
DR
, and the rate at which the outputs are switching (which is signal dependent). IDR=VDR(C0xf0+C1xf1+....C11xf11) where VDRis the output driver power supply
is total capacitance on the output pin, and fnis the average frequency at which that pin is toggling.
n
= +1.0V (2 V
REF
= 25˚C, and represent most likely parametric norms. Test limits are guaranteed to National’sAOQL (Average Outgoing Quality
A=TJ
differential input), the 12-bit LSB is 488 µV.
P-P
= 0.4V for a falling edge and VIH= 2.4V for a rising edge.
IL
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Page 10
Specification Definitions
APERTURE DELAY is the time after the rising edge of the
clock to when the input signal is acquired or held for conversion.
ADC12L066
APERTURE JITTER (APERTURE UNCERTAINTY) is the
variation in aperture delay from sample to sample. Aperture
jitter manifests itself as noise in the output.
CLOCK DUTY CYCLE is the ratio of the time that a repetitive digital waveform is high to the total time of one period.
The specification here refers to the ADC clock input signal.
COMMON MODE VOLTAGE (V
present at both signal inputs to the ADC.
CONVERSION LATENCY is the number of clock cycles
between initiation of conversion and when that data is presented to the output driver stage. Data for any given sample
is available at the output pins the Pipeline Delay plus the
Output Delay after the sample is taken. New data is available
at every clock cycle, but the data lags the conversion by the
pipeline delay.
DIFFERENTIAL NON-LINEARITY (DNL) is the measure of
the maximum deviation from the ideal step size of 1 LSB.
EFFECTIVE NUMBER OF BITS (ENOB, or EFFECTIVE
BITS) is another method of specifying Signal-to-Noise and
Distortion or SINAD. ENOB is defined as (SINAD - 1.76) /
6.02 and says that the converter is equivalent to a perfect
ADC of this (ENOB) number of bits.
FULL POWER BANDWIDTH is a measure of the frequency
at which the reconstructed output fundamental drops 3 dB
below its low frequency value for a full scale input.
GAIN ERROR is the deviation from the ideal slope of the
transfer function. It can be calculated as:
Gain Error = Positive Full Scale Error − Offset Error
LSB (LEAST SIGNIFICANT BIT) is the bit that has the
smallest value or weight of all bits. This value is V
where “n” is the ADC resolution in bits, which is 12 in the
case of the ADC12DL066.
INTEGRAL NON LINEARITY (INL) is a measure of the
deviation of each individual code from a line drawn from
negative full scale (
1
⁄2LSB below the first code transition)
through positive full scale (
transition). The deviation of any given code from this straight
line is measured from the center of that code value.
INTERMODULATION DISTORTION (IMD) is the creation of
additional spectral components as a result of two sinusoidal
frequencies being applied to the ADC input at the same time.
It is defined as the ratio of the power in the second and third
order intermodulation products to the power in one of the
original frequencies. IMD is usually expressed in dBFS.
MISSING CODES are those output codes that will never
appear at the ADC outputs. The ADC12L066 is guaranteed
not to have any missing codes.
MSB (MOST SIGNIFICANT BIT) is the bit that has the
largest value or weight. Its value is one half of full scale.
NEGATIVE FULL SCALE ERROR is the difference between
+
−
the input voltage (V
−V
IN
IN
negative full scale to the first code and its ideal value of 0.5
LSB.
) is the d.c. potential
CM
1
⁄2LSB above the last code
) just causing a transition from
REF
/2n,
OFFSET ERROR is the input voltage that will cause a transition from a code of 01 1111 1111 to a code of 10 0000 0000.
OUTPUT DELAY is the time delay after the rising edge of
the clock before the data update is presented at the output
pins.
PIPELINE DELAY (LATENCY) See Conversion Latency
POSITIVE FULL SCALE ERROR is the difference between
the actual last code transition and its ideal value of 1
1
⁄2LSB
below positive full scale.
POWER SUPPLY REJECTION RATIO (PSRR) is a mea-
sure of how well the ADC rejects a change in the power
supply voltage. For the ADC12L066, PSRR1 is the ratio of
the change in Full-Scale Error that results from a change in
the d.c. power supply voltage, expressed in dB. PSRR2 is a
measure of how well an a.c. signal riding upon the power
supply is rejected at the output.
SIGNAL TO NOISE RATIO (SNR) is the ratio, expressed in
dB, of the rms value of the input signal to the rms value of the
sum of all other spectral components below one-half the
sampling frequency, not including harmonics or d.c.
SIGNAL TO NOISE PLUS DISTORTION (S/N+D or SINAD)
Is the ratio, expressed in dB, of the rms value of the input
signal to the rms value of all of the other spectral components below half the clock frequency, including harmonics
but excluding d.c.
SPURIOUS FREE DYNAMIC RANGE (SFDR) is the difference, expressed in dB, between the rms values of the input
signal and the peak spurious signal, where a spurious signal
is any signal present in the output spectrum that is not
present at the input.
TOTAL HARMONIC DISTORTION (THD) is the ratio, expressed in dBc, of the rms total of the first nine harmonic
levels at the output to the level of the fundamental at the
output. THD is calculated as
where f1is the RMS power of the fundamental (output)
frequency and f
through f10are the RMS power in the first 9
2
harmonic frequencies.
SECOND HARMONIC DISTORTION (2ND HARM) is the
difference expressed in dB, between the RMS power in the
input frequency at the output and the power in its 2nd
harmonic level at the output.
THIRD HARMONIC DISTORTION (3RD HARM) is the difference, expressed in dB, between the RMS power in the
input frequency at the output and the power in its 3rd harmonic level at the output.
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Page 11
Timing Diagram
ADC12L066
Transfer Characteristic
Output Timing
20032809
20032810
FIGURE 1. Transfer Characteristic
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Page 12
Typical Performance Characteristics V
= 1.0V, unless otherwise stated.
V
REF
ADC12L066
DNL DNL vs. f
= 3.3V, VDR= 2.5V, f
A=VD
= 66 MHz, fIN= 25 MHz,
CLK
CLK
200328E6
DNL vs. Clock Duty Cycle DNL vs. Temperature
20032892
INL INL vs. f
CLK
20032891
20032893
200328E7
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20032894
Page 13
ADC12L066
Typical Performance Characteristics V
= 1.0V, unless otherwise stated. (Continued)
V
REF
INL vs. Clock Duty Cycle INL vs. Temperature
20032895
SNR vs. V
A
= 3.3V, VDR= 2.5V, f
A=VD
= 66 MHz, fIN= 25 MHz,
CLK
SNR vs. V
DR
20032896
SNR vs. V
CM
20032897 20032898
SNR vs. f
200328B1 200328B2
CLK
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Page 14
Typical Performance Characteristics V
= 1.0V, unless otherwise stated. (Continued)
V
REF
= 3.3V, VDR= 2.5V, f
A=VD
= 66 MHz, fIN= 25 MHz,
CLK
ADC12L066
SNR vs. Clock Duty Cycle SNR vs. V
200328B3
SNR vs. Temperature THD vs. V
REF
200328B4
A
THD vs. V
200328B5
DR
200328B7 200328B8
THD vs. V
CM
200328B6
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Page 15
ADC12L066
Typical Performance Characteristics V
= 1.0V, unless otherwise stated. (Continued)
V
REF
THD vs. f
THD vs. V
CLK
200328B9
REF
= 3.3V, VDR= 2.5V, f
A=VD
= 66 MHz, fIN= 25 MHz,
CLK
THD vs. Clock Duty Cycle
THD vs. Temperature
200328C1
SINAD vs. V
200328C2
A
200328C4 200328C5
SINAD vs. V
DR
200328C3
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Page 16
Typical Performance Characteristics V
= 1.0V, unless otherwise stated. (Continued)
V
REF
= 3.3V, VDR= 2.5V, f
A=VD
= 66 MHz, fIN= 25 MHz,
CLK
ADC12L066
SINAD vs. V
CM
200328C6 200328C7
SINAD vs. f
SINAD vs. Clock Duty Cycle SINAD vs. V
CLK
REF
200328C8
SINAD vs. Temperature SFDR vs. V
200328D1
200328C9
A
200328D2
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Page 17
ADC12L066
Typical Performance Characteristics V
= 1.0V, unless otherwise stated. (Continued)
V
REF
SFDR vs. V
SFDR vs. f
DR
200328D3 200328D4
CLK
= 3.3V, VDR= 2.5V, f
A=VD
= 66 MHz, fIN= 25 MHz,
CLK
SFDR vs. V
CM
SFDR vs. Clock Duty Cycle
SFDR vs. V
REF
200328D5
200328D7
200328D6
SFDR vs. Temperature
200328D8
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Page 18
Typical Performance Characteristics V
= 1.0V, unless otherwise stated. (Continued)
V
REF
= 3.3V, VDR= 2.5V, f
A=VD
= 66 MHz, fIN= 25 MHz,
CLK
ADC12L066
Power Consumption vs. f
CLK
200328D9 200328E1
tODvs. V
DR
Spectral Response@10 MHz Input Spectral Response@25 MHz Input
200328E4 200328E8
Spectral Response@50 MHz Input Spectral Response@75MHz Input
200328E9 200328J0
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Page 19
ADC12L066
Typical Performance Characteristics V
= 1.0V, unless otherwise stated. (Continued)
V
REF
Spectral Response
Spectral Response@240 MHz Input
@
100 MHz Input Spectral Response@150 MHz Input
200328J1 200328J2
= 3.3V, VDR= 2.5V, f
A=VD
= 66 MHz, fIN= 25 MHz,
CLK
200328E5
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Page 20
Functional Description
Operating on a single +3.3V supply, the ADC12L066 uses a
pipeline architecture and has error correction circuitry to help
ensure maximum performance.
ADC12L066
Differential analog input signals are digitized to 12 bits. Each
analog input signal should have a peak-to-peak voltage
equal to the input reference voltage, V
around a common mode voltage, V
REF
, and be 180˚ out of
CM
phase with each other. Table 1. Input to Output Relationship-
–Differential Input and Table 2. Input to Output
Relationship–Single-Ended Input indicate the input to output
relationship of the ADC12L066. Biasing one input to V
and driving the other input with its full range signal results in
a 6 dB reduction of the output range, limiting it to the range
1
⁄4to3⁄4of the minimum output range obtainable if both
of
inputs were driven with complimentary signals. Section 1.3
explains how to avoid this signal reduction.
TABLE 1. Input to Output Relationship–Differential
Input
V
IN
V
CM−VREF
V
CM−VREF
V
CM
V
CM+VREF
V
CM+VREF
+
/2 VCM+V
/4 VCM+V
/4 VCM−V
/2 VCM−V
−
V
IN
/2 0000 0000 0000
REF
/4 0100 0000 0000
REF
V
CM
/4 1100 0000 0000
REF
/2 1111 1111 1111
REF
1000 0000 0000
TABLE 2. Input to Output Relationship–Single-Ended
Input
V
IN
V
CM−VREF
V
CM−VREF
V
CM
V
CM+VREF
V
CM+VREF
+
/2 V
/2 V
−
V
IN
V
CM
CM
V
CM
CM
V
CM
0000 0000 0000
0100 0000 0000
1000 0000 0000
1100 0000 0000
1111 1111 1111
The output word rate is the same as the clock frequency,
which can be between 1 MSPS and 80 MSPS (typical). The
analog input voltage is acquired at the rising edge of the
clock and the digital data for that sample is delayed by the
pipeline for 6 clock cycles.
A logic high on the power down (PD) pin reduces the converter power consumption to 50 mW.
Applications Information
1.0 OPERATING CONDITIONS
We recommend that the following conditions be observed for
operation of the ADC12L066:
CM
≤ 3.6V
A
CLK
REF
≤ 1.5V
D
≤ 80 MHz
≤ 1.5V
3.0 V ≤ V
V
D=VA
1.8V ≤ VDR≤ V
1 MHz ≤ f
0.8V ≤ V
0.5V ≤ V
, be centered
CM
Output
Output
1.1 ANALOG INPUTS
The ADC12L066 has two analog signal inputs, V
. These two pins form a differential input pair. There is
V
IN−
one reference input pin, V
REF
.
+ and
IN
1.2 Reference Pins
The ADC12L066 is designed to operate with a 1.0V reference, but performs well with reference voltages in the range
of 0.8V to 1.5V. Lower reference voltages will decrease the
signal-to-noise ratio (SNR) of the ADC12L066. Increasing
the reference voltage (and the input signal swing) beyond
1.5V may degrade THD for a full-scale input, especially at
higher input frequencies. It is important that all grounds
associated with the reference voltage and the input signal
make connection to the analog ground plane at a single,
quiet point in that plane to minimize the effects of noise
currents in the ground path.
The ADC12L066 will perform well with reference voltages up
to 1.5V for full-scale input frequencies up to 10 MHz. However, more headroom is needed as the input frequency
increases, so the maximum reference voltage (and input
swing) will decrease for higher full-scale input frequencies.
The three Reference Bypass Pins (V
RP,VRM
and VRN) are
made available for bypass purposes only. These pins should
each be bypassed to ground with a 0.1 µF capacitor. Smaller
capacitor values will allow faster recovery from the power
down mode, but may result in degraded noise performance.
DO NOT LOAD these pins. Loading any of these pins may
result in performance degradation.
The nominal voltages for the reference bypass pins are as
follows:
V
RM=VA
V
RP=VRM+VREF
V
RN=VRM−VREF
The V
source (V
/2
/2
/2
pin may be used as a common mode voltage
RM
) for the analog input pins as long as no d.c.
CM
current is drawn from it. However, because the voltage at
this pin is half that of the V
supply pin, using these pins for
A
a common mode source will result in reduced input headroom (the difference between the V
supply voltage and the
A
peak signal voltage at either analog input) and the possibility
of reduced THD and SFDR performance. For this reason, it
is recommended that V
always exceed V
A
by at least 2
REF
Volts. For high input frequencies it may be necessary to
increase this headroom to maintain THD and SFDR performance. Alternatively, use V
foraVCMsource.
RN
1.3 SIGNAL INPUTS
The signal inputs are V
+ and VIN−. The input signal, VIN,is
IN
defined as
+
=(V
V
IN
)–(VIN−)
IN
Figure 2 shows the expected input signal range.
Note that the nominal input common mode voltage is V
REF
and the nominal input signals each run between the limits of
V
REF
/2 and 3V
/2. The Peaks of the input signals should
REF
never exceed the voltage described as
Peak Input Voltage = V
A
− 0.8
to maintain dynamic performance.
The ADC12L066 performs best with a differential input with
each input centered around a common mode voltage, V
CM
(minimum of 0.5V). The peak-to-peak voltage swing at both
+ and VIN− should each not exceed the value of the
V
IN
reference voltage or the output data will be clipped.
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Page 21
Applications Information (Continued)
The two input signals should be exactly 180˚ out of phase
from each other and of the same amplitude. For single
frequency (sine wave) inputs, angular errors result in a reduction of the effective full scale input. For a complex waveform, however, angular errors will result in distortion.
20032811
FIGURE 2. Expected Input Signal Range
For angular deviations of up to 10 degrees from these two
signals being 180 out of phase with each other, the full scale
error in LSB can be described as approximately
E
FS
Where dev is the angular difference between the two signals
having a 180˚ relative phase relationship to each other (see
Figure 3). Drive the analog inputs with a source impedance
less than 100Ω.
FIGURE 3. Angular Errors Between the Two Input
Signals Will Reduce the Output Level or Cause
Distortion
For differential operation, each analog input pin of the differential pair should have a peak-to-peak voltage equal to the
input reference voltage, V
1.3.1 Single-Ended Input Operation
Single-ended performance is inferior to that with differential
input signals, so single-ended operation is not recommended, However, if single-ended operation is required and
the resulting performance degradation is acceptable, one of
the analog inputs should be connected to the d.c. mid point
voltage of the driven input. The peak-to-peak differential
input signal should be twice the reference voltage to maximize SNR and SINAD performance (Figure 2b).
For example, set V
+ with a signal range of 0.5V to 1.5V.
V
IN
to 0.5V, bias VIN− to 1.0V and drive
REF
Because very large input signal swings can degrade distortion performance, better performance with a single-ended
input can be obtained by reducing the reference voltage
while maintaining a full-range output. Table 1. Input to Output
1.79
= dev
20032812
, and be centered around VCM.
REF
Relationship–Differential Input and Table 2. Input to Output
Relationship–Single-Ended Input indicate the input to output
relationship of the ADC12L066.
1.3.2 Driving the Analog Inputs
The V
+ and the VIN− inputs of the ADC12L066 consist of
IN
an analog switch followed by a switched-capacitor amplifier.
The capacitance seen at the analog input pins changes with
the clock level, appearing as 8 pF when the clock is low, and
7 pF when the clock is high.
As the internal sampling switch opens and closes, current
pulses occur at the analog input pins, resulting in voltage
spikes at the signal input pins. As a driving amplifier attempts
to counteract these voltage spikes, a damped oscillation
may appear at the ADC analog input. The best amplifiers for
driving the ADC12L066 input pins must be able to react to
these spikes and settle before the switch opens and another
sample is taken. The LMH6702 LMH6628, LMH6622 and the
LMH6655 are good amplifiers for driving the ADC12L066.
To help isolate the pulses at the ADC input from the amplifier
output, use RCs at the inputs, as can be seen in Figure 5
and Figure 6. These components should be placed close to
the ADC inputs because the input pins of the ADC is the
most sensitive part of the system and this is the last opportunity to filter that input.
For Nyquist applications the RC pole should be at the ADC
sample rate. The ADC input capacitance in the sample mode
should be considered with setting the RC pole. Setting the
pole in this manner will provide best SINAD performance.
To obtain best SNR performance, leave the RC values as
calculated. To obtain best SINAD and ENOB performance,
reduce the RC time constant until SNR and THD are numerically equal to each other. To obtain best distortion and SFDR
performance, eliminate the RC altogether.
For undersampling applications, the RC pole should be set
at about 1.5 to 2 times the maximum input frequency for
narrow band applications. For wide band applications, the
RC pole should be set at about 1.5 times the maximum input
frequency to maintain a linear delay response.
A single-ended to differential conversion circuit is shown in
Figure 5 and Table 3. Resistor values for Circuit of NS4771
gives resistor values for that circuit to provide input signals in
±
a range of 1.0V
0.5V at each of the differential input pins of
the ADC12L066.
TABLE 3. Resistor values for Circuit of Figure 5
SIGNAL
RANGE
R1 R2 R3 R4 R5, R6
0 - 0.25V open 0Ω 124Ω 1500Ω 1000Ω
0 - 0.5V 0Ω openΩ 499Ω 1500Ω 499Ω
±
0.25V 100Ω 698Ω 100Ω 698Ω 499Ω
1.3.3 Input Common Mode Voltage
The input common mode voltage, V
, should be in the
CM
range of 0.5V to 1.5V and be of a value such that the peak
excursions of the analog signal does not go more negative
than ground or more positive than 0.8 Volts below the V
supply voltage. The nominal VCMshould generally be about
1.0V, but V
or VRNcan be used as a VCMsource as long
RM
as no d.c. current is drawn from either of these pins.
ADC12L066
A
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Page 22
Applications Information (Continued)
2.0 DIGITAL INPUTS
Digital inputs are TTL/CMOS compatible and consist of CLK,
ADC12L066
OE and PD.
2.1 CLK
The CLK signal controls the timing of the sampling process.
Drive the clock input with a stable, low jitter clock signal in
the range of 1 MHz to 80 MHz with rise and fall times of less
than 2 ns. The trace carrying the clock signal should be as
short as possible and should not cross any other signal line,
analog or digital, not even at 90˚.
The CLK signal also drives an internal state machine. If the
CLK is interrupted, or its frequency is too low, the charge on
internal capacitors can dissipate to the point where the accuracy of the output data will degrade. This is what limits the
lowest sample rate to 1 MSPS.
The duty cycle of the clock signal can affect the performance
of any A/D Converter. Because achieving a precise duty
cycle is difficult, the ADC12L066 is designed to maintain
performance over a range of duty cycles. While it is specified
and performance is guaranteed with a 50% clock duty cycle,
performance is typically maintained over a clock duty cycle
range of 40% to 60%.
The clock line should be series terminated at the clock
source in the characteristic impedance of that line if the clock
line is longer than
where tris the clock rise time and t
of the signal along the trace. For a typical board of FR-4
material, t
is about 150 ps/in, or 60 ps/cm. The CLOCK
PROP
pin may need to be a.c. terminated with a series RC such
that the resistor value is equal to the characteristic impedance of the clock line and the capacitor value is
where "I" is the line length in inches and Zois the characteristic impedance of the clock line. This termination should be
located as close as possible to, but within one centimeter of,
the ADC12L066 clock pin as shown in Figure 6. It should
also be located beyond the ADC clock pin as seen from the
clock source.
Take care to maintain a constant clock line impedance
throughout the length of the line and to properly terminate
the source end of the line with its characteristic impedance.
Refer to Application Note AN-905 for information on setting
characteristic impedance.
2.2 OE
The OE pin, when high, puts the output pins into a high
impedance state. When this pin is low the outputs are in the
active state. The ADC12L066 will continue to convert
whether this pin is high or low, but the output can not be read
while the OE pin is high.
is the propagation rate
prop
Since ADC noise increases with increased output capacitance at the digital output pins, do use the TRI-STATE outputs of the ADC12L066 to drive a bus. Rather, each output
pin should be located close to and drive a single digital input
pin. To further reduce ADC noise, a 100 Ω resistor in series
with each ADC digital output pin, located close to their respective pins, should be added to the circuit. See Section
3.0.
2.3 PD
The PD pin, when high, holds the ADC12L066 in a powerdown mode to conserve power when the converter is not
being used. The power consumption in this state is 50 mW
with a 66 MHz clock and 30 mW if the clock is stopped. The
output data pins are undefined in this mode. The data in the
pipeline is corrupted while in the power down mode.
The Power Down Mode Exit Cycle time is determined by the
value of the capacitors on pins 30, 31 and 32 and is about
300 ns with the recommended 0.1 µF on these pins. These
capacitors loose their charge in the Power Down mode and
must be recharged by on-chip circuitry before conversions
can be accurate. Smaller capacitor values allow faster recovery from the power down mode, but can result in a
reduction in SNR, SINAD and ENOB performance.
3.0 OUTPUTS
The ADC12L066 has 12 TTL/CMOS compatible Data Output
pins. The offset binary data is present at these outputs while
the OE and PD pins are low. While the t
time provides
OD
information about output timing, a simple way to capture a
valid output is to latch the data on the rising edge of the
conversion clock (pin 10).
Be very careful when driving a high capacitance bus. The
more capacitance the output drivers must charge for each
conversion, the more instantaneous digital current flows
through V
and DR GND. These large charging current
DR
spikes can cause on-chip ground noise and couple into the
analog circuitry, degrading dynamic performance. Adequate
bypassing, limiting output capacitance and careful attention
to the ground plane will reduce this problem. Additionally,
bus capacitance beyond the specified 15 pF/pin will cause
to increase, making it difficult to properly latch the ADC
t
OD
output data. The result could be an apparent reduction in
dynamic performance.
To minimize noise due to output switching, minimize the load
currents at the digital outputs. This can be done by connecting buffers between the ADC outputs and any other circuitry
(74ACQ541, for example). Only one driven input should be
connected to each output pin. Additionally, inserting series
resistors of 100Ω at the digital outputs, close to the ADC
pins, will isolate the outputs from trace and other circuit
capacitances and limit the output currents, which could otherwise result in performance degradation. See Figure 4.
While the ADC12L066 will operate with V
to 1.8V, t
increases with reduced VDR. Be careful of
OD
external timing when using reduced V
DR
.
DR
voltages down
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Page 23
Applications Information (Continued)
ADC12L066
FIGURE 4. Simple Application Circuit with Single-Ended to Differential Buffer
20032814
FIGURE 5. Differential Drive Circuit of Figure 4
20032813
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Page 24
Applications Information (Continued)
ADC12L066
FIGURE 6. Driving the Signal Inputs with a Transformer
4.0 POWER SUPPLY CONSIDERATIONS
The power supply pins should be bypassed with a 10 µF
capacitor and with a 0.1 µF ceramic chip capacitor within a
centimeter of each power pin. Leadless chip capacitors are
preferred because they have low series inductance.
As is the case with all high-speed converters, the
ADC12L066 is sensitive to power supply noise. Accordingly,
the noise on the analog supply pin should be kept below 100
.
mV
P-P
No pin should ever have a voltage on it that is in excess of
the supply voltages, not even on a transient basis. Be especially careful of this during turn on and turn off of power.
The V
be operated from a supply in the range of 1.8V to V
pin provides power for the output drivers and may
DR
. This
D
can simplify interfacing to devices and systems operating
with supplies less than V
with reduced V
DR
voltage higher than V
. Note, however, that tODincreases
D
. DO NOT operate the VDRpin at a
.
D
5.0 LAYOUT AND GROUNDING
Proper grounding and proper routing of all signals are essential to ensure accurate conversion. Maintaining separate
analog and digital areas of the board, with the ADC12L066
between these areas, is required to achieve specified performance.
20032815
The ground return for the data outputs (DR GND) carries the
ground current for the output drivers. The output current can
exhibit high transients that could add noise to the conversion
process. To prevent this from happening, the DR GND pins
should NOT be connected to system ground in close proximity to any of the ADC12L066’s other ground pins.
Capacitive coupling between the typically noisy digital circuitry and the sensitive analog circuitry can lead to poor
performance. The solution is to keep the analog circuitry
separated from the digital circuitry, and to keep the clock line
as short as possible.
Digital circuits create substantial supply and ground current
transients. The logic noise thus generated could have significant impact upon system noise performance. The best
logic family to use in systems with A/D converters is one
which employs non-saturating transistor designs, or has low
noise characteristics, such as the 74LS, 74HC(T) and
74AC(T)Q families. The worst noise generators are logic
families that draw the largest supply current transients during clock or signal edges, like the 74F and the 74AC(T)
families.
The effects of the noise generated from the ADC output
switching can be minimized through the use of 100Ω resistors in series with each data output line. Locate these resistors as close to the ADC output pins as possible.
Since digital switching transients are composed largely of
high frequency components, total ground plane copper
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Page 25
Applications Information (Continued)
weight will have little effect upon the logic-generated noise.
This is because of the skin effect. Total surface area is more
important than is total ground plane volume.
Generally, analog and digital lines should cross each other at
90˚ to avoid crosstalk. To maximize accuracy in high speed,
high resolution systems, however, avoid crossing analog and
digital lines altogether. It is important to keep clock lines as
short as possible and isolated from ALL other lines, including
ADC12L066
other digital lines. Even the generally accepted 90˚ crossing
should be avoided with the clock line as even a little coupling
can cause problems at high frequencies. This is because
other lines can introduce jitter into the clock line, which can
lead to degradation of SNR. Also, the high speed clock can
introduce noise into the analog chain.
Best performance at high frequencies and at high resolution
is obtained with a straight signal path. That is, the signal path
through all components should form a straight line wherever
possible.
FIGURE 7. Example of a Suitable Layout
Be especially careful with the layout of inductors. Mutual
inductance can change the characteristics of the circuit in
which they are used. Inductors should not be placed side by
side, even with just a small part of their bodies beside each
other.
The analog input should be isolated from noisy signal traces
to avoid coupling of spurious signals into the input. Any
external component (e.g., a filter capacitor) connected between the converter’s input pins and ground or to the reference input pin and ground should be connected to a very
clean point in the ground plane.
Figure 7 gives an example of a suitable layout. All analog
circuitry (input amplifiers, filters, reference components, etc.)
should be placed in the analog area of the board. All digital
circuitry and I/O lines should be placed in the digital area of
the board. The ADC12L066 should be between these two
areas. Furthermore, all components in the reference circuitry
and the input signal chain that are connected to ground
should be connected together with short traces and enter the
ground plane at a single, quiet point. All ground connections
should have a low inductance path to ground.
6.0 DYNAMIC PERFORMANCE
To achieve the best dynamic performance, the clock source
driving the CLK input must be free of jitter. Isolate the ADC
clock from any digital circuitry with buffers, as with the clock
tree shown in Figure 8.
As mentioned in Section 5.0, it is good practice to keep the
ADC clock line as short as possible and to keep it well away
20032816
from any other signals. Other signals can introduce jitter into
the clock signal, which can lead to reduced SNR performance, and the clock can introduce noise into other lines.
Even lines with 90˚ crossings have capacitive coupling, so
try to avoid even these 90˚ crossings of the clock line.
20032817
FIGURE 8. Isolating the ADC Clock from other Circuitry
with a Clock Tree
7.0 COMMON APPLICATION PITFALLS Driving the inputs (analog or digital) beyond the power
supply rails. For proper operation, all inputs should not go
more than 100 mV beyond the supply rails (more than
100 mV below the ground pins or 100 mV above the supply
pins). Exceeding these limits on even a transient basis may
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Page 26
Applications Information (Continued)
cause faulty or erratic operation. It is not uncommon for high
speed digital components (e.g., 74F and 74AC devices) to
ADC12L066
exhibit overshoot or undershoot that goes above the power
supply or below ground. A resistor of about 50Ω to 100Ω in
series with any offending digital input, close to the signal
source, will eliminate the problem.
Do not allow input voltages to exceed the supply voltage,
even on a transient basis. Not even during power up or
power down.
Be careful not to overdrive the inputs of the ADC12L066 with
a device that is powered from supplies outside the range of
the ADC12L066 supply. Such practice may lead to conversion inaccuracies and even to device damage.
Attempting to drive a high capacitance digital data bus.
The more capacitance the output drivers must charge for
each conversion, the more instantaneous digital current
flows through V
rent spikes can couple into the analog circuitry, degrading
dynamic performance. Adequate bypassing and maintaining
separate analog and digital areas on the pc board will reduce
this problem.
Additionally, bus capacitance beyond the specified 15 pF/pin
will cause t
the ADC output data. The result could, again, be a reduction
in dynamic performance.
The digital data outputs should be buffered (with 74ACQ541,
for example). Dynamic performance can also be improved
by adding series resistors at each digital output, close to the
ADC12L066, which reduces the energy coupled back into
the converter output pins by limiting the output current. A
reasonable value for these resistors is 100Ω.
and DR GND. These large charging cur-
DR
to increase, making it difficult to properly latch
OD
Using an inadequate amplifier to drive the analog input.
As explained in Section 1.3, the capacitance seen at the
input alternates between 8 pF and 7 pF, depending upon the
phase of the clock. This dynamic load is more difficult to
drive than is a fixed capacitance.
If the amplifier exhibits overshoot, ringing, or any evidence of
instability, even at a very low level, it will degrade performance. A small series resistor at each amplifier output and a
capacitor across the analog inputs (as shown in Figures 5, 6)
will improve performance. The LMH6702, LMH6628,
LMH6622 and LMH6655 have been successfully used to
drive the analog inputs of the ADC12L066.
Also, it is important that the signals at the two inputs have
exactly the same amplitude and be exactly 180
o
out of phase
with each other. Board layout, especially equality of the
length of the two traces to the input pins, will affect the
effective phase between these two signals. Remember that
an operational amplifier operated in the non-inverting configuration will exhibit more time delay than will the same
device operating in the inverting configuration.
Operating with the reference pins outside of the specified range. As mentioned in Section 1.2, V
should be in
REF
the range of
0.8V ≤ V
REF
≤ 1.5V
Operating outside of these limits could lead to performance
degradation.
Using a clock source with excessive jitter, using excessively long clock signal trace, or having other signals
coupled to the clock signal trace. This will cause the
sampling interval to vary, causing excessive output noise
and a reduction in SNR and SINAD performance.
www.national.com 26
Page 27
Physical Dimensions inches (millimeters) unless otherwise noted
ADC12L066 12-Bit, 66 MSPS, 450 MHz Bandwidth A/D Converter with Internal Sample-and-Hold
32-Lead LQFP Package
Ordering Number ADC12L066CIVY
NS Package Number VBE32A
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