Rainbow Electronics ADC12L066 User Manual
December 2003
ADC12L066
12-Bit, 66 MSPS, 450 MHz Bandwidth A/D Converter with
Internal Sample-and-Hold
ADC12L066 12-Bit, 66 MSPS, 450 MHz Bandwidth A/D Converter with Internal Sample-and-Hold
General Description
The ADC12L066 is a monolithic CMOS analog-to-digital converter capable of converting analog input signals into 12-bit
digital words at 66 Megasamples per second (MSPS), minimum, with typical operation possible up to 80 MSPS. This
converter uses a differential, pipeline architecture with digital
error correction and an on-chip sample-and-hold circuit to
minimize die size and power consumption while providing
excellent dynamic performance. A unique sample-and-hold
stage yields a full-power bandwidth of 450 MHz. Operating
on a single 3.3V power supply, this device consumes just
357 mW at 66 MSPS, including the reference current. The
Power Down feature reduces power consumption to just
50 mW.
The differential inputs provide a full scale input swing equal
±
V
to
of the differential input is recommended for optimum performance. For ease of use, the buffered, high impedance,
single-ended reference input is converted on-chip to a differential reference for use by the processing circuitry. Output
data format is 12-bit offset binary.
This device is available in the 32-lead LQFP package and
will operate over the industrial temperature range of −40˚C to
+85˚C. An evaluation board is available to facilitate the
evaluation process.
with the possibility of a single-ended input. Full use
REF
Features
n Single supply operation
n Low power consumption
n Power down mode
n On-chip reference buffer
Key Specifications
n Resolution 12 Bits
n Conversion Rate 66 MSPS
n Full Power Bandwidth 450 MHz
n DNL
n SNR (f
n SFDR (f
n Data Latency 6 Clock Cycles
n Supply Voltage +3.3V
n Power Consumption, 66 MHz 357 mW (typ)
= 10 MHz) 66 dB (typ)
IN
= 10 MHz) 80 dB (typ)
IN
±
0.4 LSB (typ)
±
300 mV
Applications
n Ultrasound and Imaging
n Instrumentation
n Cellular Base Stations/Communications Receivers
n Sonar/Radar
n xDSL
n Wireless Local Loops
n Data Acquisition Systems
n DSP Front Ends
Connection Diagram
20032801
TRI-STATE®is a registered trademark of National Semiconductor Corporation.
© 2003 National Semiconductor Corporation DS200328 www.national.com
Ordering Information
ADC12L066
Block Diagram
Industrial (−40˚C ≤ TA≤ +85˚C) Package
ADC12L066CIVY 32 Pin LQFP
ADC12L066CIVYX 32 Pin LQFP Tape and Reel
ADC12L066EVAL Evaluation Board
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20032802
Pin Descriptions and Equivalent Circuits
Pin No. Symbol Equivalent Circuit Description
ANALOG I/O
ADC12L066
2V
3V
1V
31 V
32 V
IN
IN
REF
RP
RM
+
−
Analog signal Input pins. With a 1.0V reference voltage the
differential input signal level is 2.0 V
connected to V
for single-ended operation, but a differential
CM
. The VIN- pin may be
P-P
input signal is required for best performance.
Reference input. This pin should be bypassed to AGND with
a 0.1 µF monolithic capacitor. V
is 1.0V nominal and
REF
should be between 0.8V and 1.5V.
These pins are high impedance reference bypass pins.
Connect a 0.1 µF capacitor from each of these pins to AGND.
DO NOT LOAD these pins.
30 V
RN
DIGITAL I/O
10 CLK
11 OE
8PD
Digital clock input. The range of frequencies for this input is
1 MHz to 80 MHz (typical) with guaranteed performance at 66
MHz. The input is sampled on the rising edge of this input.
OE is the output enable pin that, when low, enables the
TRI-STATE®data output pins. When this pin is high, the
outputs are in a high impedance state.
PD is the Power Down input pin. When high, this input puts
the converter into the power down mode. When this pin is
low, the converter is in the active mode.
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Pin Descriptions and Equivalent Circuits (Continued)
Pin No. Symbol Equivalent Circuit Description
ADC12L066
14–19,
22–27
D0–D11
Digital data output pins that make up the 12-bit conversion
results. D0 is the LSB, while D11 is the MSB of the offset
binary output word.
ANALOG POWER
Positive analog supply pins. These pins should be connected
5, 6, 29 V
A
to a quiet +3.3V source and bypassed to AGND with 0.1 µF
monolithic capacitors located within 1 cm of these power pins,
and with a 10 µF capacitor.
4, 7, 28 AGND The ground return for the analog supply.
DIGITAL POWER
Positive digital supply pin. This pin should be connected to
13 V
D
the same quiet +3.3V source as is V
DGND with a 0.1 µF monolithic capacitor in parallel with a 10
µF capacitor, both located within 1 cm of the power pin.
9, 12 DGND The ground return for the digital supply.
Positive digital supply pin for the ADC12L066’s output drivers.
This pin should be connected to a voltage source of +1.8V to
and bypassed to DR GND with a 0.1 µF monolithic
V
D
21 V
DR
capacitor. If the supply for this pin is different from the supply
used for V
and VD, it should also be bypassed with a 10 µF
A
tantalum capacitor. The voltage at this pin should never
exceed the voltage on V
by more than 300 mV. All bypass
D
capacitors should be located within 1 cm of the supply pin.
The ground return for the digital supply for the ADC12L066’s
output drivers. This pin should be connected to the system
20 DR GND
digital ground, but not be connected in close proximity to the
ADC12L066’s DGND or AGND pins. See Section 5.0 (Layout
and Grounding) for more details.
and bypassed to
A
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ADC12L066
Absolute Maximum Ratings (Notes 1,
2)
If Military/Aerospace specified devices are required,
please contact the National Semiconductor Sales Office/
Distributors for availability and specifications.
or V
A
+0.3V)
±
25 mA
±
50 mA
4.2V
D
V
A,VD,VDR
|V
| ≤ 100 mV
A–VD
Voltage on Any Pin −0.3V to (V
Input Current at Any Pin (Note 3)
Package Input Current (Note 3)
Package Dissipation at T
= 25˚C See (Note 4)
A
Operating Ratings (Notes 1, 2)
Operating Temperature −40˚C ≤ T
Supply Voltage (V
Output Driver Supply (V
V
Input 0.8V to 1.5V
REF
CLK, PD, OE
V
Input −0V to (VA− 0.5V)
IN
V
CM
|AGND–DGND| ≤100 mV
) +3.0V to +3.60V
A,VD
) +1.8V to V
DR
−0.05V to (VD+ 0.05V)
0.5V to (VA-1.5V)
ESD Susceptibility
Human Body Model (Note 5) 2500V
Machine Model (Note 5) 250V
Soldering Temperature,
Infrared, 10 sec. (Note 6) 235˚C
Storage Temperature −65˚C to +150˚C
Converter Electrical Characteristics
Unless otherwise specified, the following specifications apply for AGND = DGND = DR GND = 0V, VA=VD= +3.3V,
= +2.5V, PD = 0V, V
V
DR
=T
MIN
to T
: all other limits TJ= 25˚C (Notes 7, 8, 9, 10)
MAX
Symbol Parameter Conditions
STATIC CONVERTER CHARACTERISTICS
Resolution with No Missing Codes 12 Bits
INL Integral Non Linearity (Note 11)
DNL Differential Non Linearity
GE Gain Error
Offset Error (V
Under Range Output Code 0 0
Over Range Output Code 4095 4095
REFERENCE AND ANALOG INPUT CHARACTERISTICS
V
CM
C
IN
V
REF
Common Mode Input Voltage 1.0
VINInput Capacitance (each pin to
GND)
Reference Voltage (Note 13) 1.0
Reference Input Resistance 100 MΩ (min)
= +1.0V, VCM= 1.0V, f
REF
= 66 MHz, tr=tf= 2 ns, CL= 15 pF/pin. Boldface limits apply for T
CLK
Typical
(Note 10)
Positive Error −0.15
Negative Error +0.4
+=VIN−) +0.2
IN
VIN+ 1.0 Vdc
+1V
P-P
(CLK LOW) 8 pF
(CLK HIGH) 7 pF
Limits
(Note 10)
±
1.2
±
0.4
+2.7 LSB (max)
−3 LSB (min)
+1 LSB (max)
−0.95 LSB (min)
±
3 %FS (max)
+4 %FS (max)
−5 %FS (min)
±
1.3 %FS (max)
0.5 V (min)
1.5 V (max)
0.8 V (min)
1.5 V (max)
≤ +85˚C
A
Units
(Limits)
D
J
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Converter Electrical Characteristics (Continued)
Unless otherwise specified, the following specifications apply for AGND = DGND = DR GND = 0V, VA=VD= +3.3V,
= +2.5V, PD = 0V, V
V
DR
ADC12L066
=T
MIN
to T
: all other limits TJ= 25˚C (Notes 7, 8, 9, 10)
MAX
Symbol Parameter Conditions
DYNAMIC CONVERTER CHARACTERISTICS
BW Full Power Bandwidth 0 dBFS Input, Output at −3 dB 450 MHz
SNR Signal-to-Noise Ratio
= +1.0V, VCM= 1.0V, f
REF
= 66 MHz, tr=tf= 2 ns, CL= 15 pF/pin. Boldface limits apply for T
CLK
= 10 MHz, VIN=
f
IN
−0.5 dBFS
= 25 MHz, VIN=
f
IN
−0.5 dBFS
= 150 MHz, V
f
IN
= −6 dBFS
f
= 240 Hz, VIN=
IN
−6 dBFS
Typical
(Note 10)
85˚C
25˚C 65 dB (min)
66
−40˚C 64.6 dB (min)
65 dB
85˚C
IN
25˚C 54 dB (min)
55
−40˚C 51 dB (min)
52 dB
Limits
(Note 10)
64.6 dB (min)
52 dB (min)
J
Units
(Limits)
SINAD Signal-to-Noise & Distortion
ENOB Effective Number of Bits
= 10 MHz, VIN=
f
IN
−0.5 dBFS
= 25 MHz, VIN=
f
IN
−0.5 dBFS
= 150 MHz, V
f
IN
= −6 dBFS
f
= 240 Hz, VIN=
IN
−6 dBFS
= 10 MHz, VIN=
f
IN
−0.5 dBFS
= 25 MHz, VIN=
f
IN
−0.5 dBFS
= 150 MHz, V
f
IN
= −6 dBFS
f
= 240 Hz, VIN=
IN
−6 dBFS
85˚C
25˚C 64.8 dB (min)
66
64.3 dB (min)
−40˚C 63 dB (min)
64 dB
IN
25˚C 53.9 dB (min)
55
85˚C
51.8 dB (min)
−40˚C 50 dB (min)
51 dB
85˚C
25˚C 10.5 Bits (min)
10.7
10.3
−40˚C 10.2
10.3 Bits
IN
25˚C 8.6 Bits (min)
8.8
85˚C
8.3
−40˚C 8.0
8.2 Bits
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Converter Electrical Characteristics (Continued)
Unless otherwise specified, the following specifications apply for AGND = DGND = DR GND = 0V, VA=VD= +3.3V,
= +2.5V, PD = 0V, V
V
DR
=T
MIN
to T
: all other limits TJ= 25˚C (Notes 7, 8, 9, 10)
MAX
Symbol Parameter Conditions
2nd
Harm
Second Harmonic Distortion
= +1.0V, VCM= 1.0V, f
REF
= 66 MHz, tr=tf= 2 ns, CL= 15 pF/pin. Boldface limits apply for T
CLK
= 10 MHz, VIN=
f
IN
−0.5 dBFS
= 25 MHz, VIN=
f
IN
−0.5 dBFS
= 150 MHz, V
f
IN
= −6 dBFS
f
= 240 Hz, VIN=
IN
−6 dBFS
Typical
(Note 10)
85˚C
25˚C −73 dB (max)
−80
−40˚C −68 dB (max)
−80 dB
85˚C
IN
25˚C −66 dB (max)
−81
−40˚C −56 dB (max)
−61 dB
Limits
(Note 10)
−73 dB(max)
−66 dB(max)
ADC12L066
J
Units
(Limits)
3rd
Harm
Third Harmonic Distortion
THD Total Harmonic Distortion
= 10 MHz, VIN=
f
IN
−0.5 dBFS
= 25 MHz, VIN=
f
IN
−0.5 dBFS
= 150 MHz, V
f
IN
= −6 dBFS
f
= 240 Hz, VIN=
IN
−6 dBFS
= 10 MHz, VIN=
f
IN
−0.5 dBFS
= 25 MHz, VIN=
f
IN
−0.5 dBFS
= 150 MHz, V
f
IN
= −6 dBFS
f
= 240 Hz, VIN=
IN
−6 dBFS
85˚C
25˚C −74 dB (max)
−84
−74 dB(max)
−40˚C −71 dB (max)
−79 dB
IN
25˚C −68 dB (max)
−78
85˚C
−68 dB(max)
−40˚C −64 dB (max)
−78 dB
85˚C
25˚C −72 dB (max)
−77
−72 dB(max)
−40˚C −66 dB (max)
−71 dB
IN
25˚C −63 dB (max)
−69
85˚C
−63 dB(max)
−40˚C −53 dB (max)
−57 dB
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Converter Electrical Characteristics (Continued)
Unless otherwise specified, the following specifications apply for AGND = DGND = DR GND = 0V, VA=VD= +3.3V,
= +2.5V, PD = 0V, V
V
DR
ADC12L066
=T
MIN
to T
: all other limits TJ= 25˚C (Notes 7, 8, 9, 10)
MAX
Symbol Parameter Conditions
SFDR Spurious Free Dynamic Range
= +1.0V, VCM= 1.0V, f
REF
= 66 MHz, tr=tf= 2 ns, CL= 15 pF/pin. Boldface limits apply for T
CLK
Typical
= 10 MHz, VIN=
f
IN
−0.5 dBFS
= 25 MHz, VIN=
f
IN
−0.5 dBFS
= 150 MHz, V
f
IN
= −6 dBFS
f
= 240 Hz, VIN=
IN
−6 dBFS
(Note 10)
85˚C
25˚C 73 dB (min)
80
−40˚C 68
73 dB
85˚C
IN
25˚C 66 dB (min)
74
−40˚C 56
61 dB
(Note 10)
DC and Logic Electrical Characteristics
Unless otherwise specified, the following specifications apply for AGND = DGND = DR GND = 0V, VA=VD= +3.3V,
= +2.5V, PD = 0V, V
V
DR
=T
to T
MIN
: all other limits TJ= 25˚C (Notes 7, 8, 9, 10)
MAX
Symbol Parameter Conditions
CLK, PD, OE DIGITAL INPUT CHARACTERISTICS
V
V
I
IN(1)
I
IN(0)
C
IN(1)
IN(0)
IN
Logical “1” Input Voltage VD= 3.3V 2.0 V (min)
Logical “0” Input Voltage VD= 3.3V 0.8 V (max)
Logical “1” Input Current V
Logical “0” Input Current V
Digital Input Capacitance 5 pF
D0–D11 DIGITAL OUTPUT CHARACTERISTICS
V
V
I
OZ
+I
−I
OUT(1)
OUT(0)
SC
SC
Logical “1” Output Voltage I
Logical “0” Output Voltage I
TRI-STATE Output Current
Output Short Circuit Source
Current
Output Short Circuit Sink Current V
POWER SUPPLY CHARACTERISTICS
I
A
I
D
I
DR
Analog Supply Current
Digital Supply Current
Digital Output Supply Current
Total Power Consumption
PSRR1 Power Supply Rejection
= +1.0V, VCM= 1.0V, f
REF
= 66 MHz, tr=tf= 2 ns, CL= 15 pF/pin. Boldface limits apply for T
CLK
Typical
(Note 10)
+
−
,V
IN
IN
OUT
OUT
V
OUT
V
OUT
V
OUT
OUT
PD Pin = DGND, V
PD Pin = V
PD Pin = DGND
PD Pin = V
PD Pin = DGND, (Note 14)
PD Pin = V
PD Pin = DGND, C
PD Pin = V
Rejection of Full-Scale Error with
V
A
= 3.3V 10 µA
IN
+
−
,V
= 0V −10 µA
IN
= −0.5 mA
= 1.6 mA 0.4 V (max)
= 3.3V 100 nA
= 0V −100 nA
= 0V −20 mA
= 2.5V 20 mA
= 1.0V
REF
DR
103
4
5.3
DR
DR
DR
= 3.0V vs. 3.6V
= 0 pF (Note 15)
L
2
<
1
0
357
50
58 dB
Limits
(Limits)
73
66
Limits
(Note 10)
V
−
DR
0.18
139 mA (max)
6.2 mA (max)
479 mW (max)
J
Units
J
Units
(Limits)
V (min)
mA
mA
mA
mA
mW
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AC Electrical Characteristics
Unless otherwise specified, the following specifications apply for AGND = DGND = DR GND = 0V, VA=VD= +3.3V,
= +2.5V, PD = 0V, V
V
DR
=TJ=T
MIN
to T
: all other limits TA=TJ= 25˚C (Notes 7, 8, 9, 10, 12)
MAX
Symbol Parameter Conditions
1 Maximum Clock Frequency 80 66 MHz (min)
f
CLK
f
2 Minimum Clock Frequency 1 MHz
CLK
DC Clock Duty Cycle
t
CH
t
CL
t
CONV
t
OD
t
AD
t
AJ
t
DIS
t
EN
t
PD
Note 1: Absolute Maximum Ratings indicate limits beyond which damage to the device may occur. Operating Ratings indicate conditions for which the device is
functional, but do not guarantee specific performance limits. For guaranteed specifications and test conditions, see the Electrical Characteristics. The guaranteed
specifications apply only for the test conditions listed. Some performance characteristics may degrade when the device is not operated under the listed test
conditions.
Note 2: All voltages are measured with respect to GND = AGND = DGND = 0V, unless otherwise specified.
Note 3: When the input voltage at any pin exceeds the power supplies (that is, V
25 mA. The 50 mA maximum package input current rating limits the number of pins that can safely exceed the power supplies with an input current of 25 mA to two.
Note 4: The absolute maximum junction temperature (T
junction-to-ambient thermal resistance (θ
LQFP, θ
this device under normal operation will typically be about 612 mW (357 typical power consumption + 255 mW output loading with 250 MHz input). The values for
maximum power dissipation listed above will be reached only when the device is operated in a severe fault condition (e.g. when input or output pins are driven
beyond the power supply voltages, or the power supply polarity is reversed). Obviously, such conditions should always be avoided.
Note 5: Human body model is 100 pF capacitor discharged through a 1.5 kΩ resistor. Machine model is 220 pF discharged through 0Ω.
Note 6: The 235˚C reflow temperature refers to infrared reflow. For Vapor Phase Reflow (VPR), the following Conditions apply: Maintain the temperature at the top
of the package body above 183˚C for a minimum 60 seconds. The temperature measured on the package body must not exceed 220˚C. Only one excursion above
183˚C is allowed per reflow cycle.
Note 7: The inputs are protected as shown below. Input voltages above V
However, errors in the A/D conversion can occur if the input goes above V
voltage must be ≤3.4V to ensure accurate conversions.
Clock High Time 6.5 ns (min)
Clock Low Time 6.5 ns (min)
Conversion Latency 6
Data Output Delay after Rising CLK
Edge
Aperture Delay 2 ns
Aperture Jitter 1.2 ps rms
Data outputs into TRI-STATE Mode 10 ns
Data Outputs Active after TRI-STATE 10 ns
Power Down Mode Exit Cycle 0.1 µF on pins 30, 31, 32 300 ns
is 79˚C/W, so PDMAX = 1,582 mW at 25˚C and 823 mW at the maximum operating ambient temperature of 85˚C. Note that the power consumption of
JA
= +1.0V, VCM= 1.0V, f
REF
= 66 MHz, tr=tf= 2 ns, CL= 15 pF/pin. Boldface limits apply for T
CLK
Typical
(Note 10)
Limits
(Note 10)
40
60
= 2.5V 7.5 11 ns (max)
V
DR
V
= 3.3V 6.7 10.5 ns (max)
DR
<
AGND, or V
IN
max) for this device is 150˚C. The maximum allowable power dissipation is dictated by TJmax, the
), and the ambient temperature, (TA), and can be calculated using the formula PDMAX-(TJmax - TA)/θJA. In the 32-pin
JA
J
or below GND will not damage this device, provided current is limited per (Note 3).
A
or below GND by more than 100 mV. As an example, if VAis 3.3V, the full-scale input
A
>
VA,VDor VDR), the current at that pin should be limited to
IN
Units
(Limits)
% (min)
% (max)
Clock
Cycles
ADC12L066
A
20032807
Note 8: To guarantee accuracy, it is required that |VA–VD| ≤ 100 mV and separate bypass capacitors are used at each power supply pin.
Note 9: With the test condition for V
Note 10: Typical figures are at T
Level).
Note 11: Integral Non Linearity is defined as the deviation of the analog value, expressed in LSBs, from the straight line that passes through positive and negative
full-scale.
Note 12: Timing specifications are tested at TTL logic levels, V
Note 13: Optimum dynamic performance will be obtained by keeping the reference input in the 0.8V to 1.5V range. The LM4051CIM3-ADJ or the LM4051CIM3-1.2
bandgap voltage reference is recommended for this application.
Note 14: I
V
DR
voltage, C
Note 15: Power consumption excludes output driver power. See (Note 14).
is the current consumed by the switching of the output drivers and is primarily determined by load capacitance on the output pins, the supply voltage,
DR
, and the rate at which the outputs are switching (which is signal dependent). IDR=VDR(C0xf0+C1xf1+....C11xf11) where VDRis the output driver power supply
is total capacitance on the output pin, and fnis the average frequency at which that pin is toggling.
n
= +1.0V (2 V
REF
= 25˚C, and represent most likely parametric norms. Test limits are guaranteed to National’sAOQL (Average Outgoing Quality
A=TJ
differential input), the 12-bit LSB is 488 µV.
P-P
= 0.4V for a falling edge and VIH= 2.4V for a rising edge.
IL
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