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ADC12L038
User Manual
40 pgs701.49 Kb0

Rainbow Electronics ADC12L038 User Manual

ADC12L030/ADC12L032/ADC12L034/ADC12L038
3.3V Self-Calibrating 12-Bit Plus Sign Serial I/O A/D Converters with MUX and Sample/Hold
March 1995
ADC12L030/ADC12L032/ADC12L034/ADC12L038
3.3V Self-Calibrating 12-Bit Plus Sign Serial I/O A/D Converters with MUX and Sample/Hold
General Description
g
(/2 LSB each.
The analog inputs can be configured to operate in various combinations of single-ended, differential, or pseudo-differ­ential modes. A fully differential unipolar analog input range
a
(0V to
3.3V) can be accommodated with a singlea3.3V supply. In the differential modes, valid outputs are obtained even when the negative inputs are greater than the positive because of the 12-bit plus sign two’s compliment output data format.
The serial I/O is configured to comply with NSC’s MICRO-
TM
WIRE
and Motorola’s SPI standards. For complementary voltage references see the LM4040, LM4041 or LM9140 data sheets.
Applications
Y
Portable Medical instruments
Y
Portable computing
Y
Portable Test equipment
ADC12L038 Simplified Block Diagram
Features
Y
0V to 3.3V analog input range with single 3.3V power supply
Y
Serial I/O (MICROWIRE and SPI Compatible)
Y
2, 4, or 8 channel differential or single-ended multiplexer
Y
Analog input sample/hold function
Y
Power down mode
Y
Variable resolution and conversion rate
Y
Programmable acquisition time
Y
Variable digital output word length and format
Y
No zero or full scale adjustment required
Y
Fully tested and guaranteed with a 2.5V reference
Y
No Missing Codes over temperature
Key Specifications
Y
Resolution 12-bit plus sign
Y
12-bit plus sign conversion time 8.8 ms (min)
Y
12-bit plus sign sampling rate 73 kHz (max)
Y
Integral linearity error
Y
Single supply 3.3Vg10%
Y
Power dissipation 15 mW (max) Ð Power down 40 mW (typ)
g
1 LSB (max)
TRI-STATEÉis a registered trademark of National Semiconductor Corporation.
TM
COPS
microcontrollers, HPCTMand MICROWIRETMare trademarks of National Semiconductor Corporation.
TM
Microsoft
is a trademark of Microsoft Corporation.
C
1995 National Semiconductor Corporation RRD-B30M75/Printed in U. S. A.
TL/H/11830
TL/H/11830– 1
Connection Diagrams
16-Pin Dual-In-Line and
Wide Body SO Packages
Top View
24-Pin Dual-In-Line and
Wide Body SO Packages
TL/H/11830– 2
20-Pin Dual-In-Line and
Wide Body SO Packages
Top View
28-Pin Dual-In-Line and
Wide Body SO Packages
TL/H/11830– 3
Top View
Ordering Information
TL/H/11830– 4
Industrial Temperature Range NS Package
b
40§CsT
s
a
85§C Number
A
ADC12L030CIN N16E
ADC12L030CIWM M16B
ADC12L032CIN N20A
ADC12L032CIWM M20B
ADC12L034CIN N24C
ADC12L034CIWM M24B
ADC12L038CIN N28B
ADC12L038CIWM M28B
2
Top View
TL/H/11830– 5
Absolute Maximum Ratings (Notes1&2)
If Military/Aerospace specified devices are required, please contact the National Semiconductor Sales Office/Distributors for availability and specifications.
Positive Supply Voltage
a
a
e
(V
V
A
Voltage at Inputs and Outputs
except CH0–CH7 and COM
Voltage at Analog Inputs
CH0–CH7 and COM GND
a
b
V
V
l
A
D
Input Current at Any Pin (Note 3)
Package Input Current (Note 3)
Package Dissipation at
e
T
25§C (Note 4) 500 mW
A
ESD Susceptability (Note 5)
Human Body Model 1500V
Soldering Information
N Packages (10 seconds) 260
SO Package (Note 6):
Vapor Phase (60 seconds) 215 Infrared (15 seconds) 220
Storage Temperature
a
e
V
) 6.5V
D
0.3V to V
b
5V to V
a
a
300 mV
g
g
120 mA
a
0.3V
a
30 mA
5V
b
a
l
§
§
§
b
65§Ctoa150§C
Operating Ratings (Notes1&2)
Operating Temperature Range T
ADC12L030CIN, ADC12L030CIWM, ADC12L032CIN, ADC12L032CIWM, ADC12L034CIN, ADC12L034CIWM, ADC12L038CIN, ADC12L038CIWM
Supply Voltage (V
a
b
V
l
A
a
V
REF
b
V
REF
V
REF(VREF
V
Common Mode Voltage Range
REF
(V
REF
A/DIN1, A/DIN2, MUXOUT1
and MUXOUT2 Voltage Range 0V to V
A/D IN Common Mode Voltage Range
C
a
(V
IN
C C
a
e
a
V
D
a
a
a
V
l
b
b
V
REF
b
V
)
REF
2
b
a
V
)
IN
2
s
s
T
MIN
b
a
e
A
40§CsT
a
V
D
a
)
T
A
s
a
A
3.0V toa5.5V
s
100 mV
0V to V
0V to V
REF
) 1VtoV
a
0.1 V
to 0.6 V
A
0V to V
MAX
85§C
A
A
A
A
A
a
a
a
a
a
a
Converter Electrical Characteristics
a
a
The following specifications apply for V sign conversion mode, f with fixed 1.250V common-mode voltage, and 10(t
e
T
e
T
A
T
J
MIN
to T
CK
MAX
e
f
SK
; all other limits T
e
5 MHz, R
e
V
A
S
A
Symbol Parameter Conditions
STATIC CONVERTER CHARACTERISTICS
Resolution with No Missing Codes 12asign Bits (min)
a
ILE Positive Integral Linearity Error After Auto-Cal (Notes 12, 18)
b
ILE Negative Integral Linearity Error After Auto-Cal (Notes 12, 18)
DNL Differential Non-Linearity After Auto-Cal
Positive Full-Scale Error After Auto-Cal (Notes 12, 18)
Negative Full-Scale Error After Auto-Cal (Notes 12, 18)
Offset Error After Auto-Cal (Notes 5, 18)
DC Common Mode Error After Auto-Cal (Note 15)
TUE Total Unadjusted Error After Auto-Cal
Resolution with No Missing Codes 8-bitasign mode 8asign Bits (min)
a
INL Positive Integral Linearity Error 8-bitasign mode (Note 12)
b
INL Negative Integral Linearity Error 8-bitasign mode (Note 12)
DNL Differential Non-Linearity 8-bitasign mode
Positive Full-Scale Error 8-bitasign mode (Note 12)
a
e
ea
V
e
25X, source impedance for V
) acquisition time unless otherwise specified. Boldface limits apply for
CK
e
e
T
J
(a)eVIN(b)e1.250V
V
IN
3.3 VDC,V
D
25§C. (Notes 7, 8 and 9)
(Notes 12, 13 and 14)
REF
a
REF
ea
b
2.500 VDC,V
a
and V
REF
b
Typical
(Note 10)
g
1/2
g
1/2
g
1/2
g
1/2
g
1/2
g
2
g
1 LSB
e
REF
s
25X, fully-differential input
Limits
(Note 11)
g
1 LSB (max)
g
1 LSB (max)
g
1 LSB (max)
g
2 LSB (max)
g
2 LSB (max)
g
2 LSB (max)
g
3.5 LSB (max)
g
1/2 LSB (max)
g
1/2 LSB (max)
g
3/4 LSB (max)
g
1/2 LSB (max)
0VDC, 12-bit
Units
(Limits)
a
3
Converter Electrical Characteristics (Continued)
a
a
e
The following specifications apply for V sign conversion mode, f with fixed 1.250V common-mode voltage, and 10(t
e
T
e
T
A
T
J
MIN
to T
e
f
CK
SK
; all other limits T
MAX
e
5 MHz, R
V
A
S
A
Symbol Parameter Conditions
STATIC CONVERTER CHARACTERISTICS (Continued)
Negative Full-Scale Error 8-bitasign mode (Note 12)
Offset Error 8-bitasign mode,
after Auto-Zero (Note 13) V
TUE Total Unadjusted Error 8-bitasign mode
after Auto-Zero (Notes 12, 13 and 14)
Multiplexer Channel to Channel Matching
Power Supply Sensitivity V
Offset Error
a
Full-Scale Error
b
Full-Scale Error
a
Integral Linearity Error
b
Integral Linearity Error
Output Data from (Note 20) ‘‘12-Bit Conversion of Offset’’ (see Table V)
Output Data from (Note 20) ‘‘12-Bit Conversion of Full-Scale’’ (see Table V)
UNIPOLAR DYNAMIC CONVERTER CHARACTERISTICS
S/(NaD) Signal-to-Noise Plus f
Distortion Ratio f
f
b
3 dB Full Power Bandwidth V
DIFFERENTIAL DYNAMIC CONVERTER CHARACTERISTICS
S/(NaD) Signal-to-Noise Plus f
Distortion Ratio f
f
b
3 dB Full Power Bandwidth V
a
e
ea
V
e
25X, source impedance for V
) acquisition time unless otherwise specified. Boldface limits apply for
CK
e
e
T
J
(a)eVIN(b)
IN
a
ea
e
1 kHz, V
IN
e
20 kHz, V
IN
e
40 kHz, V
IN
e
2.5 VPP, where S/(NaD) drops 3 dB 31 kHz
IN
e
1 kHz, V
IN
e
20 kHz, V
IN
e
40 kHz, V
IN
e
g
IN
3.3 VDC,V
D
25§C. (Notes 7, 8 and 9)
ea
3.3Vg10%
e
2.5 V
IN
e
IN
e
IN
e
g
IN
e
IN
e
IN
2.5V, where S/(NaD) drops 3 dB 40 kHz
REF
a
REF
ea
2.500 VDC,V
a
and V
REF
Typical
(Note 10)
b
e
0VDC, 12-bit
REF
b
s
25X, fully-differential input
Limits
(Note 11)
g
1/2 LSB (max)
g
1/2 LSB (max)
(Limits)
1.250V
g
3/4 LSB (max)
g
0.05 LSB
g
0.5
g
0.5
g
0.5
g
0.5 LSB
g
0.5 LSB
g
1 LSB (max)
g
1.5 LSB (max)
g
1.5 LSB (max)
a
10 LSB (max)
b
10 LSB (min)
4095 LSB (max) 4093 LSB (min)
2.5 V
2.5 V
PP
PP
PP
69.4 dB
68.3 dB
65.7 dB
2.5V 77.0 dB
g
2.5V 73.9 dB
g
2.5V 67.0 dB
a
Units
4
Electrical Characteristics
a
a
The following specifications apply for V sign conversion mode, f with fixed 1.250V common-mode voltage, and 10(t
e
T
e
T
A
T
J
MIN
to T
CK
MAX
e
f
SK
; all other limits T
e
5 MHz, R
e
V
A
S
A
Symbol Parameter Conditions
REFERENCE INPUT, ANALOG INPUTS AND MULTIPLEXER CHARACTERISTICS
C
REF
C
A/D
Reference Input Capacitance 85 pF
A/DIN1 and A/DIN2 Analog Input Capacitance
A/DIN1 and A/DIN2 Analog Input V Leakage Current V
CH0–CH7 and COM Input Voltage GNDb0.05 V (min)
C
CH
C
MUXOUT
CH0–CH7 and COM Input Capacitance 10 pF
MUX Output Capacitance 20 pF
Off Channel Leakage (Note 16) On Channele3.3V and CH0–CH7 and COM Pins Off Channel
On Channel Leakage (Note 16) On Channele3.3V and CH0–CH7 and COM Pins Off Channel
MUXOUT1 and MUXOUT2 V Leakage Current V
R
ON
MUX On Resistance V
RONMatching Channel to Channel V
Channel to Channel Crosstalk V
MUX Bandwidth 90 kHz
a
e
ea
V
D
e
25X, source impedance for V
) acquisition time unless otherwise specified. Boldface limits apply for
CK
e
e
T
J
3.3 VDC,V
REF
25§C. (Notes 7, 8 and 9)
ea
3.3V or
IN
e
0V
IN
e
0V
On Channele0V and Off Channele3.3V
e
0V
On Channele0V and
e
e
3.3V or
e
0V
1.65V and
e
1.55V
1.65V and
e
1.55V
3.3 VPP,f
3.3V
IN
e
40 kHz
Off Channel
MUXOUT
MUXOUT
e
IN
V
MUXOUT
e
IN
V
MUXOUT
e
IN
a
REF
ea
a
and V
2.500 VDC,V
REF
b
e
REF
b
s
25X, fully-differential input
Typical Limits Units
(Note 10) (Note 11) (Limits)
75 pF
g
0.1
b
0.01
g
1.0 mA (max)
a
a
V
A
b
0.3 mA (min)
0.01 0.3 mA (max)
0.01 0.3 mA (max)
b
0.01
b
0.3 mA (min)
0.01 0.3 mA (max)
1300 1900 X (max)
5%
b
72 dB
0VDC, 12-bit
a
0.05 V (max)
5
DC and Logic Electrical Characteristics
a
a
The following specifications apply for V sign conversion mode, f with fixed 1.250V common-mode voltage, and 10(t
e
T
e
T
A
T
J
MIN
to T
e
f
CK
SK
; all other limits T
MAX
e
5 MHz, R
e
V
A
S
A
Symbol Parameter Conditions
CCLK, CS, CONV, DI, PD AND SCLK INPUT CHARACTERISTICS
V
V
I
IN(1)
I
IN(0)
IN(1)
IN(0)
Logical ‘‘1’’ Input Voltage V
Logical ‘‘0’’ Input Voltage V
Logical ‘‘1’’ Input Current V
Logical ‘‘0’’ Input Current V
DO, EOC AND DOR DIGITAL OUTPUT CHARACTERISTICS
V
OUT(1)
V
OUT(0)
I
OUT
a
b
Logical ‘‘1’’ Output Voltage V
Logical ‘‘0’’ Output Voltage V
TRI-STATE Output Current V
I
Output Short Circuit Source Current V
SC
I
Output Short Circuit Sink Current V
SC
POWER SUPPLY CHARACTERISTICS
a
I
D
I
A
I
REF
Digital Supply Current Awake 1.1 1.5 mA (max)
a
Positive Analog Supply Current Awake 2.2 3.0 mA (max)
Reference Input Current Awake 70 mA
a
e
ea
V
e
25X, source impedance for V
) acquisition time unless otherwise specified. Boldface limits apply for
CK
e
e
T
J
a
e
a
e
e
IN
e
IN
a
e
a
e
V
a
e
OUT
V
OUT
OUT
OUT
e
CS
e
CS
e
CS
e
CS
e
CS
3.3 VDC,V
D
25§C. (Notes 7, 8 and 9)
3.6V 2.0 V (min)
3.0V 0.8 V (max)
3.3V 0.005 1.0 mA (max)
0V
3.0V, I
3.0V, I
3.0V, I
e e
e
e
eb
OUT
eb
OUT
e
OUT
0V
3.3V 0.1 3.0 mA (max)
0V 14 6.5 mA (min)
a
V
D
HIGH, Powered Down, CCLK on 600 mA HIGH, Powered Down, CCLK off 12 mA
HIGH, Powered Down, CCLK on 10 mA HIGH, Powered Down, CCLK off 0.1 mA
HIGH, Powered Down 0.1 mA
REF
a
REF
ea
2.500 VDC,V
a
and V
REF
b
e
0VDC, 12-bit
REF
b
s
25X, fully-differential input
Typical Limits Units
(Note 10) (Note 11) (Limits)
b
0.005
b
1.0 mA (min)
360 mA 2.4 V (min)
10 mA 2.9 V (min)
1.6 mA 0.4 V (max)
b
0.1
b
3.0 mA (max)
16 8.0 mA (min)
a
6
AC Electrical Characteristics
a
a
e
e
5 MHz, R
a
ea
V
3.3 VDC,V
D
e
25X, source impedance for V
S
) acquisition time unless otherwise specified. Boldface
CK
e
e
T
A
25§C. (Note 17)
J
8-BitaSign or 8-Bit 21(tCK) 21(tCK) (max)
10 Cycles Programmed 10(tCK) 10(tCK) (min)
18 Cycles Programmed 18(tCK) 18(tCK) (min)
34 Cycles Programmed 34(tCK) 34(tCK) (min)
to T
CK
MAX
e
V
A
e
f
SK
; all other limits T
The following specifications apply for V sign conversion mode, t differential input with fixed 1.250V common-mode voltage, and 10(t
limits apply for T
e
e
t
3 ns, f
r
f
e
e
T
A
T
J
MIN
Symbol Parameter Conditions
f
CK
f
SK
Conversion Clock (CCLK) Frequency 10 5 MHz (max)
Serial Data Clock SCLK Frequency 10 5 MHz (max)
Conversion Clock Duty Cycle 40 % (min)
Serial Data Clock Duty Cycle 40 % (min)
t
C
t
A
t
CAL
t
AZ
t
SYNC
t
DOR
Conversion Time 12-BitaSign or 12-Bit 44(tCK) 44(tCK) (max)
Acquisition Time 6 Cycles Programmed 6(tCK) 6(tCK) (min) (Note 19) 7(t
Self-Calibration Time 4944(tCK) 4944(tCK) (max)
Auto-Zero Time 76(tCK) 76(tCK) (max)
Self-Calibration or Auto-Zero 2(tCK) 2(tCK) (min) Synchronization Time from DOR
DOR High Time when CS is Low 9(tSK) 9(tSK) (max) Continuously for Read Data and Software Power Up/Down
t
CONV
CONV Valid Data Time 8(tSK) 8(tSK) (max)
REF
a
ea
2.500 VDC,V
REF
a
REF
and V
b
e
REF
Typical Limits Units
(Note 10) (Note 11) (Limits)
1 MHz (min)
0 Hz (min)
60 % (max)
60 % (max)
8.8 ms (max)
4.2 ms (max)
) (max)
CK
1.2 ms (min)
1.4 ms (max)
11(t
CK
2.0 ms (min)
2.2 ms (max)
19(t
CK
3.6 ms (min)
3.8 ms (max)
35(t
CK
6.8 ms (min)
7.0 ms (max)
988.8 ms (max)
15.2 ms (max)
3(t
) (max)
CK
0.40 ms (min)
0.60 ms (max)
1.8 ms (max)
1.6 ms (max)
0VDC, 12-bit
b
s
25X, fully-
) (max)
) (max)
) (max)
a
7
AC Electrical Characteristics (Continued)
a
a
e
The following specifications apply for V sign conversion mode, t differential input with fixed 1.250V common-mode voltage, and 10(t
limits apply for T
e
e
t
3 ns, f
r
f
e
e
T
A
T
J
MIN
CK
to T
e
MAX
V
A
f
SK
Symbol Parameter Conditions
t
t
HPU
SPU
Hardware Power-Up Time, Time from PD Falling Edge to EOC Rising Edge
Software Power-Up Time, Time from Serial Data Clock Falling Edge to 500 700 ms (max) EOC Rising Edge
t
ACC
t
SET-UP
t
DELAY
t1H,t
t
HDI
t
SDI
t
HDO
t
DDO
t
RDO
t
FDO
t
CD
t
SD
C
IN
C
OUT
Access Time Delay from CS
Falling Edge to DO Data Valid
Set-Up Time of CS Falling Edge to Serial Data Clock Rising Edge
Delay from SCLK Falling Edge to CS
Delay from CS Rising Edge to R
0H
DO TRI-STATE
Falling Edge
É
DI Hold Time from Serial Data Clock Rising Edge
DI Set-Up Time from Serial Data Clock Rising Edge
DO Hold Time from Serial Data R Clock Falling Edge 5 ns (min)
Delay from Serial Data Clock Falling Edge to DO Data Valid
DO Rise Time, TRI-STATE to High R DO Rise Time, Low to High 10 40 ns (max)
DO Fall Time, TRI-STATE to Low R DO Fall Time, High to Low 15 40 ns (max)
Delay from CS Falling Edge to DOR
Falling Edge
Delay from Serial Data Clock Falling Edge to DOR
Rising Edge
Capacitance of Logic Inputs 10 pF
Capacitance of Logic Outputs 20 pF
a
e
ea
V
D
e
5 MHz, R
S
; all other limits T
e
L
e
L
e
L
e
L
3.3 VDC,V
e
25X, source impedance for V
) acquisition time unless otherwise specified. Boldface
CK
e
T
A
e
3k, C
L
e
3k, C
L
e
3k, C
L
e
3k, C
L
a
REF
e
25§C. (Note 17)
J
ea
2.500 VDC,V
REF
a
REF
and V
b
e
REF
0VDC, 12-bit
b
s
25X, fully-
Typical Limits Units
(Note 10) (Note 11) (Limits)
250 700 ms (max)
25 60 ns (max)
50 ns (min)
0 5 ns (min)
100 pF
70 100 ns (max)
5 15 ns (min)
5 10 ns (min)
100 pF
35
65 ns (max)
50 90 ns (max)
100 pF 10 40 ns (max)
100 pF 15 40 ns (max)
50 80 ns (max)
45 80 ns (max)
a
8
Electrical Characteristics (Continued)
Note 1: Absolute Maximum Ratings indicate limits beyond which damage to the device may occur. Operating Ratings indicate conditions for which the device is
functional, but do not guarantee specific performance limits. For guaranteed specifications and test conditions, see the Electrical Characteristics. The guaranteed specifications apply only for the test conditions listed. Some performance characteristics may degrade when the device is not operated under the listed test conditions.
Note 2: All voltages are measured with respect to GND, unless otherwise specified.
Note 3: When the input voltage (V
The 120 mA maximum package input current rating limits the number of pins that can safely exceed the power supplies with an input current of 20 mA to four.
Note 4: The maximum power dissipation must be derated at elevated temperatures and is dictated by T allowable power dissipation at any temperature is P
maxe150§C. The typical thermal resistance (HJA) of these parts when board mounted follow:
device, T
J
) at any pin exceeds the power supplies (V
IN
e
(TJmaxbTA)/iJAor the number given in the Absolute Maximum Ratings, whichever is lower. For this
D
IN
k
GND or V
Part Number Resistance
ADC12L030CIN 53§C/W
ADC12L030CIWM 70§C/W
ADC12L032CIN 46§C/W
ADC12L032CIWM 64§C/W
ADC12L034CIN 42§C/W
ADC12L034CIWM 57§C/W
ADC12L038CIN 40§C/W
ADC12L038CIWM 50§C/W
Note 5: The human body model is a 100 pF capacitor discharged through a 1.5 kX resistor into each pin.
Note 6: See AN450 ‘‘Surface Mounting Methods and Their Effect on Product Reliability’’ or the section titled ‘‘Surface Mount’’ found in any post 1986 National
Semiconductor Linear Data Book for other methods of soldering surface mount devices.
Note 7: Two on-chip diodes are tied to each analog input through a series resistor as shown below. Input voltage magnitude up to 5V above V will not damage this device. However, errors in the A/D conversion can occur (if these diodes are forward biased by more than 50 mV) if the input voltage magnitude of selected or unselected analog input go above V
s
3.05 VDCto ensure accurate conversions.
must be
a
or below GND by more than 50 mV. As an example, if V
A
a
l
IN
a
V
or V
), the current at that pin should be limited to 20 mA.
A
D
max, iJAand the ambient temperature, TA. The maximum
J
Thermal
i
JA
a
is 3.0 VDC, full-scale input voltage
A
a
or 5V below GND
A
a
Note 8: To guarantee accuracy, it is required that the V pin.
Note 9: With the test condition for V
e
Note 10: Typicals are at T
Note 11: Tested limits are guaranteed to National’s AOQL (Average Outgoing Quality Level).
Note 12: Positive integral linearity error is defined as the deviation of the analog value, expressed in LSBs, from the straight line that passes through positive full-
scale and zero. For negative integral linearity error, the straight line passes through negative full-scale and zero (see
Note 13: Zero error is a measure of the deviation from the mid-scale voltage (a code of zero), expressed in LSB. It is the worst-case value of the code transitions between 1 to 0 and 0 to
J
a
1 (see
T
A
e
Figure 2
a
b
REF(VREF
25§C and represent most likely parametric norm.
V
).
a
and V
A
REF
be connected together to the same power supply with separate bypass capacitors at each V
D
b
) given asa2.500V the 12-bit LSB is 610 mV and the 8-bit LSB is 9.8 mV.
TL/H/11830– 6
Figures 1b
and1c).
Note 14: Total unadjusted error includes offset, full-scale, linearity and multiplexer errors.
Note 15: The DC common-mode error is measured in the differential multiplexer mode with the assigned positive and negative input channels shorted together.
Note 16: Channel leakage current is measured after the channel selection.
Note 17: Timing specifications are tested at the TTL logic levels, V
to 1.4V.
Note 18: The ADC12L030 family’s self-calibration technique ensures linearity and offset errors as specified, but noise inherent in the self-calibration process will result in a maximum repeatability uncertainty of 0.2 LSB.
Note 19: If SCLK and CCLK are driven from the same clock source, then t
Note 20: The ‘‘12-Bit Conversion of Offset’’ and ‘‘12-Bit Conversion of Full-Scale’’ modes are intended to test the functionality of the device. Therefore, the output
data from these modes are not an indication of the accuracy of a conversion result.
e
0.4V for a falling edge and V
IL
is 6, 10, 18 or 34 clock periods minimum and maximum.
A
e
2.4V for a rising edge. TRI-STATE output voltage is forced
IH
9
a
Electrical Characteristics (Continued)
FIGURE 1a. Transfer Characteristic
FIGURE 1b. Simplified Error Curve vs Output Code without Auto-Calibration or Auto-Zero Cycles
TL/H/11830– 7
TL/H/11830– 8
10
Electrical Characteristics (Continued)
FIGURE 1c. Simplified Error Curve vs Output Code after Auto-Calibration Cycle
TL/H/11830– 10
FIGURE 2. Offset or Zero Error Voltage
TL/H/11830– 9
11
Typical Performance Characteristics
The following curves apply for 12-bitasign mode after auto-calibration unless otherwise specified. The performance for 8-bit sign mode is equal to or better than shown. (Note 9)
a
Linearity Error Change vs Temperature
Zero Error Change vs Temperature
Full-Scale Error Change vs Temperature
Zero Error Change vs Supply Voltage
Digital Supply Current vs Temperature
Full-Scale Error Change vs Supply Voltage
Analog Supply Current vs Temperature
TL/H/11830– 11
12
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