ADC12DL066
Dual 12-Bit, 66 MSPS, 450 MHz Input Bandwidth A/D
Converter w/Internal Reference
March 2004
ADC12DL066 Dual 12-Bit, 66 MSPS, 450 MHz Input Bandwidth A/D Converter w/Internal
Reference
General Description
The ADC12DL066 is a dual, low power monolithic CMOS
analog-to-digital converter capable of converting analog input signals into 12-bit digital words at 66 Megasamples per
second (MSPS), minimum. This converter uses a differential,
pipeline architecture with digital error correction and an onchip sample-and-hold circuit to minimize die size and power
consumption while providing excellent dynamic performance
and a 450 MHz Full Power Bandwidth. Operating on a single
3.3V power supply, the ADC12DL066 achieves 10.7 effective bits and consumes just 686 mW at 66 MSPS, including
the reference current. The Power Down feature reduces
power consumption to 75 mW.
The differential inputs provide a full scale differential input
swing equal to 2 times V
ended input. Full use of the differential input is recommended for optimum performance. The digital outputs from
the two ADCs are available on separate 12-bit buses with an
output data format choice of offset binary or two’s complement.
To ease interfacing to lower voltage systems, the digital
output driver power pins of the ADC12DL066 can be connected to a separate supply voltage in the range of 2.4V to
the digital supply voltage.
This device is available in the 64-lead TQFP package and
will operate over the industrial temperature range of −40˚C to
+85˚C. An evaluation board is available to ease the evaluation process.
with the possibility of a single-
REF
Features
n Single +3.3V supply operation
n Internal sample-and-hold
n Outputs 2.4V to 3.3V compatible
n Pin compatible with ADC12D040
n Power down mode
n On-chip reference
Key Specifications
n Resolution 12 Bits
n DNL
n SNR (f
n SFDR (f
n Data Latency 6 Clock Cycles
n Power Consumption
— Operating 686 mW (typ)
— Power Down Mode 75 mW (typ)
= 10 MHz) 66 dB (typ)
IN
= 10 MHz) 81 dB (typ)
IN
±
0.5 LSB (typ)
Applications
n Ultrasound and Imaging
n Instrumentation
n Communications Receivers
n Sonar/Radar
n xDSL
n Cable Modems
n DSP Front Ends
Connection Diagram
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TRI-STATE®is a registered trademark of National Semiconductor Corporation.
© 2004 National Semiconductor Corporation DS200552 www.national.com
Ordering Information
ADC12DL066
Block Diagram
Industrial (−40˚C ≤ TA≤ +85˚C) Package
ADC12DL066CIVS 64 Pin TQFP
ADC12DL066EVAL Evaluation Board
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20055202
Pin Descriptions and Equivalent Circuits
Pin No. Symbol Equivalent Circuit Description
ANALOG I/O
15
2
16
1
7V
V
A+
IN
B+
V
IN
A−
V
IN
B−
V
IN
REF
11 INT/EXT REF
Differential analog input pins. With a 1.0V reference voltage
the differential full-scale input signal level is 2.0 V
each input pin voltage centered on a common mode voltage,
. The negative input pins may be connected to VCMfor
V
CM
single-ended operation, but a differential input signal is
required for best performance.
Reference input. This pin should be bypassed to AGND with
a 0.1 µF capacitor when an external reference is used. V
is 1.0V nominal and should be between 0.8V to 1.5V.
Reference source select pin. With a logic low at this pin the
internal 1.0V reference is selected and the V
not be driven. With a logic high on this pin an external
reference voltage should be applied to V
REF
input pin 7.
REF
with
P-P
pin need
ADC12DL066
REF
13
5
14
4
12
6
DIGITAL I/O
60 CLK
22
41
59 PD
21 OF
V
RP
V
RP
VRMA
V
RM
V
RN
V
RN
OEA
OEB
A
B
These pins are high impedance reference bypass pins.
B
Bypass per Section 1.2. DO NOT LOAD these pins.
A
B
Digital clock input. The range of frequencies for this input is
as specified in the electrical tables with guaranteed
performance at 66 MHz. The input is sampled on the rising
edge of this input.
OEA and OEB are the output enable pins that, when low,
holds their respective data output pins in the active state.
When either of these pins is high, the corresponding outputs
are in a high impedance state.
PD is the Power Down input pin. When high, this input puts
the converter into the power down mode. When this pin is
low, the converter is in the active mode.
Output Format pin. A logic low on this pin causes output
data to be in offset binary format. A logic high on this pin
causes the output data to be in 2’s complement format.
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Pin Descriptions and Equivalent Circuits (Continued)
Pin No. Symbol Equivalent Circuit Description
ADC12DL066
24–29
34–39
42–47
52–57
ANALOG POWER
9, 18, 19,
62, 63
3, 8, 10, 17,
20, 61, 64
DIGITAL POWER
33, 48 V
32, 49 DGND The ground return for the digital supply.
30, 51 V
23, 31, 40,
50, 58
DA0–DA11
Digital data output pins that make up the 12-bit conversion
results of their respective converters. DA0 and DB0 are the
LSBs, while DA11 and DB11 are the MSBs of the output
word. Output levels are TTL/CMOS compatible.
DB0–DB11
Positive analog supply pins. These pins should be connected
V
A
to a quiet +3.3V source and bypassed to AGND with 0.1 µF
capacitors located within 1 cm of these power pins, and with
a 10 µF capacitor.
AGND The ground return for the analog supply.
Positive digital supply pin. This pin should be connected to
D
the same quiet +3.3V source as is V
DGND with a 0.1 µF capacitor located within 1 cm of the
power pin and with a 10 µF capacitor.
Positive digital supply pin for the ADC12DL066’s output
drivers. This pin should be connected to a voltage source of
+2.4V to V
DR
capacitor. If the supply for this pin is different from the
supply used for V
a 10 µF capacitor. V
. All bypass capacitors should be located within 1 cm of
V
D
and be bypassed to DR GND with a 0.1 µF
D
and VD, it should also be bypassed with
A
DR
the supply pin.
The ground return for the digital supply for the
ADC12DL066’s output drivers. These pins should be
DR GND
connected to the system digital ground, but not be
connected in close proximity to the ADC12DL066’s DGND or
AGND pins. See Section 5 (Layout and Grounding) for more
details.
and be bypassed to
A
should never exceed the voltage on
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ADC12DL066
Absolute Maximum Ratings (Notes 1,
2)
If Military/Aerospace specified devices are required,
please contact the National Semiconductor Sales Office/
Distributors for availability and specifications.
or V
A
+0.3V)
±
25 mA
±
50 mA
4.2V
V
A,VD,VDR
|V
| ≤ 100 mV
A–VD
Voltage on Any Input or Output Pin −0.3V to (V
Input Current at Any Pin (Note 3)
Package Input Current (Note 3)
Package Dissipation at T
= 25˚C See (Note 4)
A
D
Operating Ratings (Notes 1, 2)
Operating Temperature −40˚C ≤ T
Supply Voltage (V
Output Driver Supply (V
V
Input 0.8V to 1.5V
REF
CLK, PD, OE
) +3.0V to +3.6V
A,VD
) +2.4V to V
DR
−0.05V to (VD+ 0.05V)
Analog Input Pins 0V to (V
V
CM
|AGND–DGND| ≤100mV
≤ +85˚C
A
A
0.5V to 1.5V
ESD Susceptibility
Human Body Model (Note 5) 2500V
Machine Model (Note 5) 250V
Soldering Temperature,
Infrared, 10 sec. (Note 6) 235˚C
Storage Temperature −65˚C to +150˚C
Converter Electrical Characteristics
Unless otherwise specified, the following specifications apply for AGND = DGND = DR GND = 0V, VA=VD= +3.3V, VDR=
+2.5V, PD = 0V, INT/EXT REF pin = +3.3V, V
face limits apply for TJ=T
MIN
to T
: all other limits TJ= 25˚C (Notes 7, 8, 9)
MAX
REF
= +1.0V, f
Symbol Parameter Conditions
STATIC CONVERTER CHARACTERISTICS
Resolution with No Missing Codes 12 Bits (min)
INL Integral Non Linearity (Note 11)
DNL Differential Non Linearity
PGE Posiitive Gain Error
NGE Negative gain Error
TC GE Gain Error Tempco −40˚C ≤ T
V
TC
V
OFF
OFF
Offset Error (VIN+=VIN−) 0.18
Offset Error Tempco −40˚C ≤ TA≤ +85˚C 0.1 ppm/˚C
Under Range Output Code 0 0
Over Range Output Code 4095 4095
REFERENCE AND ANALOG INPUT CHARACTERISTICS
V
CM
C
IN
V
REF
Common Mode Input Voltage 1.0
VINInput Capacitance (each pin to
GND)
VIN= 2.5 Vdc
+ 0.7 V
rms
Reference Voltage (Note 13) 1.00
Reference Input Resistance 100 MΩ (min)
= 66 MHz, fIN= 10 MHz, tr=tf= 2 ns, CL= 15 pF/pin. Bold-
CLK
Typical
(Note 10)
±
1.2
±
0.5
±
0.2
±
0.2
≤ +85˚C 0.5 ppm/˚C
A
Limits
(Note 10)
±
3.0 LSB (max)
±
1.0 LSB (max)
±
3.6 %FS (max)
±
3.6 %FS (max)
+1.3
-0.9
%FS (max)
%FS (min)
Units
(Limits)
0.5 V (min)
1.5 V (max)
(CLK LOW) 8 pF
(CLK HIGH) 7 pF
0.8 V (min)
1.5 V (max)
D
− 0.5V)
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Converter Electrical Characteristics (Continued)
Unless otherwise specified, the following specifications apply for AGND = DGND = DR GND = 0V, VA=VD= +3.3V, VDR=
+2.5V, PD = 0V, INT/EXT REF pin = +3.3V, V
face limits apply for TJ=T
ADC12DL066
MIN
to T
: all other limits TJ= 25˚C (Notes 7, 8, 9)
MAX
REF
= +1.0V, f
Symbol Parameter Conditions
DYNAMIC CONVERTER CHARACTERISTICS
FPBW Full Power Bandwidth 0 dBFS Input, Output at −3 dB 450 MHz
= 1 MHz, VIN= −0.5 dBFS 66 dB
f
IN
f
= 10 MHz, VIN= −0.5 dBFS 66 64 dB (min)
SNR Signal-to-Noise Ratio
SINAD Signal-to-Noise and Distortion
ENOB Effective Number of Bits
THD Total Harmonic Distortion
H2 Second Harmonic Distortion
H3 Third Harmonic Distortion
SFDR Spurious Free Dynamic Range
IMD Intermodulation Distortion
IN
f
= 33 MHz, VIN= −0.5 dBFS 64 dB
IN
f
= 146 MHz, VIN= −0.5 dBFS 55 dB
IN
= 1 MHz, VIN= −0.5 dBFS 66 dB
f
IN
f
= 10 MHz, VIN= −0.5 dBFS 66 63.3 dB (min)
IN
f
= 33 MHz, VIN= −0.5 dBFS 63 dB
IN
f
= 146MHz, VIN= −0.5 dBFS 53 dB
IN
= 1 MHz, VIN= −0.5 dBFS 10.7 Bits
f
IN
f
= 10 MHz, VIN= −0,5 dBFS 10.7 10.2 Bits (min)
IN
f
= 33 MHz, VIN= −0,5 dBFS 10.3 Bits
IN
f
= 146MHz, VIN= −0,5 dBFS 8.7 Bits
IN
= 1 MHz, VIN= −0.5 dBFS −78 dB
f
IN
f
= 10 MHz, VIN= −0.5 dBFS −78 −67.8 dB (min)
IN
f
= 33 MHz, VIN= −0.5 dBFS −70 dB
IN
f
= 146MHz, VIN= −0.5 dBFS −59 dB
IN
= 1 MHz, VIN= −0.5 dBFS −90 dB
f
IN
f
= 10 MHz, VIN= −0.5 dBFS −85 −70.4 dB (min)
IN
f
= 33 MHz, VIN= −0.5 dBFS −72 dB
IN
f
= 146MHz, VIN= −0.5 dBFS −67 dB
IN
= 1 MHz, VIN= −0.5 dBFS −83 dB
f
IN
f
= 10 MHz, VIN= −0.5 dBFS −85 −71.0 dB (min)
IN
f
= 33 MHz, VIN= −0.5 dBFS −76 dB
IN
f
= 146MHz, VIN= −0.5 dBFS −66 dB
IN
= 1 MHz, VIN= −0.5 dBFS 79 dB
f
IN
f
= 10 MHz, VIN= −0.5 dBFS 81 68.5 dB (min)
IN
f
= 33 MHz, VIN= −0.5 dBFS 72 dB
IN
f
= 146MHz, VIN= −0.5 dBFS 63 dB
IN
f
= 9.6 MHz and 10.2 MHz,
IN
each = −6.0 dBFS
INTER-CHANNEL CHARACTERISTICS
Channel —Channel Offset Match
Channel — Channel Gain Match
10 MHz Tested, Channel;
Crosstalk
20 MHz Other Channel
10 MHz Tested, Channel;
195 MHz Other Channel
= 66 MHz, fIN= 10 MHz, tr=tf= 2 ns, CL= 15 pF/pin. Bold-
CLK
Typical
(Note 10)
Limits
(Note 10)
−64 dBFS
±
0.03 %FS
±
0.1 %FS
80 dB
63 dB
Units
(Limits)
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DC and Logic Electrical Characteristics
Unless otherwise specified, the following specifications apply for AGND = DGND = DR GND = 0V, VA=VD= +3.3V, VDR=
+2.5V, PD = 0V, INT/EXT REF pin = +3.3V, V
face limits apply for TJ=T
MIN
to T
: all other limits TJ= 25˚C (Notes 7, 8, 9)
MAX
REF
= +1.0V, f
Symbol Parameter Conditions
CLK, PD, OE DIGITAL INPUT CHARACTERISTICS
V
V
I
I
C
IN(1)
IN(0)
IN(1)
IN(0)
IN
Logical “1” Input Voltage VD= 3.6V 2.0 V (min)
Logical “0” Input Voltage VD= 3.0V 1.0 V (max)
Logical “1” Input Current VIN= 3.3V 10 µA
Logical “0” Input Current VIN= 0V −10 µA
Digital Input Capacitance 5 pF
D0–D11 DIGITAL OUTPUT CHARACTERISTICS
V
V
I
OZ
+I
−I
C
OUT(1)
OUT(0)
SC
SC
OUT
Logical “1” Output Voltage I
Logical “0” Output Voltage I
TRI-STATE®Output Current
Output Short Circuit Source
Current
Output Short Circuit Sink Current V
= −0.5 mA
OUT
= 1.6 mA, VDR=3V 0.4 V (max)
OUT
= 2.5V or 3.3V 100 nA
V
OUT
V
= 0V −100 nA
OUT
= 0V −20 mA
V
OUT
OUT=VDR
Digital Output Capacitance 5 pF
POWER SUPPLY CHARACTERISTICS
I
A
I
D
I
DR
Analog Supply Current
Digital Supply Current
Digital Output Supply Current
Total Power Consumption
PSRR1 Power Supply Rejection Ratio
PSRR2 Power Supply Rejection Ratio
PD Pin = DGND, V
PD Pin = V
PD Pin = DGND
PD Pin = V
PD Pin = DGND, C
PD Pin = V
PD Pin = DGND, C
PD Pin = V
Rejection of Full-Scale Error with
= 3.0V vs. 3.6V
V
A
Rejection of Power Supply Noise with
10 MHz, 500 mV riding on V
= 66 MHz, fIN= 10 MHz, tr=tf= 2 ns, CL= 15 pF/pin. Bold-
CLK
Typical
(Note 10)
= 2.5V 2.3 V (min)
V
DR
V
=3V 2.7 V (min)
DR
Limits
(Note 10)
20 mA
D
D,fCLK
D,fCLK
D
= 1.0V
REF
=0
= 0 pF (Note 14)
L
=0
= 0 pF (Note 15)
L
177
14
31
8.7
<
0
686
75
237 mA (max)
34 mA (max)
2
895 mW (max)
56 dB
A
44 dB
Units
(Limits)
ADC12DL066
mA
mA
mA
mA
mW
AC Electrical Characteristics
Unless otherwise specified, the following specifications apply for AGND = DGND = DR GND = 0V, VA=VD= +3.3V, VDR=
+2.5V, PD = 0V, INT/EXT REF pin = +3.3V, V
face limits apply for TJ=T
MIN
to T
: all other limits TJ= 25˚C (Notes 7, 8, 9, 12)
MAX
REF
= +1.0V, f
Symbol Parameter Conditions
1
f
CLK
f
CLK
t
CH
t
CL
t
CONV
t
OD
t
AD
Maximum Clock Frequency 75 66 MHz (min)
2
Minimum Clock Frequency 15 MHz
Clock High Time 6.6 ns (min)
Clock Low Time 6.6 ns (min)
Conversion Latency 6
= 2.5V
V
Data Output Delay after Rising
CLK Edge
DR
V
= 3.3V
DR
Aperture Delay 2 ns
= 66 MHz, fIN= 10 MHz, tr=tf= 2 ns, CL= 15 pF/pin. Bold-
CLK
Typical
(Note 10)
Limits
(Note 10)
rising 6.6 9.0 ns (max)
falling 6.0 8.5 ns (max)
rising 6.4 9.0 ns (max)
falling 6.5 9.0 ns (max)
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Units
(Limits)
Clock
Cycles
AC Electrical Characteristics (Continued)
Unless otherwise specified, the following specifications apply for AGND = DGND = DR GND = 0V, VA=VD= +3.3V, VDR=
+2.5V, PD = 0V, INT/EXT REF pin = +3.3V, V
face limits apply for TJ=T
ADC12DL066
MIN
to T
: all other limits TJ= 25˚C (Notes 7, 8, 9, 12)
MAX
REF
= +1.0V, f
Symbol Parameter Conditions
t
AJ
t
HOLD
t
DIS
t
EN
Aperture Jitter 1.2 ps rms
Clock Edge to Data Transition 8 ns
Data outputs into Hi-Z Mode 10 ns
Data Outputs Active after Hi-Z
Mode
0.1 µF on pins 4, 14; series 1.5 Ω &1
t
PD
Power Down Mode Exit Cycle
µF between pins 5, 6 and between
pins 12, 13
Note 1: Absolute Maximum Ratings indicate limits beyond which damage to the device may occur. Operating Ratings indicate conditions for which the device is
functional, but do not guarantee specific performance limits. For guaranteed specifications and test conditions, see the Electrical Characteristics. The guaranteed
specifications apply only for the test conditions listed. Some performance characteristics may degrade when the device is not operated under the listed test
conditions.
Note 2: All voltages are measured with respect to GND = AGND = DGND = 0V, unless otherwise specified.
Note 3: When the input voltage at any pin exceeds the power supplies (that is, V
50 mA maximum package input current rating limits the number of pins that can safely exceed the power supplies with an input current of 25 mA to two.
Note 4: The absolute maximum junction temperature (T
junction-to-ambient thermal resistance (TQFP, θ
device under normal operation will typically be about 726 mW (686 typical power consumption + 40 mW TTL output loading). The values for maximum power
dissipation listed above will be reached only when the device is operated in a severe fault condition (e.g. when input or output pins are driven beyond the power
supply voltages, or the power supply polarity is reversed). Obviously, such conditions should always be avoided.
Note 5: Human body model is 100 pF capacitor discharged through a 1.5 kΩ resistor. Machine model is 220 pF discharged through 0Ω.
Note 6: The 235˚C reflow temperature refers to infrared reflow. For Vapor Phase Reflow (VPR), the following Conditions apply: Maintain the temperature at the top
of the package body above 183˚C for a minimum 60 seconds. The temperature measured on the package body must not exceed 220˚C. Only one excursion above
183˚C is allowed per reflow cycle.
Note 7: The inputs are protected as shown below. Input voltage magnitudes above V
(Note 3). However, errors in the A/D conversion can occur if the input goes above V
input voltage must be ≤+3.4V to ensure accurate conversions.
is 50˚C/W, so PDMAX=2Watts at 25˚C and 800 mW at the maximum operating ambient temperature of 85˚C. Note that the power consumption of this
JA
), and the ambient temperature, (TA), and can be calculated using the formula PDMAX=(TJmax - TA)/θJA. In the 64-pin
JA
max) for this device is 150˚C. The maximum allowable power dissipation is dictated by TJmax, the
J
= 66 MHz, fIN= 10 MHz, tr=tf= 2 ns, CL= 15 pF/pin. Bold-
CLK
Typical
(Note 10)
Limits
(Note 10)
10 ns
500 µs
<
AGND, or V
IN
or below GND will not damage this device, provided current is limited per
A
or below GND by more than 100 mV. As an example, if VAis +3.3V, the full-scale
A
>
VA), the current at that pin should be limited to 25 mA. The
IN
Units
(Limits)
20055207
Note 8: To guarantee accuracy, it is required that |VA–VD| ≤ 100 mV and separate bypass capacitors are used at each power supply pin.
Note 9: With the test condition for V
Note 10: Typical figures are at T
Level).
Note 11: Integral Non Linearity is defined as the deviation of the analog value, expressed in LSBs, from the straight line that passes through positive and negative
full-scale.
Note 12: Timing specifications are tested at TTL logic levels, V
Note 13: Optimum performance will be obtained by keeping the reference input in the 0.8V to 1.5V range. The LM4051CIM3-ADJ (SOT-23 package) is
recommended for external reference applications.
Note 14: I
V
DR
voltage, C
Note 15: Excludes I
is the current consumed by the switching of the output drivers and is primarily determined by load capacitance on the output pins, the supply voltage,
DR
, and the rate at which the outputs are switching (which is signal dependent). IDR=VDR(C0xf0+C1xf1+....C11xf11) where VDRis the output driver power supply
is total capacitance on the output pin, and fnis the average frequency at which that pin is toggling.
n
. See note 14.
DR
= +1.0V (2V
REF
= 25˚C, and represent most likely parametric norms. Test limits are guaranteed to National’s AOQL (Average Outgoing Quality
J
differential input), the 12-bit LSB is 488 µV.
P-P
= 0.4V for a falling edge and VIH= 2.4V for a rising edge.
IL
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Specification Definitions
APERTURE DELAY is the time after the rising edge of the
clock to when the input signal is acquired or held for conversion.
APERTURE JITTER (APERTURE UNCERTAINTY) is the
variation in aperture delay from sample to sample. Aperture
jitter manifests itself as noise in the output.
CLOCK DUTY CYCLE is the ratio of the time during one
cycle that a repetitive digital waveform is high to the total
time of one period. The specification here refers to the ADC
clock input signal.
COMMON MODE VOLTAGE (V
age applied to both input terminals of the ADC.
CONVERSION LATENCY is the number of clock cycles
between initiation of conversion and when that data is presented to the output driver stage. Data for any given sample
is available at the output pins the Pipeline Delay plus the
Output Delay after the sample is taken. New data is available
at every clock cycle, but the data lags the conversion by the
pipeline delay.
CROSSTALK is coupling of energy from one channel into
the other channel.
DIFFERENTIAL NON-LINEARITY (DNL) is the measure of
the maximum deviation from the ideal step size of 1 LSB.
EFFECTIVE NUMBER OF BITS (ENOB, or EFFECTIVE
BITS) is another method of specifying Signal-to-Noise and
Distortion or SINAD. ENOB is defined as (SINAD - 1.76) /
6.02 and says that the converter is equivalent to a perfect
ADC of this (ENOB) number of bits.
FULL POWER BANDWIDTH is a measure of the frequency
at which the reconstructed output fundamental drops 3 dB
below its low frequency value for a full scale input.
GAIN ERROR is the deviation from the ideal slope of the
transfer function. It can be calculated as:
Gain Error = Positive Full Scale Error − Offset Error
A gain of unity occurs when the negative and positive full
scale errors are equal to each other, including having the
same sign.
GAIN ERROR MATCHING is the difference in gain errors
between the two converters divided by the average gain of
the converters.
INTEGRAL NON LINEARITY (INL) is a measure of the
deviation of each individual code from a line drawn from
negative full scale (
1
⁄2LSB below the first code transition)
through positive full scale (
transition). The deviation of any given code from this straight
line is measured from the center of that code value.
INTERMODULATION DISTORTION (IMD) is the creation of
additional spectral components as a result of two sinusoidal
frequencies being applied to the ADC input at the same time.
It is defined as the ratio of the power in the intermodulation
products to the total power in the original frequencies. IMD is
usually expressed in dBFS.
LSB (LEAST SIGNIFICANT BIT) is the bit that has the
smallest value or weight of all bits. This value is V
where “n” is the ADC resolution in bits, which is 12 in the
case of the ADC12DL066.
MISSING CODES are those output codes that will never
appear at the ADC outputs. The ADC12DL066 is guaranteed
not to have any missing codes.
MSB (MOST SIGNIFICANT BIT) is the bit that has the
largest value or weight. Its value is one half of full scale.
) is the common d.c. volt-
CM
1
⁄2LSB above the last code
REF
/2n,
NEGATIVE FULL SCALE ERROR is the difference between
the actual first code transition and its ideal value of
1
⁄2LSB
above negative full scale.
OFFSET ERROR is the difference between the two input
voltages [(V
+) – (V
IN
)] required to cause a transition from
IN−
code 2047 to 2048.
OUTPUT DELAY is the time delay after the rising edge of
the clock before the data update is presented at the output
pins.
OVER RANGE RECOVERY TIME is the time required after
goes from a specified voltage out of the normal input
V
IN
range to a specified voltage within the normal input range
and the converter makes a conversion with its rated accuracy.
PIPELINE DELAY (LATENCY) See CONVERSION LATENCY.
POSITIVE FULL SCALE ERROR is the difference between
the actual last code transition and its ideal value of 1
1
⁄2LSB
below positive full scale.
POWER SUPPLY REJECTION RATIO (PSRR) is a mea-
sure of how well the ADC rejects a change in the power
supply voltage. For the ADC12DL066, PSRR1 is the ratio of
the change in Full-Scale Error that results from a change in
the d.c. power supply voltage, expressed in dB. PSRR2 is a
measure of how well an a.c. signal riding upon the power
supply is rejected at the output.
SIGNAL TO NOISE RATIO (SNR) is the ratio, expressed in
dB, of the rms value of the input signal to the rms value of the
sum of all other spectral components below one-half the
sampling frequency, not including harmonics or d.c.
SIGNAL TO NOISE PLUS DISTORTION (S/N+D or SINAD)
Is the ratio, expressed in dB, of the rms value of the input
signal to the rms value of all of the other spectral components below half the clock frequency, including harmonics
but excluding d.c.
SPURIOUS FREE DYNAMIC RANGE (SFDR) is the difference, expressed in dB, between the rms values of the input
signal and the peak spurious signal, where a spurious signal
is any signal present in the output spectrum that is not
present at the input.
TOTAL HARMONIC DISTORTION (THD) is the ratio, expressed in dB, of the rms total of the first nine harmonic
levels at the output to the level of the fundamental at the
output. THD is calculated as
where F1is the RMS power of the fundamental (output)
frequency and f
through f10are the RMS power of the first
2
9 harmonic frequencies in the output spectrum.
– Second Harmonic Distortion (2ND HARM) is the differ-
ence expressed in dB, between the RMS power in the input
frequency at the output and the power in its 2nd harmonic
level at the output.
– Third Harmonic Distortion (3RD HARM) is the difference, expressed in dB, between the RMS power in the input
frequency at the output and the power in its 3rd harmonic
level at the output.
ADC12DL066
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Timing Diagram
ADC12DL066
Transfer Characteristic
Output Timing
20055209
FIGURE 1. Transfer Characteristic
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20055210
ADC12DL066
Typical Performance Characteristics V
unless otherwise stated
DNL DNL vs. f
20055218
DNL vs. Clock Duty Cycle DNL vs. V
= +3.3V, VDR= +2.5V, f
A=VD
= 66 MHz, fIN=10MHz
CLK
CLK
20055219
DR
20055220 20055221
DNL vs. Temperature INL
20055222 20055260
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Typical Performance Characteristics V
unless otherwise stated (Continued)
= +3.3V, VDR= +2.5V, f
A=VD
= 66 MHz, fIN=10MHz
CLK
ADC12DL066
INL vs. f
INL vs. V
CLK
INL vs. Clock Duty Cycle
20055224 20055225
DR
INL vs. Temperature
20055226 20055227
SNR, SINAD, SFDR vs. f
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CLK
20055228 20055229
SNR, SINAD, SFDR vs. CLOCK DUTY CYCLE
ADC12DL066
Typical Performance Characteristics V
unless otherwise stated (Continued)
SNR, SINAD, SFDR vs. V
SNR, SINAD, SFDR vs. V
REF
20055231 20055232
DR
= +3.3V, VDR= +2.5V, f
A=VD
SNR, SINAD, SFDR vs. Temperature
= 66 MHz, fIN=10MHz
CLK
SNR, SINAD, SFDR vs. V
CM
Distortion vs. F
CLK
20055233 20055234
Distortion vs. Clock Duty Cycle
20055236 20055237
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Typical Performance Characteristics V
unless otherwise stated (Continued)
= +3.3V, VDR= +2.5V, f
A=VD
= 66 MHz, fIN=10MHz
CLK
ADC12DL066
Distortion vs. V
Distortion vs. V
REF
DR
Distortion vs. V
20055238 20055239
CM
Distortion vs. Temperature
20055240 20055241
tODvs. V
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DR
20055243 20055261
SPECTRAL PLOT, FIN=10MHz
ADC12DL066
Typical Performance Characteristics V
unless otherwise stated (Continued)
SPECTRAL PLOT, F
= 33 MHz IMD PERFORMANCE, FIN1 = 9.6 MHz, FIN2 = 10.2 MHz
IN
20055262 20055263
= +3.3V, VDR= +2.5V, f
A=VD
= 66 MHz, fIN=10MHz
CLK
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Functional Description
Operating on a single +3.3V supply, the ADC12DL066 uses
a pipeline architecture and has error correction circuitry to
help ensure maximum performance. The differential analog
ADC12DL066
input signal is digitized to 12 bits. The user has the choice of
using an internal 1.0 Volt stable reference or using an external reference. Any external reference is buffered on-chip to
ease the task of driving that pin.
The output word rate is the same as the clock frequency,
which can be between 15 MSPS and 75 MSPS (typical) with
fully specified performance at 66 Msps. The analog input for
both channels is acquired at the rising edge of the clock and
the digital data for a given sample is delayed by the pipeline
for 6 clock cycles. A choice of Offset Binary or Two’s Complement output format is selected with the OF pin.
A logic high on the power down (PD) pin reduces the converter power consumption to 75 mW.
Applications Information
1.0 OPERATING CONDITIONS
We recommend that the following conditions be observed for
operation of the ADC12DL066:
3.0V ≤ V
V
D=VA
2.4V ≤ VDR≤ V
15 MHz ≤ f
0.8V ≤ V
0.5V ≤ V
1.1 Analog Inputs
There is one reference input pin, V
external reference. The ADC12DL066 has two analog signal
input pairs, V
and V
differential input pair.
1.2 Reference Pins
The ADC12DL066 is designed to operate with a 1.0V reference, but performs well with reference voltages in the range
of 0.8V to 1.5V. Lower reference voltages will decrease the
signal-to-noise ratio (SNR) of the ADC12DL066. Increasing
the reference voltage (and the input signal swing) beyond
1.5V may degrade THD for a full-scale input, especially at
higher input frequencies.
It is important that all grounds associated with the reference
voltage and the analog input signal make connection to the
ground plane at a single, quiet point to minimize the effects
of noise currents in the ground path.
The ADC12DL066 will perform well with reference voltages
up to 1.5V for full-scale input frequencies up to 10 MHz.
However, more headroom is needed as the input frequency
increases, so the maximum reference voltage (and input
swing) will decrease for higher full-scale input frequencies.
The six Reference Bypass Pins (V
B and VRNB) are made available for bypass purposes.
V
RM
The V
ground with a 0.1 µF capacitor. A series 1.5Ω resistor (5%)
and 1.0 µF capacitor (
A and VRNA pins and between the VRPB and VRNB pins,
V
RP
as shown in Figure 4. This configuration is necessary to
avoid reference oscillation, which could result in reduced
SFDR and/or SNR.
≤ 3.6V
A
D
≤ 75 MHz
CLK
≤ 1.5V
REF
≤ 1.5V
CM
, for use of an optional
REF
A+ and VINA- for one converter and VINB+
IN
B- for the other converter. Each pair of pins forms a
IN
A, VRMA, VRNA, VRPB,
RP
A and VRMB pins should each be bypassed to
RM
±
20%) should be placed between the
Smaller capacitor values than those specified will allow
faster recovery from the power down mode, but may result in
degraded noise performance. DO NOT LOAD these pins.
Loading any of these pins may result in performance degradation.
The nominal voltages for the reference bypass pins are as
follows:
V
RM=VA
V
RP=VRM+VREF
V
RN=VRM−VREF
The V
voltage (V
/2
/2
/2
or the VRNpins may be used as common mode
RM
) sources for the analog input pins as long as no
CM
d.c. current is drawn from them. However, because the
voltages at the V
pins are half that of the VAsupply pin,
RM
using these pins for common mode voltage sources will
result in reduced input headroom (the difference between
supply voltage and the peak signal voltage at either
the V
A
analog input) and the possibility of reduced THD and SFDR
performance. For this reason, it is recommended that V
always exceed V
by at least 2 Volts when using the V
REF
RM
pins as VCMsources. For high input frequencies it may be
necessary to increase this headroom to maintain THD and
SFDR performance.
User choice of an on-chip or external reference voltage is
provided. The internal 1.0 Volt reference is in use when the
the INT/EXT REF pin is at a logic low, regardless of any
voltage applied to the V
is at a logic high, the voltage at the V
pin. When the INT/EXT REF pin
REF
pin is used for the
REF
voltage reference. Optimum ADC dynamic performance is
obtained when the reference voltage is in the range of 0.8V
to 1.5V. When an external reference is used, the V
REF
pin
should be bypassed to ground with a 0.1 µF capacitor close
to the reference input pin. There is no need to bypass the
pin when the internal reference is used.
V
REF
There is no direct access to the internal reference voltage.
However the nominal value of the reference voltage,
whether the internal or an external reference is used, is
approximately equal to V
RP−VRN
.
1.3 Signal Inputs
The signal inputs are V
B+ and VINB− for the other ADC . The input signal, VIN,is
V
IN
A+ and VINA− for one ADC and
IN
defined as
A=(VINA+) – (VINA−)
V
IN
for the "A" converter and
B=(VINB+) – (VINB−)
V
IN
for the "B" converter. Figure 2 shows the expected input
signal range. Note that the common mode input voltage,
, should be in the range of 0.5V to 1.5V with a nominal
V
CM
value of 1.0V.
The peaks of the individual input signals should each never
exceed the voltage described as
Peak Input Voltage = V
– 1.0V
A
to maintain THD and SINAD performance.
The ADC12DL066 performs best with a differential input
signal with each input centered around a common mode
voltage, V
. The peak-to-peak voltage swing at each ana-
CM
log input pin should not exceed the value of the reference
voltage or the output data will be clipped.
The two input signals should be exactly 180˚ out of phase
from each other and of the same amplitude. For single
A
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ADC12DL066
Applications Information (Continued)
frequency inputs, angular errors result in a reduction of the
effective full scale input. For complex waveforms, however,
angular errors will result in distortion.
20055211
FIGURE 2. Expected Input Signal Range
For single frequency sine waves the full scale error in LSB
can be described as approximately
=4096(1-sin(90˚ + dev))
E
FS
Where dev is the angular difference in degrees between the
two signals having a 180˚ relative phase relationship to each
other (see Figure 3). Drive the analog inputs with a source
impedance less than 100Ω.
TABLE 1. Input to Output Relationship – Differential
Input
2’s Complement
Output
V
V
V
V
V
V
V
V
V
IN
CM
REF
CM
REF/4
V
CM
CM
REF
CM
REF
+
−
/2
−
+
/4
+
/2
V
V
CM
V
REF/2
VCM+
V
REF
V
V
CM
V
REF
V
CM
V
REF
−
Binary Output
IN
+
0000 0000 0000 1000 0000 0000
0100 0000 0000 1100 0000 0000
/4
1000 0000 0000 0000 0000 0000
CM
−
1100 0000 0000 0100 0000 0000
/4
−
1111 1111 1111 0111 1111 1111
/2
TABLE 2. Input to Output Relationship – Single-Ended
Input
+
V
IN
V
−
CM
V
REF
V
−
CM
/2
V
REF
V
CM
V
+
CM
/2
V
REF
V
+
CM
V
REF
−
V
V
V
V
V
V
Binary Output
IN
0000 0000 0000 1000 0000 0000
CM
0100 0000 0000 1100 0000 0000
CM
1000 0000 0000 0000 0000 0000
CM
1100 0000 0000 0100 0000 0000
CM
1111 1111 1111 0111 1111 1111
CM
2’s Complement
Output
20055212
FIGURE 3. Angular Errors Between the Two Input
Signals Will Reduce the Output Level or Cause
Distortion
For differential operation, each analog input pin of the differential pair should have a peak-to-peak voltage equal to the
reference voltage, V
each other and be centered around V
, be 180 degrees out of phase with
REF
CM
.
1.3.1 Single-Ended Operation
Performance with differential input signals is better than with
single-ended signals. For this reason, single-ended operation is not recommended. However, if single ended-operation
is required and the resulting performance degradation is
acceptable, one of the analog inputs should be connected to
the d.c. mid point voltage of the driven input. The peak-topeak differential input signal at the driven input pin should be
twice the reference voltage to maximize SNR and SINAD
performance (Figure 2b). For example, set V
bias V
− to 1.0V and drive VIN+ with a signal range of 0.5V
IN
REF
to 0.5V,
to 1.5V.
Because very large input signal swings can degrade distor-
tion performance, better performance with a single-ended
input can be obtained by reducing the reference voltage
when maintaining a full-range output. Table 1 and Table 2
indicate the input to output relationship of the ADC12DL066.
1.3.2 Driving the Analog Inputs
The V
+ and the VIN− inputs of the ADC12DL066 consist of
IN
an analog switch followed by a switched-capacitor amplifier.
The capacitance seen at the analog input pins changes with
the clock level, appearing as 8 pF when the clock is low, and
7 pF when the clock is high.
As the internal sampling switch opens and closes, current
pulses occur at the analog input pins, resulting in voltage
spikes at the signal input pins. As a driving amplifier attempts
to counteract these voltage spikes, a damped oscillation
may appear at the ADC analog input. Do not attempt to filter
out these pulses. Rather, use amplifiers to drive the
ADC11DL066 input pins that are able to react to these
pluses and settle before the switch opens and another
sample is taken. The LMH6702 LMH6628, LMH6622 and the
LMH6655 are good amplifiers for driving the ADC12DL066.
To help isolate the pulses at the ADC input from the amplifier
output, use RCs at the inputs, as can be seen in Figure 4
and Figure 5 . These components should be placed close to
the ADC inputs because the input pins of the ADC is the
most sensitive part of the system and this is the last opportunity to filter that input.
For Nyquist applications the RC pole should be at the ADC
sample rate. The ADC input capacitance in the sample mode
should be considered when setting the RC pole. For wideband undersampling applications, the RC pole should be set
at about 1.5 to 2 times the maximum input frequency to
maintain a linear delay response.
www.national.com17
Applications Information (Continued)
A single-ended to differential conversion circuit is shown in
Figure 5. Table 3 gives resistor values for that circuit to
provide input signals in a range of 1.0V
ADC12DL066
differential input pins of the ADC12DL066.
TABLE 3. Resistor Values for Circuit of Figure 5
SIGNAL
RANGE
R1 R2 R3 R4 R5, R6
0 - 0.25V open 0Ω 124Ω 1500Ω 1000Ω
0 - 0.5V 0Ω openΩ 499Ω 1500Ω 499Ω
±
0.25V 100Ω 698Ω 100Ω 698Ω 499Ω
1.3.3 Input Common Mode Voltage
The input common mode voltage, V
range of 0.5V to 1.5V and be a value such that the peak
excursions of the analog signal does not go more negative
than ground or more positive than one Volt below the V
supply voltage. The nominal VCMshould generally be about
1.0V, but V
or VRNcan be used as a VCMsource as long
RM
as no d.c. current is drawn from either of these pins. See
Section 1.2
2.0 DIGITAL INPUTS
Digital TTL/CMOS compatible inputs consist of CLK, OEA,
OEB, OF, INT/EXT REF and PD.
2.1 CLK
The CLK signal controls the timing of the sampling process.
Drive the clock input with a stable, low jitter clock signal in
the range of 15 MHz to 75 MHz with rise and fall times of 2
ns or less. The trace carrying the clock signal should be as
short as possible and should not cross any other signal line,
analog or digital, not even at 90˚.
The CLK signal also drives an internal state machine. If the
CLK is interrupted, or its frequency too low, the charge on
internal capacitors can dissipate to the point where the accuracy of the output data will degrade. This is what limits the
lowest sample rate to 15 MSPS.
The clock line should be terminated at its source in the
characteristic impedance of that line. Take care to maintain a
constant clock line impedance throughout the length of the
line. Refer to Application Note AN-905 for information on
setting characteristic impedance.
It is highly desirable that the the source driving the ADC CLK
pin only drive that pin. However, if that source is used to
drive other things, each driven pin should be a.c. terminated
with a series RC to ground, as shown in Figure 4, such that
the resistor value is equal to the characteristic impedance of
the clock line and the capacitor value is
±
0.5V at each of the
, should be in the
CM
The duty cycle of the clock signal can affect the performance
of the A/D Converter. Because achieving a precise duty
cycle is difficult, the ADC12DL066 is designed to maintain
performance over a range of duty cycles. While it is specified
and performance is guaranteed with a 50% clock duty cycle,
performance is typically maintained over a clock duty cycle
range of 43% to 57% at 66 MSPS.
2.2 OEA, OEB
The OEA and OEB pins, when high, put the output pins of
their respective converters into a high impedance state.
When either of these pin is low, the corresponding outputs
are in the active state. The ADC12DL066 will continue to
convert whether these pins are high or low, but the output
can not be read while the pin is high.
Since ADC noise increases with increased output capacitance at the digital output pins, do not use the TRI-STATE
outputs of the ADC12DL066 to drive a bus. Rather, each
output pin should be located close to and drive a single
digital input pin. To further reduce ADC noise, a 100 Ω
A
resistor in series with each ADC digital output pin, located
close to their respective pins, should be added to the circuit.
2.3 PD
The PD pin, when high, holds the ADC12DL066 in a powerdown mode to conserve power when the converter is not
being used. The power consumption in this state is 75 mW
with a 66MHz clock and 40mW if the clock is stopped when
PD is high. The output data pins are undefined and the data
in the pipeline is corrupted while in the power down mode.
The Power Down Mode Exit Cycle time is determined by the
value of the components on pins 4, 5, 6, 12, 13 and 14 and
is about 500 µs with the recommended components on the
V
RP,VRM
and VRNreference bypass pins. These capacitors
loose their charge in the Power Down mode and must be
recharged by on-chip circuitry before conversions can be
accurate. Smaller capacitor values allow slightly faster recovery from the power down mode, but can result in a
reduction in SNR, SINAD and ENOB performance.
2.4 OF
The output data format is offset binary when the OF pin is at
a logic low or 2’s complement when the OF pin is at a logic
high. While the sense of this pin may be changed "on the fly,"
doing this is not recommended as the output data could be
erroneous for a few clock cycles after this change is made.
2.5 INT/EXT REF
The INT/EXT REF pin determines whether the internal reference or an external reference voltage is used. With this pin
at a logic low, the internal 1.0V reference is in use. With this
pin at a logic high an external reference must be applied to
the V
There is no need to bypass the V
pin, which should then be bypassed to ground.
REF
pin when the internal
REF
reference is used. There is no access to the internal reference voltage, but its value is approximately equal to V
.
V
RN
−
RP
where tPDis the signal propagation rate down the clock line,
"L" is the line length and Z
is the characteristic impedance
O
of the clock line. This termination should be as close as
possible to the ADC clock pin but beyond it as seen from the
clock source. Typical t
FR-4 board material. The units of "L" and t
is about 150 ps/inch (60 ps/cm) on
PD
should be the
PD
same (inches or centimeters).
www.national.com 18
3.0 OUTPUTS
The ADC12DL066 has 12 TTL/CMOS compatible Data Output pins. Valid data is present at these outputs while the OE
and PD pins are low. While the tODtime provides information
about output timing, a simple way to capture a valid output is
to latch the data on the falling edge of the conversion clock
(pin 10).
Applications Information (Continued)
Be very careful when driving a high capacitance bus. The
more capacitance the output drivers must charge for each
conversion, the more instantaneous digital current flows
through V
spikes can cause on-chip ground noise and couple into the
analog circuitry, degrading dynamic performance. Adequate
bypassing, limiting output capacitance and careful attention
to the ground plane will reduce this problem. Additionally,
bus capacitance beyond the specified 15 pF/pin will cause
to increase, making it difficult to properly latch the ADC
t
OD
and DR GND. These large charging current
DR
ADC12DL066
output data. The result could be an apparent reduction in
dynamic performance.
To minimize noise due to output switching, minimize the load
currents at the digital outputs. This can be done by connecting buffers (74ACQ541, for example) between the ADC outputs and any other circuitry. Only one driven input should be
connected to each output pin. Additionally, inserting series
resistors of about 100Ω at the digital outputs, close to the
ADC pins, will isolate the outputs from trace and other circuit
capacitances and limit the output currents, which could otherwise result in performance degradation. See Figure 4.
FIGURE 4. Application Circuit using Transformer or Differential Op-Amp Drive Circuit
20055213
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Applications Information (Continued)
ADC12DL066
FIGURE 5. Differential Drive Circuit of Figure 4
20055214
4.0 POWER SUPPLY CONSIDERATIONS
The power supply pins should be bypassed with a 10 µF
capacitor and with a 0.1 µF ceramic chip capacitor within a
centimeter of each power pin. Leadless chip capacitors are
preferred because they have low series inductance.
As is the case with all high-speed converters, the
ADC12DL066 is sensitive to power supply noise. Accordingly, the noise on the analog supply pin should be kept
below 100 mV
P-P
.
No pin should ever have a voltage on it that is in excess of
the supply voltages, not even on a transient basis. Be especially careful of this during power turn on and turn off.
The V
be operated from a supply in the range of 2.4V to V
pin provides power for the output drivers and may
DR
. This
D
can simplify interfacing to lower voltage devices and systems. Note, however, that t
DO NOT operate the V
increases with reduced VDR.
OD
pin at a voltage higher than VD.
DR
5.0 LAYOUT AND GROUNDING
Proper grounding and proper routing of all signals are essential to ensure accurate conversion. Maintaining separate
analog and digital areas of the board, with the ADC12DL066
between these areas, is required to achieve specified performance.
The ground return for the data outputs (DR GND) carries the
ground current for the output drivers. The output current can
exhibit high transients that could add noise to the conversion
process. To prevent this from happening, the DR GND pins
should NOT be connected to system ground in close proximity to any of the ADC12DL066’s other ground pins.
Capacitive coupling between the typically noisy digital circuitry and the sensitive analog circuitry can lead to poor
performance. The solution is to keep the analog circuitry
separated from the digital circuitry, and to keep the clock line
as short as possible.
Digital circuits create substantial supply and ground current
transients. The logic noise thus generated could have significant impact upon system noise performance. The best
logic family to use in systems with A/D converters is one
which employs non-saturating transistor designs, or has low
noise characteristics, such as the 74LS, 74HC(T) and
74AC(T)Q families. The worst noise generators are logic
families that draw the largest supply current transients during clock or signal edges, like the 74F and the 74AC(T)
families.
The effects of the noise generated from the ADC output
switching can be minimized through the use of 100Ω resistors in series with each data output line. Locate these resistors as close to the ADC output pins as possible.
Since digital switching transients are composed largely of
high frequency components, total ground plane copper
weight will have little effect upon the logic-generated noise.
This is because of the skin effect. Total surface area is more
important than is total ground plane volume.
Generally, analog and digital lines should cross each other at
90˚ to avoid crosstalk. To maximize accuracy in high speed,
high resolution systems, however, avoid crossing analog and
digital lines altogether. It is important to keep clock lines as
short as possible and isolated from ALL other lines, including
other digital lines. Even the generally accepted 90˚ crossing
should be avoided with the clock line as even a little coupling
can cause problems at high frequencies. This is because
other lines can introduce jitter into the clock line, which can
lead to degradation of SNR. Also, the high speed clock can
introduce noise into the analog chain.
Best performance at high frequencies and at high resolution
is obtained with a straight signal path. That is, the signal path
through all components should form a straight line wherever
possible.
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Applications Information (Continued)
ADC12DL066
FIGURE 6. Example of a Suitable Layout
Be especially careful with the layout of inductors. Mutual
inductance can change the characteristics of the circuit in
which they are used. Inductors should not be placed side by
side, even with just a small part of their bodies beside each
other.
The analog input should be isolated from noisy signal traces
to avoid coupling of spurious signals into the input. Any
external component (e.g., a filter capacitor) connected between the converter’s input pins and ground or to the reference input pin and ground should be connected to a very
clean point in the ground plane.
Figure 6 gives an example of a suitable layout. All analog
circuitry (input amplifiers, filters, reference components, etc.)
should be placed in the analog area of the board. All digital
circuitry and I/O lines should be placed in the digital area of
the board. The ADC12DL066 should be between these two
areas. Furthermore, all components in the reference circuitry
and the input signal chain that are connected to ground
should be connected together with short traces and enter the
ground plane at a single, quiet point. All ground connections
should have a low inductance path to ground.
20055216
6.0 DYNAMIC PERFORMANCE
To achieve the best dynamic performance, the clock source
driving the CLK input must be free of jitter. Isolate the ADC
clock from any digital circuitry with buffers, as with the clock
tree shown in Figure 7. The gates used in the clock tree must
be capable of operating at frequencies much higher than
those used if added jitter is to be prevented.
Best performance will be obtained with a differential input
drive, compared with a single-ended drive, as discussed in
Sections 1.3.1 and 1.3.2.
As mentioned in Section 5.0, it is good practice to keep the
ADC clock line as short as possible and to keep it well away
from any other signals. Other signals can introduce jitter into
the clock signal, which can lead to reduced SNR performance, and the clock can introduce noise into other lines.
Even lines with 90˚ crossings have capacitive coupling, so
try to avoid even these 90˚ crossings of the clock line.
www.national.com21
Applications Information (Continued)
ADC12DL066
FIGURE 7. Isolating the ADC Clock from other Circuitry
with a Clock Tree
7.0 COMMON APPLICATION PITFALLS Driving the inputs (analog or digital) beyond the power
supply rails. For proper operation, all inputs should not go
more than 100 mV beyond the supply rails (more than
100 mV below the ground pins or 100 mV above the supply
pins). Exceeding these limits on even a transient basis may
cause faulty or erratic operation. It is not uncommon for high
speed digital components (e.g., 74F and 74AC devices) to
exhibit overshoot or undershoot that goes above the power
supply or below ground. A resistor of about 47Ω to 100Ω in
series with any offending digital input, close to the signal
source, will eliminate the problem.
Do not allow input voltages to exceed the supply voltage,
even on a transient basis. Not even during power up or
power down.
Be careful not to overdrive the inputs of the ADC12DL066
with a device that is powered from supplies outside the
range of the ADC12DL066 supply. Such practice may lead to
conversion inaccuracies and even to device damage.
Attempting to drive a high capacitance digital data bus.
The more capacitance the output drivers must charge for
each conversion, the more instantaneous digital current
flows through V
rent spikes can couple into the analog circuitry, degrading
dynamic performance. Adequate bypassing and maintaining
separate analog and digital areas on the pc board will reduce
this problem.
Additionally, bus capacitance beyond the specified 15 pF/pin
will cause t
the ADC output data. The result could, again, be an apparent
reduction in dynamic performance.
and DR GND. These large charging cur-
DR
to increase, making it difficult to properly latch
OD
20055217
The digital data outputs should be buffered (with 74ACQ541,
for example). Dynamic performance can also be improved
by adding series resistors at each digital output, close to the
ADC12DL066, which reduces the energy coupled back into
the converter output pins by limiting the output current. A
reasonable value for these resistors is 100Ω.
Using an inadequate amplifier to drive the analog input.
As explained in Section 1.3, the capacitance seen at the
input alternates between 8 pF and 7 pF, depending upon the
phase of the clock. This dynamic load is more difficult to
drive than is a fixed capacitance.
If the amplifier exhibits overshoot, ringing, or any evidence of
instability, even at a very low level, it will degrade performance. A small series resistor at each amplifier output and a
capacitor at the analog inputs (as shown in Figure 4 and
Figure 5) will improve performance. The LMH6702 and the
LMH6628 have been successfully used to drive the analog
inputs of the ADC12DL066.
Also, it is important that the signals at the two inputs have
exactly the same amplitude and be exactly 180
o
out of phase
with each other. Board layout, especially equality of the
length of the two traces to the input pins, will affect the
effective phase between these two signals. Remember that
an operational amplifier operated in the non-inverting configuration will exhibit more time delay than will the same
device operating in the inverting configuration.
Operating with the reference pins outside of the specified range. As mentioned in Section 1.2, V
should be in
REF
the range of
0.8V ≤ V
REF
≤ 1.5V
Operating outside of these limits could lead to performance
degradation.
Inadequate network on Reference Bypass pins (V
A, VRMA, VRPB, VRNB and VRMB). As mentioned in
V
RN
A,
RP
Section 1.2, these pins should be bypassed with 0.1 µF
capacitors to ground at V
RC of 1.5 Ω and 1.0 µF between pins V
between V
B and VRNB for best performance.
RP
A and VRMB and with a series
RM
A and VRNA and
RP
Using a clock source with excessive jitter, using excessively long clock signal trace, or having other signals
coupled to the clock signal trace. This will cause the
sampling interval to vary, causing excessive output noise
and a reduction in SNR and SINAD performance.
www.national.com 22
Physical Dimensions inches (millimeters) unless otherwise noted
ADC12DL066 Dual 12-Bit, 66 MSPS, 450 MHz Input Bandwidth A/D Converter w/Internal
Reference
64-Lead TQFP Package
Ordering Number ADC12DL066CIVS
NS Package Number VECO64A
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