Rainbow Electronics ADC12DL066 User Manual
ADC12DL066
Dual 12-Bit, 66 MSPS, 450 MHz Input Bandwidth A/D
Converter w/Internal Reference
March 2004
ADC12DL066 Dual 12-Bit, 66 MSPS, 450 MHz Input Bandwidth A/D Converter w/Internal
Reference
General Description
The ADC12DL066 is a dual, low power monolithic CMOS
analog-to-digital converter capable of converting analog input signals into 12-bit digital words at 66 Megasamples per
second (MSPS), minimum. This converter uses a differential,
pipeline architecture with digital error correction and an onchip sample-and-hold circuit to minimize die size and power
consumption while providing excellent dynamic performance
and a 450 MHz Full Power Bandwidth. Operating on a single
3.3V power supply, the ADC12DL066 achieves 10.7 effective bits and consumes just 686 mW at 66 MSPS, including
the reference current. The Power Down feature reduces
power consumption to 75 mW.
The differential inputs provide a full scale differential input
swing equal to 2 times V
ended input. Full use of the differential input is recommended for optimum performance. The digital outputs from
the two ADCs are available on separate 12-bit buses with an
output data format choice of offset binary or two’s complement.
To ease interfacing to lower voltage systems, the digital
output driver power pins of the ADC12DL066 can be connected to a separate supply voltage in the range of 2.4V to
the digital supply voltage.
This device is available in the 64-lead TQFP package and
will operate over the industrial temperature range of −40˚C to
+85˚C. An evaluation board is available to ease the evaluation process.
with the possibility of a single-
REF
Features
n Single +3.3V supply operation
n Internal sample-and-hold
n Outputs 2.4V to 3.3V compatible
n Pin compatible with ADC12D040
n Power down mode
n On-chip reference
Key Specifications
n Resolution 12 Bits
n DNL
n SNR (f
n SFDR (f
n Data Latency 6 Clock Cycles
n Power Consumption
— Operating 686 mW (typ)
— Power Down Mode 75 mW (typ)
= 10 MHz) 66 dB (typ)
IN
= 10 MHz) 81 dB (typ)
IN
±
0.5 LSB (typ)
Applications
n Ultrasound and Imaging
n Instrumentation
n Communications Receivers
n Sonar/Radar
n xDSL
n Cable Modems
n DSP Front Ends
Connection Diagram
20055201
20040319
TRI-STATE®is a registered trademark of National Semiconductor Corporation.
© 2004 National Semiconductor Corporation DS200552 www.national.com
Ordering Information
ADC12DL066
Block Diagram
Industrial (−40˚C ≤ TA≤ +85˚C) Package
ADC12DL066CIVS 64 Pin TQFP
ADC12DL066EVAL Evaluation Board
www.national.com 2
20055202
Pin Descriptions and Equivalent Circuits
Pin No. Symbol Equivalent Circuit Description
ANALOG I/O
15
2
16
1
7V
V
A+
IN
B+
V
IN
A−
V
IN
B−
V
IN
REF
11 INT/EXT REF
Differential analog input pins. With a 1.0V reference voltage
the differential full-scale input signal level is 2.0 V
each input pin voltage centered on a common mode voltage,
. The negative input pins may be connected to VCMfor
V
CM
single-ended operation, but a differential input signal is
required for best performance.
Reference input. This pin should be bypassed to AGND with
a 0.1 µF capacitor when an external reference is used. V
is 1.0V nominal and should be between 0.8V to 1.5V.
Reference source select pin. With a logic low at this pin the
internal 1.0V reference is selected and the V
not be driven. With a logic high on this pin an external
reference voltage should be applied to V
REF
input pin 7.
REF
with
P-P
pin need
ADC12DL066
REF
13
5
14
4
12
6
DIGITAL I/O
60 CLK
22
41
59 PD
21 OF
V
RP
V
RP
VRMA
V
RM
V
RN
V
RN
OEA
OEB
A
B
These pins are high impedance reference bypass pins.
B
Bypass per Section 1.2. DO NOT LOAD these pins.
A
B
Digital clock input. The range of frequencies for this input is
as specified in the electrical tables with guaranteed
performance at 66 MHz. The input is sampled on the rising
edge of this input.
OEA and OEB are the output enable pins that, when low,
holds their respective data output pins in the active state.
When either of these pins is high, the corresponding outputs
are in a high impedance state.
PD is the Power Down input pin. When high, this input puts
the converter into the power down mode. When this pin is
low, the converter is in the active mode.
Output Format pin. A logic low on this pin causes output
data to be in offset binary format. A logic high on this pin
causes the output data to be in 2’s complement format.
www.national.com3
Pin Descriptions and Equivalent Circuits (Continued)
Pin No. Symbol Equivalent Circuit Description
ADC12DL066
24–29
34–39
42–47
52–57
ANALOG POWER
9, 18, 19,
62, 63
3, 8, 10, 17,
20, 61, 64
DIGITAL POWER
33, 48 V
32, 49 DGND The ground return for the digital supply.
30, 51 V
23, 31, 40,
50, 58
DA0–DA11
Digital data output pins that make up the 12-bit conversion
results of their respective converters. DA0 and DB0 are the
LSBs, while DA11 and DB11 are the MSBs of the output
word. Output levels are TTL/CMOS compatible.
DB0–DB11
Positive analog supply pins. These pins should be connected
V
A
to a quiet +3.3V source and bypassed to AGND with 0.1 µF
capacitors located within 1 cm of these power pins, and with
a 10 µF capacitor.
AGND The ground return for the analog supply.
Positive digital supply pin. This pin should be connected to
D
the same quiet +3.3V source as is V
DGND with a 0.1 µF capacitor located within 1 cm of the
power pin and with a 10 µF capacitor.
Positive digital supply pin for the ADC12DL066’s output
drivers. This pin should be connected to a voltage source of
+2.4V to V
DR
capacitor. If the supply for this pin is different from the
supply used for V
a 10 µF capacitor. V
. All bypass capacitors should be located within 1 cm of
V
D
and be bypassed to DR GND with a 0.1 µF
D
and VD, it should also be bypassed with
A
DR
the supply pin.
The ground return for the digital supply for the
ADC12DL066’s output drivers. These pins should be
DR GND
connected to the system digital ground, but not be
connected in close proximity to the ADC12DL066’s DGND or
AGND pins. See Section 5 (Layout and Grounding) for more
details.
and be bypassed to
A
should never exceed the voltage on
www.national.com 4
ADC12DL066
Absolute Maximum Ratings (Notes 1,
2)
If Military/Aerospace specified devices are required,
please contact the National Semiconductor Sales Office/
Distributors for availability and specifications.
or V
A
+0.3V)
±
25 mA
±
50 mA
4.2V
V
A,VD,VDR
|V
| ≤ 100 mV
A–VD
Voltage on Any Input or Output Pin −0.3V to (V
Input Current at Any Pin (Note 3)
Package Input Current (Note 3)
Package Dissipation at T
= 25˚C See (Note 4)
A
D
Operating Ratings (Notes 1, 2)
Operating Temperature −40˚C ≤ T
Supply Voltage (V
Output Driver Supply (V
V
Input 0.8V to 1.5V
REF
CLK, PD, OE
) +3.0V to +3.6V
A,VD
) +2.4V to V
DR
−0.05V to (VD+ 0.05V)
Analog Input Pins 0V to (V
V
CM
|AGND–DGND| ≤100mV
≤ +85˚C
A
A
0.5V to 1.5V
ESD Susceptibility
Human Body Model (Note 5) 2500V
Machine Model (Note 5) 250V
Soldering Temperature,
Infrared, 10 sec. (Note 6) 235˚C
Storage Temperature −65˚C to +150˚C
Converter Electrical Characteristics
Unless otherwise specified, the following specifications apply for AGND = DGND = DR GND = 0V, VA=VD= +3.3V, VDR=
+2.5V, PD = 0V, INT/EXT REF pin = +3.3V, V
face limits apply for TJ=T
MIN
to T
: all other limits TJ= 25˚C (Notes 7, 8, 9)
MAX
REF
= +1.0V, f
Symbol Parameter Conditions
STATIC CONVERTER CHARACTERISTICS
Resolution with No Missing Codes 12 Bits (min)
INL Integral Non Linearity (Note 11)
DNL Differential Non Linearity
PGE Posiitive Gain Error
NGE Negative gain Error
TC GE Gain Error Tempco −40˚C ≤ T
V
TC
V
OFF
OFF
Offset Error (VIN+=VIN−) 0.18
Offset Error Tempco −40˚C ≤ TA≤ +85˚C 0.1 ppm/˚C
Under Range Output Code 0 0
Over Range Output Code 4095 4095
REFERENCE AND ANALOG INPUT CHARACTERISTICS
V
CM
C
IN
V
REF
Common Mode Input Voltage 1.0
VINInput Capacitance (each pin to
GND)
VIN= 2.5 Vdc
+ 0.7 V
rms
Reference Voltage (Note 13) 1.00
Reference Input Resistance 100 MΩ (min)
= 66 MHz, fIN= 10 MHz, tr=tf= 2 ns, CL= 15 pF/pin. Bold-
CLK
Typical
(Note 10)
±
1.2
±
0.5
±
0.2
±
0.2
≤ +85˚C 0.5 ppm/˚C
A
Limits
(Note 10)
±
3.0 LSB (max)
±
1.0 LSB (max)
±
3.6 %FS (max)
±
3.6 %FS (max)
+1.3
-0.9
%FS (max)
%FS (min)
Units
(Limits)
0.5 V (min)
1.5 V (max)
(CLK LOW) 8 pF
(CLK HIGH) 7 pF
0.8 V (min)
1.5 V (max)
D
− 0.5V)
www.national.com5
Converter Electrical Characteristics (Continued)
Unless otherwise specified, the following specifications apply for AGND = DGND = DR GND = 0V, VA=VD= +3.3V, VDR=
+2.5V, PD = 0V, INT/EXT REF pin = +3.3V, V
face limits apply for TJ=T
ADC12DL066
MIN
to T
: all other limits TJ= 25˚C (Notes 7, 8, 9)
MAX
REF
= +1.0V, f
Symbol Parameter Conditions
DYNAMIC CONVERTER CHARACTERISTICS
FPBW Full Power Bandwidth 0 dBFS Input, Output at −3 dB 450 MHz
= 1 MHz, VIN= −0.5 dBFS 66 dB
f
IN
f
= 10 MHz, VIN= −0.5 dBFS 66 64 dB (min)
SNR Signal-to-Noise Ratio
SINAD Signal-to-Noise and Distortion
ENOB Effective Number of Bits
THD Total Harmonic Distortion
H2 Second Harmonic Distortion
H3 Third Harmonic Distortion
SFDR Spurious Free Dynamic Range
IMD Intermodulation Distortion
IN
f
= 33 MHz, VIN= −0.5 dBFS 64 dB
IN
f
= 146 MHz, VIN= −0.5 dBFS 55 dB
IN
= 1 MHz, VIN= −0.5 dBFS 66 dB
f
IN
f
= 10 MHz, VIN= −0.5 dBFS 66 63.3 dB (min)
IN
f
= 33 MHz, VIN= −0.5 dBFS 63 dB
IN
f
= 146MHz, VIN= −0.5 dBFS 53 dB
IN
= 1 MHz, VIN= −0.5 dBFS 10.7 Bits
f
IN
f
= 10 MHz, VIN= −0,5 dBFS 10.7 10.2 Bits (min)
IN
f
= 33 MHz, VIN= −0,5 dBFS 10.3 Bits
IN
f
= 146MHz, VIN= −0,5 dBFS 8.7 Bits
IN
= 1 MHz, VIN= −0.5 dBFS −78 dB
f
IN
f
= 10 MHz, VIN= −0.5 dBFS −78 −67.8 dB (min)
IN
f
= 33 MHz, VIN= −0.5 dBFS −70 dB
IN
f
= 146MHz, VIN= −0.5 dBFS −59 dB
IN
= 1 MHz, VIN= −0.5 dBFS −90 dB
f
IN
f
= 10 MHz, VIN= −0.5 dBFS −85 −70.4 dB (min)
IN
f
= 33 MHz, VIN= −0.5 dBFS −72 dB
IN
f
= 146MHz, VIN= −0.5 dBFS −67 dB
IN
= 1 MHz, VIN= −0.5 dBFS −83 dB
f
IN
f
= 10 MHz, VIN= −0.5 dBFS −85 −71.0 dB (min)
IN
f
= 33 MHz, VIN= −0.5 dBFS −76 dB
IN
f
= 146MHz, VIN= −0.5 dBFS −66 dB
IN
= 1 MHz, VIN= −0.5 dBFS 79 dB
f
IN
f
= 10 MHz, VIN= −0.5 dBFS 81 68.5 dB (min)
IN
f
= 33 MHz, VIN= −0.5 dBFS 72 dB
IN
f
= 146MHz, VIN= −0.5 dBFS 63 dB
IN
f
= 9.6 MHz and 10.2 MHz,
IN
each = −6.0 dBFS
INTER-CHANNEL CHARACTERISTICS
Channel —Channel Offset Match
Channel — Channel Gain Match
10 MHz Tested, Channel;
Crosstalk
20 MHz Other Channel
10 MHz Tested, Channel;
195 MHz Other Channel
= 66 MHz, fIN= 10 MHz, tr=tf= 2 ns, CL= 15 pF/pin. Bold-
CLK
Typical
(Note 10)
Limits
(Note 10)
−64 dBFS
±
0.03 %FS
±
0.1 %FS
80 dB
63 dB
Units
(Limits)
www.national.com 6
DC and Logic Electrical Characteristics
Unless otherwise specified, the following specifications apply for AGND = DGND = DR GND = 0V, VA=VD= +3.3V, VDR=
+2.5V, PD = 0V, INT/EXT REF pin = +3.3V, V
face limits apply for TJ=T
MIN
to T
: all other limits TJ= 25˚C (Notes 7, 8, 9)
MAX
REF
= +1.0V, f
Symbol Parameter Conditions
CLK, PD, OE DIGITAL INPUT CHARACTERISTICS
V
V
I
I
C
IN(1)
IN(0)
IN(1)
IN(0)
IN
Logical “1” Input Voltage VD= 3.6V 2.0 V (min)
Logical “0” Input Voltage VD= 3.0V 1.0 V (max)
Logical “1” Input Current VIN= 3.3V 10 µA
Logical “0” Input Current VIN= 0V −10 µA
Digital Input Capacitance 5 pF
D0–D11 DIGITAL OUTPUT CHARACTERISTICS
V
V
I
OZ
+I
−I
C
OUT(1)
OUT(0)
SC
SC
OUT
Logical “1” Output Voltage I
Logical “0” Output Voltage I
TRI-STATE®Output Current
Output Short Circuit Source
Current
Output Short Circuit Sink Current V
= −0.5 mA
OUT
= 1.6 mA, VDR=3V 0.4 V (max)
OUT
= 2.5V or 3.3V 100 nA
V
OUT
V
= 0V −100 nA
OUT
= 0V −20 mA
V
OUT
OUT=VDR
Digital Output Capacitance 5 pF
POWER SUPPLY CHARACTERISTICS
I
A
I
D
I
DR
Analog Supply Current
Digital Supply Current
Digital Output Supply Current
Total Power Consumption
PSRR1 Power Supply Rejection Ratio
PSRR2 Power Supply Rejection Ratio
PD Pin = DGND, V
PD Pin = V
PD Pin = DGND
PD Pin = V
PD Pin = DGND, C
PD Pin = V
PD Pin = DGND, C
PD Pin = V
Rejection of Full-Scale Error with
= 3.0V vs. 3.6V
V
A
Rejection of Power Supply Noise with
10 MHz, 500 mV riding on V
= 66 MHz, fIN= 10 MHz, tr=tf= 2 ns, CL= 15 pF/pin. Bold-
CLK
Typical
(Note 10)
= 2.5V 2.3 V (min)
V
DR
V
=3V 2.7 V (min)
DR
Limits
(Note 10)
20 mA
D
D,fCLK
D,fCLK
D
= 1.0V
REF
=0
= 0 pF (Note 14)
L
=0
= 0 pF (Note 15)
L
177
14
31
8.7
<
0
686
75
237 mA (max)
34 mA (max)
2
895 mW (max)
56 dB
A
44 dB
Units
(Limits)
ADC12DL066
mA
mA
mA
mA
mW
AC Electrical Characteristics
Unless otherwise specified, the following specifications apply for AGND = DGND = DR GND = 0V, VA=VD= +3.3V, VDR=
+2.5V, PD = 0V, INT/EXT REF pin = +3.3V, V
face limits apply for TJ=T
MIN
to T
: all other limits TJ= 25˚C (Notes 7, 8, 9, 12)
MAX
REF
= +1.0V, f
Symbol Parameter Conditions
1
f
CLK
f
CLK
t
CH
t
CL
t
CONV
t
OD
t
AD
Maximum Clock Frequency 75 66 MHz (min)
2
Minimum Clock Frequency 15 MHz
Clock High Time 6.6 ns (min)
Clock Low Time 6.6 ns (min)
Conversion Latency 6
= 2.5V
V
Data Output Delay after Rising
CLK Edge
DR
V
= 3.3V
DR
Aperture Delay 2 ns
= 66 MHz, fIN= 10 MHz, tr=tf= 2 ns, CL= 15 pF/pin. Bold-
CLK
Typical
(Note 10)
Limits
(Note 10)
rising 6.6 9.0 ns (max)
falling 6.0 8.5 ns (max)
rising 6.4 9.0 ns (max)
falling 6.5 9.0 ns (max)
www.national.com7
Units
(Limits)
Clock
Cycles
Loading...