Rainbow Electronics ADC1251 User Manual
December 1994
ADC12451 Dynamically-Tested Self-Calibrating
12-Bit Plus Sign A/D Converter with Sample-and-Hold
Y
General Description
The ADC12451 is a CMOS 12-bit plus sign successive approximation analog-to-digital converter whose dynamic
specifications (S/N, THD, etc.) are tested and guaranteed.
On request, the ADC12451 goes through a self-calibration
cycle that adjusts linearity, zero and full-scale errors. The
ADC12451 also has the ability to go through an Auto-Zero
cycle that corrects the zero error during every conversion.
The analog input to the ADC12451 is tracked and held by
the internal circuitry, so an external sample-and-hold is not
required. The ADC12451 has a S
rectly controls the track-and-hold state of the A/D. A unipolar analog input voltage range (0V to
b
range (
5V toa5V) can be accommodated withg5V sup-
/H control input which di-
a
5V) or a bipolar
plies.
The 13-bit data result is available on the eight outputs of the
ADC12451 in two bytes, high-byte first and sign extended.
The digital inputs and outputs are compatible with TTL or
CMOS logic levels.
Applications
Y
Digital Signal Processing
Y
Audio
Telecommunications
Y
High Resolution Process Control
Y
Instrumentation
Features
Y
Self-calibration provides excellent temperature stability
Y
Internal sample-and-hold
Y
8-bit mP/DSP interface
Y
Bipolar input range with a singlea5V reference
Key Specifications
Y
Resolution 12 bits plus sign
Y
Conversion Time 7.7 ms (max)
Y
Sampling Rate 83 kHz (max)
Y
Bipolar Signal/Noise 73.5 dB (min)
Y
Total Harmonic Distortion
Y
Aperture Time 100 ns
Y
Aperture Jitter 100 ps
Y
Zero Error
Y
Positive Full-Scale Error
Y
Power Consumption
@
g
5V 113 mW (max)
b
78.0 dB (max)
g
2 LSB (max)
g
1.5 LSB (max)
ADC12451 Dynamically-Tested Self-Calibrating 12-Bit
Plus Sign A/D Converter with Sample-and-Hold
rms
Simplified Block Diagram
Connection Diagram
Dual-In-Line Package
Top View
TL/H/11025– 2
Ordering Information
Industrial
b
(
40§CsT
s
A
ADC12451CIJ J24A
Military
TL/H/11025– 1
b
(
55§CsT
s
A
ADC12451CMJ,
TRI-STATEÉis a registered trademark of National Semiconductor Corporation.
C
1995 National Semiconductor Corporation RRD-B30M115/Printed in U. S. A.
TL/H/11025
ADC12451CMJ/883
85§C)
125§C)
Package
Package
J24A
Absolute Maximum Ratings (Notes1&2)
If Military/Aerospace specified devices are required,
please contact the National Semiconductor Sales
Office/Distributors for availability and specifications.
Supply Voltage (V
Negative Supply Voltage (Vb)
Voltage at Logic Control Inputs
Voltage at Analog Inputs
(V
IN,VREF
AVCC-DVCC(Note 7) 0.3V
Input Current at any Pin (Note 3)
Package Input Current (Note 3)
Power Dissipation at 25
Storage Temperature Range
ESD Susceptability (Note 5) 2000V
Soldering Information
J Package (10 Seconds) 300
e
e
DV
CC
)(V
AVCC) 6.5V
CC
b
0.3V to (V
b
b
0.3V) to (V
C (Note 4) 875 mW
§
b
65§Ctoa150§C
CC
CC
b
a
a
g
g
6.5V
0.3V)
0.3V)
5mA
20 mA
§
Operating Ratings (Notes1&2)
Temperature Range T
ADC12451CIJ
ADC12451CMJ,
ADC12451CMJ/883
DVCCand AVCCVoltage
(Notes6&7) 4.5V to 5.5V
Negative Supply Voltage (V
Reference Voltage
(V
, Notes6&7) 3.5V to AV
REF
C
s
s
T
MIN
b
40§CsT
b
55§CsT
b
)
b
T
A
MAX
s
a
85§C
A
s
a
125§C
A
4.5V tob5.5V
a
50 mV
CC
Converter Electrical Characteristics
The following specifications apply for V
conversion control, and f
other limits T
e
T
A
J
e
3.5 MHz unless otherwise specified. Boldface limits apply for T
CLK
e
25§C. (Notes 6, 7 and 8)
CC
e
e
DV
AV
CC
CC
ea
5.0V, V
b
Symbol Parameter Conditions
STATIC CHARACTERISTICS
Positive Integral Linearity Error After Auto-Cal, (Notes 11 & 12)
Negative Integral Linearity Error After Auto-Cal, (Notes 11 & 12)
Positive or Negative Differential Linearity After Auto-Cal (Notes 11 & 12) 12 Bits
Zero Error (Notes 12 & 13) AZe‘‘0’’, f
CLK
e
After Auto-Cal Only
Positive Full-Scale Error (Note 12) AZe‘‘0’’, f
CLK
e
Auto-Cal Only
Negative Full-Scale Error (Note 12) AZe‘‘0’’, f
CLK
e
Auto-Cal Only
V
Analog Input Voltage V
IN
e
Power Supply Sensitivity Zero Error (Note 14) AV
Full-Scale Error
V
CC
REF
e
4.75V, V
DV
CC
e
5Vg5%,
b
Linearity Error
C
REFVREF
C
IN
Input Capacitance 80 pF
Analog Input Capacitance 65 pF
DYNAMIC CHARACTERISTICS
Bipolar Effective Bits (Note 17) f
Unipolar Effective Bits (Note 17) f
S/N Bipolar Signal to Noise Ratio (Note 17) f
e
IN
e
f
IN
e
IN
e
f
IN
e
IN
e
f
IN
e
f
IN
1 kHz, V
20.67 kHz, V
1 kHz, V
20.67 kHz, V
1 kHz, V
10 kHz, V
20.67 kHz, V
e
IN
e
IN
e
IN
e
IN
eb
5.0V, V
REF
ea
5.0V, using S/H input for
e
e
T
A
T
J
MIN
to T
Typical Limit Units
(Note 9) (Note 10, 19) (Limit)
g
(/2 LSB
g
(/2 LSB
1.75 MHz
1.75 MHz
1.75 MHz
eb
5Vg5%
g
4.85V 12.6 Bits
e
g
4.85V 12.6 11.9 Bits(min)
IN
4.85 V
p-p
e
4.85 V
IN
g
4.85V 78 dB
g
4.85V 78 dB
e
g
4.85V 78 73.5 dB(min)
IN
g
1 LSB
g2/g
g
1 LSB
g
1.5/g2.5 LSB(max)
g
1 LSB
g
1.5/g3.0 LSB(max)
b
b
0.05 V(min)
a
V
CC
g
(/8 LSB
g
(/8 LSB
g
(/8 LSB
11.8 Bits
11.8 11.1 Bits(min)
p-p
3.0 LSB(max)
0.05 V(max)
MAX
; all
2
Converter Electrical Characteristics (Continued)
The following specifications apply for V
conversion control, and f
other limits T
e
T
A
J
e
3.5 MHz unless otherwise specified. Boldface limits apply for T
CLK
e
25§C. (Notes 6, 7 and 8)
CC
e
e
AV
CC
ea
DV
CC
5.0V, V
b
eb
Symbol Parameter Conditions
DYNAMIC CHARACTERISTICS (Continued)
S/N Unipolar Signal to Noise Ratio (Note 17) f
THD Bipolar Total Harmonic Distortion (Note 17) f
THD Unipolar Total Harmonic Distortion (Note 17) f
Bipolar Peak Harmonic or Spurious Noise f
(Note 17)
Unipolar Peak Harmonic or Spurious Noise f
(Note 17)
Bipolar Two Tone Intermodulation Distortion V
(Note 17) f
Unipolar Two Tone Intermodulation Distortion V
(Note 17) f
b
3 dB Bipolar Full Power Bandwidth V
b
3 dB Unipolar Full Power Bandwidth V
e
IN
e
f
IN
e
f
IN
e
IN
e
f
IN
e
IN
e
f
IN
e
IN
e
f
IN
e
f
IN
e
IN
e
f
IN
e
f
IN
e
IN
e
IN2
e
IN
e
IN2
e
IN
e
IN
1 kHz, V
10 kHz, V
20.67 kHz, V
1 kHz, V
20.67 kHz, V
1 kHz, V
20.67 kHz, V
1 kHz, V
10 kHz, V
20 kHz, V
1 kHz, V
10 kHz, V
20 kHz, V
g
20 kHz
4.85 V
20 kHz
g
4.85 V
e
4.85 V
IN
e
IN
IN
e
g
IN
IN
e
4.85 V
IN
IN
e
g
IN
e
IN
e
IN
e
4.85 V
IN
e
IN
e
IN
4.85V, f
IN1
p-p,fIN1
4.85V, (Note 17) 25 20.67 kHz(min)
, (Note 17) 32 20.67 kHz(min)
p-p
Aperture Time 100 ns
Aperture Jitter 100 ps
5.0V, V
p-p
4.85 V
e
4.85 V
4.85V
e
g
4.85V
p-p
e
4.85 V
4.85V
g
4.85V
g
4.85V
p-p
4.85 V
4.85 V
e
19.375 kHz,
e
19.375 kHz,
p-p
p-p
p-p
ea
REF
5.0V, using S/H input for
e
e
T
A
T
J
MIN
Typical Limit Units
(Note 9) (Note 10, 19) (Limit)
73 dB
73 dB
p-p
p-p
73 68.7 dB(min)
b
82 dB
b
b
b
b
b
b
b
b
b
b
b
b
80
78.0 dB(max)
82 dB
b
80
73.1 dB(max)
88 dB
84 dB
80 dB
90 dB
86 dB
82 dB
78
78
to T
MAX
dB(max)
dB(max)
; all
rms
3
Digital and DC Electrical Characteristics
The following specifications apply for DV
otherwise specified. Boldface limits apply for T
CC
e
ea
AV
A
CC
5.0V, V
e
e
T
T
J
MIN
Symbol Parameter Condition
V
IN(1)
V
IN(0)
I
IN(1)
I
IN(0)
a
V
T
b
V
T
V
H
V
OUT(1)
V
OUT(0)
I
OUT
I
SOURCE
I
SINK
DI
CC
AI
CC
b
I
Logical ‘‘1’’ Input Voltage for V
All Inputs except CLK IN
Logical ‘‘0’’ Input Voltage for V
All Inputs except CLK IN
Logical ‘‘1’’ Input Current V
Logical ‘‘0’’ Input Current V
CLK IN Positive-Going
Threshold Voltage
CLK IN Negative-Going
Threshold Voltage
CLK IN Hysteresis
[
V
a
(min)bV
T
b
]
(max)
T
Logical ‘‘1’’ Output Voltage V
Logical ‘‘0’’ Output Voltage V
TRI-STATEÉOutput Leakage V
Current
Output Source Current V
Output Sink Current V
DVCCSupply Current CSe‘‘1’’ 1 2.5 mA(max)
AVCCSupply Current CSe‘‘1’’ 2.8 10 mA(max)
VbSupply Current CSe‘‘1’’ 2.8 10 mA(max)
e
5.25V
CC
e
4.75V
CC
e
5V 0.005 1 mA(max)
IN
e
0V
IN
e
4.75V:
CC
eb
I
OUT
eb
I
OUT
e
4.75V,
CC
e
I
1.6 mA
OUT
e
0V
OUT
e
V
5V 0.01 3 mA(max)
OUT
e
0V
OUT
e
5V 20 8.0 mA(min)
OUT
b
to T
eb
MAX
5.0V, V
; all other limits T
REF
ea
5.0V, and f
e
T
A
J
e
3.5 MHz unless
CLK
e
25§C. (Notes 6 and 7)
Typical Limit Units
(Note 9) (Note 10, 19) (Limit)
2.0 V(min)
0.8 V(max)
b
0.005
b
1 mA(max)
2.8 2.7 V(min)
2.1 2.3 V(max)
0.7 0.4 V(min)
360 mA 2.4 V(min)
10 mA 4.5 V(min)
0.4 V(max)
b
0.01
b
20
b
3 mA(max)
b
6.0 mA(min)
AC Electrical Characteristics
The following specifications apply for DV
Boldface limits apply for T
e
T
A
J
e
CC
e
T
MIN
to T
AV
CC
MAX
ea
; all other limits T
Symbol Parameter Conditions
f
CLK
Clock Frequency MHz
Clock Duty Cycle 50 %
t
C
t
C
Conversion Time using WR 27(1/f
to start a Conversion
e
f
3.5 MHz, AZe‘‘1’’ 7.7 7.95 ms(max)
CLK
e
f
1.75 MHz, AZe‘‘0’’ 15.4 15.65 ms(max)
CLK
Conversion Time using S/H AZe‘‘1’’ 34(1/f
to start a Conversion
e
f
3.5 MHz, AZe‘‘1’’ 9.7 9.95 ms(max)
CLK
5.0V, V
4
b
eb
e
A
e
5.0V, t
T
t
r
f
e
25§C. (Notes 6 and 7)
J
e
20 ns unless otherwise specified.
Typical Limit Units
(Note 9) (Note 10, 19) (Limit)
0.5 MHz(min)
6.0 3.5 MHz(max)
40 %(min)
60 %(max)
) 27(1/f
CLK
) 34(1/f
CLK
)a250 ns (max)
CLK
)a250 ns (max)
CLK
AC Electrical Characteristics (Continued)
The following specifications apply for DV
Boldface limits apply for T
e
T
A
J
e
CC
e
T
MIN
to T
AV
CC
MAX
ea
; all other limits T
Symbol Parameter Conditions
t
A
t
IA
t
ZA
t
D(EOC)L
t
CAL
t
W(CAL)L
t
W(WR)L
t
ACC
t0H,t
t
PD(INT)
t
RR
Note 1: Absolute Maximum Ratings indicate limits beyond which damage to the device may occur. Operating Ratings indicate conditions for which the device is
functional, but do not guarantee specific performance limits. For guaranteed specifications and test conditions, see the Electrical Characteristics. The guaranteed
specifications apply only for the test conditions listed. Some performance characteristics may degrade when the device is not operated under the listed test
conditions.
Note 2: All voltages are measured with respect to AGND and DGND, unless otherwise specified.
Note 3: When the input voltage (V
5 mA. The 20 mA maximum package input current rating allows the voltage at any four pins, with an input current limit of 5 mA, to simultaneously exceed the power
supply voltages.
Note 4: The power dissipation of this device under normal operation should never exceed 191 mW (Quiescent Power Dissipation
output). Caution should be taken not to exceed absolute maximum power rating when the device is operating in a severe fault condition (ex. when any inputs or
outputs exceed the power supply). The maximum power dissipation must be derated at elevated temperatures and is dictated by T
temperature), i
is P
resistance (i
Note 5: Human body model, 100 pF discharged through a 1.5 kX resistor.
Note 6: Two on-chip diodes are tied to the analog input as shown below. Errors in the A/D conversion can occur if these diodes are forward biased more than
50 mV. This means that if AV
Acquisition Time R
(Note 15)
SOURCE
Internal Acquisition Time
(when using WR
Auto Zero Time
Acquisition Time
Control Only)
a
f
CLK
e
Delay from Hold Command Using WR Control 200 350 ns(max)
to Falling Edge of EOC
Using S/H Control 100 150 ns(max)
Calibration Time 1399 (1/f
e
f
CLK
Calibration Pulse Width (Note 16) 60 200 ns(min)
minimum WR Pulse Width 60 200 ns(min)
maximum Access Time C
(Delay from Falling Edge of 50 95 ns(max)
RD
to Output Data Valid)
TRI-STATE Control (Delay R
1H
from Rising Edge of RD C
to Hi-Z State)
e
100 pF
L
e
1kX,
L
e
100 pF 30 70 ns(max)
L
maximum Delay from Falling Edge
of RD
or WR to Reset of INT
Delay between Successive RD Pulses 30 60 ns(min)
) at any pin exceeds the power supply rails (V
IN
(package junction to ambient thermal resistance), and TA(ambient temperature). The maximum allowable power dissipation at any temperature
JA
e
b
(T
DMax
TA)/iJAor the number given in the Absolute Maximum Ratings, whichever is lower. For this device, T
JMax
) of the ADC12451 with CMJ, and CIJ suffixes when board mounted is 51§C/W.
JA
and DVCCare minimum (4.75 VDC) and Vbis maximum (b4.75 VDC), the analog input full-scale voltage must be
CC
b
5.0V, V
eb
e
A
e
5.0V, t
T
t
r
f
e
25§C. (Notes 6 and 7)
J
e
20 ns unless otherwise specified.
Typical Limit Units
(Note 9) (Note 10, 19) (Limit)
e
50X
3.5 3.5 ms(min)
7(1/f
) 7(1/f
33(1/f
CLK
) 33(1/f
CLK
CLK)
)a250 ns (max)
CLK
(max)
1.75 MHz 18.8 19.05 ms(max)
) 1399 (1/f
CLK
) (max)
CLK
3.5 MHz 399 400 ms(max)
100 175 ns(max)
k
IN
Vbor V
l
(AVCCor DVCC), the current at that pin should be limited to
IN
a
1 TTL Load on each digital
(maximum junction
JMax
e
150§C, and the typical thermal
JMax
s
g
4.8 VDC.
TL/H/11025– 4
5
Electrical Characteristics (Continued)
Note 7: A diode exists between AVCCand DVCCas shown below.
Figures 1b
TL/H/11025– 5
and1c).
To guarantee accuracy, it is required that the AVCCand DVCCbe connected together to a power supply with separate bypass filters at each VCCpin.
Note 8: Accuracy is guaranteed at f
Note 9: Typicals are at T
Note 10: Limits are guaranteed to National’s AOQL (Average Outgoing Quality Level).
Note 11: Positive linearity error is defined as the deviation of the analog value, expressed in LSBs, from the straight line that passes through positive full scale and
zero. For negative linearity error the straight line passes through negative full scale and zero. (See
Note 12: The ADC12451’s self-calibration technique ensures linearity, full scale, and offset errors as specified, but noise inherent in the self-calibration process will
result in a repeatability uncertainty of
Note 13: If T
Note 14: After an Auto-Zero or Auto-Cal cycle at the specified power supply extremes.
Note 15: When using the WR
end of the interval of t
clock is synchronous to the rising edge of WR
Note 16: The CAL
Note 17: The specifications for these parameters are valid after an Auto-Cal cycle has been completed.
Note 18: The ADC12451 reference ladder is composed solely of capacitors.
Note 19: A military RETS electrical test specification is available on request. At time of printing, the ADC12451CMJ/883 RETS specification complies fully with the
boldface limits in this column.
A
J
changes then an Auto-Zero or Auto-Cal cycle will have to be re-started, see the typical performance characteristic curves.
, therefore making tAend a minimum 6 clock periods or a maximum 7 clock periods after the rising edge of WR. If the falling edge of the
A
line must be high before a conversion is started.
e
3.5 MHz. At higher or lower clock frequencies accuracy may degrade, see the typical performance characteristic curves.
CLK
e
25§C and represent most likely parametric norm.
g
0.20 LSB.
control to start a conversion if the clock is asynchronous to the rising edge of WR an uncertainty of one clock period will exist in the
then tAwill end exactly 6.5 clock periods after the rising edge of WR. This does not occur when S/H control is used.
FIGURE 1a. Transfer Characteristic
6
TL/H/11025– 6
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