Rainbow Electronics ADC1241 User Manual

ADC1241 Self-Calibrating 12-Bit Plus Sign mP-Compatible A/D Converter with Sample-and-Hold

November 1994

General Description

The ADC1241 is a CMOS 12-bit plus sign successive approximation analog-to-digital converter. On request, the ADC1241 goes through a self-calibration cycle that adjusts positive linearity and full-scale errors to less than each and zero error to less than

g

1 LSB. The ADC1241

g

(/2 LSB

also has the ability to go through an Auto-Zero cycle that corrects the zero error during every conversion.

The analog input to the ADC1241 is tracked and held by the internal circuitry, and therefore does not require an external sample-and-hold. A unipolar analog input voltage range (0V

a

to

5V) or a bipolar range (b5V toa5V) can be accom-

modated with

g

5V supplies.

The 13-bit word on the outputs of the ADC1241 gives a 2’s complement representation of negative numbers. The digital inputs and outputs are compatible with TTL or CMOS logic levels.

Applications

Y

Digital Signal Processing

Y

High Resolution Process Control

Y

Instrumentation

Simplified Schematic

Key Specifications

Y

Resolution 12 Bits plus Sign

Y

Conversion Time 13.8ms (max)

Y

Linearity Error

Y

Zero Error

Y

Positive Full Scale Error

Y

Power Consumption 70mW (max)

g

(/2 LSB (g0.0122%) (max)

g

1LSB (max)

g

1LSB (max)

Features

Y

Self-calibrating

Y

Internal sample-and-hold

Y

Bipolar input range withg5V supplies and single

a

5V reference

Y

No missing codes over temperature

Y

TTL/MOS input/output compatible

Y

Standard 28-pin DIP

TRI-STATEÉis a registered trademark of National Semiconductor Corporation.

Connection Diagram

Dual-In-Line Package

Top View

TL/H/10554– 2

Order Number ADC1241CMJ,

ADC1241CMJ/883, ADC1241BIJ or

ADC1241CIJ

See NS Package Number J28A

TL/H/10554– 1

C

1995 National Semiconductor Corporation RRD-B30M115/Printed in U. S. A.

TL/H/10554

Absolute Maximum Ratings (Notes1&2)

If Military/Aerospace specified devices are required, please contact the National Semiconductor Sales Office/Distributors for availability and specifications.

Supply Voltage (V

Negative Supply Voltage (Vb)

Voltage at Logic Control Inputs

Voltage at Analog Input (VIN)(V

AVCC-DVCC(Note 7) 0.3V

Input Current at any Pin (Note 3)

Package Input Current (Note 3)

Power Dissipation at 25§C (Note 4) 875 mW

Storage Temperature Range

ESD Susceptability (Note 5) 2000V

Soldering Information

J Package (10 sec) 300

CC

e

DV

AVCC) 6.5V

CC

b

0.3V to (V

0.3V) to (V

b

6.5V

a

0.3V)

CC

a

0.3V)

CC

g

5mA

g

20 mA

65§Ctoa150§C

§

Operating Ratings (Notes1&2)

Temperature Range T

ADC1241BIJ, ADC1241CIJ ADC1241CMJ, ADC1241CMJ/883

DVCCand AVCCVoltage

(Notes6&7) 4.5V to 5.5V

Negative Supply Voltage (V

Reference Voltage

(V

, Notes6&7) 3.5V to AV

REF

C

s

T

MIN

b

40§CsT

b

55§CsT

b

)

b

T

A

MAX

s

a

85§C

A

s

a

125§C

A

4.5V tob5.5V

a

50 mV

CC

Converter Electrical Characteristics

The following specifications apply for V unless otherwise specified. Boldface limits apply for T and 8)

CC

e

DV

AV

CC

A

ea

CC

e

T

J

5.0V, V

T

MIN

b

to T

Symbol Parameter Conditions

STATIC CHARACTERISTICS

Positive Integral ADC1241BIJ After Auto-Cal Linearity Error

ADC1241CMJ, CIJ

(Notes 11 & 12)

Negative Integral ADC1241BIJ After Auto-Cal Linearity Error

ADC1241CMJ, CIJ

(Notes 11 & 12)

Differential Linearity After Auto-Cal (Notes 11 & 12)

Zero Error After Auto-Zero or Auto-Cal

(Notes 12 & 13)

Positive Full-Scale Error After Auto-Cal (Note 12)

Negative Full-Scale Error After Auto-Cal (Note 12)

C

V

REF

IN

Input Capacitance 80 pF

REF

Analog Input Capacitance 65 pF

Analog Input Voltage V

e

Power Supply Zero Error (Note 14) AV Sensitivity

Full-Scale Error

V

CC

REF

e

4.75V, V

DV

CC

e

b

Linearity Error

DYNAMIC CHARACTERISTICS

S/(NaD) Unipolar Signal-to-NoiseaDistortion f

Ratio (Note 17)

S/(NaD) Bipolar Signal-to-NoiseaDistortion f

Ratio (Note 17)

Unipolar Full Power Bandwidth (Note 17) V

Bipolar Full Power Bandwidth (Note 17) V

t

Ap

Aperture Time 100 ns

e

1 kHz, V

IN

e

10 kHz, V

f

IN

e

1 kHz, V

IN

e

10 kHz, V

f

IN

e

0V to 4.85V 32 kHz

IN

e

g

IN

4.85 V

e

IN

e

IN

p-p

Aperture Jitter 100 ps

eb

5.0V, V

; all other limits T

MAX

5Vg5%,

eb

5Vg5%

4.85 V

p-p

e

4.85 V

p-p

g

4.85 V

e

g

4.85 V

ea

REF

5.0V, and f

e

T

A

J

e

25§C. (Notes 6, 7

Typical Limit Units

(Note 9) (Notes 10, 18) (Limit)

g

(/2 LSB(max)

g

1 LSB max

g

1 LSB(max)

g

1 LSB(max)

12 Bits(min)

g

1 LSB(max)

g

(/2

g

(/8 LSB

g

(/8 LSB

g

(/8 LSB

g

1 LSB(max)

g1/g

b

a

V

CC

72 dB

p-p

76 dB

p-p

25 kHz

e

2.0 MHz

CLK

2 LSB(max)

0.05 V(min)

0.05 V(max)

rms

2

Digital and DC Electrical Characteristics

The following specifications apply for V unless otherwise specified. Boldface limits apply for T (Notes 6 and 7)

CC

e

AV

ea

CC

e

T

A

J

DV

CC

Symbol Parameter Condition

V

IN(1)

V

IN(0)

I

IN(1)

I

IN(0)

a

V

T

b

V

T

V

H

V

OUT(1)

V

OUT(0)

I

OUT

I

SOURCE

I

SINK

DI

CC

AI

CC

b

I

Logical ‘‘1’’ Input Voltage for V All Inputs except CLK IN

Logical ‘‘0’’ Input Voltage for V All Inputs except CLK IN

Logical ‘‘1’’ Input Current V

Logical ‘‘0’’ Input Current V

CLK IN Positive-Going Threshold Voltage

CLK IN Negative-Going Threshold Voltage

CLK IN Hysteresis

[

V

a

(min)bV

T

b

]

(max)

T

Logical ‘‘1’’ Output Voltage V

Logical ‘‘0’’ Output Voltage V

TRI-STATEÉOutput Leakage V Current

Output Source Current V

Output Sink Current V

DVCCSupply Current f

AVCCSupply Current f

VbSupply Current f

e

5.25V

CC

e

4.75V

CC

e

5V 0.005 1 mA(max)

IN

e

0V

IN

e

4.75V:

CC

eb

I

OUT

I

OUT

I

OUT

V

CLK

360 mA 2.4 V(min)

eb

10 mA 4.5 V(min)

e

4.75V

CC

e

1.6 mA

e

0V

OUT

e

5V 0.01 3 mA(max)

OUT

e

0V

OUT

e

5V 20 8.0 mA(min)

OUT

e

2 MHz, CSe‘‘1’’ 1 2 mA(max)

e

2 MHz, CSe‘‘1’’ 2.8 6 mA(max)

e

2 MHz, CSe‘‘1’’ 2.8 6 mA(max)

5.0V, V

e

b

eb

to T

MAX

5.0V, V

; all other limits T

T

MIN

REF

ea

5.0V, and f

e

T

A

J

CLK

25§C.

e

2.0 MHz

Typical Limit Units

(Note 9) (Notes 10, 18) (Limits)

2.0 V(min)

0.8 V(max)

b

0.005

b

1 mA(max)

2.8 2.7 V(min)

2.1 2.3 V(max)

0.7 0.4 V(min)

0.4

b

0.01

b

20

b

3 mA(max)

b

6.0 mA(min)

V(max)

3

AC Electrical Characteristics

The following specifications apply for DV

Boldface limits apply for T

e

T

A

J

e

CC

e

T

MIN

to T

AV

CC

MAX

ea

; all other limits T

Symbol Parameter Conditions

f

CLK

Clock Frequency 2.0 MHz

5.0V, V

b

eb

e

A

e

5.0V, t T

t

r

f

e

25§C. (Notes 6 and 7)

J

e

20 ns unless otherwise specified.

Typical Limit Units

(Note 9) (Notes 10, 18) (Limits)

0.5 MHz(min)

4.0 MHZ(max)

Clock Duty Cycle 50 %

40 %(min) 60 %(max)

t

C

t

A

t

Z

t

CAL

t

W(CAL)L

t

W(WR)L

t

ACC

t0H,t

t

PD(INT)

Note 1: Absolute Maximum Ratings indicate limits beyond which damage to the device may occur. Operating Ratings indicate conditions for which the device is functional, but do not guarantee specific performance limits. For guaranteed specifications and test conditions, see the Electrical Characteristics. The guaranteed specifications apply only for the test conditions listed. Some performance characteristics may degrade when the device is not operated under the listed test conditions.

Note 2: All voltages are measured with respect to AGND and DGND, unless otherwise specified.

Note 3: When the input voltage (V

5 mA. The 20 mA maximum package input current rating allows the voltage at any four pins, with an input current limit of 5 mA, to simultaneously exceed the power supply voltages.

Note 4: The maximum power dissipation must be derated at elevated temperatures and is dictated by T junction to ambient thermal resistance), and T TA)/iJAor the number given in the Absolute Maximum Ratings, whichever is lower. For this device, T ADC1241 with CMJ, BIJ, and CIJ suffixes when board mounted is 47

Note 5: Human body model, 100 pF discharged through a 1.5 kX resistor.

Note 6: Two on-chip diodes are tied to the analog input as shown below. Errors in the A/D conversion can occur if these diodes are forward biased more than

50 mV.

Conversion Time 27(1/f

e

f

2.0 MHz 13.5 ms

CLK

Acquisition Time R (Note 15) f

CLK

e

SOURCE

50X 7(1/f

e

2.0 MHz 3.5 ms

) 27(1/f

CLK

) 7(1/f

CLK

)a300 ns (max)

CLK

)a300 ns (max)

CLK

Auto Zero Time 26 26 1/f

e

f

2.0 MHz 13 ms

CLK

Calibration Time 1396 1/f

e

f

2.0 MHz 698 706 ms (max)

CLK

Calibration Pulse Width (Note 16) 60 200 ns(min)

Minimum WR Pulse Width 60 200 ns(min)

Maximum Access Time C (Delay from Falling Edge of 50 85 ns(max) RD

to Output Data Valid)

TRI-STATE Control (Delay R

1H

from Rising Edge of RD to Hi-Z State)

Maximum Delay from Falling Edge of RD

or WR to Reset of INT

) at any pin exceeds the power supply rails (V

IN

(ambient temperature). The maximum allowable power dissipation at any temperature is P

A

e

100 pF

L

e

1kX,

L

e

C

100 pF 30 90 ns(max)

L

100 175 ns(max)

C/W.

§

k

IN

Vbor V

l

(AVCCor DVCC), the current at that pin should be limited to

IN

(maximum junction temperature), iJA(package

JMAX

e

125§C, and the typical thermal resistance ( iJA)ofthe

Jmax

Dmax

CLK

e

(T

Jmax

(max)

b

This means that if AVCCand DVCCare minimum (4.75 VDC) and Vbis maximum (b4.75 VDC), full-scale must bes4.8 VDC.

TL/H/10554– 3

4

AC Electrical Characteristics (Continued)

Note 7: A diode exists between AVCCand DVCCas shown below.

Figures 1b

TL/H/10554– 4

and1c).

A

To guarantee accuracy, it is required that the AVCCand DVCCbe connected together to a power supply with separate bypass filters at each VCCpin.

Note 8: Accuracy is guaranteed at f Characteristics Section.

Note 9: Typicals are at T

Note 10: Limits are guaranteed to National’s AOQL (Average Outgoing Quality Level).

Note 11: Positive linearity error is defined as the deviation of the analog value, expressed in LSBs, from the straight line that passes through positive full scale and

zero. For negative linearity error the straight line passes through negative full scale and zero. (See

Note 12: The ADC1241’s self-calibration technique ensures linearity, full scale, and offset errors as specified, but noise inherent in the self-calibration process will result in a repeatability uncertainty of

Note 13: If T

Note 14: After an Auto-Zero or Auto-Cal cycle at the specified power supply extremes.

Note 15: If the clock is asynchronous to the falling edge of WR

6 clock periods and the maximum t periods.

Note 16: The CAL

Note 17: The specifications for these parameters are valid after an Auto-Cal cycle has been completed.

Note 18: A military RETS electrical test specification is available on request. At time of printing, the ADC1241CMJ/883 RETS specification complies fully with the

boldface limits in this column.

A

e

25§C and represent most likely parametric norm.

J

changes then an Auto-Zero or Auto-Cal cycle will have to be re-started, see the typical performance characteristic curves.

line must be high before any other conversion is started.

e

2.0 MHz. At higher and lower clock frequencies accuracy may degrade. See curves in the Typical Performance

CLK

g

0.20 LSB.

e

7 clock periods. If the falling edge of the clock is synchronous to the rising edge of WR then tAwill be exactly 6.5 clock

A

an uncertainty of one clock period will exist in the interval of tA, therefore making the minimum t

e

FIGURE 1a. Transfer Characteristic

5

TL/H/10554– 5

Rainbow Electronics ADC1241 User Manual

Specifications and Main Features

Frequently Asked Questions

User Manual