Rainbow Electronics ADC12081 User Manual

November 2002

ADC12081
12-Bit, 5 MHz Self-Calibrating, Pipelined A/D Converter
with Internal Sample & Hold

General Description

The ADC12081 is a monolithic CMOS analog-to-digital con­verter capable of converting analog input signals into 12-bit
digital words at 5 megasamples per second (MSPS). The
ADC12081 utilizes an innovative pipeline architecture to
minimize die size and power consumption. The ADC12081
uses self-calibration and error correction to maintain accu­racy and performance over temperature.

The ADC12081 converter operates on a 5V power supply
and can digitize analog input signals in the range of 0 to 2V.
A single convert clock controls the conversion operation. All
digital I/O is TTL compatible.

The ADC12081 is designed to minimize external compo­nents necessary for the analog input interface. An internal
sample-and-hold circuit samples the analog input and an
internal amplifier buffers the reference voltage input.

The ADC12081 is available in the 32-lead LQFP package
and is designed to operate over the extended commercial
temperature range of -40˚C to +85˚C.

Features

n Single 5V power supply
n Simple analog input interface

n Internal Sample-and-hold
n Internal Reference buffer amplifier
n Low power consumption

Key Specifications

n Resolution 12 Bits
n Conversion Rate 5 Msps (min)
n DNL
n SNR 68 dB (typ)
n ENOB 10.9 Bits (typ)
n Analog Input Range 2 Vpp (min)
n Supply Voltage +5V
n Power Consumption, 5 MHz 105 mW (typ)

±

0.35 LSB (typ)

Applications

n Image processing front end
n PC-based data acquisition
n Scanners
n Fax machines
n Waveform digitizer

ADC12081 12-Bit, 5 MHz Self-Calibrating, Pipelined A/D Converter with Internal Sample & Hold

±

5%

Connection Diagram

10015001

© 2002 National Semiconductor Corporation DS100150 www.national.com

Ordering Information

ADC12081

ADC12081CIVT 32 pin LQFP

ADC12181 EVAL Evaluation Board

Simplified Block Diagram

Industrial

(−40˚C ≤ TA ≤ +85˚C) Package

10015002

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Pin Descriptions and Equivalent Circuits #2

No. Symbol Equivalent Circuit Description

Analog signal input. With a 2.0V reference voltage,

2V

1V

32 V

31 V

IN

REF

RP

RM

input signal voltages in the range of 0 to 2.0 Volts
will be converted. See section 1.2.

Reference voltage input. This pin should be driven
from an accurate, stable reference source in the
range of 1.8 to 2.2V and bypassed to a low-noise
analog ground with a monolithic ceramic capacitor,
nominally 0.01µF. See section 1.1.

Positive reference bypass pin. Bypass with a 0.1µF
capacitor. Do not connect anything else to this pin.
See section 3.1

Reference midpoint bypass pin. Bypass with a 0.1µF
capacitor. Do not connect anything else to this pin.
See section 3.1

ADC12081

30 V

RN

10 CLOCK

8 CAL

7PD

11 OE

28 OR

29 READY

Negative reverence bypass pin. Bypass with a 0.1µF
capacitor. Do not connect anything else to this pin.
See section 3.1

Sample Clock input, TTL compatible. Maximum
amplitude should not exceed 3V.

Calibration request, active High. Calibration cycle
starts when CAL returns to logic low. CAL is ignored
during power-down mode. See section 2.2.

Power-down, active High, ignored during calibration
cycle. See paragraph 2.4

Output enable control, active low. When this pin is
high the data outputs are in Tri-state
(high-impedance) mode.

Over range indicator. This pin is at a logic High for
V

IN

<

0 or for V

>

V

REF

.

IN

Device ready indicator, active High. This pin is at a
logic Low during a calibration cycle and while the
device is in the power down mode.

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Pin Descriptions and Equivalent Circuits #2 (Continued)

ADC12081

No. Symbol Equivalent Circuit Description

14-19,

22-27

3V

5V

4, 6 AGND

13 V

9, 12 DGND

21 V

20 DGND I/O

D0 - D11

IN com

A

D

I/O

D

Digital output word, CMOS compatible. D0 (pin 14) is
LSB, D11 (pin 27) is MSB. Load with no more than
50pF.

Analog input common. Connect to a quiet point in
analog ground near the driving device. See section

1.2.

Positive analog supply pin. Connect to a clean, quiet
voltage source of +5V. V

and VDshould have a

A

common supply and be separately bypassed with a
5µF to 10µF capacitor and a 0.1µF chip capacitor.

The ground return for the analog supply. AGND and
DGND should be connected together close to the
ADC12081 package. See section 5.0.

Positive analog supply pin. Connect to a clean, quiet
voltage source of +5V. V

and VDshould have a

A

common supply and be separately bypassed with a
5µF to 10µF capacitor and a 0.1 µF chip capacitor.

The ground return for the analog supply. AGND and
DGND should be connected together close to the
ADC12081 package. See section 5.0

The digital output driver supply pin. This pin can be
operated from a supply voltage of 3V to 5V, but the
voltage on this pin should never exceed the V

D

supply pin voltage.

The ground return for the output drivers. This pin
should be returned to a point in the digital ground
that is removed from the other ground pins of the
ADC12081.

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ADC12081

Absolute Maximum Ratings (Notes 1,

2)

Storage Temp. −65˚C to +150˚C

Maximum Junction Temp. 150˚C

If Military/Aerospace specified devices are required,
please contact the National Semiconductor Sales Office/
Distributors for availability and specifications.

Supply Voltage 6.5V

Voltage on Any Output −0.3V to V

Input Current at Any Pin (Note 3)

Package Input Current (Note 3)

+

+0.3V

±

25mA

±

50mA

Package Dissipation See (Note 4)

ESD Susceptibility

Operating Ratings

Operating Temp. Range −40˚C ≤ TA≤ +85˚C

Supply Voltage +4.75V to +5.25V

V

I/O +2.7V to V

D

V

Input 1.8V to 2.2V

REF

CLOCK, CAL, PD, OE −0.05V to V

|AGND −DGND| ≤100mV

+ 0.05V

D

Human Body Model 1500V

Machine Model 150V

Soldering Temp., Infrared, 10

300˚C

sec.(Note 6)

Converter Electrical Characteristics

The following specifications apply for AGND = DGND = DGND I/O = 0V, VA=VD=VDI/O = +5V, PD = +5V, V

= 5MHz, CL= 50 pF/pin. After Auto-Cal at Temperature. Boldface limits apply for TA=TJto T

f

CLK

limits T

= 25˚C (Notes 7, 8) and (Note 9)

A=TJ

Symbol Parameter Conditions

Typical

(Note

10)

MIN

Limits

(Note

to T

11)

Static Converter Characteristics

Resolution with No Missing Codes 12 Bits(min)

INL Integral Non Linearity

DNL Differential Non Linearity

Full-Scale Error

Zero Error

±
±
±
±

0.6

0.35

0.05

0.15

±

1.7 LSB( max)

±

0.75 LSB( max)

±

0.1 %FS(max)

±

0.24 %FS(max)

Dynamic Converter Characteristics

BW Full Power Bandwidth 100 MHz

SNR Signal-to-Noise Ratio f

SINAD Signal-to-Noise & Distortion f

ENOB Effective Number of Bits f

THD Total Hamonic Distortion f

SFDR Spurious Free Dynamic Range f

= 2.5 MHz, VIN= 2.0V

in

= 2.5 MHz, VIN= 2.0V

in

= 2.5 MHz, VIN= 2.0V

in

= 2.5 MHz, VIN= 2.0V

in

= 2.5 MHz, VIN= 2.0V

in

P-P

P-P

P-P

P-P

P-P

68 65 dB

67.6 64.5 dB

10.9 10.4 Bits

79 dB

79 dB

Reference and Analog Input Characteristics

V

IN

C

IN

V

REF

Input Voltage Range V

VINInput Capacitance

= 2.0V

REF

V

= 1.0Vdc +

IN

0.7Vrms

(CLK LOW) 10 pF

(CLK HIGH) 15 pF

Reference Voltage (Note 14) 2.00

0

V

REF

1.8 V(min)

2.2 V(max)

Reference Input Leakage Current 10 µA

Reference Input Resistance 1 MΩ(min)

REF

MAX

= +2.0V,

: all other

Units

(Limits)

V(min)

V(max)

D

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DC and Logic Electrical Characteristics

The following specifications apply for AGND = DGND = DGND I/O = 0V, VA=VD=VDI/O = +5V, PD = +5V, V

= 50MHz, CL= 50 pF/pin. After Auto-Cal at Temperature. Boldface limits apply for TA=T

f

CLK

ADC12081

T

= 25˚C (Note 7) (Note 8) and (Note 9)

A=TJ

Symbol Parameter Conditions

CLK, OE Digital Input Characteristics

V

IH

V

IL

I

IH

I

IL

C

IN

Logical "1" Input Voltage V+ = 5.25V 2.0 V(min)

Logical "0" Input Voltage V+ = 4.75V 0.8 V(min)

Logical "1" Input Current VIN= 5.0V 5 µA

Logical "0" Input Current VIN=0V −5 µA

VINInput Capacitance 8 pF

D0 - D11 Digital Output Characteristics

V

OH

V

OL

I

OZ

+I

SC

−I

SC

Logical "1" Output Voltage I

Logical "0" Output Voltage I

TRI-STATE®Output Current V

Output Short Circuit Source
Current

= −1mA 4 V (min)

OUT

= 1.6mA 0.4 V (max)

OUT

=3Vor5V 10 µA

OUT

V

= 0V −10 µA

OUT

VDDO= 3V, V

Output Short Circuit Sink Current VDDO= 3V, V

Power Supply Characteristics

I

A

I

D

Analog Supply Current

Digital Supply Current

Total Power Consumption

PD = VDDO
PD = DGND

PD = VDDO
PD = DGND

PD = VDDO
PD = DGND

= 0V −14

OUT

OUT=VO

MIN

Typical

(Note

10)

16 mA(min)

2.5
20

0.5

1

15

105

to T

Limits

; all other limits

MAX

(Note

11)

4

26

2
2

30

140

REF

mA(max)
mA(max)

mA(max)
mA(max)

mW(max)
mW(max)

= +2.0V,

Units

(Limits)

mA(min)

AC Electrical Characteristics

The following specifications apply for AGND = DGND = DGND I/O = 0V, VA=VD=VDI/O = +5V, PD = +5V, V

= 5 MHz, CL= 50 pF/pin. After Auto-Cal at Temperature. Boldface limits apply for TA=T

f

CLK

=TJ= 25˚C (Note 7) (Note 8) and (Note 10)

Symbol Parameter Conditions

f

CLK

Clock Frequency

Clock Duty Cycle 50 %

t

CONV

t

AD

t

OD

t

DIS

t

EN

t

WCAL

t

RDYC

t

CAL

t

WPD

t

RDYPD

t

PD

Conversion Latency 10.25

Aperture Delay Time 3.5 ns

I/O=3V 44

Data output delay after rising clk
edge

V

D

V

I/O=5V 40

D

Data outputs into Tristate mode 21 nA (max)

Data outputs active after Tristate 21 ns (max)

Calibration request pulse width 3 Tclk(min)

Ready Low after CAL request 3 Tclk

Calibration cycle 4000 Tclk

Power-down pulse width 3 Tclk(min)

Ready Low after PD request 3 Tclk

Power down mode exit cycle 4000 Tclk

Typical

(Note

to T

MIN

MAX

Limits

(Note

10)

11)

0.5 MHz(min)

5 MHz(max)

= +2.0V,

REF

; all other limits T

Units

(Limits)

Clock

Cycles

ns

A

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