Rainbow Electronics ADC12048 User Manual
ADC12048
12-Bit Plus Sign 216 kHz 8-Channel Sampling
Analog-to-Digital Converter
ADC12048 12-Bit Plus Sign 216 kHz 8-Channel Sampling Analog-to-Digital Converter
December 1995
General Description
Operating from a single 5V power supply the ADC12048 is a
a
12 bit
sign, parallel I/O, self-calibrating, sampling analogto-digital converter (ADC) with an eight input fully differential
analog multiplexer. The maximum sampling rate is 216 kHz.
On request, the ADC goes through a self-calibration process that adjusts linearity, zero and full-scale errors.
The ADC12048’s 8-channel multiplexer is software programmable to operate in a variety of combinations of singleended, differential, or pseudo-differential modes. The fully
differential MUX and the 12-bit
a
sign ADC allows for the
difference between two signals to be digitized.
The ADC12048 can be configured to work with many popular microprocessors/microcontrollers including National’s
HPC family, Intel386 and 8051, TMS320C25, Motorola
MC68HC11/16, Hitachi 64180 and Analog Devices
ADSP21xx.
For complementary voltage references see the LM4040,
LM4041 or LM9140.
Key Specifications (f
Y
Resolution 12-bitsasign
Y
13-bit conversion time 3.6 ms, max
Y
13-bit throughput rate 216 ksamples/s, min
Y
Integral Linearity Error (ILE)
CLK
e
12 MHz)
g
1 LSB, max
Block Diagram
Y
Single Supply
Y
VINRange GND to V
Y
Power consumption:
a
5Vg10%
Normal operation 34 mW, max
Stand-by mode 75 mw, max
Features
Y
8-channel programmable Differential or Single-Ended
multiplexer
Y
Programmable Acquisition Times and user-controllable
Throughput Rates
Y
Programmable data bus width (8/13 bits)
Y
Built-in Sample-and-Hold
Y
Programmable Auto-Calibration and Auto-Zero cycles
Y
Low power standby mode
Y
No missing codes
Applications
Y
Medical instrumentation
Y
Process control systems
Y
Test equipment
Y
Data logging
Y
Inertial guidance
a
A
TL/H/12387– 1
TRI-STATEÉis a registered trademark of National Semiconductor Corporation.
C
1996 National Semiconductor Corporation RRD-B30M26/Printed in U. S. A.
TL/H/12387
Connection Diagrams
PLCC Package
Order Number ADC12048CIV
See NS Package Number V44A
Ordering Information
TL/H/12387– 2
Industrial Temperature Range
b
40§CsT
ADC12048CIV V44A
ADC12048CIVF VGZ44A
s
a
85§C
A
PQFP Package
TL/H/12387– 3
Order Number ADC12048CIVF
See NS Package Number VGZ44A
Package
2
Absolute Maximum Ratings (Notes 1 and 2)
If Military/Aerospace specified devices are required,
please contact the National Semiconductor Sales
Office/Distributors for availability and specifications.
Supply Voltage (V
a
A
Voltage at all Inputs
a
a
b
V
V
l
A
AGNDbDGND
l
l
D
l
Input Current at Any Pin (Note 3)
Package Input Current (Note 3)
Power Dissipation (Note 4)
e
at T
25§C 875 mW
A
Storage Temperature
Converter DC Characteristics The following specifications apply to the ADC12048 for V
a
e
V
and V
otherwise specified. Boldface limits apply for T
REF
4.096V, V
b
s
1X, fully differential input with fixed 2.048V common-mode voltage (V
REF
a
and V
) 6.0V
REF
D
b
e
b
0.3V to V
b
65§Ctoa150§C
0.0V, 12-bitasign conversion mode, f
a
a
300 mV
300 mV
g
g
120 mA
A
0.3V
30 mA
e
Symbol Parameter Conditions
Resolution with No Missing Codes After Auto-Cal 13 Bits (max)
ILE Positive and Negative Integral After Auto-Cal
Linearity Error (Notes 12 and 17)
DNL Differential Non-Linearity After Auto-Cal
Zero Error After Auto-Cal (Notes 13 and 17)
V
INCM
V
INCM
V
INCM
Positive Full-Scale Error After Auto-Cal (Notes 12 and 17)
Negative Full-Scale Error After Auto-Cal (Notes 12 and 17)
DC Common Mode Error After Auto-Cal (Note 14)
TUE Total Unadjusted Error After Auto-Cal (Note 18)
Lead Temperature
VF Package
Vapor Phase (60 sec.) 210
Infared (15 sec.) 220
V Package, Infared (15 sec.) 300
ESD Susceptibility (Note 5) 3.0 kV
Operating Ratings (Notes 1 and 2)
Temperature Range
s
(T
Supply Voltage
V
A
a
V
l
A
AGNDbDGND
l
VINVoltage Range at all Inputs GNDsV
V
REF
V
REF
V
REF
V
REF
CLK
e
T
T
MIN
5.0V
2.048V
0V
to T
J
e
e
e
s
T
T
min
a
a
,V
D
a
b
V
D
)
A
max
l
l
a
Input Voltage 1VsV
b
Input Voltage 0sV
a
Common Mode 0.1 V
e
b
b
V
REF
12.0 MHz, R
INCM
; all other limits T
MAX
a
A
e
25X, source impedance for V
S
), and minimum acquisition time, unless
e
T
A
Typical Limits Unit
(Note 10) (Note 11) (Limit)
g
0.6
g
1.0
g
1.0
g
2
g
1 LSB
b
40§CsT
s
A
4.5V to 5.5V
s
100 mV
s
100 mV
s
IN
a
s
REF
b
REF
1VsV
s
V
REFCM
A
e
25§C
J
g
1 LSB (max)
g
1 LSB (max)
g
5.5
g
2.5
g
5.5
g
2.5 LSB (max)
g
2.5 LSB (max)
g
5.5 LSB (max)
a
s
e
V
REF
REF
s
a
V
D
LSB (max)
a
s
0.6 V
b
e
REF
85§C
V
A
V
A
1V
V
A
A
5V,
C
§
C
§
C
§
a
a
a
a
a
3
a
Power Supply Characteristics The following specifications apply to the ADC12048 for V
a
e
V
and V
otherwise specified. Boldface limits apply for T
REF
REF
4.096V, V
b
s
Symbol Parameter Conditions
PSS Power Supply Sensitivity V
Zero Error V
Full-Scale Error V
Linearity Error
a
I
D
a
V
D
b
1X, fully differential input with fixed 2.048V common-mode voltage, and minimum acquisition time, unless
e
e
T
A
J
e
0.0V, 12-bitasign conversion mode, f
REF
e
12.0 MHz, R
CLK
T
to T
MIN
MAX
e
25X, source impedance for V
S
; all other limits T
e
A
Typical Limits Unit
(Note 10) (Note 11) (Limit)
a
a
e
e
V
A
e
e
4.096V
0V
5.0Vg10%
g
0.1 LSB
g
0.5 LSB
g
0.1 LSB
D
REF
REF
a
b
Digital Supply Current Start Command (Performing a conversion) with
SYNC configured as an input and driven with a
e
A
e
T
25§C
J
214 kHz signal. Bus width set to 13.
e
f
12.0 MHz, Reset Mode 850 mA
CLK
e
f
12.0 MHz, Conversion 2.45 2.8 mA (max)
a
I
A
a
V
Analog Supply Current Start Command (Performing a conversion) with
A
CLK
SYNC configured as an input and driven with a
214 kHz signal. Bus width set to 13.
e
f
12.0 MHz, Reset Mode 2.3 mA
CLK
e
f
12.0 MHz, Conversion 2.3 4.0 mA (max)
CLK
I
ST
I
ON
I
OFF
I
ADCIN
R
C
C
C
Standby Supply Current Standby Mode
a
a
a
(I
I
D
Analog MUX Inputs Characteristics The following specifications apply to the ADC12048 for V
e
V
5V, V
a
D
impedance for V
tion time, unless otherwise specified. Boldface limits apply for T
)f
A
a
e
REF
a
4.096V, V
and V
REF
REF
a
s
REF
25§C
Symbol Parameter Conditions
e
Stopped 5 15 mA (max)
CLK
e
f
12.0 MHz 100 120 mA (max)
CLK
b
e
0.0V, 12-Bitasign conversion mode, f
1X, fully differential input with fixed 2.048V common-mode voltage, and minimum acquisi-
e
e
T
A
J
e
12.0 MHz, R
CLK
T
to T
MIN
; all other limits T
MAX
e
S
25X, source
Typical Limits Unit
(Note 10) (Note 11) (Limit)
MUX ON Channel Leakage ON Channele5V, OFF Channele0V 0.05 1.0 mA (min)
Current
ON Channel
e
0V, OFF Channele5V
b
0.05
b
1.0 mA (max)
MUX OFF Channel Leakage ON Channele5V, OFF Channele0V 0.05 1.0 mA (min)
Current
ON Channel
e
0V, OFF Channele5V
b
0.05
b
1.0 mA (max)
ADCIN Input Leakage Current 0.05 2.0 mA (max)
ON
MUX
ADC
MUXOUT
MUX On Resistance V
MUX Channel-to-Channel V
Matching
R
ON
MUX Channel and COM Input
Capacitance
ADCIN Input Capacitance 70 pF
MUX Output Capacitance 20 pF
e
2.5V 310 500 X (max)
IN
e
2.5V
IN
g
20% X
10 pF
a
e
V
5V,
D
a
REF
a
e
A
e
e
T
A
J
4
a
a
e
Reference Inputs The following specifications apply to the ADC12048 for V
b
e
V
1X, fully differential input with fixed 2.048V common-mode voltage, and minimum acquisition time, unless otherwise specified.
Boldface limits apply for T
0.0V, 12-bitasign conversion mode, f
REF
e
e
T
A
T
J
MIN
CLK
to T
e
MAX
12.0 MHz, R
S
; all other limits T
e
25X, source impedance for V
A
Symbol Parameter Conditions
I
REF
Reference Input Current V
a
4.096V, V
REF
Analog Input Signal: 1 kHz 145 mA
REF
e
0V
b
A
e
e
T
25§C
J
Typical Limits Unit
(Note 10) (Note 11) (Limit)
e
V
D
5V, V
REF
REF
a
a
and V
e
REF
4.096V,
b
(Note 20) 80 kHz 136 mA
C
REF
Digital Logic Input/Output Characteristics The following specifications apply to the ADC12048 for
a
V
A
impedance for V
tion time, unless otherwise specified. Boldface limits apply for T
25§C
Symbol Parameter Conditions
V
IH
V
IL
I
IH
I
IL
V
OH
V
OL
I
OFF
C
IN
Reference Input Capacitance 85 pF
a
e
e
V
D
REF
5V, V
a
REF
and V
a
e
4.096V, V
b
REF
s
b
1X, fully differential input with fixed 2.048V common-mode voltage, and minimum acquisi-
e
e
T
A
T
J
MIN
e
0.0V, 12-bitasign conversion mode, f
REF
CLK
to T
e
12.0 MHz, R
; all other limits T
MAX
Typical Limits Unit
(Note 10) (Note 11) (Limit)
a
a
e
Logic High Input Voltage V
Logic Low Input Voltage V
Logic High Input Current V
Logic Low Input Current V
Logic High Output Voltage V
Logic Low Output Voltage V
TRI-STATEÉOutput V
Leakage Current
I
OUT
I
OUT
V
A
a
A
IN
IN
a
A
a
A
OUT
OUT
e
e
e
V
5.5V 2.0 V (min)
D
a
e
e
V
4.5V 0.8 V (max)
D
5V 0.035 2.0 mA (max)
0V
a
e
e
V
4.5V
D
eb
1.6 mA 2.4 V (min)
a
e
e
V
4.5V
D
e
1.6 mA 0.4 V (max)
e
0V
e
5V
b
0.035
b
g
D12–D0 Input Capacitance 10 pF
e
25X, source
S
e
T
A
J
2.0 mA (max)
2.0 mA (max)
s
e
Converter AC Characteristics The following specifications apply to the ADC12048 for V
a
e
V
and V
otherwise specified. Boldface limits apply for T
REF
REF
4.096V, V
b
s
Symbol Parameter Conditions
t
Z
t
CAL
b
1X, fully differential input with fixed 2.048V common-mode voltage, and minimum acquisition time, unless
e
e
T
A
J
e
0.0V, 12-bitasign conversion mode, f
REF
e
12.0 MHz, R
CLK
T
to T
MIN
MAX
e
25X, source impedance for V
S
; all other limits T
e
T
A
J
Typical Limits Unit
(Note 10) (Note 11) (Limit)
Auto Zero Time 78 78 clksa120 ns clks (max)
Full Calibration Time 4946 4946 clksa120 ns clks (max)
CLK Duty Cycle 50 %
40 % (min)
60 % (max)
t
CONV
t
AcqSYNCOUT
Conversion Time Sync-Out Mode 44 44 clks (max)
Acquisition Time Minimum for 13 Bits 9 9 clksa120 ns clks (max)
(Programmable)
Maximum for 13 Bits 79 79 clks
a
120 ns clks (max)
5
a
a
e
e
V
S
e
25§C
5V,
D
a
REF
Digital Timing Characteristics The following specifications apply to the ADC12048, 13-bit data bus width,
a
a
e
V
A
Symbol
(Figure 7)
t
TPR
e
V
D
Throughput Rate Sync-Out Mode (SYNC Bit
5V, f
CLK
e
12 MHz, t
e
f
3 ns and C
e
50 pF on data I/O lines
L
Parameter Conditions
‘‘0’’) 9 Clock Cycles of
Typical Limits Units
(Note 10) (Note 11) (Limit)
e
222
kHz
Acquisition Time
t
CSWR
t
WRCS
Falling Edge of CS to Falling Edge of WR 0ns
Active Edge of WR to Rising Edge of CS 0ns
tWRWR Pulse Width 20 30 ns (min)
t
WRSETFalling
t
WRHOLDFalling
t
WRSETRising
t
WRHOLDRising
t
CSRD
t
RDCS
t
RDDATA
t
RDDATA
t
RDHOLD
t
RDRDY
t
WRRDY
t
STNDBY
Write Setup Time WMODEe‘‘1’’ 20 ns (min)
Write Hold Time WMODEe‘‘1’’ 5 ns (min)
Write Setup Time WMODEe‘‘0’’ 20 ns (min)
Write Hold Time WMODEe‘‘0’’ 5 ns (min)
Falling Edge of CS to Falling Edge of RD 0ns
Rising Edge of RD to Rising Edge of CS 0ns
Falling Edge of RD to Valid Data 8-Bit Mode (BW Bite‘‘0’’) 40 58 ns (max)
Falling Edge of RD to Valid Data 13-Bit Mode (BW Bite‘‘1’’) 26 44 ns (max)
Read Hold Time 23 32 ns (max)
Rising Edge of RD to Rising Edge of RDY 24 38 ns (max)
Active Edge of WR to Rising Edge of RDY WMODEe‘‘1’’ 42 65 ns (max)
Active Edge of WR to Falling Edge of WMODEe‘‘0’’. Writing the 200 230 ns (max)
STDBY
Standby Command into the
Configuration Register
t
STDONE
Active Edge of WR to Rising Edge of WMODEe‘‘0’’. Writing the 30 45 ns (max)
STDBY
RESET Command into the
Configuration Register
t
STDRDY
Active Edge of WR to Falling Edge of RDY WMODEe‘‘0’’. Writing the 1.4 2.5 ms (max)
RESET Command into the
Configuration Register
t
SYNC
Minimum SYNC Pulse Width 5 10 ns (min)
Notes on Specifications
Note 1: Absolute Maximum Ratings indicate limits beyond which damage to the device may occur. Operating Ratings indicate conditions for which the device is
functional, but do not guarantee specific performance limits. For guaranteed specifications and test conditions, see the Electrical Characteristics. The guaranteed
specifications apply only for the test conditions listed. Some performance characteristics may degrade when the device is not operated under the listed test
conditions.
Note 2: All voltages are measured with respect to GND, unless otherwise specified.
Note 3: When the input voltage (V
30 mA. The 120 mA maximum package input current limits the number of pins that can safely exceed the power supplies with an input current of 30 mA to four.
Note 4: The maximum power dissipation must he derated at elevated temperatures and is dictated by T
junction to ambient thermal resistance), and T
or the number given in the Absolute Maximum Ratings, whichever is lower. For this device, T
i
JA
ADC12048 in the V package, when board mounted, is 55
Note 5: Human body model, 100 pF discharged through 1.5 kX resistor.
) at any pin exceeds the power supply rails (V
IN
(ambient temperature). The maximum allowable power dissipation at any temperature is P
A
C/W, and in the VF package, when board mounted, is 67.8§C/W.
§
IN
k
GND or V
6
a
l
IN
Jmax
a
(V
or V
)), the current at that pin should be limited to
A
D
, (maximum junction temperature), iJA(package
Jmax
e
150§C, and the typical thermal resistance (iJA)ofthe
Dmax
e
b
(T
TA)/
Jmax
Notes on Specifications (Continued)
Note 6: Each input and output is protected by a nominal 6.5V breakdown voltage zener diode to GND; as shown below, input voltage magnitude up to 0.3V above
a
or 0.3V below GND will not damage the ADC12048. There are parasitic diodes that exist between the inputs and the power supply rails and errors in the A/D
V
A
conversion can occur if these diodes are forward biased by more than 50 mV. As an example, if V
ensure accurate conversions.
a
is 4.50 VDC, full-scale input voltage must bes4.55 VDCto
A
a
A
TL/H/12387– 4
a
and V
at the specified extremes.
D
a
Note 7: V
conversion/comparison accuracy. Refer to the Power Supply Considerations section for a detailed discussion.
Note 8: Accuracy is guaranteed when operating at f
Note 9: With the test condition for V
Note 10: Typicals are at T
Note 11: Limits are guaranteed to National’s AOQL (Average Outgoing Quality Level).
Note 12: Positive integral linearity error is defined as the deviation of the analog value, expressed in LSBs, from the straight line that passes through positive full-
scale and zero. For negative integral linearity error, the straight line passes through negative full-scale and zero.
Note 13: Zero error is a measure of the deviation from the mid-scale voltage (a code of zero), expressed in LSB. It is the average value of the code transitions
b
between
Note 14: The DC common-mode error is measured with both inputs shorted together and driven from 0V to 5V. The measured value is referred to the resulting
output value when the inputs are driven with a 2.5V input.
Note 15: Power Supply Sensitivity is measured after an Auto-Zero and Auto Calibration cycle has been completed with V
Note 16: V
Note 17: The ADC12048’s self-calibration technique ensures linearity and offset errors as specified, but noise inherent in the self-calibration process will result in a
repeatability uncertainly of
a
and V
A
1to0and0toa1 (see
REFCM
must be connected together to the same power supply voltage and bypassed with separate capacitors at each Vapin to assure
D
CLK
a
b
REF(VREF
e
25§C and represent most likely parametric norm.
A
Figure 6
V
REF
).
(Reference Voltage Common Mode Range) is defined as
g
0.20 LSB.
e
12 MHz.
b
) given asa4.096V, the 12-bit LSB is 1.000 mV.
a
b
a
V
V
REF
REF
2
#
J
Note 18: Total Unadjusted Error (TUE) includes offset, full scale linearity and MUX errors.
Note 19: The ADC12048 parts used to gather the information for these curves were auto-calibrated prior to taking the measurements at each test condition. The
auto-calibration cycle cancels any first order drifts due to test conditions. However, each measurement has a repeatability uncertainty error of 0.2 LSB. See Note
17.
Note 20: This is a DC average current drawn by the reference input with a full-scale sinewave input. The ADC12048 is continuously converting with a throughput
rate of 206 kHz.
Note 21: These typical curves were measured during continuous conversions with a positive half-scale DC input. A 240 ns RD
signal went low. The data bus lines were loaded with 2 HC family CMOS inputs (C
RDY
Note 22: Any other values placed in the command field are meaningless. However, if a code of 101 or 110 is placed in the command field and the CS
go low at the same time, the ADC12048 will enter a test mode. These test modes are only to be used by the manufacturer of this device. A hardware power-off and
power-on reset must be done to get out of these test modes.
E
20 pF).
L
pulse was applied 25 ns after the
,RDand WR
7
Electrical Characteristics
FIGURE 1. Output Digital Code vs the Operating Input Voltage Range (General Case)
FIGURE 2. Output Digital Code vs the Operating Input Voltage Range for V
REF
e
TL/H/12387– 5
TL/H/12387– 6
4.096V
8
Electrical Characteristics (Continued)
FIGURE 3. V
FIGURE 4. V
Operating Range (General Case)
REF
Operating Range for V
REF
TL/H/12387– 7
e
5V
A
TL/H/12387– 8
9
Loading...