Page 1
ADC12048
12-Bit Plus Sign 216 kHz 8-Channel Sampling
Analog-to-Digital Converter
ADC12048 12-Bit Plus Sign 216 kHz 8-Channel Sampling Analog-to-Digital Converter
December 1995
General Description
Operating from a single 5V power supply the ADC12048 is a
a
12 bit
sign, parallel I/O, self-calibrating, sampling analogto-digital converter (ADC) with an eight input fully differential
analog multiplexer. The maximum sampling rate is 216 kHz.
On request, the ADC goes through a self-calibration process that adjusts linearity, zero and full-scale errors.
The ADC12048’s 8-channel multiplexer is software programmable to operate in a variety of combinations of singleended, differential, or pseudo-differential modes. The fully
differential MUX and the 12-bit
a
sign ADC allows for the
difference between two signals to be digitized.
The ADC12048 can be configured to work with many popular microprocessors/microcontrollers including National’s
HPC family, Intel386 and 8051, TMS320C25, Motorola
MC68HC11/16, Hitachi 64180 and Analog Devices
ADSP21xx.
For complementary voltage references see the LM4040,
LM4041 or LM9140.
Key Specifications (f
Y
Resolution 12-bitsasign
Y
13-bit conversion time 3.6 ms, max
Y
13-bit throughput rate 216 ksamples/s, min
Y
Integral Linearity Error (ILE)
CLK
e
12 MHz)
g
1 LSB, max
Block Diagram
Y
Single Supply
Y
VINRange GND to V
Y
Power consumption:
a
5Vg10%
Normal operation 34 mW, max
Stand-by mode 75 mw, max
Features
Y
8-channel programmable Differential or Single-Ended
multiplexer
Y
Programmable Acquisition Times and user-controllable
Throughput Rates
Y
Programmable data bus width (8/13 bits)
Y
Built-in Sample-and-Hold
Y
Programmable Auto-Calibration and Auto-Zero cycles
Y
Low power standby mode
Y
No missing codes
Applications
Y
Medical instrumentation
Y
Process control systems
Y
Test equipment
Y
Data logging
Y
Inertial guidance
a
A
TL/H/12387– 1
TRI-STATEÉis a registered trademark of National Semiconductor Corporation.
C
1996 National Semiconductor Corporation RRD-B30M26/Printed in U. S. A.
TL/H/12387
Page 2
Connection Diagrams
PLCC Package
Order Number ADC12048CIV
See NS Package Number V44A
Ordering Information
TL/H/12387– 2
Industrial Temperature Range
b
40§CsT
ADC12048CIV V44A
ADC12048CIVF VGZ44A
s
a
85§C
A
PQFP Package
TL/H/12387– 3
Order Number ADC12048CIVF
See NS Package Number VGZ44A
Package
2
Page 3
Absolute Maximum Ratings (Notes 1 and 2)
If Military/Aerospace specified devices are required,
please contact the National Semiconductor Sales
Office/Distributors for availability and specifications.
Supply Voltage (V
a
A
Voltage at all Inputs
a
a
b
V
V
l
A
AGNDbDGND
l
l
D
l
Input Current at Any Pin (Note 3)
Package Input Current (Note 3)
Power Dissipation (Note 4)
e
at T
25§C 875 mW
A
Storage Temperature
Converter DC Characteristics The following specifications apply to the ADC12048 for V
a
e
V
and V
otherwise specified. Boldface limits apply for T
REF
4.096V, V
b
s
1X, fully differential input with fixed 2.048V common-mode voltage (V
REF
a
and V
) 6.0V
REF
D
b
e
b
0.3V to V
b
65§Ctoa150§C
0.0V, 12-bitasign conversion mode, f
a
a
300 mV
300 mV
g
g
120 mA
A
0.3V
30 mA
e
Symbol Parameter Conditions
Resolution with No Missing Codes After Auto-Cal 13 Bits (max)
ILE Positive and Negative Integral After Auto-Cal
Linearity Error (Notes 12 and 17)
DNL Differential Non-Linearity After Auto-Cal
Zero Error After Auto-Cal (Notes 13 and 17)
V
INCM
V
INCM
V
INCM
Positive Full-Scale Error After Auto-Cal (Notes 12 and 17)
Negative Full-Scale Error After Auto-Cal (Notes 12 and 17)
DC Common Mode Error After Auto-Cal (Note 14)
TUE Total Unadjusted Error After Auto-Cal (Note 18)
Lead Temperature
VF Package
Vapor Phase (60 sec.) 210
Infared (15 sec.) 220
V Package, Infared (15 sec.) 300
ESD Susceptibility (Note 5) 3.0 kV
Operating Ratings (Notes 1 and 2)
Temperature Range
s
(T
Supply Voltage
V
A
a
V
l
A
AGNDbDGND
l
VINVoltage Range at all Inputs GNDsV
V
REF
V
REF
V
REF
V
REF
CLK
e
T
T
MIN
5.0V
2.048V
0V
to T
J
e
e
e
s
T
T
min
a
a
,V
D
a
b
V
D
)
A
max
l
l
a
Input Voltage 1VsV
b
Input Voltage 0sV
a
Common Mode 0.1 V
e
b
b
V
REF
12.0 MHz, R
INCM
; all other limits T
MAX
a
A
e
25X, source impedance for V
S
), and minimum acquisition time, unless
e
T
A
Typical Limits Unit
(Note 10) (Note 11) (Limit)
g
0.6
g
1.0
g
1.0
g
2
g
1 LSB
b
40§CsT
s
A
4.5V to 5.5V
s
100 mV
s
100 mV
s
IN
a
s
REF
b
REF
1VsV
s
V
REFCM
A
e
25§C
J
g
1 LSB (max)
g
1 LSB (max)
g
5.5
g
2.5
g
5.5
g
2.5 LSB (max)
g
2.5 LSB (max)
g
5.5 LSB (max)
a
s
e
V
REF
REF
s
a
V
D
LSB (max)
a
s
0.6 V
b
e
REF
85§C
V
A
V
A
1V
V
A
A
5V,
C
§
C
§
C
§
a
a
a
a
a
3
Page 4
a
Power Supply Characteristics The following specifications apply to the ADC12048 for V
a
e
V
and V
otherwise specified. Boldface limits apply for T
REF
REF
4.096V, V
b
s
Symbol Parameter Conditions
PSS Power Supply Sensitivity V
Zero Error V
Full-Scale Error V
Linearity Error
a
I
D
a
V
D
b
1X, fully differential input with fixed 2.048V common-mode voltage, and minimum acquisition time, unless
e
e
T
A
J
e
0.0V, 12-bitasign conversion mode, f
REF
e
12.0 MHz, R
CLK
T
to T
MIN
MAX
e
25X, source impedance for V
S
; all other limits T
e
A
Typical Limits Unit
(Note 10) (Note 11) (Limit)
a
a
e
e
V
A
e
e
4.096V
0V
5.0Vg10%
g
0.1 LSB
g
0.5 LSB
g
0.1 LSB
D
REF
REF
a
b
Digital Supply Current Start Command (Performing a conversion) with
SYNC configured as an input and driven with a
e
A
e
T
25§C
J
214 kHz signal. Bus width set to 13.
e
f
12.0 MHz, Reset Mode 850 mA
CLK
e
f
12.0 MHz, Conversion 2.45 2.8 mA (max)
a
I
A
a
V
Analog Supply Current Start Command (Performing a conversion) with
A
CLK
SYNC configured as an input and driven with a
214 kHz signal. Bus width set to 13.
e
f
12.0 MHz, Reset Mode 2.3 mA
CLK
e
f
12.0 MHz, Conversion 2.3 4.0 mA (max)
CLK
I
ST
I
ON
I
OFF
I
ADCIN
R
C
C
C
Standby Supply Current Standby Mode
a
a
a
(I
I
D
Analog MUX Inputs Characteristics The following specifications apply to the ADC12048 for V
e
V
5V, V
a
D
impedance for V
tion time, unless otherwise specified. Boldface limits apply for T
)f
A
a
e
REF
a
4.096V, V
and V
REF
REF
a
s
REF
25§C
Symbol Parameter Conditions
e
Stopped 5 15 mA (max)
CLK
e
f
12.0 MHz 100 120 mA (max)
CLK
b
e
0.0V, 12-Bitasign conversion mode, f
1X, fully differential input with fixed 2.048V common-mode voltage, and minimum acquisi-
e
e
T
A
J
e
12.0 MHz, R
CLK
T
to T
MIN
; all other limits T
MAX
e
S
25X, source
Typical Limits Unit
(Note 10) (Note 11) (Limit)
MUX ON Channel Leakage ON Channele5V, OFF Channele0V 0.05 1.0 mA (min)
Current
ON Channel
e
0V, OFF Channele5V
b
0.05
b
1.0 mA (max)
MUX OFF Channel Leakage ON Channele5V, OFF Channele0V 0.05 1.0 mA (min)
Current
ON Channel
e
0V, OFF Channele5V
b
0.05
b
1.0 mA (max)
ADCIN Input Leakage Current 0.05 2.0 mA (max)
ON
MUX
ADC
MUXOUT
MUX On Resistance V
MUX Channel-to-Channel V
Matching
R
ON
MUX Channel and COM Input
Capacitance
ADCIN Input Capacitance 70 pF
MUX Output Capacitance 20 pF
e
2.5V 310 500 X (max)
IN
e
2.5V
IN
g
20% X
10 pF
a
e
V
5V,
D
a
REF
a
e
A
e
e
T
A
J
4
Page 5
a
a
e
Reference Inputs The following specifications apply to the ADC12048 for V
b
e
V
1X, fully differential input with fixed 2.048V common-mode voltage, and minimum acquisition time, unless otherwise specified.
Boldface limits apply for T
0.0V, 12-bitasign conversion mode, f
REF
e
e
T
A
T
J
MIN
CLK
to T
e
MAX
12.0 MHz, R
S
; all other limits T
e
25X, source impedance for V
A
Symbol Parameter Conditions
I
REF
Reference Input Current V
a
4.096V, V
REF
Analog Input Signal: 1 kHz 145 mA
REF
e
0V
b
A
e
e
T
25§C
J
Typical Limits Unit
(Note 10) (Note 11) (Limit)
e
V
D
5V, V
REF
REF
a
a
and V
e
REF
4.096V,
b
(Note 20) 80 kHz 136 mA
C
REF
Digital Logic Input/Output Characteristics The following specifications apply to the ADC12048 for
a
V
A
impedance for V
tion time, unless otherwise specified. Boldface limits apply for T
25§C
Symbol Parameter Conditions
V
IH
V
IL
I
IH
I
IL
V
OH
V
OL
I
OFF
C
IN
Reference Input Capacitance 85 pF
a
e
e
V
D
REF
5V, V
a
REF
and V
a
e
4.096V, V
b
REF
s
b
1X, fully differential input with fixed 2.048V common-mode voltage, and minimum acquisi-
e
e
T
A
T
J
MIN
e
0.0V, 12-bitasign conversion mode, f
REF
CLK
to T
e
12.0 MHz, R
; all other limits T
MAX
Typical Limits Unit
(Note 10) (Note 11) (Limit)
a
a
e
Logic High Input Voltage V
Logic Low Input Voltage V
Logic High Input Current V
Logic Low Input Current V
Logic High Output Voltage V
Logic Low Output Voltage V
TRI-STATEÉOutput V
Leakage Current
I
OUT
I
OUT
V
A
a
A
IN
IN
a
A
a
A
OUT
OUT
e
e
e
V
5.5V 2.0 V (min)
D
a
e
e
V
4.5V 0.8 V (max)
D
5V 0.035 2.0 mA (max)
0V
a
e
e
V
4.5V
D
eb
1.6 mA 2.4 V (min)
a
e
e
V
4.5V
D
e
1.6 mA 0.4 V (max)
e
0V
e
5V
b
0.035
b
g
D12–D0 Input Capacitance 10 pF
e
25X, source
S
e
T
A
J
2.0 mA (max)
2.0 mA (max)
s
e
Converter AC Characteristics The following specifications apply to the ADC12048 for V
a
e
V
and V
otherwise specified. Boldface limits apply for T
REF
REF
4.096V, V
b
s
Symbol Parameter Conditions
t
Z
t
CAL
b
1X, fully differential input with fixed 2.048V common-mode voltage, and minimum acquisition time, unless
e
e
T
A
J
e
0.0V, 12-bitasign conversion mode, f
REF
e
12.0 MHz, R
CLK
T
to T
MIN
MAX
e
25X, source impedance for V
S
; all other limits T
e
T
A
J
Typical Limits Unit
(Note 10) (Note 11) (Limit)
Auto Zero Time 78 78 clksa120 ns clks (max)
Full Calibration Time 4946 4946 clksa120 ns clks (max)
CLK Duty Cycle 50 %
40 % (min)
60 % (max)
t
CONV
t
AcqSYNCOUT
Conversion Time Sync-Out Mode 44 44 clks (max)
Acquisition Time Minimum for 13 Bits 9 9 clksa120 ns clks (max)
(Programmable)
Maximum for 13 Bits 79 79 clks
a
120 ns clks (max)
5
a
a
e
e
V
S
e
25§C
5V,
D
a
REF
Page 6
Digital Timing Characteristics The following specifications apply to the ADC12048, 13-bit data bus width,
a
a
e
V
A
Symbol
(Figure 7)
t
TPR
e
V
D
Throughput Rate Sync-Out Mode (SYNC Bit
5V, f
CLK
e
12 MHz, t
e
f
3 ns and C
e
50 pF on data I/O lines
L
Parameter Conditions
‘‘0’’) 9 Clock Cycles of
Typical Limits Units
(Note 10) (Note 11) (Limit)
e
222
kHz
Acquisition Time
t
CSWR
t
WRCS
Falling Edge of CS to Falling Edge of WR 0ns
Active Edge of WR to Rising Edge of CS 0ns
tWRWR Pulse Width 20 30 ns (min)
t
WRSETFalling
t
WRHOLDFalling
t
WRSETRising
t
WRHOLDRising
t
CSRD
t
RDCS
t
RDDATA
t
RDDATA
t
RDHOLD
t
RDRDY
t
WRRDY
t
STNDBY
Write Setup Time WMODEe‘‘1’’ 20 ns (min)
Write Hold Time WMODEe‘‘1’’ 5 ns (min)
Write Setup Time WMODEe‘‘0’’ 20 ns (min)
Write Hold Time WMODEe‘‘0’’ 5 ns (min)
Falling Edge of CS to Falling Edge of RD 0ns
Rising Edge of RD to Rising Edge of CS 0ns
Falling Edge of RD to Valid Data 8-Bit Mode (BW Bite‘‘0’’) 40 58 ns (max)
Falling Edge of RD to Valid Data 13-Bit Mode (BW Bite‘‘1’’) 26 44 ns (max)
Read Hold Time 23 32 ns (max)
Rising Edge of RD to Rising Edge of RDY 24 38 ns (max)
Active Edge of WR to Rising Edge of RDY WMODEe‘‘1’’ 42 65 ns (max)
Active Edge of WR to Falling Edge of WMODEe‘‘0’’. Writing the 200 230 ns (max)
STDBY
Standby Command into the
Configuration Register
t
STDONE
Active Edge of WR to Rising Edge of WMODEe‘‘0’’. Writing the 30 45 ns (max)
STDBY
RESET Command into the
Configuration Register
t
STDRDY
Active Edge of WR to Falling Edge of RDY WMODEe‘‘0’’. Writing the 1.4 2.5 ms (max)
RESET Command into the
Configuration Register
t
SYNC
Minimum SYNC Pulse Width 5 10 ns (min)
Notes on Specifications
Note 1: Absolute Maximum Ratings indicate limits beyond which damage to the device may occur. Operating Ratings indicate conditions for which the device is
functional, but do not guarantee specific performance limits. For guaranteed specifications and test conditions, see the Electrical Characteristics. The guaranteed
specifications apply only for the test conditions listed. Some performance characteristics may degrade when the device is not operated under the listed test
conditions.
Note 2: All voltages are measured with respect to GND, unless otherwise specified.
Note 3: When the input voltage (V
30 mA. The 120 mA maximum package input current limits the number of pins that can safely exceed the power supplies with an input current of 30 mA to four.
Note 4: The maximum power dissipation must he derated at elevated temperatures and is dictated by T
junction to ambient thermal resistance), and T
or the number given in the Absolute Maximum Ratings, whichever is lower. For this device, T
i
JA
ADC12048 in the V package, when board mounted, is 55
Note 5: Human body model, 100 pF discharged through 1.5 kX resistor.
) at any pin exceeds the power supply rails (V
IN
(ambient temperature). The maximum allowable power dissipation at any temperature is P
A
C/W, and in the VF package, when board mounted, is 67.8§C/W.
§
IN
k
GND or V
6
a
l
IN
Jmax
a
(V
or V
)), the current at that pin should be limited to
A
D
, (maximum junction temperature), iJA(package
Jmax
e
150§C, and the typical thermal resistance (iJA)ofthe
Dmax
e
b
(T
TA)/
Jmax
Page 7
Notes on Specifications (Continued)
Note 6: Each input and output is protected by a nominal 6.5V breakdown voltage zener diode to GND; as shown below, input voltage magnitude up to 0.3V above
a
or 0.3V below GND will not damage the ADC12048. There are parasitic diodes that exist between the inputs and the power supply rails and errors in the A/D
V
A
conversion can occur if these diodes are forward biased by more than 50 mV. As an example, if V
ensure accurate conversions.
a
is 4.50 VDC, full-scale input voltage must bes4.55 VDCto
A
a
A
TL/H/12387– 4
a
and V
at the specified extremes.
D
a
Note 7: V
conversion/comparison accuracy. Refer to the Power Supply Considerations section for a detailed discussion.
Note 8: Accuracy is guaranteed when operating at f
Note 9: With the test condition for V
Note 10: Typicals are at T
Note 11: Limits are guaranteed to National’s AOQL (Average Outgoing Quality Level).
Note 12: Positive integral linearity error is defined as the deviation of the analog value, expressed in LSBs, from the straight line that passes through positive full-
scale and zero. For negative integral linearity error, the straight line passes through negative full-scale and zero.
Note 13: Zero error is a measure of the deviation from the mid-scale voltage (a code of zero), expressed in LSB. It is the average value of the code transitions
b
between
Note 14: The DC common-mode error is measured with both inputs shorted together and driven from 0V to 5V. The measured value is referred to the resulting
output value when the inputs are driven with a 2.5V input.
Note 15: Power Supply Sensitivity is measured after an Auto-Zero and Auto Calibration cycle has been completed with V
Note 16: V
Note 17: The ADC12048’s self-calibration technique ensures linearity and offset errors as specified, but noise inherent in the self-calibration process will result in a
repeatability uncertainly of
a
and V
A
1to0and0toa1 (see
REFCM
must be connected together to the same power supply voltage and bypassed with separate capacitors at each Vapin to assure
D
CLK
a
b
REF(VREF
e
25§C and represent most likely parametric norm.
A
Figure 6
V
REF
).
(Reference Voltage Common Mode Range) is defined as
g
0.20 LSB.
e
12 MHz.
b
) given asa4.096V, the 12-bit LSB is 1.000 mV.
a
b
a
V
V
REF
REF
2
#
J
Note 18: Total Unadjusted Error (TUE) includes offset, full scale linearity and MUX errors.
Note 19: The ADC12048 parts used to gather the information for these curves were auto-calibrated prior to taking the measurements at each test condition. The
auto-calibration cycle cancels any first order drifts due to test conditions. However, each measurement has a repeatability uncertainty error of 0.2 LSB. See Note
17.
Note 20: This is a DC average current drawn by the reference input with a full-scale sinewave input. The ADC12048 is continuously converting with a throughput
rate of 206 kHz.
Note 21: These typical curves were measured during continuous conversions with a positive half-scale DC input. A 240 ns RD
signal went low. The data bus lines were loaded with 2 HC family CMOS inputs (C
RDY
Note 22: Any other values placed in the command field are meaningless. However, if a code of 101 or 110 is placed in the command field and the CS
go low at the same time, the ADC12048 will enter a test mode. These test modes are only to be used by the manufacturer of this device. A hardware power-off and
power-on reset must be done to get out of these test modes.
E
20 pF).
L
pulse was applied 25 ns after the
,RDand WR
7
Page 8
Electrical Characteristics
FIGURE 1. Output Digital Code vs the Operating Input Voltage Range (General Case)
FIGURE 2. Output Digital Code vs the Operating Input Voltage Range for V
REF
e
TL/H/12387– 5
TL/H/12387– 6
4.096V
8
Page 9
Electrical Characteristics (Continued)
FIGURE 3. V
FIGURE 4. V
Operating Range (General Case)
REF
Operating Range for V
REF
TL/H/12387– 7
e
5V
A
TL/H/12387– 8
9
Page 10
Electrical Characteristics (Continued)
FIGURE 5a. Transfer Characteristic
FIGURE 5b. Simplified Error vs Output Code without Auto-Calibration or Auto-Zero Cycles
TL/H/12387– 9
TL/H/12387– 10
10
Page 11
Electrical Characteristics (Continued)
FIGURE 5c. Simplified Error vs Output Code after Auto-Calibration Cycle
TL/H/12387– 12
FIGURE 6. Offset or Zero Error Voltage (Note 13)
TL/H/12387– 11
11
Page 12
Timing Diagrams
FIGURE 7a. Sync-Out Write (WMODEe1, BWe1), Read and Convert Cycles
FIGURE 7b. Sync-In Write (WMODEe1, BWe1), Read and Convert Cycles
TL/H/12387– 13
TL/H/12387– 14
12
Page 13
Timing Diagrams (Continued)
FIGURE 7c. Sync-Out Write (WMODEe0, BWe1), Read and Convert Cycles
FIGURE 7d. Sync-In Write (WMODEe0, BWe1), Read and Convert Cycles
TL/H/12387– 46
TL/H/12387– 47
13
Page 14
Timing Diagrams (Continued)
FIGURE 7e. Sync-Out Read and Convert Cycles. The MUX channel
is the channel selected on the most recent write cycle.
FIGURE 7f. Sync-In Read and Convert Cycles. The MUX channel
is the channel selected on the most recent write cycle.
TL/H/12387– 48
TL/H/12387– 49
14
Page 15
Timing Diagrams (Continued)
FIGURE 7g. 8-Bit Bus Read Cycle (Sync-Out)
FIGURE 7h. 8-Bit Bus Read Cycle (Sync-In)
TL/H/12387– 50
TL/H/12387– 51
15
Page 16
Timing Diagrams (Continued)
FIGURE 7i. Write Signal Negates RDY (Writing the Standby, Auto-Cal or Auto-Zero Command)
FIGURE 7j. Standby and Reset Timing (13-Bit Data Bus Width)
TL/H/12387– 15
TL/H/12387– 16
16
Page 17
Typical Performance Characteristics (See Note 19, Electrical Characteristic Section)
Integral Linearity Error (INL)
Change vs Clock Frequency
TL/H/12387– 17
Integral Linearity Error (INL)
Change vs Temperature
TL/H/12387– 20
Integral Linearity Error (INL)
Change vs Reference Voltage
Full-Scale Error Change vs
Clock Frequency
TL/H/12387– 18
Full-Scale Error Change vs
Temperature
TL/H/12387– 21
Full-Scale Error Change vs
Reference Voltage
Zero Error Change vs
Clock Frequency
TL/H/12387– 19
Zero Error Change vs
Temperature
TL/H/12387– 22
Zero Error Change vs
Reference Voltage
TL/H/12387– 23
Integral Linearity Error (INL)
Change vs Supply Voltage
TL/H/12387– 39
TL/H/12387– 24
Full-Scale Error Change
vs Supply Voltage
TL/H/12387– 40
17
TL/H/12387– 25
Zero Error Change
vs Supply Voltage
TL/H/12387– 41
Page 18
Typical Performance Characteristics (Continued) (See Note 21, Electrical Characteristic Section)
Supply Currents vs
Clock Frequency
Analog Supply Current
vs Temperature
TL/H/12387– 42
TL/H/12387– 44
Reference Currents vs
Clock Frequency
TL/H/12387– 43
Digital Supply Current
vs Temperature
TL/H/12387– 45
18
Page 19
Typical Performance Characteristics (Continued) The curves were obtained under the following
conditions. R
unless otherwise stated.
S
e
50X,T
A
e
25§C, V
ae
A
V
ae
D
5V, V
REF
e
4.096V, f
e
12 MHz, and the sampling rate f
CLK
S
e
215 kHz
Full Scale Differential 1,099 Hz
Sine Wave Input
Full Scale Differential 38,452 Hz
Sine Wave Input
Half Scale Differential 1 kHz
Sine Wave Input, f
e
S
153.6 kHz
TL/H/12387– 26
TL/H/12387– 28
Full Scale Differential 18,677 Hz
Sine Wave Input
Full Scale Differential 79,468 Hz
Sine Wave Input
Half Scale Differential 20 kHz
Sine Wave Input, f
e
S
153.6 kHz
TL/H/12387– 27
TL/H/12387– 29
Half Scale Differential 40 kHz
Sine Wave Input, f
e
S
153.6 kHz
TL/H/12387– 30
TL/H/12387– 32
TL/H/12387– 31
Half Scale Differential 75 kHz
Sine Wave Input, f
e
S
153.6 kHz
TL/H/12387– 33
19
Page 20
Pin Description
PLCC Pkg. PQFP Pkg.
Pin Number Pin Number
6 44 CH0 The eight analog inputs to the Multiplexer. Active channels are selected based on the contents of bits b3– b0 of the
7 1 CH1 Configuration register. Refer to section titled MUX for more details.
8 2 CH2
9 3 CH3
15 9 CH4
16 10 CH5
17 11 CH6
18 12 CH7
14 8 COM This pin is another analog input pin used as a pseudo ground when the multiplexer is configured in single-ended mode.
13 7 V
12 6 V
19 13 MUX OUTbThe inverting (negative) and non-inverting (positive) outputs of the multiplexer.
21 15 MUX OUT
20 14 ADCIN
22 16 ADCIN
24 18 WMODE The logic state of this pin at power-up determines which edge of the write signal (WR) will latch in data from the data
25 19 SYNC The SYNC pin can be programmed as an input or an output. The Configuration register’s bit b8 controls the function of
26– 31 20 –25 D0 –D5 13-bit Data bus of the ADC12048. D12 is the most significant bit and D0 is the least significant. The BW (bus width) bit of
34– 40 29 –34 D6 –D12 the Configuration register (b12) selects between an 8-bit or 13-bit data bus width. When the BW bit is cleared (BWe0),
43 37 CLK The clock input pin used to drive the ADC12048. The operating range is 0.05 MHz to 12 MHz.
44 38 WR WR is the active low WRITE control input pin. A logic low on this pin and the CS will enable the input buffers of the data
139RDRD is the active low read control input pin. A logic low on this pin and CS will enable the active output buffers to drive the
240CSCS is the active low Chip Select input pin. Used in conjunction with the WR and RD signals to control the active data bus
3 41 RDY RDY is an active low output pin. The signal at this pin indicates when a requested function has begun or ended. Refer to
4 42 STDBY This is the standby active low output pin. This pin is low when the ADC12048 is in the standby mode and high when the
10 4 V
11 5 AGND Analog ground pin. This is the device’s analog supply ground connection. It should be connected through a low
32 and 41 26 and 35 V
33 and 42 27 and 36 DGND Digital ground pin. This is the device’s digital supply ground connection. It should be connected through a low resistance
Pin Name Description
a
REF
REF
Positive reference input. The operating voltage range for this input is 1VsV
pin should be bypassed to AGND at least with a parallel combination of a 10 mF and a 0.1 mF (ceramic) capacitors. The
capacitors should be placed as close to the part as possible.
b
Negative reference input. The operating voltage range for this input is 0VsV
4
). This pin should be bypassed to AGND at least with a parallel combination of a 10 mF and a 0.1 mF (ceramic)
capacitor. The capacitors should be placed as close to the part as possible.
a
The analog inputs to the MUX selected by bits b3 –b0 of the Configuration register appear at these pins.
b
ADC inputs. The inverting (negative) and non-inverting (positive) inputs into the ADC.
a
bus. If tied low, the ADC12048 will latch in data on the rising edge of the WR
latched in on the falling edge of the WR
this pin. When programmed as an input pin (b8
hold the analog input signal and begin conversion. When programmed as an output pin (b8
high when a conversion begins and returns low when completed.
signal. The state of this pin should not be changed after power-up.
e
1), a rising edge on this pin causes the ADC’s sample-and-hold to
D7– D0 are active and D12– D8 are always in TRI-STATE. When the BW bit is set (BW
pins D12 –D0. The signal at this pin is used by the ADC12048 to latch in data on D12– D0. The sense of the WMODE pin
at power-up will determine which edge of the WR
signal the ADC12048 will latch in data. See WMODE pin description.
data bus.
input/output buffers of the data bus.
section Functional Description and the digital timing diagrams for more detail.
a
A
a
D
ADC12048 is out of the standby mode or has been requested to leave the standby mode.
Analog supply input pin. The device operating supply voltage range isa5Vg10%. Accuracy is guaranteed only if the
a
a
and V
V
A
ofa10mF and a 0.1 m F (ceramic) capacitor. The capacitors should be placed as close to the supply pins of the part as
possible.
are connected to the same potential. This pin should be bypassed to AGND with a parallel combination
D
resistance and low inductance ground return to the system power supply.
Digital supply input pins. The device operating supply voltage range isa5Vg10%. Accuracy is guaranteed only if the
a
a
and V
V
A
ofa10mF and a 0.1 m F (ceramic) capacitor. The capacitors should be placed as close to the supply pins of the part as
possible.
are connected to the same potential. This pin should be bypassed to DGND with a parallel combination
D
and low inductance ground return to the system power supply.
a
a
s
V
(see
Figures 3
b
1 (see
and4). This
Figures 3
REF
REF
A
b
a
s
V
REF
signal. If tied to a logic high, data will he
e
0), the SYNC pin goes
e
1), D12 –D0 are active.
and
44-Pin
PLCC Package
Order Number
ADC12048CIV
See NS Package
Number V44A
*NCeNo Connection.
These pins maybe
grounded.
44-Pin
PQFP Package
Order Number
ADC12048CIVF
See NS Package
Number VGZ44A
TL/H/12387– 34 TL/H/12387– 35
20
Page 21
Register Bit Description
CONFIGURATION REGISTER (Write Only)
This is a 13-bit write-only register that is used to program the functionality of the ADC12048. All data written to the ADC12048 will always go to this register only.
The contents of this register cannot be read.
Power on State: 0100Hex
b
: The MUX ADDRESS bits configure the analog input MUX. They select which input channels of the MUX will connect to the MUXOUTaand MUXOUT
3–b0
pins. (Refer to the MUX section for more details on the MUX.) Power-up value is 0000.
b
–b4: The ACQ TIME bits select one of four possible acquistion times in SYNC-OUT mode. (Refer to Selectable Acquisition Time section.)
5
b
:When the Single-Ended bit (SE bit) is set, conversion results will be limited to positive values only and any negative conversion results will appear as a code of
6
zero in the Data register. The SE bit is cleared at power-up.
b
: The High Byte bit (HB) is meaningful only in 8-bit mode (BW bit b
7
access the upper byte of the Configuration Register in 8-bit mode. When this bit is set and bit b
upper byte of the Configuration register. The HB bit will automatically be cleared when data is written to the upper byte of the Configuration register, allowing the
lower byte to be accessed with the next write. The HB bit is cleared at power-up.
b
: The SYNC bit. When the SYNC bit is set, the SYNC pin is programmed as an input and the converter is in synchronous mode. In this mode a rising edge on the
8
SYNC pin causes the ADC to hold the input signal and begin a conversion. When b
asynchronous mode. In this mode the signal at the SYNC pin indicates the status of the converter. The SYNC pin is high when a conversion is taking place. The
SYNC bit is set at power-up.
b
: The command field. These bits select the mode of operation of the ADC12048. Power-up value is 000. (See Note 22)
11–b9
b11b10b
9
0 0 0 Standby command. This puts the ADC in a low power consumption mode
0 0 1 Ful-Cal command. This will cause the ADC to perform a self-calibrating cycle that will correct linearity and zero errors.
0 1 0 Auto-zero command. This will cause the ADC to perform an auto-zero cycle that corrects offset errors.
0 1 1 Reset command. This puts the ADC in an idle mode.
1 0 0 Start command. This will put the converter in a start mode, preparing it to perform a conversion. If in asynchronous mode (b
b12: This is the Bus Width (BW) bit. When this bit is cleared the ADC12048 is configured to interface with an 8-bit data bus; data pins D7–D0are active and pins
are in TRI-STATE. When the BW bit is set, the ADC12048 is configured to interface with a 16-bit data bus and data pins D13–D0are all active. The BW bit
D
12–D9
is cleared at power-up.
DATA REGISTER (Read Only)
This is a 13-bit read only register that holds the 12-bitasign conversion result in two’s compliment form. All reads performed from the ADC12048 will place the
contents of this register on the data bus. When reading the data register in 8-bit mode, the sign bit is extended.
MSB LSB
sign Conversion Data
Power on State: 0000Hex
b
: b11is the most significant bit and b0is the least significant bit of the conversion result.
11–b0
b
: This bit contains the sign of the conversion result. 0 for positive results and 1 for negative.
12
MSB LSB
b12b11b10b9b8b7b6b5b4b3b2b1b
COMMAND
BW
FIELD
SYNC HB SE ACQ TIME MUX ADDRESS
0
TABLE I. MUX Channel Assignment
b
3
0000 CH0 CH1
0001 CH1 CH0
0010 CH2 CH3
0011 CH3 CH2
0100 CH4 CH5
0101 CH5 CH4
0110 CH6 CH7
0111 CH7 CH6
1000 CH0 COM
1001 CH1 COM
1010 CH2 COM
1011 CH3 COM
1100 CH4 COM
1101 CH5 COM
1110 CH6 COM
1111 CH7 COM
b
2
b
1
b
5
00 9
01 15
10 47
11 79
b
0
b
4
e
‘‘0’’) and is a don’t care condition in 13-bit mode (BW bit b
12
Clocks
cleared, the SYNC pin is programmed as an output and the converter is in an
15
a
MUXOUT
e
0, the next byte written to the ADC12048 will program the
12
Command
e
will immediately begin after the programmed acquisition time has ended. In synchronous mode (b
edge appears on the SYNC pin.
b
12b11b10
b
b
b
b
b
9
8
7
6
b
5
4
‘‘1’’), conversions will begin after a rising
8
b
b
3
2
MUXOUT
12
b
1
b
e
‘‘1’’). This bit is used to
e
‘‘0’’), conversions
8
b
0
b
21
Page 22
Functional Description
The ADC12048 is programmed through a digital interface
that supports an 8-bit or 16-bit data bus. The digital interface consists of a 13-bit data input/output bus (D
digital control signals and two internal registers: a write only
12–D0
13-bit Configuration register and a read only 13-bit Data
register.
The Configuration register programs the functionality of the
ADC12048. The 13 bits of the Configuration register are divided into 7 fields. Each field controls a specific function of
the ADC12048: the channel selection of the MUX, the acquisition time, synchronous or asynchronous conversions,
mode of operation and the data bus size.
Features and Operating Modes
SELECTABLE BUS WIDTH
The ADC12048 can be programmed to interface with an
8-bit or 16-bit data bus. The BW bit (b
tion register controls the bus size. The bus width is set to
8 bits (D
the BW bit is cleared or 13 bits (D
are active and D12–D8are in TRI-STATE) if
7–D0
BW bit is set. At power-up the bus width defaults to 8 bits
and any initial programming of the ADC12048 should take
this into consideration.
In 8-bit mode the Configuration register is byte accessible.
The HB bit in the lower byte of the Configuration register is
used to access the upper byte. If the HB bit is set with a
write to the lower byte, the next byte written to the ADC will
be placed in the upper byte of the Configuration register.
After data is written to the upper byte of the Configuration
register, the HB bit will automatically be cleared, causing the
next byte written to the ADC to go to the lower byte of the
Configuration register. When reading the ADC in 8-bit mode,
the first read cycle places the lower byte of the Data register
on the data bus followed by the upper byte during the next
read cycle.
In 13-bit mode the HB bit is a don’t care condition and all
bits of the data register and Configuration register are accessible with a single read or write cycle. Since the bus
width of the ADC12048 defaults to 8 bits after power-up, the
first action when 13-bit mode is desired must be set to the
bus width to 13 bits.
WMODE
The WMODE pin is used to determine the active edge of the
write pulse. The state of this pin determines which edge of
the WR
signal will cause the ADC to latch in data. This is
processor dependent. If the processor has valid data on the
bus during the falling edge of the WR
pin must be tied to V
the data on the falling edge of the WR
on the rising edge of the WR
a
. This will cause the ADC to latch
D
signal, the WMODE pin must
be tied to DGND causing the ADC to latch in the data on the
rising edge of the WR
signal.
INPUT MULTIPLEXER
The ADC12048 has an eight channel input multiplexer with
a COM input that can be used in a single-ended, pseudo-differential or fully-differential mode. The MUX select bits (b
b
) in the Configuration register determine which channels
0
will appear at the MUXOUT
a
and MUXOUTbmultiplexer
output pins. (Refer to Register Bit Description Section.) Analog signal conditioning with fixed-gain amplifiers, programmable-gain amplifiers, filters and other processing circuits
) in the Configura-
12
are active) if the
12–D0
signal, the WMODE
signal. If data is valid
3
can be used at the output of the multiplexer before being
applied to the ADC inputs. The ADCIN
the fully differential non-inverting (positive) and inverting
(negative) inputs to the analog-to-digital converter (ADC) of
),
the ADC12048. If no external signal conditioning is required
on the signal output of the multiplexer, MUXOUT
be connected to ADCIN
nected to ADCIN
a
b
and MUXOUTbshould be con-
.
The analog input multiplexer can be set up to operate in
either one of eight differential or eight single-ended (the
COM input as the zero reference) modes. In the differential
mode, the analog inputs are paired as follows: CH0 with
CH1, CH2 with CH3, CH4 with CH5 and CH6 with CH7. The
input channel pairs can be connected to the MUXOUT
and MUXOUTbpins in any order. In the single-ended
mode, one of the input channels, CH0 through CH7, can be
assigned to MUXOUT
a
while the MUXOUTbis always as-
signed to the COM input.
STANDBY MODE
The ADC12048 has a low power consumption mode (75 mW
@
5V). This mode is entered when a Standby command is
written in the command field of the Configuration register. A
logic low appearing on the STDBY
output pin indicates that
the ADC12048 is in the Standby mode. Any command other
than the Standby command written to the Configuration register will get the ADC12048 out of the Standby mode. The
STDBY
pin will immediately switch to a logic ‘‘1’’ as soon as
the ADC12048 is requested to get out of the standby mode.
The RDY
pin will then be asserted low when the ADC is
actually out of the Standby mode and ready for normal operation. The ADC12048 defaults to the Standby mode following a hardware power-up. This can be verified by examining
the logic low status of the STDBY
pin.
SYNC/ASYNC MODE
The ADC12048 may be programmed to operate in synchronous (SYNC-IN) or asynchronous (SYNC-OUT) mode. To
enter synchronous mode, the SYNC bit in the Configuration
register must be set. The ADC12048 is in synchronous
mode after a hardware power-up. In this mode, the SYNC
pin is programmed as an input and conversions are synchronized to the rising edges of the signal applied at the
SYNC pin. Acquisition time can also be controlled by the
SYNC signal when in synchronous mode. Refer to the syncin timing diagrams. When the SYNC bit is cleared, the ADC
is in asynchronous mode and the SYNC pin is programmed
as an output. In asynchronous mode, the signal at the
SYNC pin indicates the status of the converter. This pin is
high when the converter is performing a conversion. Refer
to the sync-out timing diagrams.
SELECTABLE ACQUISITION TIME
The ADC12048’s internal sample/hold circuitry samples an
input voltage by connecting the input to an internal sampling
capacitor (approximately 70 pF) through an effective resistance equal to the multiplexer ‘‘On’’ resistance (300X max)
plus the ‘‘On’’ resistance of the analog switch at the input to
the sample/hold circuit (2500X typical) and the effective
output resistance of the source. For conversion results to be
accurate, the period during which the sampling capacitor is
–
connected to the source (the ‘‘acquisition time’’) must be
long enough to charge the capacitor to within a small fraction of an LSB of the input voltage. An acquisition time of
750 ns is sufficient when the external source resistance is
a
and ADCINbare
a
should
a
22
Page 23
Features and Operating Modes (Continued)
less than 1 kX and any active or reactive source circuitry
settles to 12 bits in less than 500 ns. When source resistance or source settling time increase beyond these limits,
the acquisition time must also be increased to preserve precision.
In asynchronous (SYNC-OUT) mode, the acquisition time is
controlled by an internal counter. The minimum acquisition
period is 9 clock cycles, which corresponds to the nominal
value of 750 ns when the clock frequency is 12 MHz. Bits b
and b5of the Configuration Register are used to select the
acquisition time from among four possible values (9, 15, 47,
or 79 clock cycles). Since acquisition time in the asynchronous mode is based on counting clock cycles, it is also inversely proportional to clock frequency:
ACQ
(ms)
e
f
(MHz)
CLK
T
number of clock cycles
Note that the actual acquisition time will be longer than
T
because acquisition begins either when the multiplex-
ACQ
er channel is changed or when RDY
goes low, if the multiplexer channel is not changed. After a read is performed,
RDY
goes high, which starts the T
7
).
ACQ
counter (see
In synchronous (SYNC-IN) mode, bits b4and b5are ignored, and the acquisition time depends on the sync signal
applied at the SYNC pin. If a new MUX channel is selected
at the start of the conversion, the acquisition period begins
on the active edge of the WR
MUX channel (see
Figure 7
signal that latches in the new
). If no new MUX channel is
selected, the acquisition period begins on the falling edge of
RDY
, which occurs at the end of the previous conversion (or
at the end of an autozero or autocalibration procedure). The
acquisition period ends when SYNC goes high.
To estimate the acquisition time necessary for accurate
conversions when the source resistance is greater than
1kX, use the following expression:
a
T
ACQMIN
where R
resistance, and R
is the source resistance, RMis the MUX ‘‘On’’
S
0.75(R
e
(ms)
1kXaR
0.75(R
e
is the sample/hold ‘‘On’’ resistance.
S/H
S
S
3800
a
R
M
a
M
2800)
a
R
S/H
R
S/H
If the settling time of the source is greater than 500 ns, the
acquisition time should be about 300 ns longer than the
settling time for a ‘‘well-behaved’’, smooth settling characteristic.
FULL CALIBRATION CYCLE
A full calibration cycle compensates for the ADC’s linearity
and offset errors. The converter’s DC specifications are
guaranteed only after a full calibration has been performed.
A full calibration cycle is initated by writing a Ful-Cal command to the ADC12048. During a full calibration, the offset
error is measured eight times, averaged and a correction
coefficient is created. The offset correction coefficient is
stored in an internal offset correction register.
The overall Iinearity correction is achieved by correctng the
internal DAC’s capacitor mismatches. Each capacitor is
compared eight times against all remaining smaller value
capacitors. The errors are averaged and correction coefficients are created.
4
Figure
)
Once the converter has been calibrated, an arithmetic logic
unit (ALU) uses the offset and linearity correction coefficients to reduce the conversion offset and linearity errors to
within guaranteed limits.
AUTO-ZERO CYCLE
During an auto-zero cycle, the offset is measured only once
and a correction coefficient is created and stored in an internal offset register. An auto-zero cycle is initiated by writing
an Auto-Zero command to the ADC12048.
DIGITAL INTERFACE
The digital control signals are CS
STDBY
. Specific timing relationships are associated with
,RD,WR,RDY and
the interaction of these signals. Refer to the Digital Timing
Diagrams section for detailed timing specifications. The active low RDY
signal indicates when a certain event begins
and ends. It is recommended that the ADC12048 should
only be accessed when the RDY
signal is low. It is in this
state that the ADC12048 is ready to accept a new command. This will minimize the effect of noise generated by a
switching data bus on the ADC. The only exception to this is
when the ADC12048 is in the standby mode at which time
the RDY
is high and the STDBY signal is low. The
ADC12048 is in the standby mode at power up or when a
STANDBY command is issued. A Ful-Cal, Auto-Zero, Reset
or Start command will get the ADC12048 out of the standby
mode. This may be observed by monitoring the status of the
RDY
and STDBY signals. The RDY signal will go low and
the STDBY
signal high when the ADC12048 leaves the
standby mode.
The following describes the state of the digital control signals for each programmed event in both 8-bit and 13-bit
mode. RDY
should be low before each command is issued
except for the case when the device is in standby mode.
FUL-CAL OR AUTO-ZERO COMMAND
8-bit
mode: The first write to the ADC12048 will place the
data in the lower byte of the Configuration register. This byte
must set the HB bit (b
the Configuration register during the next write cycle. During
) to allow access to the upper byte of
7
the second write cycle, the Ful-Cal or Auto-Zero command
must be issued. The edge of the second write pulse on the
WR
pin will force the RDY signal high. At this time the converter begins executing a full calibration or auto-zero cycle.
The RDY
signal will automatically go low when the full cali-
bration or auto-zero cycle is done.
13-bit
mode: In a single write cycle the Ful-Cal or Auto-Zero
command must be written to the ADC12048. The edge of
the WR
signal will force the RDY high. At this time the converter begins executing a full calibration or auto-zero cycle.
The RDY
signal will automatically go low when the full cali-
bration or auto-zero cycle is done.
STARTING A CONVERSION: START COMMAND
In order to completely describe the events associated with
the Start command, both the SYNC-OUT and SYNC-IN
modes must be considered.
SYNC-OUT/Asynchronous
8-bit
mode: The first byte written to the ADC12048 should
set the MUX channel, the acquisition time and the HB bit.
The second byte should clear the SYNC bit, write the
START command and clear the BW bit. In order to initiate a
23
Page 24
Features and Operating Modes (Continued)
conversion, two reads must be performed from the
ADC12048. The rising edge of the second read pulse will
force the RDY
tion time selected by bits b
register. The SYNC pin will go high indicating that a conversion sequence has begun following the end of the acquisition period. The RDY
conversion is done. At this time new information, such as a
new MUX channel, acquisition time and operational command can be written into the configuration register or it can
remain unchanged. Assuming that the START command is
in the Configuration register, the previous conversion can be
read. The first read places the lower byte of the conversion
result contained in the Data register on the data bus. The
second read will place the upper byte of the conversion
result stored in the Data register on the data bus. The rising
edge on the second read pulse will begin another conversion sequence and raise the RDY
priately.
13-bit
should be set, the SYNC bit cleared and the START command issued with a single write to the ADC12048. In order
to initiate a conversion, a single read must be performed
from the ADC12048. The rising edge of the read signal will
force the RDY
sition time selected by bits b
register. The SYNC pin will go high indicating that a conversion sequence has begun following the end of the acquisition period. The RDY
conversion is done. At this time new information, such as a
new MUX channel, acquisition time and operational command can be written into the configuration register or it can
remain unchanged. With the START command in the Configuration register, a read from the ADC12048 will place the
entire 13-bit conversion result stored in the data register on
the data bus. The rising edge of the read pulse will immediately force the RDY
following the elapse of the programmed acquisition time in
the configuration register’s bits b
SYNC-IN/Synchronous
For the SYNC-IN case, it is assumed that a series of SYNC
pulses at the desired sampling rate are applied at the SYNC
pin of the ADC12048.
8-bit
mode: The first byte written to the ADC12048 should
set the MUX channel and the HB bit. The second byte
should set the SYNC bit, write the START command and
clear the BW bit.
A rising edge on the SYNC pin or the second rising edge of
two consecutive reads from the ADC12048 will force the
RDY
signal high. It is recommended that the action of reading from the ADC12048 (not the rising edge of the SYNC
signal) be used to raise the RDY
mode, only the rising edge of the SYNC signal will begin a
conversion cycle. The rising edge of the SYNC also ends
the acquisition period. The acquisition period begins following a write cycle containing MUX channel information. The
selected MUX channel is sampled after the rising edge of
the WR
which time the signal will be held and conversion begins.
pin high and begin the programmed acquisi-
and b4of the configuration
5
and SYNC signal will fall low when the
and SYNC signals appro-
mode: The MUX channel and the acquisition time
signal high and begin the programmed acqui-
and b4of the configuration
5
and SYNC signal will fall low when the
output high. The SYNC will then go high
and b4.
5
signal. In the SYNC-IN
signal until the rising edge of the SYNC pulse, at
The RDY
signal will go low when the conversion is done. A
new MUX channel and/or operational command may be
written into the Configuration register at this time, if needed.
Two consecutive read cycles are required to retrieve the
entire 13-bit conversion result from the ADC12048’s data
register. The first read will place the lower byte of the conversion result contained in the Data register on the data
bus. The second read will place the upper byte of the conversion result stored in the Data register on the data bus.
With the START command in the configuration register, the
rising edge of the second read pulse will raise the RDY
signal high and begin a conversion cycle following a rising
edge on the SYNC pin.
13-bit
mode: The MUX channel should be selected, the
SYNC bit should be set and the START command issued
with a single write to the ADC12048. A rising edge on the
SYNC pin or on the RD
pin will force the RDY signal high. It
is recommended that the action of reading from the
ADC12048 (not the rising edge of the SYNC signal) be used
to raise the RDY
signal. This will ensure that the conversion
result is read during the acquisition period of the next conversion cycle, eliminating a read from the ADC12048 while it
is performing a conversion. Noise generated by accessing
the ADC12048 while it is converting may degrade the conversion result. In the SYNC-IN mode, only the rising edge of
the SYNC signal will begin a conversion cycle. The RDY
signal will go low when the conversion cycle is done. The
acquisition time is controlled by the SYNC signal. The acquisition period begins following a write cycle containing MUX
channel information. The selected MUX channel is sampled
after the rising edge of the WR
signal until the rising edge of
the SYNC pulse, at which time the signal will be held and
conversion begins. A new MUX channel and/or operational
command may be written into the Configuration register at
this time, if needed. With the START command in the Configuration register, a read from the ADC12048 will place the
entire conversion result stored in the Data register on the
data bus and the rising edge of the read pulse will force the
RDY
signal high. The selected MUX channel will be sampled until a rising edge appears on the SYNC pin, at which
the time sampled signal will be held and a conversion cycle
started.
STANDBY COMMAND
8-bit
mode: The first byte written to the ADC12048 should
set the HB bit in the Configuration register (bit b
ond byte must issue the Standby command (bits b
e
0, 0, 0).
13-bit
mode: The Standby command must be issued to the
ADC12048 in single write (bits b
11,b10,b9
e
). The sec-
7
11,b10,b9
0, 0, 0).
RESET
The RESET command places the ADC12048 into a ready
state and forces the RDY
signal low. The RESET command
can be used to interrupt the ADC12048 while it is performing
a conversion, full-calibration or auto-zero cycle. It can also
be used to get the ADC12048 out of the standby mode.
24
Page 25
Analog Application Information
REFERENCE VOLTAGE
The ADC12048 has two reference inputs, V
b
V
. They define the zero to full-scale range of the ana-
REF
log input signals over which 4095 positive and 4096 negative codes exist. The reference inputs can be connected to
span the entire supply voltage range (V
a
a
e
V
ages when other input spans are required. The reference
REF
V
) or they can be connected to different volt-
A
REF
inputs of the ADC12048 have transient capacitive switching
currents. The voltage sources driving V
must have very low output impedence and noise and must
be adequately bypassed. The circuit in
REF
Figure 8
ple of a very stable reference source.
The ADC12048 can be used in either ratiometric or absolute
reference appplications. In ratiometric systems, the analog
REF
b
e
a
and V
is an exam-
a
and
AGND,
REF
input voltage is proportional to the voltage used for the
ADC’s reference voltage. This technique relaxes the system
reference requirements because the analog input voltage
moves with the ADC’s reference. The system power supply
can be used as the reference voltage by connecting the
a
V
REF
lute accuracy, where the analog input voltage varies be-
pin to V
a
A
and the V
b
pin to AGND. For abso-
REF
tween very specific voltage limits, a time and temperature
stable voltage source can be connected to the reference
b
inputs. Typically, the reference voltage’s magnitude will require an initial adjustment to null reference voltage induced
full-scale errors.
The reference voltage inputs are not fully differential. The
ADC12048 will not generate correct conversions if V
b
V
is below 1V.
REF
ship between V
REF
Figure 9
a
and V
shows the allowable relation-
b
.
REF
REF
a
–
OUTPUT DIGITAL CODE VERSUS ANALOG INPUT
VOLTAGE
The ADC12048’s fully differential 12-bit
a
sign ADC generates a two’s complement output that is found by using the
equation shown below:
a
b
b
(V
V
IN
Output code
Round off the result to the nearest integer value between
b
4096 and 4095.
e
(V
REF
) (4096)
IN
a
b
b
V
)
REF
FIGURE 9. V
*Tantalum
**Ceramic
TL/H/12387– 37
Operating Range
REF
FIGURE 8. Low Drift Extremely Stable Reference Circuit
Part Number
LM4041CI-Adj
LM4040AI-4.1
LM9140BYZ-4.1
LM368Y-5.0
Circuit of
Figure 8
Output Voltage Temperature
Tolerance Coefficient
g
0.5%
g
0.1%
g
0.5%
g
0.1%
Adjustable
25
g
100ppm/§C
g
100ppm/§C
g
25ppm/§C
g
20ppm/§C
g
2ppm/§C
TL/H/12387– 36
Page 26
Analog Application Information (Continued)
INPUT CURRENT
At the start of the acquisition window (t
ing current (due to capacitive switching) flows through the
analog input pins (CH0 –CH7, ADCIN
AcqSYNOUT
a
the COM). The peak value of this input current will depend
on the amplitude and frequency of the input voltage applied,
the source impedance and the input switch ON resistance.
With the MUXOUT
b
MUXOUT
typically 2800X. Bypassing the MUX and using just the
a
ADCIN
a
connected to the ADCINaand the
connected to the ADCINbthe on resistance is
and ADCINbinputs the on resistance is typically
2500X.
For low impedance voltage sources (1000
operation), the input charging current will decay to a value
that will not introduce any conversion errors before the end
of the default sample-and-hold (S/H) acquisition time (9
clock cycles). For higher source impedances (1000
12 MHz operation), the S/H acquisition time should be increased to allow the charging current to settle within specified limits. In asynchronous mode, the acquisition time may
be increased to 15, 47 or 79 clock cycles. If different acquisition times are needed, the synchronous mode can be
used to fully control the acquisition time.
INPUT BYPASS CAPACITANCE
External capacitors (0.01 mF – 0.1 mF) can be connected between the analog input pins (CH0– CH7) and the analog
ground to filter any noise caused by inconductive pickup
associated with long leads.
POWER SUPPLY CONSIDERATIONS
Decoupling and bypassing the power supply on a high resolution ADC is an important design task. Noise spikes on the
a
V
(analog supply) or V
A
version errors. The analog comparator used in the ADC will
a
(digital supply) can cause con-
D
respond to power supply noise and will make erroneous
conversion decisions. The ADC is especially sensitive to
power supply spikes that occur during the auto-zero or linearity calibration cycles.
The ADC12048 is designed to operate from a single
power supply. The separate supply and ground pins for the
analog and digital portions of the circuit allow separate external bypassing. To minimize power supply noise and ripple, adequate bypass capacitors should be placed directly
between power supply pins and their associated grounds.
Both supply pins should be connected to the same supply
source. In systems with separate analog and digital supplies, the ADC should be powered from the analog supply.
At least a 10 mF tantalum electrolytic capacitor in parallel
with a 0.1 mF monolithic ceramic capacitor is recommended
for bypassing each power supply. The key consideration for
these capacitors is to have low series resistance and inductance. The capacitors should be placed as close as physically possible to the supply and ground pins with the smaller
capacitor closer to the device. The capacitors also should
have the shortest possible leads in order to minimize series
lead inductance. Surface mount chip capacitors are optimal
in this respect and should be used when possible.
When the power supply regulator is not local on the board,
adequate bypassing (a high value electrolytic capacitor)
should be placed at the power entry point. The value of the
capacitor depends on the total supply current of the circuits
) a charg-
and ADCINb, and
k
X for 12 MHz
l
X for
a
5V
on the PC board. All supply currents should be supplied by
the capacitor instead of being drawn from the external supply lines, while the external supply charges the capacitor at
a steady rate.
The ADC has two V
to use a 0.1 mFplusa10mF capacitor between pins 15 and
a
16 (V
) and 14 (DGND) and a 0.1 mF capacitor between
D
pins 28 (V
respective pins for the SO package are 21 and 22 (V
D
and 20 (DGND), 6 (V
in
Figure 10
a
and DGND pins. It is recommended
D
a
) and 1 (DGND) for the PLCC package. The
a
) and 7 (DGND). The layout diagram
D
shows the recommended placement for the
D
supply bypass capacitors.
PC BOARD LAYOUT AND GROUNDING
CONSIDERATlONS
To get the best possible performance from the ADC12048,
the printed circuit boards should have separate analog and
digital ground planes. The reason for using two ground
planes is to prevent digital and analog ground currents from
sharing the same path until they reach a very low impedance power supply point. This will prevent noisy digital
switching currents from being injected into the analog
ground.
Figure 10
illustrates a favorable layout for ground planes,
power supply and reference input bypass capacitors. It
shows a layout using a 44-pin PLCC socket and throughhole assembly. A similar approach should be used for the
PQFP package.
The analog ground plane should encompass the area under
the analog pins and any other analog components such as
the reference circuit, input amplifiers, signal conditioning circuits, and analog signal traces.
The digital ground plane should encompass the area under
the digital circuits and the digital input/output pins of the
ADC12048. Having a continuous digital ground plane under
the data and clock traces is very important. This reduces
the overshoot/undershoot and high frequency ringing on
these lines that can be capacitively coupled to analog circuitry sections through stray capacitances.
The AGND and DGND in the ADC12048 are not internally
connected together. They should be connected together on
the PC board right at the chip. This will provide the shortest
return path for the signals being exchanged between the
internal analog and digital sections of the ADC.
It is also a good design practice to have power plane layers
in the PC board. This will improve the supply bypassing (an
effective distributed capacitance between power and
ground plane layers) and voltage drops on the supply lines.
However, power planes are not as essential as ground
planes are for satisfactory performance. If power planes are
used, they should be separated into two planes and the
area and connections should follow the same guidelines as
mentioned for the ground planes. Each power plane should
be laid out over its associated ground planes, avoiding any
overlap between power and ground planes of different
types. When the power planes are not used, it is recommended to use separate supply traces for the V
a
V
pins from a low impedance supply point (the regulator
D
output or the power entry point to the PC board). This will
a
and
A
help ensure that the noisy digital supply does not corrupt
the analog supply.
a
)
26
Page 27
Analog Application Information (Continued)
FIGURE 10. Top View of Printed Circuit Board for a 44-Pin PLCC ADC12048
When measuring AC input signals, any crosstalk between
analog input/output lines and the reference lines (CH0–
CH7, MUXOUT
g
, ADC INg,V
Crosstalk is minimized by reducing any stray capacitance
g
) should be minimized.
REF
between the lines. This can be done by increasing the clearance between traces, keeping the traces as short as possible, shielding traces from each other by placing them on
different sides of the AGND plane, or running AGND traces
between them.
Figure 10
also shows the reference input bypass capacitors.
Here the reference inputs are considered to be differential.
The performance improves by having a 0.1 mF capacitor
between the V
manner similar to that described for the supply pins. When a
single ended reference is used, V
AGND and only two capacitors are used between V
b
and V
REF
connect the AGND side of these capacitors to the V
instead of connecting V
capacitors separately to the ground planes. This provides a
REF
a
and V
b
, and by bypassing in a
REF
b
is connected to
REF
(0.1 mFa10 mF). It is recommended to directly
b
and the ground sides of the
REF
significantly lower-impedance connection when using surface mount technology.
27
TL/H/12387– 38
REF
REF
a
b
Page 28
28
Page 29
Physical Dimensions inches (millimeters)
44-Lead Molded Plastic Leaded Chip Carrier
Order Number ADC12048CIV
NS Package Number V44A
29
Page 30
Physical Dimensions inches (millimeters) (Continued)
44-Lead (10mm x 10mm) Molded Plastic Quad Flat Package
Order Number ADC12048CIVF
NS Package Number VGZ44A
LIFE SUPPORT POLICY
NATIONAL’S PRODUCTS ARE NOT AUTHORIZED FOR USE AS CRITICAL COMPONENTS IN LIFE SUPPORT
DEVICES OR SYSTEMS WITHOUT THE EXPRESS WRITTEN APPROVAL OF THE PRESIDENT OF NATIONAL
SEMICONDUCTOR CORPORATION. As used herein:
1. Life support devices or systems are devices or 2. A critical component is any component of a life
systems which, (a) are intended for surgical implant support device or system whose failure to perform can
into the body, or (b) support or sustain life, and whose be reasonably expected to cause the failure of the life
failure to perform, when properly used in accordance support device or system, or to affect its safety or
with instructions for use provided in the labeling, can effectiveness.
be reasonably expected to result in a significant injury
ADC12048 12-Bit Plus Sign 216 kHz 8-Channel Sampling Analog-to-Digital Converter
to the user.
National Semiconductor National Semiconductor National Semiconductor National Semiconductor
Corporation Europe Hong Kong Ltd. Japan Ltd.
1111 West Bardin Road Fax:
Arlington, TX 76017 Email: europe.support@nsc.com Ocean Centre, 5 Canton Rd. Fax: 81-043-299-2408
Tel: 1(800) 272-9959 Deutsch Tel:
Fax: 1(800) 737-7018 English Tel:
National does not assume any responsibility for use of any circuitry described, no circuit patent licenses are implied and National reserves the right at any time without notice to change said circuitry and specifications.
Fran3ais Tel:
Italiano Tel:
a
49 (0) 180-530 85 86 13th Floor, Straight Block, Tel: 81-043-299-2308
a
49 (0) 180-530 85 85 Tsimshatsui, Kowloon
a
49 (0) 180-532 78 32 Hong Kong
a
49 (0) 180-532 93 58 Tel: (852) 2737-1600
a
49 (0) 180-534 16 80 Fax: (852) 2736-9960
Loading...