Rainbow Electronics ADC12041 User Manual
ADC12041
12-Bit Plus Sign 216 kHz Sampling
Analog-to-Digital Converter
ADC12041 12-Bit Plus Sign 216 kHz Sampling Analog-to-Digital Converter
December 1995
General Description
Operating from a single 5V power supply the ADC12041 is a
a
12 bit
sign, parallel I/O, self-calibrating, sampling analogto-digital converter (ADC). The maximum sampling rate is
216 kHz. On request, the ADC goes through a self-calibration process that adjusts linearity, zero and full-scale errors.
The ADC12041 can be configured to work with many popular microprocessors/microcontrollers including National’s
HPC family, Intel386 and 8051, TMS320C25, Motorola
MC68HC11/16, Hitachi 64180 and Analog Devices
ADSP21xx.
For complementary voltage references see the LM4040,
LM4041 or LM9140.
Key Specifications (f
Y
Resolution 12-bitsasign
Y
13-bit conversion time 3.6 ms, max
Y
13-bit throughput rate 216 ksamples/s, min
Y
Integral Linearity Error (ILE)
Y
Single supply
CLK
e
12 MHz)
g
1 LSB, max
a
5Vg10%
Block Diagram
Y
VINrange GND to V
Y
Power consumption:
Normal operation 33 mW, max
Stand-by mode 75 mw, max
Features
Y
Fully differential analog input
Y
Programmable acquisition times and user-controllable
throughput rates
Y
Programmable data bus width (8/13 bits)
Y
Built-in Sample-and-Hold
Y
Programmable auto-calibration and auto-zero cycles
Y
Low power standby mode
Y
No missing codes
Applications
Y
Medical instrumentation
Y
Process control systems
Y
Test equipment
Y
Data logging
Y
Inertial guidance
a
A
TL/H/12441– 1
TRI-STATEÉis a registered trademark of National Semiconductor Corporations.
C
1996 National Semiconductor Corporation RRD-B30M26/Printed in U. S. A.
TL/H/12441
Connection Diagrams
28-Pin SSOP
28-Pin PLCC
Order Number ADC12041CIMSA
See NS Package Number MSA28
Ordering Information
Order Number ADC12041CIV
See NS Package Number V28A
TL/H/12441– 2
Industrial Temperature Range
b
40§CsT
ADC12041CIV V28A
ADC12041CIMSA MSA28, SSOP
s
a
85§C
A
NS
Package
Number
TL/H/12441– 3
2
Absolute Maximum Ratings
(Notes 1 and 2)
Supply Voltage (V
Voltage at all Inputs
ab
V
l
A
AGNDbDGND
l
Input Current at Any Pin (Note 3)
Package Input Current (Note 3)
Power Dissipation (Note 4)
e
at T
A
Storage Temperature
Lead Temperature
SSOP Package
Vapor Phase (60 sec.) 210
Infared (15 sec.) 220
V Package, Infared (15 sec.) 300
a
A
a
V
l
D
a
and V
) 6.0V
D
b
0.3V to V
a
l
g
25§C 500 mW
b
65§Ctoa150§C
a
0.3V
300 mV
300 mV
g
30 mA
120 mA
§
§
§
Operating Ratings (Notes 1 and 2)
Temperature Range
s
(T
Supply Voltage
V
A
a
V
l
A
AGNDbDGND
l
VINVoltage Range at all Inputs GNDsV
V
REF
V
REF
V
REF
V
REF
C
C
C
s
T
T
min
a
a
,V
D
a
b
V
D
)
A
max
l
l
a
Input Voltage 1VsV
b
Input Voltage 0sV
a
Common Mode 0.1 V
b
b
V
REF
a
A
ESD Susceptibility (Note 5) 3.0 kV
Converter DC Characteristics The following specifications apply to the ADC12041 for V
a
e
V
and V
otherwise specified. Boldface limits apply for T
REF
4.096V, V
b
s
1X, fully differential input with fixed 2.048V common-mode voltage (V
REF
Symbol Parameter Conditions
b
e
0.0V, 12-bitasign conversion mode, f
REF
e
12.0 MHz, R
CLK
e
e
T
T
A
J
MIN
to T
MAX
e
25X, source impedance for V
S
), and minimum acquisition time, unless
INCM
; all other limits T
e
T
A
Typical Limits Units
(Note 10) (Note 11) (Limit)
Resolution with No Missing Codes After Auto-Cal 13 Bits (max)
ILE Positive and Negative Integral After Auto-Cal
Linearity Error (Notes 12 and 17)
g
0.6
DNL Differential Non-Linearity After Auto-Cal
Zero Error After Auto-Cal (Notes 13 and 17)
e
V
V
V
Positive Full-Scale Error After Auto-Cal (Notes 12 and 17)
Negative Full-Scale Error After Auto-Cal (Notes 12 and 17)
DC Common Mode Error After Auto-Cal (Note 14)
TUE Total Unadjusted Error After Auto-Cal (Note 18)
INCM
INCM
INCM
e
e
5.0V
2.048V
0V
g
1.0
g
1.0
g
2
g
1 LSB
b
40§CsT
s
A
4.5V to 5.5V
s
100 mV
s
100 mV
a
s
IN
a
s
REF
b
REF
1VsV
s
V
REFCM
A
e
25§C
J
g
1 LSB (max)
g
1 LSB (max)
g
5.5
g
2.0
g
5.5
g
2.5 LSB (max)
g
2.5 LSB (max)
g
5.5 LSB (max)
a
s
V
REF
s
REF
s
0.6 V
a
a
e
V
D
LSB (max)
b
e
REF
85§C
V
A
V
A
1V
V
A
A
5V,
a
a
a
a
a
3
Power Supply Characteristics The following specifications apply to the ADC12041 for V
a
e
V
and V
specified. Boldface limits apply for T
REF
4.096V, V
b
1X, fully differential input with fixed 2.048V common-mode voltage, and minimum acquisition time, unless otherwise
REF
Symbol Parameter Conditions
PSS Power Supply Sensitivity V
Zero Error V
Full-Scale Error V
Linearity Error
a
I
D
a
V
Digital Supply Current Start Command (Performing a conversion) with SYNC
D
b
e
0.0V, 12-bitasign conversion mode, f
REF
e
T
A
a
e
V
D
a
e
REF
b
e
REF
configured as an input and driven with a 214 kHz
e
J
a
A
4.096V
0V
T
to T
MIN
e
5.0Vg10%
CLK
; all other limits T
MAX
e
12.0 MHz, R
e
25X, source impedance for V
S
e
e
T
A
25§C
J
Typical Limits Unit
(Note 10) (Note 11) (Limit)
g
0.1 LSB
g
0.5 LSB
g
0.1 LSB
signal. Bus width set to 13.
e
f
12.0 MHz, Reset Mode 850 mA
CLK
e
f
12.0 MHz, Conversion 2.45 2.6 mA (max)
a
I
A
a
V
Analog Supply Current Start Command (Performing a conversion) with SYNC
A
CLK
configured as an input and driven with a 214 kHz
signal. Bus width set to 13.
e
f
12.0 MHz, Reset Mode 2.3 mA
CLK
e
f
12.0 MHz, Conversion 2.3 4.0 mA (max)
CLK
I
ST
Symbol Parameter Conditions
I
IN
R
CV
Standby Supply Current Standby Mode
a
a
a
(I
I
D
Analog Input Characteristics The following specifications apply to the ADC12041 for V
a
e
V
REF
a
V
and V
REF
otherwise specified. Boldface limits apply for T
)f
A
b
4.096V, V
a
REF
e
REF
s
0.0V, 12-Bitasign conversion mode, f
1X, fully differential input with fixed 2.048V common-mode voltage, and minimum acquisition time, unless
e
Stopped 5 15 mA (max)
CLK
e
f
12.0 MHz 100 120 mA (max)
CLK
e
12.0 MHz, R
CLK
e
e
T
T
to T
A
J
MIN
; all other limits T
MAX
e
25X, source impedance for
S
Typical Limits Unit
(Note 10) (Note 11) (Limit)
a
V
IN
ADC Input On Resistance V
ON
ADC Input Capacitance 10 pF
IN
and V
b
Input Leakage Current V
IN
a
e
5V 0.05
IN
b
e
V
0V
IN
e
2.5V
IN
Refer to section titled INPUT CURRENT.
b
0.05
1000 X
a
A
a
A
e
T
A
J
2.0 mA (max)
e
e
e
V
D
V
D
25§C
a
e
5V,
a
REF
a
e
5V,
a
a
e
Reference Inputs The following specifications apply to the ADC12041 for V
b
e
V
1X, fully differential input with fixed 2.048V common-mode voltage, and minimum acquisition time, unless otherwise specified.
Boldface limits apply for T
0.0V, 12-bitasign conversion mode, f
REF
e
e
T
A
T
J
MIN
CLK
to T
e
MAX
12.0 MHz, R
S
; all other limits T
e
25X, source impedance for V
e
T
A
Symbol Parameter Conditions
I
REF
Reference Input Current V
a
4.096V, V
REF
Analog Input Signal: 1 kHz 145 mA
REF
b
e
0V
e
V
A
e
25§C
J
5V, V
D
Typical Limits Unit
(Note 10) (Note 11) (Limit)
REF
REF
a
a
and V
e
4.096V,
b
REF
(Note 20) 80 kHz 136 mA
C
REF
Reference Input Capacitance 85 pF
4
s
Digital Logic Input/Output Characteristics The following specifications apply to the ADC12041 for
a
a
e
V
A
impedance for V
tion time, unless otherwise specified. Boldface limits apply for T
e
V
D
REF
25§C
Symbol Parameter Conditions
V
IH
V
IL
I
IH
I
IL
V
OH
V
OL
I
OFF
C
IN
Converter AC Characteristics The following specifications apply to the ADC12041 for V
V
REF
and V
otherwise specified. Boldface limits apply for T
Logic High Input Voltage V
Logic Low Input Voltage V
Logic High Input Current V
Logic Low Input Current V
Logic High Output Voltage V
Logic Low Output Voltage V
TRI-STATE Output Leakage Current V
D12–D0 Input Capacitance 10 pF
a
e
4.096V, V
b
s
REF
1X, fully differential input with fixed 2.048V common-mode voltage, and minimum acquisition time, unless
Symbol Parameter Conditions
t
Z
t
CAL
5V, V
a
REF
and V
a
e
4.096V, V
b
REF
s
b
1X, fully differential input with fixed 2.048V common-mode voltage, and minimum acquisi-
e
e
T
A
T
J
MIN
e
0.0V, 12-bitasign conversion mode, f
REF
CLK
to T
e
12.0 MHz, R
; all other limits T
MAX
e
S
25X, source
e
A
Typical Limits Unit
(Note 10) (Note 11) (Limit)
a
a
e
e
V
5.5V 2.2 V (min)
D
a
e
V
4.5V 0.8 V (max)
D
a
V
D
1.6 mA
V
D
1.6 mA
0V
5V
CLK
T
MIN
e
a
e
to T
4.5V
4.5V
e
12.0 MHz, R
MAX
b
0.035
2.4 2.4 V (min)
0.4 0.4 V (max)
e
25X, source impedance for V
S
; all other limits T
b
g
e
T
A
J
2.0 mA (max)
2.0 mA (max)
a
a
e
V
S
D
e
25§C
b
e
0.0V, 12-bitasign conversion mode, f
REF
A
a
e
A
e
5V 0.035 2.0 mA (max)
IN
e
0V
IN
ae
A
eb
I
OUT
a
e
A
e
I
OUT
e
OUT
e
V
OUT
e
e
T
A
J
Typical Limits Unit
(Note 10) (Note 11) (Limit)
Auto Zero Time 78 78 clksa120 ns clks (max)
Full Calibration Time 4946 4946 clksa120 ns clks (max)
e
REF
T
J
5V,
CLK Duty Cycle 50 %
40 % (min)
60 % (max)
t
CONV
t
AcqSYNCOUT
Conversion Time Sync-Out Mode 44 44 clks (max)
Acquisition Time Minimum for 13 Bits 9 9 clksa120 ns clks (max)
(Programmable) Maximum for 13 Bits 79 79 clks
a
120 ns clks (max)
e
a
5
Digital Timing Characteristics The following specifications apply to the ADC12041, 13-bit data bus width,
a
a
e
V
A
Symbol
(Figure 7)
t
TPR
e
V
D
Throughput Rate Sync-Out Mode (SYNC Bite‘‘0’’) 222 kHz
5V, f
CLK
e
12 MHz, t
e
f
3 ns and C
e
50 pF on data I/O lines
L
Parameter Conditions
9 Clock Cycles of Acquisition
Typical Limits Unit
(Note 10) (Note 11) (Limit)
Time
t
CSWR
t
WRCS
t
WR
t
WRSETFalling
t
WRHOLDFalling
t
WRSETRising
t
WRHOLDRising
t
CSRD
t
RDCS
t
RDDATA
t
RDDATA
t
RDHOLD
t
RDRDY
t
WRRDY
t
STDRDY
Falling Edge of CS
to Falling Edge of WR
Active Edge of WR
to Rising Edge of CS
0ns
0ns
WR Pulse Width 20 30 ns (min)
Write Setup Time WMODEe‘‘1’’ 20 ns (min)
Write Hold Time WMODEe‘‘1’’ 5 ns (min)
Write Setup Time WMODEe‘‘0’’ 20 ns (min)
Write Hold Time WMODEe‘‘0’’ 5 ns (min)
Falling Edge of CS
to Falling Edge of RD
Rising Edge of RD
to Rising Edge of CS
0ns
0ns
Falling Edge of RD to Valid Data 8-Bit Mode (BW Bite‘‘0’’) 40 58 ns (max)
Falling Edge of RD to Valid Data 13-Bit Mode (BW Bite‘‘1’’) 26 44 ns (max)
Read Hold Time 23 32 ns (max)
Rising Edge of RD
to Rising Edge of RDY
Active Edge of WR WMODEe‘‘1’’
to Rising Edge of RDY
24 38 ns (max)
37 60 ns (max)
Active Edge of WR WMODEe‘‘0’’. Writing the
to Falling Edge of RDY
RESET Command into the
1.4 2.5 ms (max)
Configuration Register
t
SYNC
Minimum SYNC Pulse Width 5 10 ns (min)
Notes on Specifications
Note 1: Absolute Maximum Ratings indicate limits beyond which damage to the device may occur. Operating Ratings indicate conditions for which the device is
functional, but do not guarantee specific performance limits. For guaranteed specifications and test conditions, see the Electrical Characteristics. The guaranteed
specifications apply only for the test conditions listed. Some performance characteristics may degrade when the device is not operated under the listed test
conditions.
Note 2: All voltages are measured with respect to GND, unless otherwise specified.
Note 3: When the input voltage (V
mA. The 120 mA maximum package input current limits the number of pins that can safely exceed the power supplies with an input current of 30 mA to four.
Note 4: The maximum power dissipation must he derated at elevated temperatures and is dictated by T
junction to ambient thermal resistance), and T
or the number given in the Absolute Maximum Ratings, whichever is lower. For this device, T
i
JA
ADC12041 in the V package, when board mounted, is 55
Note 5: Human body model, 100 pF discharged through 1.5 Xk resistor.
) at any pin exceeds the power supply rails (V
IN
(ambient temperature). The maximum allowable power dissipation at any temperature is P
A
C/W, and in the SSOP package, when board mounted, is 130§C/W.
§
IN
k
GND or V
6
a
l
IN
Jmax
a
(V
or V
)), the current at that pin should be limited to 30
A
D
, (maximum junction temperature), iJA(package
Jmax
e
150§C, and the typical thermal resistance (iJA)ofthe
Dmax
e
b
(T
TA)/
Jmax
Notes on Specifications (Continued)
Note 6: Each input is protected by a nominal 6.5V breakdown voltage zener diode to GND, as shown below, input voltage magnitude up to 5V above V
below GND will not damage the ADC12041. There are parasitic diodes that exist between the inputs and the power supply rails and errors in the A/D conversion
can occur if these diodes are forward biased by more than 50 mV. As an example, if V
conversions.
a
is 4.50 VDC, full-scale input voltage must be 4.55 VDCto ensure accurate
A
a
or 5V
A
a
A
TL/H/12441– 4
a
and V
at the specified extremes.
D
a
Note 7: V
conversion/comparison accuracy. Refer to the Power Supply Considerations section for a detailed discussion.
Note 8: Accuracy is guaranteed when operating at f
Note 9: With the test condition for V
Note 10: Typicals are at T
Note 11: Limits are guaranteed to National’s AOQL (Average Outgoing Quality Level).
Note 12: Positive integral linearity error is defined as the deviation of the analog value, expressed in LSBs, from the straight line that passes through positive full-
scale and zero. For negative integral linearity error, the straight line passes through negative full-scale and zero.
Note 13: Zero error is a measure of the deviation from the mid-scale voltage (a code of zero), expressed in LSB. It is the average value of the code transitions
b
between
Note 14: The DC common-mode error is measured with both inputs shorted together and driven from 0V to 5V. The measured value is referred to the resulting
output value when the inputs are driven with a 2.5V input.
Note 15: Power Supply Sensitivity is measured after an Auto-Zero and Auto Calibration cycle has been completed with V
Note 16: V
Note 17: The ADC12041’s self-calibration technique ensures linearity and offset errors as specified, but noise inherent in the self-calibration process will result in a
repeatability uncertainty of
a
and V
A
1to0and0toa1 (see
REFCM
must be connected together to the same power supply voltage and bypassed with separate capacitors at each Vapin to assure
D
CLK
a
b
REF(VREF
e
25§C and represent most likely parametric norm.
A
Figure 6
V
REF
).
(Reference Voltage Common Mode Range) is defined as
g
0.20 LSB.
e
12 MHz.
b
) given asa4.096V, the 12-bit LSB is 1.000 mV.
a
b
a
V
V
REF
REF
2
#
J
Note 18: Total Unadjusted Error (TUE) includes offset, full scale linearity and MUX errors.
Note 19: The ADC12041 parts used to gather the information for these curves were auto-calibrated prior to taking the measurements at each test condition. The
auto-calibration cycle cancels any first order drifts due to test conditions. However, each measurement has a repeatability uncertainty error of 0.2 LSB. See Note
17.
Note 20: This is a DC average current drawn by the reference input with a full-scale sinewave input. The ADC12041 is continuously converting with a throughput
rate of 206 kHz.
Note 21: These typical curves were measured during continuous conversions with a positive half-scale DC input. A 240 ns RD
signal went low. The data bus lines were loaded with 2 HC family CMOS inputs (C
RDY
Note 22: Any other values placed in the command field are meaningless. However, if a code of 101 or 110 is placed in the command field and the CS
go low at the same time, the ADC12041 will enter a test mode. These test modes are only to be used by the manufacturer of this device. A hardware power-off and
power-on reset must be done to get out of these test modes.
E
20 pF).
L
pulse was applied 25 ns after the
,RDand WR
7
Electrical Characteristics
FIGURE 1. Output Digital Code vs the Operating Input Voltage Range (General Case)
FIGURE 2. Output Digital Code vs the Operating Input Voltage Range for V
REF
e
TL/H/12441– 5
TL/H/12441– 6
4.096V
8
Electrical Characteristics (Continued)
FIGURE 3. V
FIGURE 4. V
Operating Range (General Case)
REF
Operating Range for V
REF
TL/H/12441– 7
e
5V
A
TL/H/12441– 8
9
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