Rainbow Electronics ADC12040 User Manual
ADC12040
12-Bit, 40 MSPS, 340 mW A/D Converter with Internal
Sample-and-Hold
ADC12040 12-Bit, 40 MSPS, 340 mW A/D Converter with Internal Sample-and-Hold
June 2003
General Description
The ADC12040 is a monolithic CMOS analog-to-digital converter capable of converting analog input signals into 12-bit
digital words at 40 Megasamples per second (MSPS), minimum. This converter uses a differential, pipeline architecture
with digital error correction and an on-chip sample-and-hold
circuit to minimize die size and power consumption while
providing excellent dynamic performance. Operating on a
single 5V power supply, this device consumes just 340 mW
at 40 MSPS, including the reference current. The Power
Down feature reduces power consumption to 40 mW.
The differential inputs provide a full scale input swing equal
to V
of the differential input is recommended for optimum performance. For ease of use, the buffered, high impedance,
single-ended reference input is converted on-chip to a differential reference for use by the processing circuitry. Output
data format is 12-bit offset binary.
This device is available in the 32-lead LQFP package and
will operate over the industrial temperature range of −40˚C to
+85˚C.
with the possibility of a single-ended input. Full use
REF
Features
n Single supply operation
n Internal sample-and-hold
n Outputs 2.5V to 5V compatible
n TTL/CMOS compatible input/outputs
n Low power consumption
n Power down mode
n On-chip reference buffer
Key Specifications
n Resolution 12 Bits
n Conversion Rate 40 MSPS (min)
n DNL
n INL
n SNR (f
n ENOB (f
n Data Latency 6 Clock Cycles
n Supply Voltage +5V
n Power Consumption, 40 MHz 340 mW (typ)
= 10MHz) 69 dB (typ)
IN
= 10MHz) 11.2 bits (typ)
IN
±
0.4 LSB (typ)
±
0.7 LSB (typ)
±
5%
Applications
n Ultrasound and Imaging
n Instrumentation
n Cellular Base Stations/Communications Receivers
n Sonar/Radar
n xDSL
n Wireless Local Loops/Cable Modems
n HDTV/DTV
n DSP Front Ends
Connection Diagram
20014801
© 2003 National Semiconductor Corporation DS200148 www.national.com
Ordering Information
ADC12040
Block Diagram
Industrial (−40˚C ≤ TA≤ +85˚C) Package
ADC12040CIVY 32 Pin LQFP
ADC12040CIVYX 32 Pin LQFP Tape and Reel
ADC12040EVAL Evaluation Board
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20014802
Pin Descriptions and Equivalent Circuits
Pin No. Symbol Equivalent Circuit Description
ANALOG I/O
Non-Inverting analog signal Input. With a 2.0V reference
2V
3V
1V
IN
IN
REF
+
voltage, the differential input signal level is 2.0 V
.
on V
CM
Inverting analog signal Input. With a 2.0V reference voltage
−
the input signal level is 2.0 V
may be connected to V
P-P
for single-ended operation, but a
CM
differential input signal is required for best performance.
Reference input. This pin should be bypassed to AGND with
a 0.1 µF monolithic capacitor. V
should be between 1.0V to 2.2V.
centered
P-P
centered on VCM. This pin
is 2.0V nominal and
REF
ADC12040
31 V
32 V
30 V
DIGITAL I/O
10 CLK
11 OE
RP
RM
RN
These pins are high impedance reference bypass pins only.
Connect a 0.1 µF capacitor from each of these pins to AGND.
DO NOT connect anything else to these pins.
Digital clock input. The range of frequencies for this input is
100 kHz to 50 MHz (typical) with guaranteed performance at
40 MHz. The input is sampled on the rising edge of this input.
OE is the output enable pin that, when low, enables the
TRI-STATE™data output pins. When this pin is high, the
outputs are in a high impedance state.
8PD
PD is the Power Down input pin. When high, this input puts
the converter into the power down mode. When this pin is
low, the converter is in the active mode.
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Pin Descriptions and Equivalent Circuits (Continued)
Pin No. Symbol Equivalent Circuit Description
ADC12040
14–19,
22–27
D0–D11
Digital data output pins that make up the 12-bit conversion
results. D0 is the LSB, while D11 is the MSB of the offset
binary output word. Output levels are TTL/CMOS compatible.
ANALOG POWER
Positive analog supply pins. These pins should be connected
5, 6, 29 V
A
to a quiet +5V voltage source and bypassed to AGND with
0.1 µF monolithic capacitors located within 1 cm of these
power pins, and with a 10 µF capacitor.
4, 7, 28 AGND The ground return for the analog supply.
DIGITAL POWER
Positive digital supply pin. This pin should be connected to
13 V
D
the same quiet +5V source as is V
with a 0.1 µF monolithic capacitor in parallel with a 10 µF
capacitor, both located within 1 cm of the power pin.
9, 12 DGND The ground return for the digital supply.
Positive digital supply pin for the ADC12040’s output drivers.
This pin should be connected to a voltage source of +2.5V to
+5V and bypassed to DR GND with a 0.1 µF monolithic
21 V
DR
capacitor. If the supply for this pin is different from the supply
used for V
tantalum capacitor. V
. All bypass capacitors should be located within 1 cm of the
V
D
and VD, it should also be bypassed with a 10 µF
A
should never exceed the voltage on
DR
supply pin.
The ground return for the digital supply for the ADC12040’s
output drivers. This pin should be connected to the system
20 DR GND
digital ground, but not be connected in close proximity to the
ADC12040’s DGND or AGND pins. See Section 5 (Layout
and Grounding) for more details.
and bypassed to DGND
A
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ADC12040
Absolute Maximum Ratings (Notes 1,
2)
If Military/Aerospace specified devices are required,
please contact the National Semiconductor Sales Office/
Distributors for availability and specifications.
or V
A
+0.3V)
±
25 mA
±
50 mA
6.5V
V
A,VD,VDR
|V
| ≤ 100 mV
A–VD
Voltage on Any Input or Output Pin −0.3V to (V
Input Current at Any Pin (Note 3)
Package Input Current (Note 3)
Package Dissipation at T
= 25˚C See (Note 4)
A
D
Operating Ratings (Notes 1, 2)
Operating Temperature −40˚C ≤ T
Supply Voltage (V
Output Driver Supply (V
V
Input 1.0V to 2.2V
REF
CLK, PD, OE
V
Input −0V to (VA− 0.5V)
IN
) +4.75V to +5.25V
A,VD
) +2.35V to V
DR
−0.05V to (VD+ 0.05V)
|AGND–DGND| ≤100mV
≤ +85˚C
A
ESD Susceptibility
Human Body Model (Note 5) 2500V
Machine Model (Note 5) 250V
Soldering Temperature,
Infrared, 10 sec. (Note 6) 235˚C
Storage Temperature −65˚C to +150˚C
Converter Electrical Characteristics
Unless otherwise specified, the following specifications apply for AGND = DGND = DR GND = 0V, VA=VD= +5V, VDR=
+3.0V, PD = 0V, V
: all other limits TA=TJ= 25˚C (Notes 7, 8, 9)
T
MAX
REF
= +2.0V, f
Symbol Parameter Conditions
STATIC CONVERTER CHARACTERISTICS
Resolution with No Missing Codes 12 Bits (min)
INL Integral Non Linearity (Note 11)
DNL Differential Non Linearity
GE Gain Error
Offset Error (V
+=VIN−) −0.1
IN
Under Range Output Code 0 0
Over Range Output Code 4095 4095
DYNAMIC CONVERTER CHARACTERISTICS
FPBW Full Power Bandwidth 0 dBFS Input, Output at −3 dB 100 MHz
SNR Signal-to-Noise Ratio
SINAD Signal-to-Noise and Distortion
ENOB Effective Number of Bits
THD Total Harmonic Distortion
SFDR Spurious Free Dynamic Range
IMD Intermodulation Distortion
= 40 MHz, tr=tf= 3 ns, CL= 20 pF/pin. Boldface limits apply for TA=TJ=T
CLK
Typical
(Note 10)
±
0.7
±
0.4
±
0.1
f
1 MHz, VIN−0.5 dBFS 70 dB
IN
f
= 10 MHz, VIN= −0.5 dBFS 69.5 66.5 dB (min)
IN
f
= 1 MHz, VIN= −0.5 dBFS 69.5 dB
IN
f
= 10 MHz, VIN= −0.5 dBFS 69 66 dB (min)
IN
f
= 1 MHz, VIN= −0,5 dBFS 11.2 Bits
IN
f
= 10 MHz, VIN= −0,5 dBFS 11.2 10.7 Bits (min)
IN
f
= 1 MHz, VIN= −0,5 dBFS −82 dB
IN
f
= 10 MHz, VIN= −0,5 dBFS −80 −67 dB (max)
IN
f
= 1 MHz, VIN= −0,5 dBFS 86 dB
IN
f
= 10 MHz, VIN= −0.5 dBFS 84 -68 dB (min)
IN
f
= 9.5 MHz and 10.5 MHz,
IN
each = −8 dBFS
−75 dBFS
Limits
(Note 10)
±
1.8 LSB (max)
±
1.0 LSB (max)
±
2.1 %FS (max)
±
0.9 %FS (max)
to
MIN
Units
(Limits)
D
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Converter Electrical Characteristics (Continued)
Unless otherwise specified, the following specifications apply for AGND = DGND = DR GND = 0V, VA=VD= +5V, VDR=
+3.0V, PD = 0V, V
ADC12040
: all other limits TA=TJ= 25˚C (Notes 7, 8, 9)
T
MAX
REF
= +2.0V, f
Symbol Parameter Conditions
= 40 MHz, tr=tf= 3 ns, CL= 20 pF/pin. Boldface limits apply for TA=TJ=T
CLK
Typical
(Note 10)
Limits
(Note 10)
REFERENCE AND ANALOG INPUT CHARACTERISTICS
V
CM
C
IN
V
REF
Common Mode Input Voltage VA/2 V
VINInput Capacitance (each pin to
GND)
VIN= 2.5 Vdc
+ 0.7 V
rms
Reference Voltage (Note 13) 2.00
(CLK LOW) 8 pF
(CLK HIGH) 7 pF
1.0 V (min)
2.2 V (max)
Reference Input Resistance 100 MΩ (min)
DC and Logic Electrical Characteristics
Unless otherwise specified, the following specifications apply for AGND = DGND = DR GND = 0V, VA=VD= +5V, VDR=
+3.0V, PD = 0V, V
: all other limits TA=TJ= 25˚C (Notes 7, 8, 9)
T
MAX
REF
= +2.0V, f
Symbol Parameter Conditions
CLK, PD, OE DIGITAL INPUT CHARACTERISTICS
V
V
I
I
C
IN(1)
IN(0)
IN(1)
IN(0)
IN
Logical “1” Input Voltage VD= 5.25V 2.0 V (min)
Logical “0” Input Voltage VD= 4.75V 1.0 V (max)
Logical “1” Input Current VIN= 5.0V 10 µA
Logical “0” Input Current VIN= 0V −10 µA
Digital Input Capacitance 5 pF
D0–D11 DIGITAL OUTPUT CHARACTERISTICS
V
V
I
OZ
+I
OUT(1)
OUT(0)
SC
Logical “1” Output Voltage I
Logical “0” Output Voltage I
TRI-STATE Output Current
Output Short Circuit Source
Current
−I
SC
Output Short Circuit Sink Current V
POWER SUPPLY CHARACTERISTICS
I
A
I
D
I
DR
Analog Supply Current
Digital Supply Current
Digital Output Supply Current
Total Power Consumption
PSRR1 Power Supply Rejection
PSRR2 Power Supply Rejection
= 40 MHz, tr=tf= 3 ns, CL= 20 pF/pin. Boldface limits apply for TA=TJ=T
CLK
Typical
(Note 10)
= 2.5V 2.3 V (min)
V
= −0.5 mA
OUT
= 1.6 mA, VDR=3V 0.4 V (max)
OUT
= 2.5V or 5V 100 nA
V
OUT
V
= 0V −100 nA
OUT
= 0V −20 mA (min)
V
OUT
OUT=VDR
PD Pin = DGND, V
PD Pin = V
REF
DR
PD Pin = DGND
PD Pin = V
DR,fCLK
PD Pin = DGND, C
PD Pin = V
DR,fCLK
PD Pin = DGND, C
PD Pin = V
DR,fCLK
Rejection of Full-Scale Error with
= 4.75V vs. 5.25V
V
A
SNR Degradation w/10 MHz,
200 mV
riding on V
P-P
DR
V
=3V 2.7 V (min)
DR
= 2.0V
=0
= 0 pF (Note 14)
L
=0
= 0 pF (Note 15)
L
=0
A
20 mA (min)
59
8
6
0
3
0
340
40
58 dB
50 dB
Limits
(Note 10)
66 mA (max)
7.3 mA (max)
366 mW
to
MIN
Units
(Limits)
to
MIN
Units
(Limits)
mA
mA
mA (max)
mA
mW
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