Rainbow Electronics ADC12038 User Manual
ADC12H030/ADC12H032/ADC12H034/ADC12H038,
ADC12030/ADC12032/ADC12034/ADC12038
Self-Calibrating 12-Bit Plus Sign Serial I/O
A/D Converters with MUX and Sample/Hold
January 1995
ADC12H030/ADC12H032/ADC12H034/ADC12H038,
ADC12030/ADC12032/ADC12034/ADC12038
Self-Calibrating 12-Bit Plus Sign Serial I/O A/D Converters with MUX and Sample/Hold
General Description
The ADC12030, and ADC12H030 families are 12-bit plus
sign successive approximation A/D converters with serial
I/O and configurable input multiplexers. The ADC12032/
ADC12H032, ADC12034/ADC12H034 and ADC12038/
ADC12H038 have 2, 4 and 8 channel multiplexers, respectively. The differential multiplexer outputs and A/D inputs
are available on the MUXOUT1, MUXOUT2, A/DIN1 and
A/DIN2 pins. The ADC12030/ADC12H030 has a two channel multiplexer with the multiplexer outputs and A/D inputs
internally connected. The ADC12030 family is tested with a
5 MHz clock, while the ADC12H030 family is tested with an
8 MHz clock. On request, these A/Ds go through a self
calibration process that adjusts linearity, zero and full-scale
errors to less than
g
1 LSB each.
The analog inputs can be configured to operate in various
combinations of single-ended, differential, or pseudo-differential modes. A fully differential unipolar analog input range
a
(0V to
5V) can be accommodated with a singlea5V supply. In the differential modes, valid outputs are obtained
even when the negative inputs are greater than the positive
because of the 12-bit plus sign output data format.
The serial I/O is configured to comply with the NSC
MICROWIRE
TM
. For complementary voltage references see
the LM4040, LM4041 or LM9140.
Applications
Y
Medical instruments
Y
Process control systems
Y
Test equipment
ADC12038 Simplified Block Diagram
Features
Y
Serial I/O (MICROWIRE Compatible)
Y
2, 4, or 8 channel differential or single-ended
multiplexer
Y
Analog input sample/hold function
Y
Power down mode
Y
Variable resolution and conversion rate
Y
Programmable acquisition time
Y
Variable digital output word length and format
Y
No zero or full scale adjustment required
Y
Fully tested and guaranteed with a 4.096V reference
Y
0V to 5V analog input range with single 5V power
supply
Y
No Missing Codes over temperature
Key Specifications
Y
Resolution 12-bit plus sign
Y
12-bit plus sign conversion time
Ð ADC12H030 family 5.5 ms (max)
Ð ADC12030 family 8.8 ms (max)
Y
12-bit plus sign throughput time
Ð ADC12H030 family 8.6 ms (max)
Ð ADC12030 family 14 ms (max)
Y
Integral linearity error
Y
Single supply 5Vg10%
Y
Power dissipation 33 mW (max)
Ð Power down 100 mW (typ)
g
1 LSB (max)
TRI-STATEÉis a registered trademark of National Semiconductor Corporation.
TM
COPS
microcontrollers, HPCTMand MICROWIRETMare trademarks of National Semiconductor Corporation.
C
1995 National Semiconductor Corporation RRD-B30M75/Printed in U. S. A.
TL/H/11354
TL/H/11354– 1
Connection Diagrams
16-Pin Dual-In-Line and
Wide Body SO Packages
Top View
24-Pin Dual-In-Line and
Wide Body SO Packages
TL/H/11354– 6
20-Pin Dual-In-Line and
Wide Body SO Packages
Top View
28-Pin Dual-In-Line and
Wide Body SO Packages
TL/H/11354– 7
Top View
Ordering Information
TL/H/11354– 8
Industrial Temperature Range
b
40§CsT
s
a
85§C
A
Package
ADC12H030CIN, ADC12030CIN N16E
ADC12H030CIWM, ADC12030CIWM M16B
ADC12H032CIN, ADC12032CIN N20A
ADC12H032CIWM, ADC12032CIWM M20B
ADC12H034CIN, ADC12034CIN N24C
ADC12H034CIWM, ADC12034CIWM M24B
ADC12H038CIN, ADC12038CIN N28B
ADC12H038CIWM, ADC12038CIWM M28B
2
Top View
TL/H/11354– 9
Absolute Maximum Ratings (Notes1&2)
If Military/Aerospace specified devices are required,
please contact the National Semiconductor Sales
Office/Distributors for availability and specifications.
Positive Supply Voltage
a
a
e
(V
V
A
Voltage at Inputs and Outputs
except CH0–CH7 and COM
Voltage at Analog Inputs
CH0–CH7 and COM GND
a
b
V
V
l
A
D
Input Current at Any Pin (Note 3)
Package Input Current (Note 3)
Package Dissipation at
e
T
25§C (Note 4) 500 mW
A
ESD Susceptability (Note 5)
Human Body Model 1500V
Soldering Information
N Packages (10 seconds) 260
SO Package (Note 6):
Vapor Phase (60 seconds) 215
Infrared (15 seconds) 220
Storage Temperature
a
e
V
) 6.5V
D
0.3V to V
b
5V to V
a
a
a
300 mV
g
g
120 mA
0.3V
a
5V
30 mA
b
a
l
§
§
§
b
65§Ctoa150§C
Operating Ratings (Notes1&2)
Operating Temperature Range T
ADC12030CIN, ADC12030CIWM,
ADC12H030CIN, ADC12H030CIWM,
ADC12032CIN, ADC12032CIWM,
ADC12H032CIN, ADC12H032CIWM,
ADC12034CIN, ADC12034CIWM,
ADC12H034CIN, ADC12H034CIWM,
ADC12038CIN, ADC12038CIWM,
ADC12H038CIN,
ADC12H038CIWM
Supply Voltage (V
a
b
V
l
A
a
V
REF
b
V
REF
V
REF(VREF
V
Common Mode Voltage Range
REF
(V
REF
C
A/DIN1, A/DIN2, MUXOUT1
C
C
and MUXOUT2 Voltage Range 0V to V
A/D IN Common Mode Voltage Range
a
(V
IN
a
e
a
V
D
a
a
a
V
l
b
b
V
REF
b
V
)
REF
2
b
a
V
)
IN
2
s
s
T
MIN
b
a
e
A
40§CsT
a
V
D
a
)
T
A
s
a
A
4.5V toa5.5V
s
100 mV
0V to V
0V to V
REF
) 1VtoV
a
0.1 V
to 0.6 V
A
0V to V
MAX
85§C
A
A
A
A
A
a
a
a
a
a
a
Converter Electrical Characteristics
a
a
The following specifications apply for V
sign conversion mode, f
5 MHz for the ADC12030, ADC12032, ADC12034 and ADC12038, R
25X, fully-differential input with fixed 2.048V common-mode voltage, and 10(tCK) acquisition time unless otherwise specified.
Boldface limits apply for T
CK
e
f
SK
e
A
e
V
e
T
J
A
8 MHz for the ADC12H030, ADC12H032, ADC12H034 and ADC12H038, f
e
T
to T
MIN
a
e
ea
V
D
; all other limits T
MAX
5.0 VDC,V
S
Symbol Parameter Conditions
STATIC CONVERTER CHARACTERISTICS
Resolution with No Missing Codes 12asign Bits (min)
a
ILE Positive Integral Linearity Error After Auto-Cal (Notes 12, 18)
b
ILE Negative Integral Linearity Error After Auto-Cal (Notes 12, 18)
DNL Differential Non-Linearity After Auto-Cal
Positive Full-Scale Error After Auto-Cal (Notes 12, 18)
Negative Full-Scale Error After Auto-Cal (Notes 12, 18)
Offset Error After Auto-Cal (Notes 5, 18)
(a)eVIN(b)e2.048V
V
IN
DC Common Mode Error After Auto-Cal (Note 15)
TUE Total Unadjusted Error After Auto-Cal
(Notes 12, 13 and 14)
Resolution with No Missing Codes 8-bitasign mode 8asign Bits (min)
a
INL Positive Integral Linearity Error 8-bitasign mode (Note 12)
b
INL Negative Integral Linearity Error 8-bitasign mode (Note 12)
DNL Differential Non-Linearity 8-bitasign mode
Positive Full-Scale Error 8-bitasign mode (Note 12)
a
ea
REF
e
25X, source impedance for V
e
T
A
4.096 VDC,V
e
25§C. (Notes 7, 8 and 9)
J
Typical
(Note 10)
g
1/2
g
1/2
g
1/2
g
1/2
g
1/2
g
2
g
1 LSB
b
e
0VDC, 12-bit
REF
REF
a
CK
and V
e
Limits
(Note 11)
g
1 LSB (max)
g
1 LSB (max)
g
1 LSB (max)
g
3.0 LSB (max)
g
3.0 LSB (max)
g
2 LSB (max)
g
3.5 LSB (max)
g
1/2 LSB (max)
g
1/2 LSB (max)
g
3/4 LSB (max)
g
1/2 LSB (max)
REF
(Limits)
f
SK
b
Units
a
e
s
3
Converter Electrical Characteristics (Continued)
a
a
e
The following specifications apply for V
sign conversion mode, f
5 MHz for the ADC12030, ADC12032, ADC12034 and ADC12038, R
25X, fully-differential input with fixed 2.048V common-mode voltage, and 10(tCK) acquisition time unless otherwise specified.
Boldface limits apply for T
CK
e
e
f
SK
e
T
A
J
V
A
8 MHz for the ADC12H030, ADC12H032, ADC12H034 and ADC12H038, f
e
T
to T
MIN
a
e
ea
V
D
; all other limits T
MAX
5.0 VDC,V
S
Symbol Parameter Conditions
STATIC CONVERTER CHARACTERISTICS (Continued)
Negative Full-Scale Error 8-bitasign mode (Note 12)
Offset Error 8-bitasign mode,
after Auto-Zero (Note 13)
V
(a)eVIN(b)
IN
ea
TUE Total Unadjusted Error 8-bitasign mode
after Auto-Zero
(Notes 12, 13 and 14)
Multiplexer Channel to Channel
Matching
a
Power Supply Sensitivity V
Offset Error
a
Full-Scale Error
b
Full-Scale Error
a
Integral Linearity Error
b
Integral Linearity Error
ea
5Vg10%
ea
V
REF
4.096V
Output Data from (Note 20)
‘‘12-Bit Conversion of Offset’’
(see Table V)
Output Data from (Note 20)
‘‘12-Bit Conversion of Full-Scale’’
(see Table V)
UNIPOLAR DYNAMIC CONVERTER CHARACTERISTICS
S/(NaD) Signal-to-Noise Plus f
Distortion Ratio f
b
3 dB Full Power Bandwidth V
e
1 kHz, V
IN
e
20 kHz, V
IN
e
f
40 kHz, V
IN
e
5VPP, where S/(NaD) drops 3 dB 31 kHz
IN
IN
e
IN
IN
5VPP,V
e
5VPP,V
e
5VPP,V
DIFFERENTIAL DYNAMIC CONVERTER CHARACTERISTICS
S/(NaD) Signal-to-Noise Plus f
Distortion Ratio f
b
3 dB Full Power Bandwidth V
IN
IN
f
IN
e
e
e
IN
1 kHz, V
20 kHz, V
40 kHz, V
e
g
e
g
5V, V
IN
e
g
5V, V
IN
e
g
5V, V
IN
5V, where S/(NaD) drops 3 dB 40 kHz
a
ea
REF
e
25X, source impedance for V
e
T
A
4.096 VDC,V
e
25§C. (Notes 7, 8 and 9)
J
Typical
(Note 10)
2.048V
a
e
5.0V 69.4 dB
REF
a
e
5.0V 68.3 dB
REF
a
e
5.0V 65.7 dB
REF
a
e
5.0V 77.0 dB
REF
a
e
5.0V 73.9 dB
REF
a
e
5.0V 67.0 dB
REF
b
e
0VDC, 12-bit
REF
REF
a
CK
and V
e
REF
Limits
(Note 11)
g
1/2 LSB (max)
g
1/2 LSB (max)
g
3/4 LSB (max)
g
0.05 LSB
g
0.5
g
0.5
g
0.5
g
0.5 LSB
g
0.5 LSB
g
1 LSB (max)
g
1.5 LSB (max)
g
1.5 LSB (max)
a
10 LSB (max)
b
10 LSB (min)
4095 LSB (max)
4093 LSB (min)
a
e
f
SK
b
Units
(Limits)
s
4
Electrical Characteristics
a
a
The following specifications apply for V
sign conversion mode, f
5 MHz for the ADC12030, ADC12032, ADC12034 and ADC12038, R
25X, fully-differential input with fixed 2.048V common-mode voltage, and 10(tCK) acquisition time unless otherwise specified.
Boldface limits apply for T
CK
e
f
SK
e
A
e
V
e
T
J
A
8 MHz for the ADC12H030, ADC12H032, ADC12H034 and ADC12H038, f
e
T
to T
MIN
a
e
ea
V
D
; all other limits T
MAX
5.0 VDC,V
Symbol Parameter Conditions
REFERENCE INPUT, ANALOG INPUTS AND MULTIPLEXER CHARACTERISTICS
C
REF
C
A/D
Reference Input Capacitance 85 pF
A/DIN1 and A/DIN2 Analog Input
Capacitance
A/DIN1 and A/DIN2 Analog Input V
Leakage Current V
IN
IN
ea
e
0V
5.0V or
CH0–CH7 and COM Input Voltage GNDb0.05 V (min)
C
CH
C
MUXOUT
CH0–CH7 and COM Input Capacitance 10 pF
MUX Output Capacitance 20 pF
Off Channel Leakage (Note 16) On Channele5V and
CH0–CH7 and COM Pins Off Channel
e
On Channele0V and
Off Channele5V
On Channel Leakage (Note 16) On Channele5V and
CH0–CH7 and COM Pins Off Channel
e
On Channele0V and
e
2.5V and
e
2.5V and
e
5V
e
e
5.0V or
e
0V
e
2.4V
e
2.4V
PP,fIN
Off Channel
MUXOUT1 and MUXOUT2 V
Leakage Current V
R
ON
MUX On Resistance V
RONMatching Channel to Channel V
Channel to Channel Crosstalk V
MUXOUT
MUXOUT
IN
V
MUXOUT
IN
V
MUXOUT
IN
MUX Bandwidth 90 kHz
a
ea
REF
e
25X, source impedance for V
S
e
T
A
4.096 VDC,V
e
25§C. (Notes 7, 8 and 9)
J
Typical Limits Units
(Note 10) (Note 11) (Limits)
75 pF
g
0.1
b
0V
0.01
0.01 0.3 mA (max)
0V
5V
0.01 0.3 mA (max)
b
0.01
0.01 0.3 mA (max)
850 1150 X (max)
5%
e
40 kHz
b
72 dB
b
e
0VDC, 12-bit
REF
a
and V
REF
g
1.0 mA (max)
a
a
V
0.05 V (max)
A
b
0.3 mA (min)
b
0.3 mA (min)
CK
e
REF
a
e
f
SK
b
s
5
DC and Logic Electrical Characteristics
a
a
The following specifications apply for V
sign conversion mode, f
5 MHz for the ADC12030, ADC12032, ADC12034 and ADC12038, R
25X, fully-differential input with fixed 2.048V common-mode voltage, and 10(tCK) acquisition time unless otherwise specified.
Boldface limits apply for T
CK
e
f
SK
e
A
e
V
e
T
J
A
8 MHz for the ADC12H030, ADC12H032, ADC12H034 and ADC12H038, f
e
T
to T
MIN
a
e
ea
V
D
; all other limits T
MAX
5.0 VDC,V
S
Symbol Parameter Conditions
CCLK, CS, CONV, DI, PD AND SCLK INPUT CHARACTERISTICS
a
V
V
I
IN(1)
I
IN(0)
Logical ‘‘1’’ Input Voltage V
IN(1)
Logical ‘‘0’’ Input Voltage V
IN(0)
Logical ‘‘1’’ Input Current V
Logical ‘‘0’’ Input Current V
e
5.5V 2.0 V (min)
a
e
4.5V 0.8 V (max)
e
5.0V 0.005 1.0 mA (max)
IN
e
0V
IN
DO, EOC AND DOR DIGITAL OUTPUT CHARACTERISTICS
V
OUT(1)
V
OUT(0)
I
OUT
a
b
Logical ‘‘1’’ Output Voltage V
Logical ‘‘0’’ Output Voltage V
TRI-STATE Output Current V
I
Output Short Circuit Source Current V
SC
I
Output Short Circuit Sink Current V
SC
V
V
a
a
OUT
OUT
OUT
OUT
e
e
e
4.5V, I
4.5V, I
4.5V, I
e
e
e
e
eb
OUT
eb
OUT
e
OUT
0V
5V 0.1 3.0 mA (max)
0V 14 6.5 mA (min)
a
V
D
a
POWER SUPPLY CHARACTERISTICS
a
I
D
Digital Supply Current Awake 1.6 2.5 mA (max)
ADC12030, ADC12032, ADC12034 CS
and ADC12038 CS
e
HIGH, Powered Down, CCLK on 600 mA
e
HIGH, Powered Down, CCLK off 20 mA
Digital Supply Current Awake 2.3 3.2 mA
e
HIGH, Powered Down, CCLK on 0.9 mA
e
HIGH, Powered Down, CCLK off 20 mA
e
CS
HIGH, Powered Down, CCLK on 10 mA
e
CS
HIGH, Powered Down, CCLK off 0.1 mA
e
CS
HIGH, Powered Down 0.1 mA
I
I
A
REF
ADC12H030, ADC12H032, ADC12H034 CS
and ADC12H038 CS
a
Positive Analog Supply Current Awake 2.7 4.0 mA (max)
Reference Input Current Awake 70 mA
a
ea
REF
e
25X, source impedance for V
e
T
A
4.096 VDC,V
e
25§C. (Notes 7, 8 and 9)
J
REF
b
REF
e
a
0VDC, 12-bit
e
CK
and V
REF
Typical Limits Units
(Note 10) (Note 11) (Limits)
b
0.005
b
1.0 mA (min)
360 mA 2.4 V (min)
10 mA 4.25 V (min)
1.6 mA 0.4 V (max)
b
0.1
b
3.0 mA (max)
16 8.0 mA (min)
a
e
f
SK
b
s
6
AC Electrical Characteristics
a
a
e
The following specifications apply for V
sign conversion mode, t
e
f
CK
V
specified. Boldface limits apply for T
e
f
5 MHz for the ADC12030, ADC12032, ADC12034 and ADC12038, R
SK
b
s
25X, fully-differential input with fixed 2.048V common-mode voltage, and 10(tCK) acquisition time unless otherwise
REF
e
e
t
3 ns, f
r
f
CK
e
A
Symbol Parameter Conditions
f
f
Conversion Clock 10 85MHz (max)
CK
(CCLK) Frequency 1 MHz (min)
Serial Data Clock 10 85MHz (max)
SK
SCLK Frequency 0 Hz (min)
Conversion Clock 40 40 % (min)
Duty Cycle 60 60 % (max)
Serial Data Clock 40 40 % (min)
Duty Cycle 60 60 % (max)
t
Conversion Time 12-BitaSign or 12-Bit 44(tCK) 44(tCK) 44(tCK) (max)
C
8-BitaSign or 8-Bit 21(tCK) 21(tCK) 21(tCK) (max)
t
Acquisition Time 6 Cycles Programmed 6(tCK) 6(tCK) 6(tCK) (min)
A
(Note 19) 7(t
10 Cycles Programmed 10(tCK) 10(tCK) 10(tCK) (min)
18 Cycles Programmed 18(tCK) 18(tCK) 18(tCK) (min)
34 Cycles Programmed 34(tCK) 34(tCK) 34(tCK) (min)
t
t
t
Self-Calibration Time 4944(tCK) 4944(tCK) 4944(tCK) (max)
CKAL
Auto-Zero Time 76(tCK) 76(tCK) 76(tCK) (max)
AZ
Self-Calibration or 2(tCK) 2(tCK) 2(tCK) (min)
SYNC
Auto-Zero Synchronization 3(t
Time from DOR
t
DOR High Time 9(tSK) 9(tSK) 9(tSK) (max)
DOR
when CS is Low
Continuously for Read
Data and Software
Power Up/Down
t
CONV Valid Data Time 8(tSK) 8(tSK) 8(tSK) (max)
CONV
e
V
A
e
e
f
SK
e
T
T
J
MIN
a
ea
V
8 MHz for the ADC12H030, ADC12H032, ADC12H034 and ADC12H038,
D
to T
MAX
5.0 VDC,V
; all other limits T
Typical
(Note 10)
REF
a
ea
4.096 VDC,V
e
25X, source impedance for V
S
e
e
T
A
25§C. (Note 17)
J
REF
b
e
0VDC, 12-bit
ADC12H030/2/4/8 ADC12030/2/4/8
Limits Limits
(Note 11) (Note 11)
REF
(Limits)
a
and
Units
5.5 8.8 ms (max)
2.625 4.2 ms (max)
) 7(tCK) (max)
CK
0.75 1.2 ms (min)
0.875 1.4 ms (max)
) 11(tCK) (max)
11(t
CK
1.25 2.0 ms (min)
1.375 2.2 ms (max)
) 19(tCK) (max)
19(t
CK
2.25 3.6 ms (min)
2.375 3.8 ms (max)
) 35(tCK) (max)
35(t
CK
4.25 6.8 ms (min)
4.375 7.0 ms (max)
618.0 988.8 ms (max)
9.5 15.2 ms (max)
) 3(tCK) (max)
CK
0.250 0.40 ms (min)
0.375 0.60 m s (max)
1.125 1.8 ms (max)
1.0 1.6 ms (max)
a
7
AC Electrical Characteristics (Continued)
a
a
e
The following specifications apply for V
sign conversion mode, t
e
f
CK
V
specified. Boldface limits apply for T
e
f
5 MHz for the ADC12030, ADC12032, ADC12034 and ADC12038, R
SK
b
s
25X, fully-differential input with fixed 2.048V common-mode voltage, and 10(tCK) acquisition time unless otherwise
REF
e
e
t
3 ns, f
r
f
V
A
e
f
CK
e
T
A
J
Symbol Parameter Conditions
t
HPU
t
SPU
Hardware Power-Up Time, Time from
PD Falling Edge to EOC Rising Edge
Software Power-Up Time, Time from
Serial Data Clock Falling Edge to 140 250 ms (max)
EOC Rising Edge
t
ACC
t
SET-UP
t
DELAY
t1H,t
t
HDI
t
SDI
t
HDO
t
DDO
t
RDO
t
FDO
t
CD
t
SD
C
IN
C
OUT
Access Time Delay from
CS
Falling Edge to DO Data Valid
Set-Up Time of CS Falling Edge to
Serial Data Clock Rising Edge
Delay from SCLK Falling
Edge to CS
Delay from CS Rising Edge to R
0H
DO TRI-STATE
Falling Edge
É
DI Hold Time from Serial Data
Clock Rising Edge
DI Set-Up Time from Serial Data
Clock Rising Edge
DO Hold Time from Serial Data R
Clock Falling Edge 5 ns (min)
Delay from Serial Data Clock
Falling Edge to DO Data Valid
DO Rise Time, TRI-STATE to High R
DO Rise Time, Low to High 10 30 ns (max)
DO Fall Time, TRI-STATE to Low R
DO Fall Time, High to Low 12 30 ns (max)
Delay from CS Falling Edge
to DOR
Falling Edge
Delay from Serial Data Clock Falling
Edge to DOR
Rising Edge
Capacitance of Logic Inputs 10 pF
Capacitance of Logic Outputs 20 pF
a
e
ea
V
D
e
8 MHz for the ADC12H030, ADC12H032, ADC12H034 and ADC12H038,
SK
e
T
MIN
to T
L
L
L
L
MAX
e
e
e
e
5.0 VDC,V
; all other limits T
e
3k, C
L
e
3k, C
L
e
3k, C
L
e
3k, C
L
REF
a
ea
4.096 VDC,V
e
25X, source impedance for V
S
e
e
T
A
25§C. (Note 17)
J
REF
b
e
0VDC, 12-bit
a
REF
and
Typical Limits Units
(Note 10) (Note 11) (Limits)
140 250 ms (max)
20 50 ns (max)
30 ns (min)
0 5 ns (min)
100 pF
40 100 ns (max)
5 15 ns (min)
5 10 ns (min)
100 pF
25
50 ns (max)
35 50 ns (max)
100 pF 10 30 ns (max)
100 pF 12 30 ns (max)
25 45 ns (max)
25 45 ns (max)
a
8
Electrical Characteristics (Continued)
Note 1: Absolute Maximum Ratings indicate limits beyond which damage to the device may occur. Operating Ratings indicate conditions for which the device is
functional, but do not guarantee specific performance limits. For guaranteed specifications and test conditions, see the Electrical Characteristics. The guaranteed
specifications apply only for the test conditions listed. Some performance characteristics may degrade when the device is not operated under the listed test
conditions.
Note 2: All voltages are measured with respect to GND, unless otherwise specified.
Note 3: When the input voltage (V
The 120 mA maximum package input current rating limits the number of pins that can safely exceed the power supplies with an input current of 30 mA to four.
Note 4: The maximum power dissipation must be derated at elevated temperatures and is dictated by T
allowable power dissipation at any temperature is P
maxe150§C. The typical thermal resistance (HJA) of these parts when board mounted follow:
device, T
J
) at any pin exceeds the power supplies (V
IN
e
(TJmaxbTA)/iJAor the number given in the Absolute Maximum Ratings, whichever is lower. For this
D
IN
k
GND or V
Part Number Resistance
ADC12H030CIN, ADC12030CIN 53§C/W
ADC12H030CIWM, ADC12030CIWM 70§C/W
ADC12H032CIN, ADC12032CIN 46§C/W
ADC12H032CIWM, ADC12032CIWM 64§C/W
ADC12H034CIN, ADC12034CIN 42§C/W
ADC12H034CIWM, ADC12034CIWM 57§C/W
ADC12H038CIN, ADC12038CIN 40§C/W
ADC12H038CIWM, ADC12038CIWM 50§C/W
Note 5: The human body model is a 100 pF capacitor discharged through a 1.5 kX resistor into each pin.
Note 6: See AN450 ‘‘Surface Mounting Methods and Their Effect on Product Reliability’’ or the section titled ‘‘Surface Mount’’ found in any post 1986 National
Semiconductor Linear Data Book for other methods of soldering surface mount devices.
Note 7: Two on-chip diodes are tied to each analog input through a series resistor as shown below. Input voltage magnitude up to 5V above V
will not damage this device. However, errors in the A/D conversion can occur (if these diodes are forward biased by more than 50 mV) if the input voltage
magnitude of selected or unselected analog input go above V
s
4.55 VDCto ensure accurate conversions.
must be
a
or below GND by more than 50 mV. As an example, if V
A
a
l
IN
a
V
or V
), the current at that pin should be limited to 30 mA.
A
D
max, iJAand the ambient temperature, TA. The maximum
J
Thermal
i
JA
a
is 4.5 VDC, full-scale input voltage
A
a
or 5V below GND
A
a
Note 8: To guarantee accuracy, it is required that the V
pin.
Note 9: With the test condition for V
e
a
J
1 (see
T
A
e
Figure 2
Note 10: Typicals are at T
Note 11: Tested limits are guaranteed to National’s AOQL (Average Outgoing Quality Level).
Note 12: Positive integral linearity error is defined as the deviation of the analog value, expressed in LSBs, from the straight line that passes through positive full-
scale and zero. For negative integral linearity error, the straight line passes through negative full-scale and zero (see
Note 13: Zero error is a measure of the deviation from the mid-scale voltage (a code of zero), expressed in LSB. It is the worst-case value of the code transitions
between 1 to 0 and 0 to
a
b
REF(VREF
25§C and represent most likely parametric norm.
V
).
a
and V
A
REF
be connected together to the same power supply with separate bypass capacitors at each V
D
b
) given asa4.096V, the 12-bit LSB is 1.0 mV and the 8-bit LSB is 16.0 mV.
TL/H/11354– 2
Figures 1b
and1c).
Note 14: Total unadjusted error includes offset, full-scale, linearity and multiplexer errors.
Note 15: The DC common-mode error is measured in the differential multiplexer mode with the assigned positive and negative input channels shorted together.
Note 16: Channel leakage current is measured after the channel selection.
Note 17: Timing specifications are tested at the TTL logic levels, V
to 1.4V.
Note 18: The ADC12030 family’s self-calibration technique ensures linearity and offset errors as specified, but noise inherent in the self-calibration process will
result in a maximum repeatability uncertainty of 0.2 LSB.
Note 19: If SCLK and CCLK are driven from the same clock source, then t
Note 20: The ‘‘12-Bit Conversion of Offset’’ and ‘‘12-Bit Conversion of Full-Scale’’ modes are intended to test the functionality of the device. Therefore, the output
data from these modes are not an indication of the accuracy of a conversion result.
e
0.4V for a falling edge and V
IL
is 6, 10, 18 or 34 clock periods minimum and maximum.
A
e
2.4V for a rising edge. TRI-STATE output voltage is forced
IH
9
a
Electrical Characteristics (Continued)
FIGURE 1a. Transfer Characteristic
FIGURE 1b. Simplified Error Curve vs Output Code without Auto-Calibration or Auto-Zero Cycles
TL/H/11354– 10
TL/H/11354– 11
10
Electrical Characteristics (Continued)
FIGURE 1c. Simplified Error Curve vs Output Code after Auto-Calibration Cycle
TL/H/11354– 13
FIGURE 2. Offset or Zero Error Voltage
TL/H/11354– 12
11
Typical Performance Characteristics
The following curves apply for 12-bitasign mode after auto-calibration unless otherwise specified. The performance for 8-bit
sign mode is equal to or better than shown. (Note 9)
a
Linearity Error Change
vs Clock Frequency
Linearity Error Change
vs Supply Voltage
Full-Scale Error Change
vs Reference Voltage
Linearity Error Change
vs Temperature
Full-Scale Error Change
vs Clock Frequency
Full-Scale Error Change
vs Supply Voltage
Linearity Error Change
vs Reference Voltage
Full-Scale Error Change
vs Temperature
Zero Error Change
vs Clock Frequency
Zero Error Change
vs Temperature
Zero Error Change
vs Reference Voltage
12
Zero Error Change
vs Supply Voltage
TL/H/11354– 14
Typical Performance Characteristics (Continued)
The following curves apply for 12-bit
sign mode is equal to or better than shown.
a
sign mode after auto-calibration unless otherwise specified. The performance for 8-bit
a
Analog Supply Current
vs Temperature
Digital Supply Current
vs Clock Frequency
Digital Supply Current
vs Temperature
Typical Dynamic Performance Characteristics
The following curves apply for 12-bitasign mode after auto-calibration unless otherwise specified.
Bipolar Spectral Response
with 1 kHz Sine Wave Input
Bipolar Spectral Response
with 10 kHz Sine Wave Input
Bipolar Spectral Response
with 20 kHz Sine Wave Input
TL/H/11354– 15
Bipolar Spectral Response
with 30 kHz Sine Wave Input
Bipolar Spectral Response
with 40 kHz Sine Wave Input
13
Bipolar Spectral Response
with 50 kHz Sine Wave Input
TL/H/11354– 16
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