Rainbow Electronics ADC12010 User Manual

ADC12010
12-Bit, 10 MSPS, 160 mW A/D Converter with Internal
Sample-and-Hold

ADC12010 12-Bit, 10 MSPS, 160 mW A/D Converter with Internal Sample-and-Hold

April 2003

General Description

The ADC12010 is a monolithic CMOS analog-to-digital con­verter capable of converting analog input signals into 12-bit
digital words at 10 Megasamples per second (MSPS), mini­mum. This converter uses a differential, pipeline architecture
with digital error correction and an on-chip sample-and-hold
circuit to minimize die size and power consumption while
providing excellent dynamic performance. Operating on a
single 5V power supply, this device consumes just 160 mW
at 10 MSPS, including the reference current. The Power
Down feature reduces power consumption to 25 mW.

The differential inputs provide a full scale input swing equal
to 2V
of the differential input is recommended for optimum perfor­mance. For ease of use, the buffered, high impedance,
single-ended reference input is converted on-chip to a differ­ential reference for use by the processing circuitry. Output
data format is 12-bit offset binary.

This device is available in the 32-lead LQFP package and
will operate over the industrial temperature range of −40˚C to
+85˚C.

with the possibility of a single-ended input. Full use

REF

Features

n Internal sample-and-hold
n Outputs 2.4V to 5V compatible
n TTL/CMOS compatible input/outputs
n Power down mode
n On-chip reference buffer

Key Specifications

n Resolution 12 Bits
n Conversion Rate 10 MSPS (min)
n DNL
n INL
n SNR (f
n ENOB (f
n Data Latency 6 Clock Cycles
n Supply Voltage +5V
n Power Consumption, 10 MHz 160 mW (typ)

= 10.1 MHz) 70 dB (typ)

IN

= 10.1 MHz) 11.3 bits (typ)

IN

±

0.3 LSB (typ)

±

0.5 LSB (typ)

±

5%

Applications

n Image Processing Front End
n Instrumentation
n PC-Based Data Acquisition
n Fax Machines
n Wireless Local Loops/Cable Modems
n Waveform Digitizers
n DSP Front Ends

Connection Diagram

20051601

TRI-STATE®is a registered trademark of National Semiconductor Corporation.

© 2003 National Semiconductor Corporation DS200516 www.national.com

Ordering Information

ADC12010

Block Diagram

Industrial (−40˚C ≤ TA≤ +85˚C) Package

ADC12010CIVY 32 Pin LQFP

ADC12010CIVYX 32 Pin LQFP Tape and Reel

ADC12010EVAL Evaluation Board

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20051602

Pin Descriptions and Equivalent Circuits

Pin No. Symbol Equivalent Circuit Description

ANALOG I/O

Non-Inverting analog signal Input. With a 2.0V reference

2V

3V

1V

IN

IN

REF

+

voltage, the ground-referenced input signal level is 2.0 V
centered on VCM.

Inverting analog signal Input. With a 2.0V reference voltage
the ground-referenced input signal level is 2.0 V

−

. This pin may be connected to VCMfor single-ended

on V

CM

operation, but a differential input signal is required for best
performance.

Reference input. This pin should be bypassed to AGND with
a 0.1 µF monolithic capacitor. V
should be between 1.0V to 2.4V.

is 2.0V nominal and

REF

P-P

ADC12010

P-P

centered

31 V

32 V

30 V

DIGITAL I/O

10 CLK

11 OE

RP

RM

RN

These pins are high impedance reference bypass pins.
Connect a 0.1 µF capacitor from each of these pins to AGND.
DO NOT LOAD these pins.

Digital clock input. The range of frequencies for this input is
100 kHz to 15 MHz (typical) with guaranteed performance at
10 MHz. The input is sampled on the rising edge of this input.

OE is the output enable pin that, when low, enables the
TRI-STATE®data output pins. When this pin is high, the
outputs are in a high impedance state.

8PD

PD is the Power Down input pin. When high, this input puts
the converter into the power down mode. When this pin is
low, the converter is in the active mode.

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Pin Descriptions and Equivalent Circuits (Continued)

Pin No. Symbol Equivalent Circuit Description

ADC12010

14–19,

22–27

D0–D11

Digital data output pins that make up the 12-bit conversion
results. D0 is the LSB, while D11 is the MSB of the offset
binary output word. Output levels are TTL/CMOS compatible.

ANALOG POWER

Positive analog supply pins. These pins should be connected

5, 6, 29 V

A

to a quiet +5V voltage source and be bypassed to AGND with

0.1 µF monolithic capacitors located within 1 cm of these
power pins, and with a 10 µF capacitor.

4, 7, 28 AGND The ground return for the analog supply.

DIGITAL POWER

Positive digital supply pin. This pin should be connected to

13 V

D

the same quiet +5V source as is V
with a 0.1 µF monolithic capacitor in parallel with a 10 µF
capacitor, both located within 1 cm of the power pin.

9, 12 DGND The ground return for the digital supply.

Positive digital supply pin for the ADC12010’s output drivers.
This pin should be connected to a voltage source of +2.35V
to +5V and be bypassed to DR GND with a 0.1 µF monolithic

21 V

DR

capacitor. If the supply for this pin is different from the supply
used for V
tantalum capacitor. V

. All bypass capacitors should be located within 1 cm of the

V

D

and VD, it should also be bypassed with a 10 µF

A

should never exceed the voltage on

DR

supply pin.

The ground return for the digital supply for the ADC12010’s
output drivers. This pin should be connected to the system

20 DR GND

digital ground, but not be connected in close proximity to the
ADC12010’s DGND or AGND pins. See Section 5 (Layout
and Grounding) for more details.

and bypassed to DGND

A

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ADC12010

Absolute Maximum Ratings (Notes 1,

2)

If Military/Aerospace specified devices are required,
please contact the National Semiconductor Sales Office/
Distributors for availability and specifications.

V

A,VD

V

DR

|V

| ≤ 100 mV

A–VD

Voltage on Any Input or Output Pin −0.3V to (V

Input Current at Any Pin (Note 3)

Package Input Current (Note 3)

Package Dissipation at T

= 25˚C See (Note 4)

A

6.5V

≤VD+0.3V

or V

A

+0.3V)

±

25 mA

±

50 mA

D

Operating Ratings (Notes 1, 2)

Operating Temperature −40˚C ≤ T

Supply Voltage (V

Output Driver Supply (V

V

Input 1.0V to 2.4V

REF

CLK, PD, OE

V

Input −0V to (VA− 0.5V)

IN

V

CM

) +4.75V to +5.25V

A,VD

) +2.35V to V

DR

−0.05V to (VD+ 0.05V)

|AGND–DGND| ≤100mV

≤ +85˚C

A

1.0V to 4.0V

ESD Susceptibility

Human Body Model (Note 5) 2500V

Machine Model (Note 5) 250V

Soldering Temperature,

Infrared, 10 sec. (Note 6) 235˚C

Storage Temperature −65˚C to +150˚C

Converter Electrical Characteristics

Unless otherwise specified, the following specifications apply for AGND = DGND = DR GND = 0V, VA=VD= +5V, VDR=
+3.0V, PD = 0V, V

: all other limits TA=TJ= 25˚C (Notes 7, 8, 9)

T

MAX

REF

= +2.0V, f

Symbol Parameter Conditions

STATIC CONVERTER CHARACTERISTICS

Resolution with No Missing Codes 12 Bits (min)

INL Integral Non Linearity (Note 11)

DNL Differential Non Linearity

GE Gain Error

Offset Error (V

IN=VIN

Under Range Output Code 0 0

Over Range Output Code 4095 4095

DYNAMIC CONVERTER CHARACTERISTICS

FPBW Full Power Bandwidth 0 dBFS Input, Output at −3 dB 100 MHz

SNR Signal-to-Noise Ratio

SINAD Signal-to-Noise and Distortion

ENOB Effective Number of Bits

THD Total Harmonic Distortion

SFDR Spurious Free Dynamic Range

= 10 MHz, tr=tf= 3 ns, CL= 25 pF/pin. Boldface limits apply for TA=TJ=T

CLK

Typical

(Note 10)

±

0.5

±

0.3

±

0.2 2.9 %FS (max)

Limits

(Note 10)

±

1.5 LSB (max)

±

0.9 LSB (max)

to

MIN

Units

(Limits)

−) −0.1 1.75 %FS (max)

f

= 1 MHz, VIN= −0.5 dBFS 70 dB

IN

f

= 4.4 MHz, VIN= −0.5 dBFS 70 dB

IN

f

= 10.1 MHz, VIN= −0.5 dBFS 70 66 dB (min)

IN

= 1 MHz, VIN= −0.5 dBFS 70 dB

f

IN

f

= 4.4 MHz, VIN= −0.5 dBFS 70 dB

IN

f

= 10.1 MHz, VIN= −0.5 dBFS 69 66 dB (min)

IN

= 1 MHz, VIN= −0.5 dBFS 11.4 dB

f

IN

f

= 4.4 MHz, VIN= −0.5 dBFS 11.4 dB

IN

f

= 10.1 MHz, VIN= −0.5 dBFS 11.3 10.7 dB (min)

IN

= 1 MHz, VIN= −0.5 dBFS −88 dB

f

IN

f

= 4.4 MHz, VIN= −0.5 dBFS −86 dB

IN

f

= 10.1 MHz, VIN= −0.5 dBFS −79 −74 dB (min)

IN

= 1 MHz, VIN= −0.5 dBFS 92 dB

f

IN

f

= 4.4 MHz, VIN= −0.5 dBFS 89 dB

IN

f

= 10.1 MHz, VIN= −0.5 dBFS 83 69 dB (min)

IN

D

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Converter Electrical Characteristics (Continued)

Unless otherwise specified, the following specifications apply for AGND = DGND = DR GND = 0V, VA=VD= +5V, VDR=
+3.0V, PD = 0V, V

ADC12010

: all other limits TA=TJ= 25˚C (Notes 7, 8, 9)

T

MAX

REF

= +2.0V, f

Symbol Parameter Conditions

IMD Intermodulation Distortion

= 10 MHz, tr=tf= 3 ns, CL= 25 pF/pin. Boldface limits apply for TA=TJ=T

CLK

= 4.7 MHz and 4.9 MHz,

f

IN

each = −7 dBFS

Typical

(Note 10)

−75 dBFS

Limits

(Note 10)

REFERENCE AND ANALOG INPUT CHARACTERISTICS

V

CM

C

IN

V

REF

Common Mode Input Voltage VA/2 V

VINInput Capacitance (each pin to
GND)

VIN= 2.5 Vdc
+ 0.7 V

rms

Reference Voltage (Note 13) 2.00

(CLK LOW) 8 pF

(CLK HIGH) 7 pF

1.0 V (min)

2.4 V (max)

Reference Input Resistance 100 MΩ(min)

DC and Logic Electrical Characteristics

Unless otherwise specified, the following specifications apply for AGND = DGND = DR GND = 0V, VA=VD= +5V, VDR=
+3.0V, PD = 0V, V

: all other limits TA=TJ= 25˚C (Notes 7, 8, 9)

T

MAX

REF

= +2.0V, f

Symbol Parameter Conditions

CLK, PD, OE DIGITAL INPUT CHARACTERISTICS

V

V

I

I

C

IN(1)

IN(0)

IN(1)

IN(0)

IN

Logical “1” Input Voltage VD= 5.25V 2.0 V (min)

Logical “0” Input Voltage VD= 4.75V 1.0 V (max)

Logical “1” Input Current VIN= 5.0V 10 µA

Logical “0” Input Current VIN= 0V −10 µA

Digital Input Capacitance 5 pF

D0–D11 DIGITAL OUTPUT CHARACTERISTICS

V

V

I

OZ

+I

−I

OUT(1)

OUT(0)

SC

SC

Logical “1” Output Voltage I

Logical “0” Output Voltage I

TRI-STATE Output Current

Output Short Circuit Source
Current

Output Short Circuit Sink Current V

POWER SUPPLY CHARACTERISTICS

I

A

I

D

I

DR

Analog Supply Current

Digital Supply Current

Digital Output Supply Current

Total Power Consumption

PSRR1+ Power Supply Rejection Ratio

PSRR1− Power Supply Rejection Ratio

PSRR2 Power Supply Rejection Ratio

= 10 MHz, tr=tf= 3 ns, CL= 25 pF/pin. Boldface limits apply for TA=TJ=T

CLK

Typical

(Note 10)

= 2.5V 2.3 V (min)

V

= 2.0V

DR

V

=3V 2.7 V (min)

DR

20 mA (min)

30

2.8

2

2.2

0
0

160

25

69 dBFS

51 dBFS

A

48 dBFS

= −0.5 mA

OUT

= 1.6 mA, VDR=3V 0.4 V (max)

OUT

= 2.5V or 5V 100 nA

V

OUT

V

= 0V −100 nA

OUT

= 0V −20 mA (min)

V

OUT

OUT=VDR

PD Pin = DGND, V
PD Pin = V

REF

DR

PD Pin = DGND
PD Pin = V

DR,fCLK

PD Pin = DGND, C
PD Pin = V

DR,fCLK

PD Pin = DGND, C
PD Pin = V

DR,fCLK

=0

= 0 pF (Note 14)

L

=0

= 0 pF (Note 15)

L

=0

Rejection of Positive Full-Scale Error
with VA= 4.75V vs. 5.25V

Rejection of Negative Full-Scale Error
with VA= 4.75V vs. 5.25V

Rejection of Power Supply Noise with
10 MHz, 250 mV

riding on V

P-P

Limits

(Note 10)

39 mA (max)

2.5 mA (max)

207 mW

to

MIN

Units

(Limits)

to

MIN

Units

(Limits)

mA

mA

mA
mA

mW

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AC Electrical Characteristics

Unless otherwise specified, the following specifications apply for AGND = DGND = DR GND = 0V, VA=VD= +5V, VDR=
+3.0V, PD = 0V, V

: all other limits TA=TJ= 25˚C (Notes 7, 8, 9, 12)

T

MAX

REF

= +2.0V, f

Symbol Parameter Conditions

1

f

CLK

f

CLK

t

CH

t

CL

t

CONV

t

OD

t

AD

t

AJ

t

DIS

t

EN

t

PD

Note 1: Absolute Maximum Ratings indicate limits beyond which damage to the device may occur. Operating Ratings indicate conditions for which the device is
functional, but do not guarantee specific performance limits. For guaranteed specifications and test conditions, see the Electrical Characteristics. The guaranteed
specifications apply only for the test conditions listed. Some performance characteristics may degrade when the device is not operated under the listed test
conditions.

Note 2: All voltages are measured with respect to GND = AGND = DGND = 0V, unless otherwise specified.

Note 3: When the input voltage at any pin exceeds the power supplies (that is, V

50 mA maximum package input current rating limits the number of pins that can safely exceed the power supplies with an input current of 25 mA to two.

Note 4: The absolute maximum junction temperature (T
junction-to-ambient thermal resistance (θ
LQFP, θ
this device under normal operation will typically be about 180 mW (160 typical power consumption + 20 mW TTL output loading). The values for maximum power
dissipation listed above will be reached only when the device is operated in a severe fault condition (e.g. when input or output pins are driven beyond the power
supply voltages, or the power supply polarity is reversed). Obviously, such conditions should always be avoided.

Note 5: Human body model is 100 pF capacitor discharged through a 1.5 kΩ resistor. Machine model is 220 pF discharged through 0Ω.

Note 6: The 235˚C reflow temperature refers to infrared reflow. For Vapor Phase Reflow (VPR), the following Conditions apply: Maintain the temperature at the top

of the package body above 183˚C for a minimum 60 seconds. The temperature measured on the package body must not exceed 220˚C. Only one excursion above
183˚C is allowed per reflow cycle.

Note 7: The inputs are protected as shown below. Input voltage magnitudes above V
(Note 3). However, errors in the A/D conversion can occur if the input goes above V
input voltage must be ≤4.85V to ensure accurate conversions.

Maximum Clock Frequency 10 15 MHz (min)

2

Minimum Clock Frequency 100 kHz

Clock High Time 30 ns (min)

Clock Low Time 30 ns(min)

Conversion Latency 6

Data Output Delay after Rising
CLK Edge

Aperture Delay 1.2 ns

Aperture Jitter 2 ps rms

Data outputs into TRI-STATE
Mode

Data Outputs Active after
TRI-STATE

Power Down Mode Exit Cycle 0.1 µF cap on pins 30, 31,32 500 ns

is 79˚C/W, so PDMAX = 1,582 mW at 25˚C and 823 mW at the maximum operating ambient temperature of 85˚C. Note that the power consumption of

JA

= 10 MHz, tr=tf= 3 ns, CL= 25 pF/pin. Boldface limits apply for TA=TJ=T

CLK

Typical

(Note 10)

Limits

(Note 10)

MIN

Units

(Limits)

Clock

Cycles

= 2.5V 11 16.8 ns (max)

V

DR

V

= 3.0V 11 16.8 ns (max)

DR

4ns

4ns

<

AGND, or V

IN

max) for this device is 150˚C. The maximum allowable power dissipation is dictated by TJmax, the

), and the ambient temperature, (TA), and can be calculated using the formula PDMAX=(TJmax - TA)/θJA. In the 32-pin

JA

J

or below GND will not damage this device, provided current is limited per

A

or below GND by more than 100 mV. As an example, if VAis 4.75V, the full-scale

A

>

VA), the current at that pin should be limited to 25 mA. The

IN

to

ADC12010

20051607

Note 8: To guarantee accuracy, it is required that |VA–VD| ≤ 100 mV and separate bypass capacitors are used at each power supply pin.

Note 9: With the test condition for V

Note 10: Typical figures are at T

Level).

Note 11: Integral Non Linearity is defined as the deviation of the analog value, expressed in LSBs, from the straight line that passes through positive and negative
full-scale.

Note 12: Timing specifications are tested at TTL logic levels, V

Note 13: Optimum performance will be obtained by keeping the reference input in the 1.8V to 2.2V range. The LM4051CIM3-ADJ (SOT-23 package) is

recommended for this application.

= +2.0V (4V

REF

= 25˚C, and represent most likely parametric norms. Test limits are guaranteed to National’sAOQL (Average Outgoing Quality

A=TJ

differential input), the 12-bit LSB is 977 µV.

P-P

= 0.4V for a falling edge and VIH= 2.4V for a rising edge.

IL

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