ADC12010
12-Bit, 10 MSPS, 160 mW A/D Converter with Internal
Sample-and-Hold
ADC12010 12-Bit, 10 MSPS, 160 mW A/D Converter with Internal Sample-and-Hold
April 2003
General Description
The ADC12010 is a monolithic CMOS analog-to-digital converter capable of converting analog input signals into 12-bit
digital words at 10 Megasamples per second (MSPS), minimum. This converter uses a differential, pipeline architecture
with digital error correction and an on-chip sample-and-hold
circuit to minimize die size and power consumption while
providing excellent dynamic performance. Operating on a
single 5V power supply, this device consumes just 160 mW
at 10 MSPS, including the reference current. The Power
Down feature reduces power consumption to 25 mW.
The differential inputs provide a full scale input swing equal
to 2V
of the differential input is recommended for optimum performance. For ease of use, the buffered, high impedance,
single-ended reference input is converted on-chip to a differential reference for use by the processing circuitry. Output
data format is 12-bit offset binary.
This device is available in the 32-lead LQFP package and
will operate over the industrial temperature range of −40˚C to
+85˚C.
with the possibility of a single-ended input. Full use
REF
Features
n Internal sample-and-hold
n Outputs 2.4V to 5V compatible
n TTL/CMOS compatible input/outputs
n Power down mode
n On-chip reference buffer
Key Specifications
n Resolution 12 Bits
n Conversion Rate 10 MSPS (min)
n DNL
n INL
n SNR (f
n ENOB (f
n Data Latency 6 Clock Cycles
n Supply Voltage +5V
n Power Consumption, 10 MHz 160 mW (typ)
= 10.1 MHz) 70 dB (typ)
IN
= 10.1 MHz) 11.3 bits (typ)
IN
±
0.3 LSB (typ)
±
0.5 LSB (typ)
±
5%
Applications
n Image Processing Front End
n Instrumentation
n PC-Based Data Acquisition
n Fax Machines
n Wireless Local Loops/Cable Modems
n Waveform Digitizers
n DSP Front Ends
Connection Diagram
20051601
TRI-STATE®is a registered trademark of National Semiconductor Corporation.
© 2003 National Semiconductor Corporation DS200516 www.national.com
Ordering Information
ADC12010
Block Diagram
Industrial (−40˚C ≤ TA≤ +85˚C) Package
ADC12010CIVY 32 Pin LQFP
ADC12010CIVYX 32 Pin LQFP Tape and Reel
ADC12010EVAL Evaluation Board
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20051602
Pin Descriptions and Equivalent Circuits
Pin No. Symbol Equivalent Circuit Description
ANALOG I/O
Non-Inverting analog signal Input. With a 2.0V reference
2V
3V
1V
IN
IN
REF
+
voltage, the ground-referenced input signal level is 2.0 V
centered on VCM.
Inverting analog signal Input. With a 2.0V reference voltage
the ground-referenced input signal level is 2.0 V
−
. This pin may be connected to VCMfor single-ended
on V
CM
operation, but a differential input signal is required for best
performance.
Reference input. This pin should be bypassed to AGND with
a 0.1 µF monolithic capacitor. V
should be between 1.0V to 2.4V.
is 2.0V nominal and
REF
P-P
ADC12010
P-P
centered
31 V
32 V
30 V
DIGITAL I/O
10 CLK
11 OE
RP
RM
RN
These pins are high impedance reference bypass pins.
Connect a 0.1 µF capacitor from each of these pins to AGND.
DO NOT LOAD these pins.
Digital clock input. The range of frequencies for this input is
100 kHz to 15 MHz (typical) with guaranteed performance at
10 MHz. The input is sampled on the rising edge of this input.
OE is the output enable pin that, when low, enables the
TRI-STATE®data output pins. When this pin is high, the
outputs are in a high impedance state.
8PD
PD is the Power Down input pin. When high, this input puts
the converter into the power down mode. When this pin is
low, the converter is in the active mode.
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Pin Descriptions and Equivalent Circuits (Continued)
Pin No. Symbol Equivalent Circuit Description
ADC12010
14–19,
22–27
D0–D11
Digital data output pins that make up the 12-bit conversion
results. D0 is the LSB, while D11 is the MSB of the offset
binary output word. Output levels are TTL/CMOS compatible.
ANALOG POWER
Positive analog supply pins. These pins should be connected
5, 6, 29 V
A
to a quiet +5V voltage source and be bypassed to AGND with
0.1 µF monolithic capacitors located within 1 cm of these
power pins, and with a 10 µF capacitor.
4, 7, 28 AGND The ground return for the analog supply.
DIGITAL POWER
Positive digital supply pin. This pin should be connected to
13 V
D
the same quiet +5V source as is V
with a 0.1 µF monolithic capacitor in parallel with a 10 µF
capacitor, both located within 1 cm of the power pin.
9, 12 DGND The ground return for the digital supply.
Positive digital supply pin for the ADC12010’s output drivers.
This pin should be connected to a voltage source of +2.35V
to +5V and be bypassed to DR GND with a 0.1 µF monolithic
21 V
DR
capacitor. If the supply for this pin is different from the supply
used for V
tantalum capacitor. V
. All bypass capacitors should be located within 1 cm of the
V
D
and VD, it should also be bypassed with a 10 µF
A
should never exceed the voltage on
DR
supply pin.
The ground return for the digital supply for the ADC12010’s
output drivers. This pin should be connected to the system
20 DR GND
digital ground, but not be connected in close proximity to the
ADC12010’s DGND or AGND pins. See Section 5 (Layout
and Grounding) for more details.
and bypassed to DGND
A
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ADC12010
Absolute Maximum Ratings (Notes 1,
2)
If Military/Aerospace specified devices are required,
please contact the National Semiconductor Sales Office/
Distributors for availability and specifications.
V
A,VD
V
DR
|V
| ≤ 100 mV
A–VD
Voltage on Any Input or Output Pin −0.3V to (V
Input Current at Any Pin (Note 3)
Package Input Current (Note 3)
Package Dissipation at T
= 25˚C See (Note 4)
A
6.5V
≤VD+0.3V
or V
A
+0.3V)
±
25 mA
±
50 mA
D
Operating Ratings (Notes 1, 2)
Operating Temperature −40˚C ≤ T
Supply Voltage (V
Output Driver Supply (V
V
Input 1.0V to 2.4V
REF
CLK, PD, OE
V
Input −0V to (VA− 0.5V)
IN
V
CM
) +4.75V to +5.25V
A,VD
) +2.35V to V
DR
−0.05V to (VD+ 0.05V)
|AGND–DGND| ≤100mV
≤ +85˚C
A
1.0V to 4.0V
ESD Susceptibility
Human Body Model (Note 5) 2500V
Machine Model (Note 5) 250V
Soldering Temperature,
Infrared, 10 sec. (Note 6) 235˚C
Storage Temperature −65˚C to +150˚C
Converter Electrical Characteristics
Unless otherwise specified, the following specifications apply for AGND = DGND = DR GND = 0V, VA=VD= +5V, VDR=
+3.0V, PD = 0V, V
: all other limits TA=TJ= 25˚C (Notes 7, 8, 9)
T
MAX
REF
= +2.0V, f
Symbol Parameter Conditions
STATIC CONVERTER CHARACTERISTICS
Resolution with No Missing Codes 12 Bits (min)
INL Integral Non Linearity (Note 11)
DNL Differential Non Linearity
GE Gain Error
Offset Error (V
IN=VIN
Under Range Output Code 0 0
Over Range Output Code 4095 4095
DYNAMIC CONVERTER CHARACTERISTICS
FPBW Full Power Bandwidth 0 dBFS Input, Output at −3 dB 100 MHz
SNR Signal-to-Noise Ratio
SINAD Signal-to-Noise and Distortion
ENOB Effective Number of Bits
THD Total Harmonic Distortion
SFDR Spurious Free Dynamic Range
= 10 MHz, tr=tf= 3 ns, CL= 25 pF/pin. Boldface limits apply for TA=TJ=T
CLK
Typical
(Note 10)
±
0.5
±
0.3
±
0.2 2.9 %FS (max)
Limits
(Note 10)
±
1.5 LSB (max)
±
0.9 LSB (max)
to
MIN
Units
(Limits)
−) −0.1 1.75 %FS (max)
f
= 1 MHz, VIN= −0.5 dBFS 70 dB
IN
f
= 4.4 MHz, VIN= −0.5 dBFS 70 dB
IN
f
= 10.1 MHz, VIN= −0.5 dBFS 70 66 dB (min)
IN
= 1 MHz, VIN= −0.5 dBFS 70 dB
f
IN
f
= 4.4 MHz, VIN= −0.5 dBFS 70 dB
IN
f
= 10.1 MHz, VIN= −0.5 dBFS 69 66 dB (min)
IN
= 1 MHz, VIN= −0.5 dBFS 11.4 dB
f
IN
f
= 4.4 MHz, VIN= −0.5 dBFS 11.4 dB
IN
f
= 10.1 MHz, VIN= −0.5 dBFS 11.3 10.7 dB (min)
IN
= 1 MHz, VIN= −0.5 dBFS −88 dB
f
IN
f
= 4.4 MHz, VIN= −0.5 dBFS −86 dB
IN
f
= 10.1 MHz, VIN= −0.5 dBFS −79 −74 dB (min)
IN
= 1 MHz, VIN= −0.5 dBFS 92 dB
f
IN
f
= 4.4 MHz, VIN= −0.5 dBFS 89 dB
IN
f
= 10.1 MHz, VIN= −0.5 dBFS 83 69 dB (min)
IN
D
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Converter Electrical Characteristics (Continued)
Unless otherwise specified, the following specifications apply for AGND = DGND = DR GND = 0V, VA=VD= +5V, VDR=
+3.0V, PD = 0V, V
ADC12010
: all other limits TA=TJ= 25˚C (Notes 7, 8, 9)
T
MAX
REF
= +2.0V, f
Symbol Parameter Conditions
IMD Intermodulation Distortion
= 10 MHz, tr=tf= 3 ns, CL= 25 pF/pin. Boldface limits apply for TA=TJ=T
CLK
= 4.7 MHz and 4.9 MHz,
f
IN
each = −7 dBFS
Typical
(Note 10)
−75 dBFS
Limits
(Note 10)
REFERENCE AND ANALOG INPUT CHARACTERISTICS
V
CM
C
IN
V
REF
Common Mode Input Voltage VA/2 V
VINInput Capacitance (each pin to
GND)
VIN= 2.5 Vdc
+ 0.7 V
rms
Reference Voltage (Note 13) 2.00
(CLK LOW) 8 pF
(CLK HIGH) 7 pF
1.0 V (min)
2.4 V (max)
Reference Input Resistance 100 MΩ(min)
DC and Logic Electrical Characteristics
Unless otherwise specified, the following specifications apply for AGND = DGND = DR GND = 0V, VA=VD= +5V, VDR=
+3.0V, PD = 0V, V
: all other limits TA=TJ= 25˚C (Notes 7, 8, 9)
T
MAX
REF
= +2.0V, f
Symbol Parameter Conditions
CLK, PD, OE DIGITAL INPUT CHARACTERISTICS
V
V
I
I
C
IN(1)
IN(0)
IN(1)
IN(0)
IN
Logical “1” Input Voltage VD= 5.25V 2.0 V (min)
Logical “0” Input Voltage VD= 4.75V 1.0 V (max)
Logical “1” Input Current VIN= 5.0V 10 µA
Logical “0” Input Current VIN= 0V −10 µA
Digital Input Capacitance 5 pF
D0–D11 DIGITAL OUTPUT CHARACTERISTICS
V
V
I
OZ
+I
−I
OUT(1)
OUT(0)
SC
SC
Logical “1” Output Voltage I
Logical “0” Output Voltage I
TRI-STATE Output Current
Output Short Circuit Source
Current
Output Short Circuit Sink Current V
POWER SUPPLY CHARACTERISTICS
I
A
I
D
I
DR
Analog Supply Current
Digital Supply Current
Digital Output Supply Current
Total Power Consumption
PSRR1+ Power Supply Rejection Ratio
PSRR1− Power Supply Rejection Ratio
PSRR2 Power Supply Rejection Ratio
= 10 MHz, tr=tf= 3 ns, CL= 25 pF/pin. Boldface limits apply for TA=TJ=T
CLK
Typical
(Note 10)
= 2.5V 2.3 V (min)
V
= 2.0V
DR
V
=3V 2.7 V (min)
DR
20 mA (min)
30
2.8
2
2.2
0
0
160
25
69 dBFS
51 dBFS
A
48 dBFS
= −0.5 mA
OUT
= 1.6 mA, VDR=3V 0.4 V (max)
OUT
= 2.5V or 5V 100 nA
V
OUT
V
= 0V −100 nA
OUT
= 0V −20 mA (min)
V
OUT
OUT=VDR
PD Pin = DGND, V
PD Pin = V
REF
DR
PD Pin = DGND
PD Pin = V
DR,fCLK
PD Pin = DGND, C
PD Pin = V
DR,fCLK
PD Pin = DGND, C
PD Pin = V
DR,fCLK
=0
= 0 pF (Note 14)
L
=0
= 0 pF (Note 15)
L
=0
Rejection of Positive Full-Scale Error
with VA= 4.75V vs. 5.25V
Rejection of Negative Full-Scale Error
with VA= 4.75V vs. 5.25V
Rejection of Power Supply Noise with
10 MHz, 250 mV
riding on V
P-P
Limits
(Note 10)
39 mA (max)
2.5 mA (max)
207 mW
to
MIN
Units
(Limits)
to
MIN
Units
(Limits)
mA
mA
mA
mA
mW
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AC Electrical Characteristics
Unless otherwise specified, the following specifications apply for AGND = DGND = DR GND = 0V, VA=VD= +5V, VDR=
+3.0V, PD = 0V, V
: all other limits TA=TJ= 25˚C (Notes 7, 8, 9, 12)
T
MAX
REF
= +2.0V, f
Symbol Parameter Conditions
1
f
CLK
f
CLK
t
CH
t
CL
t
CONV
t
OD
t
AD
t
AJ
t
DIS
t
EN
t
PD
Note 1: Absolute Maximum Ratings indicate limits beyond which damage to the device may occur. Operating Ratings indicate conditions for which the device is
functional, but do not guarantee specific performance limits. For guaranteed specifications and test conditions, see the Electrical Characteristics. The guaranteed
specifications apply only for the test conditions listed. Some performance characteristics may degrade when the device is not operated under the listed test
conditions.
Note 2: All voltages are measured with respect to GND = AGND = DGND = 0V, unless otherwise specified.
Note 3: When the input voltage at any pin exceeds the power supplies (that is, V
50 mA maximum package input current rating limits the number of pins that can safely exceed the power supplies with an input current of 25 mA to two.
Note 4: The absolute maximum junction temperature (T
junction-to-ambient thermal resistance (θ
LQFP, θ
this device under normal operation will typically be about 180 mW (160 typical power consumption + 20 mW TTL output loading). The values for maximum power
dissipation listed above will be reached only when the device is operated in a severe fault condition (e.g. when input or output pins are driven beyond the power
supply voltages, or the power supply polarity is reversed). Obviously, such conditions should always be avoided.
Note 5: Human body model is 100 pF capacitor discharged through a 1.5 kΩ resistor. Machine model is 220 pF discharged through 0Ω.
Note 6: The 235˚C reflow temperature refers to infrared reflow. For Vapor Phase Reflow (VPR), the following Conditions apply: Maintain the temperature at the top
of the package body above 183˚C for a minimum 60 seconds. The temperature measured on the package body must not exceed 220˚C. Only one excursion above
183˚C is allowed per reflow cycle.
Note 7: The inputs are protected as shown below. Input voltage magnitudes above V
(Note 3). However, errors in the A/D conversion can occur if the input goes above V
input voltage must be ≤4.85V to ensure accurate conversions.
Maximum Clock Frequency 10 15 MHz (min)
2
Minimum Clock Frequency 100 kHz
Clock High Time 30 ns (min)
Clock Low Time 30 ns(min)
Conversion Latency 6
Data Output Delay after Rising
CLK Edge
Aperture Delay 1.2 ns
Aperture Jitter 2 ps rms
Data outputs into TRI-STATE
Mode
Data Outputs Active after
TRI-STATE
Power Down Mode Exit Cycle 0.1 µF cap on pins 30, 31,32 500 ns
is 79˚C/W, so PDMAX = 1,582 mW at 25˚C and 823 mW at the maximum operating ambient temperature of 85˚C. Note that the power consumption of
JA
= 10 MHz, tr=tf= 3 ns, CL= 25 pF/pin. Boldface limits apply for TA=TJ=T
CLK
Typical
(Note 10)
Limits
(Note 10)
MIN
Units
(Limits)
Clock
Cycles
= 2.5V 11 16.8 ns (max)
V
DR
V
= 3.0V 11 16.8 ns (max)
DR
4ns
4ns
<
AGND, or V
IN
max) for this device is 150˚C. The maximum allowable power dissipation is dictated by TJmax, the
), and the ambient temperature, (TA), and can be calculated using the formula PDMAX=(TJmax - TA)/θJA. In the 32-pin
JA
J
or below GND will not damage this device, provided current is limited per
A
or below GND by more than 100 mV. As an example, if VAis 4.75V, the full-scale
A
>
VA), the current at that pin should be limited to 25 mA. The
IN
to
ADC12010
20051607
Note 8: To guarantee accuracy, it is required that |VA–VD| ≤ 100 mV and separate bypass capacitors are used at each power supply pin.
Note 9: With the test condition for V
Note 10: Typical figures are at T
Level).
Note 11: Integral Non Linearity is defined as the deviation of the analog value, expressed in LSBs, from the straight line that passes through positive and negative
full-scale.
Note 12: Timing specifications are tested at TTL logic levels, V
Note 13: Optimum performance will be obtained by keeping the reference input in the 1.8V to 2.2V range. The LM4051CIM3-ADJ (SOT-23 package) is
recommended for this application.
= +2.0V (4V
REF
= 25˚C, and represent most likely parametric norms. Test limits are guaranteed to National’sAOQL (Average Outgoing Quality
A=TJ
differential input), the 12-bit LSB is 977 µV.
P-P
= 0.4V for a falling edge and VIH= 2.4V for a rising edge.
IL
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AC Electrical Characteristics (Continued)
Note 14: IDRis the current consumed by the switching of the output drivers and is primarily determined by load capacitance on the output pins, the supply voltage,
V
, and the rate at which the outputs are switching (which is signal dependent). IDR=VDR(C0xf0+C1xf1+....C11xf11) where VDRis the output driver power supply
DR
ADC12010
voltage, C
Note 15: Excludes I
is total capacitance on the output pin, and fnis the average frequency at which that pin is toggling.
n
. See note 14.
DR
Specification Definitions
APERTURE DELAY is the time after the rising edge of the
clock to when the input signal is acquired or held for conversion.
APERTURE JITTER (APERTURE UNCERTAINTY) is the
variation in aperture delay from sample to sample. Aperture
jitter manifests itself as noise in the output.
CLOCK DUTY CYCLE is the ratio of the time during one
cycle that a repetitive digital waveform is high to the total
time of one period. The specification here refers to the ADC
clock input signal.
COMMON MODE VOLTAGE (V
present at both signal inputs to the ADC.
CONVERSION LATENCY is the number of clock cycles
between initiation of conversion and when that data is presented to the output driver stage. Data for any given sample
is available at the output pins the Pipeline Delay plus the
Output Delay after the sample is taken. New data is available
at every clock cycle, but the data lags the conversion by the
pipeline delay.
DIFFERENTIAL NON-LINEARITY (DNL) is the measure of
the maximum deviation from the ideal step size of 1 LSB.
EFFECTIVE NUMBER OF BITS (ENOB, or EFFECTIVE
BITS) is another method of specifying Signal-to-Noise and
Distortion or SINAD. ENOB is defined as (SINAD - 1.76) /
6.02 and says that the converter is equivalent to a perfect
ADC of this (ENOB) number of bits.
FULL POWER BANDWIDTH is a measure of the frequency
at which the reconstructed output fundamental drops 3 dB
below its low frequency value for a full scale input.
GAIN ERROR is the deviation from the ideal slope of the
transfer function. It can be calculated as:
Gain Error = Positive Full Scale Error − Offset Error
INTEGRAL NON LINEARITY (INL) is a measure of the
deviation of each individual code from a line drawn from
negative full scale (
1
⁄2LSB below the first code transition)
through positive full scale (
transition). The deviation of any given code from this straight
line is measured from the center of that code value.
INTERMODULATION DISTORTION (IMD) is the creation of
additional spectral components as a result of two sinusoidal
frequencies being applied to the ADC input at the same time.
It is defined as the ratio of the power in the intermodulation
products to the total power in the original frequencies. IMD is
usually expressed in dBFS.
MISSING CODES are those output codes that will never
appear at the ADC outputs. The ADC12010 is guaranteed
not to have any missing codes.
) is the d.c. potential
CM
1
⁄2LSB above the last code
NEGATIVE FULL SCALE ERROR is the difference between
the actual first code transition and its ideal value of
1
⁄2LSB
above negative full scale.
OFFSET ERROR is the difference between the two input
voltages (V
+−VIN−) required to cause a transition from
IN
code 2047 to 2048.
OUTPUT DELAY is the time delay after the rising edge of
the clock before the data update is presented at the output
pins.
PIPELINE DELAY (LATENCY)See CONVERSION LATENCY
POSITIVE FULL SCALE ERROR is the difference between
the actual last code transition and its ideal value of 1
1
⁄2LSB
below positive full scale.
POWER SUPPLY REJECTION RATIO (PSRR) is a mea-
sure of how well the ADC rejects a change in the power
supply voltage. For the ADC12010, PSRR1 is the ratio of the
change in Full-Scale Error that results from a change in the
dc power supply voltage, expressed in dB. PSRR2 is a
measure of how well an a.c. signal riding upon the power
supply is rejected at the output.
SIGNAL TO NOISE RATIO (SNR) is the ratio, expressed in
dB, of the rms value of the input signal to the rms value of the
sum of all other spectral components below one-half the
sampling frequency, not including harmonics or dc.
SIGNAL TO NOISE PLUS DISTORTION (S/N+D or SINAD)
Is the ratio, expressed in dB, of the rms value of the input
signal to the rms value of all of the other spectral components below half the clock frequency, including harmonics
but excluding dc.
SPURIOUS FREE DYNAMIC RANGE (SFDR) is the difference, expressed in dB, between the rms values of the input
signal and the peak spurious signal, where a spurious signal
is any signal present in the output spectrum that is not
present at the input.
TOTAL HARMONIC DISTORTION (THD) is the ratio, expressed in dBc, of the rms total of the first nine harmonic
levels at the output to the level of the fundamental at the
output. THD is calculated as
where f1is the RMS power of the fundamental (output)
frequency and f
through f10are the RMS power in the first 9
2
harmonic frequencies.
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Timing Diagram
ADC12010
Transfer Characteristic
Output Timing
20051609
20051610
FIGURE 1. Transfer Characteristic
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ADC12010 Typical Performance Characteristics V
= 10 MHz, fIN= 10.1 MHz, V
f
CLK
ADC12010
DNL DNL vs. Temperature
DNL vs. Clock Duty Cycle DNL vs. Sample Rate
= 2.0V unless otherwise stated
REF
20051638 20051639
= 5,0V, VDR= 3.0V,
A=VD
20051640 20051641
INL INL vs. Temperature
20051642 20051643
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ADC12010
ADC12010 Typical Performance Characteristics V
= 10.1 MHz, V
f
IN
= 2.0V unless otherwise stated (Continued)
REF
INL vs. Clock Duty Cycle INL vs. Sample Rate
20051644 20051645
SNR vs. Temperature SNR vs. Clock Duty Cycle
= 5,0V, VDR= 3.0V, f
A=VD
= 10 MHz,
CLK
20051646 20051647
SNR vs. Sample Rate SNR vs. F
20051648 20051649
IN
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ADC12010 Typical Performance Characteristics V
= 10.1 MHz, V
f
IN
= 2.0V unless otherwise stated (Continued)
REF
= 5,0V, VDR= 3.0V, f
A=VD
= 10 MHz,
CLK
ADC12010
SNR vs. V
REF
20051650 20051651
THD vs. Temperature
THD vs. Clock Duty Cycle THD vs. Sample Rate
20051652 20051653
THD vs. F
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IN
20051654 20051655
THD vs. V
REF
ADC12010
ADC12010 Typical Performance Characteristics V
= 10.1 MHz, V
f
IN
= 2.0V unless otherwise stated (Continued)
REF
SINAD vs. Temperature SINAD vs. Clock Duty Cycle
20051656 20051657
SINAD vs. Sample Rate SINAD vs. F
= 5,0V, VDR= 3.0V, f
A=VD
= 10 MHz,
CLK
IN
SINAD vs. V
REF
20051658 20051659
SFDR vs. Temperature
20051660 20051661
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ADC12010 Typical Performance Characteristics V
= 10.1 MHz, V
f
IN
= 2.0V unless otherwise stated (Continued)
REF
= 5,0V, VDR= 3.0V, f
A=VD
= 10 MHz,
CLK
ADC12010
SFDR vs. Clock Duty Cycle SFDR vs. Sample Rate
20051662 20051663
SFDR vs. F
IN
SFDR vs. V
REF
20051664 20051665
tODvs. V
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DR
20051669 20051666
Spectral Response, 1.1 MHz Input
ADC12010
ADC12010 Typical Performance Characteristics V
= 10.1 MHz, V
f
IN
Spectral Response, 4.4 MHz Input Spectral Response, 10.1 MHz Input
= 2.0V unless otherwise stated (Continued)
REF
20051667 20051668
= 5,0V, VDR= 3.0V, f
A=VD
= 10 MHz,
CLK
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Functional Description
Operating on a single +5V supply, the ADC12010 uses a
pipeline architecture with error correction circuitry to help
ADC12010
ensure maximum performance. The differential analog input
signal is digitized to 12 bits.
The reference input is buffered to ease the task of driving
that pin.
The output word rate is the same as the clock frequency,
which can be between 100 kSPS and 15 MSPS (typical).
The analog input voltage is acquired at the rising edge of the
clock and the digital data for a given sample is delayed by
the pipeline for 6 clock cycles.
A logic high on the power down (PD) pin reduces the converter power consumption to 40 mW.
20051611
Applications Information
1.0 OPERATING CONDITIONS
We recommend that the following conditions be observed for
operation of the ADC12010:
4.75V ≤ V
V
D=VA
2.35V ≤ VDR≤ V
100 kHz ≤ f
1.0V ≤ V
1.1 Analog Inputs
The ADC12010 has two analog signal inputs, V
These two pins form a differential input pair. There is one
reference input pin, V
1.2 Reference Pins
The ADC12010 is designed to operate with a 2.0V reference,
but performs well with reference voltages in the range of
1.0V to 2.4V. Lower reference voltages will decrease the
signal-to-noise ratio (SNR) of the ADC12010. Increasing the
reference voltage (and the input signal swing) beyond 2.4V
will degrade THD for a full-scale input. It is very important
that all grounds associated with the reference voltage and
the input signal make connection to the analog ground plane
at a single point to minimize the effects of noise currents in
the ground path.
The three Reference Bypass Pins (V
made available for bypass purposes. These pins should
each be bypassed to ground with a 0.1 µF capacitor. Smaller
capacitor values will allow faster recovery from the power
down mode, but may result in degraded noise performance.
DO NOT LOAD these pins.
1.3 Signal Inputs
The signal inputs are V
defined as
Figure 2 shows the expected input signal range.
Note that the common mode input voltage range is 1V to 3V
with a nominal value of V
main between ground and 4V.
The Peaks of the individual input signals (V
should each never exceed the voltage described as
to maintain THD and SINAD performance.
A
REF
≤ 5.25V
D
≤ 15 MHz
CLK
≤ 2.4V
V
V
IN
+ and VIN−.
IN
.
REF
RP,VRM
+ and VIN−. The input signal, VIN,is
IN
=(VIN+) – (VIN−)
IN
/2. The input signals should re-
A
+, VIN−=V
REF+VCM
and VRN) are
+ and VIN−)
IN
FIGURE 2. Expected Input Signal Range
The ADC12010 performs best with a differential input with
each input centered around V
swing at both V
+ and VIN− each should not exceed the
IN
. The peak-to-peak voltage
CM
value of the reference voltage or the output data will be
clipped. The two input signals should be exactly 180˚ out of
phase from each other and of the same amplitude. For single
frequency inputs, angular errors result in a reduction of the
effective full scale input. For a complex waveform, however,
angular errors will result in distortion.
For angular deviations of up to 10 degrees from these two
signals being 180 out of phase, the full scale error in LSB
can be described as approximately
1.79
= dev
E
FS
Where dev is the angular difference, in degrees, between
the two signals having a 180˚ relative phase relationship to
each other (see Figure 3). Drive the analog inputs with a
source impedance less than 100Ω.
20051612
FIGURE 3. Angular Errors Between the Two Input
Signals Will Reduce the Output Level
For differential operation, each analog input signal should
have a peak-to-peak voltage equal to the input reference
voltage, V
voltage, V
, and be centered around a common mode
REF
.
CM
TABLE 1. Input to Output Relationship —
Differential Input
VIN+V
V
CM−VREF
V
CM−VREF
V
CM+VREF
V
CM+VREF
/4 VCM+V
V
CM
/4 VCM−V
/2 VCM−V
/2 VCM+V
− Output
IN
/2 0000 0000 0000
REF
/4 0100 0000 0000
REF
V
CM
REF
REF
1000 0000 0000
/4 1100 0000 0000
/2 1111 1111 1111
www.national.com 16
Applications Information (Continued)
TABLE 2. Input to Output Relationship —
Single-Ended Input
V
V
CM−VREF
V
CM−VREF
V
V
CM+VREF
V
CM+VREF
+
IN
/2 V
CM
/2 V
−
V
IN
V
CM
CM
V
CM
CM
V
CM
Output
0000 0000 0000
0100 0000 0000
1000 0000 0000
1100 0000 0000
1111 1111 1111
1.3.3 Input Common Mode Voltage
The input common mode voltage, V
, should be in the
CM
range of 0.5V to 4.0V and be of a value such that the peak
excursions of the analog signal does not go more negative
than ground or more positive than 0.5 Volts below the V
supply voltage. The nominal VCMshould generally be equal
/2, but VRMcan be used as a VCMsource as long as
to V
REF
need not supply more than 10 µA of current.
V
CM
2.0 DIGITAL INPUTS
The digital TTL/CMOS compatible inputs consist of CLK, OE
and PD.
ADC12010
A
1.3.1 Single-Ended Operation
Single-ended performance is lower than with differential input signals. For this reason, single-ended operation is not
recommended. However, if single ended-operation is required, one of the analog inputs should be connected to the
d.c. common mode voltage of the driven input. The peak-topeak differential input signal should be twice the reference
voltage to maximize SNR and SINAD performance
(Figure 2b).
For example, set V
+ with a signal range of 0V to 2.0V. Because very large
V
IN
to 1.0V, bias VIN− to 1.0V and drive
REF
input signal swings can degrade distortion performance, better performance with a single-ended input can be obtained
by reducing the reference voltage when maintaining a fullrange output. Table 1 and Table 2 indicate the input to output
relationship of the ADC12010.
1.3.2 Driving the Analog Input
+ and the VIN− inputs of the ADC12010 consist of an
The V
IN
analog switch followed by a switched-capacitor amplifier.
The capacitance seen at the analog input pins changes with
the clock level, appearing as 8 pF when the clock is low, and
7 pF when the clock is high. Although this difference is small,
a dynamic capacitance is more difficult to drive than is a
fixed capacitance, so choose the driving amplifier carefully.
The LMH6702 and the LMH6628 are good amplifiers for
driving the ADC12010.
The internal switching action at the analog inputs causes
energy to be output from the input pins.As the driving source
tries to compensate for this, it adds noise to the signal. To
prevent this, use 100Ω series resistors at each of the signal
inputs with a 150 pF at each of the inputs, as can be seen in
Figure 5 and Figure 6. These components should be placed
close to the ADC because the input pins of the ADC is the
most sensitive part of the system and this is the last opportunity to filter the input. Table 3 gives component values for
Figure 5 to convert individual input signals to a range of 2.5V
±
2.0V at each of the input pins of the ADC12010.
TABLE 3. Resistor Values for Circuit of Figure 5
SIGNAL
RANGE
R1 R2 R3 R4 R5, R6
0 - 0.5V 392Ω 1540Ω 102Ω 11 5Ω 1000Ω
0 - 1.0V 634Ω 1470Ω 2490Ω 1050Ω 499Ω
±
0.25V 499Ω 499Ω 499Ω 499Ω 1000Ω
±
0.5V 100Ω 200Ω 100Ω 200Ω 499Ω
2.1 CLK
The CLK signal controls the timing of the sampling process.
Drive the clock input with a stable, low jitter clock signal in
the range of 100 kHz to 15 MHz with rise and fall times of
less than 3ns. The trace carrying the clock signal should be
as short as possible and should not cross any other signal
line, analog or digital, not even at 90˚.
If the CLK is interrupted, or its frequency too low, the charge
on internal capacitors can dissipate to the point where the
accuracy of the output data will degrade. This is what limits
the lowest sample rate to 100 kSPS.
The duty cycle of the clock signal can affect the performance
of the A/D Converter. Because achieving a precise duty
cycle is difficult, the ADC12010 is designed to maintain
performance over a range of duty cycles. While it is specified
and performance is guaranteed with a 50% clock duty cycle,
performance is typically maintained over a clock duty cycle
range of 20% to 80%.
The clock line should be series terminated at the source end
in the characteristic impedance of that line if the clock line is
longer than
where tris the rise time of the clock signal and tPRis the
propagation rate along the line. For a Board of FR-4 material, t
is typically about 150 ps/inch, or 60 ps/cm. This
PR
resistor should be as close to the source as possible.
It might also be necessary to AC terminate the ADC end of
the clock line with a series RC to ground such that the
resistor value equals the characteristic impedance of the
clock line and the capacitor value is
where tPRis again the propagation rate down the clock line,
L is the length of the line in inches and Z
is the character-
O
istic impedance of the clock line. A.C. termination should be
near the ADC clock pin but beyond that pin as seen from the
clock source.
Take care to maintain a constant clock line impedance
throughout the length of the line. Refer to Application Note
AN-905 or AN-1113 for information on setting and determining characteristic impedance.
www.national.com17
Applications Information (Continued)
2.2 OE
The OE pin, when high, puts the output pins into a high
ADC12010
impedance state. When this pin is low the outputs are in the
active state. The ADC12010 will continue to convert whether
this pin is high or low, but the output can not be read while
the OE pin is high.
The OE pin should NOT be used to multiplex devices together to drive a common bus as this will result in excessive
capacitance on the data output pins, reducing SNR and
SINAD performance of the converter. See Section 3.0.
2.3 PD
The PD pin, when high, holds the ADC12010 in a powerdown mode to conserve power when the converter is not
being used. The power consumption is 25 mW and the
output data pins are undefined in this mode. The data in the
pipeline is corrupted while in the power down mode.
The Power Down Mode Exit Cycle time is determined by the
value of the capacitors on pins 30, 31 and 32. These capacitors loose their charge in the Power Down mode and must
be charged by on-chip circuitry before conversions can be
accurate.
3.0 OUTPUTS
The ADC12010 has 12 TTL/CMOS compatible Data Output
pins. Valid offset binary data is present at these outputs while
the OE and PD pins are low. While the t
time provides
OD
information about output timing, a simple way to capture a
valid output is to latch the data on the falling edge of the
conversion clock (pin 10).
Be very careful when driving a high capacitance bus. The
more capacitance the output drivers must charge for each
conversion, the more instantaneous digital current flows
through V
and DR GND. These large charging current
DR
spikes can cause on-chip noise that can couple into the
analog circuitry, degrading dynamic performance. Adequate
power supply bypassing and careful attention to the ground
plane will reduce this problem. Additionally, bus capacitance
beyond the specified 25 pF/pin will cause t
to increase,
OD
making it difficult to properly latch the ADC output data. The
result could be an apparent reduction in dynamic performance.
To minimize noise due to output switching, minimize the load
currents at the digital outputs. This can be done by connecting buffers (74ACQ541, for example) between the ADC outputs and any other circuitry. Only one driven input should be
connected to each output pin. Additionally, inserting series
resistors of 47Ω to 100Ω at the digital outputs, close to the
ADC pins, will isolate the outputs from trace and other circuit
capacitances and limit the output currents, which could otherwise result in performance degradation. See Figure 4.
While the ADC12010 will operate with V
1.8V, t
timing when using reduced V
increases with reduced VDR. Be careful of external
OD
.
DR
voltages down to
DR
FIGURE 4. Simple Application Circuit with Single-Ended to Differential Buffer
www.national.com 18
20051613
Applications Information (Continued)
FIGURE 5. Differential Drive Circuit of Figure 4
ADC12010
20051614
FIGURE 6. Driving the Signal Inputs with a Transformer
20051615
www.national.com19
Applications Information (Continued)
4.0 POWER SUPPLY CONSIDERATIONS
The power supply pins should be bypassed with a 10 µF
ADC12010
capacitor and with a 0.1 µF ceramic chip capacitor within a
centimeter of each power pin. Leadless chip capacitors are
preferred because they have low series inductance.
As is the case with all high-speed converters, the ADC12010
is sensitive to power supply noise. Accordingly, the noise on
the analog supply pin should be kept below 100 mV
No pin should ever have a voltage on it that is in excess of
the supply voltages, not even on a transient basis. Be especially careful of this during turn on and turn off of power.
The V
be operated from a supply in the range of 2.35V to V
(nominal 5V). This can simplify interfacing to 3V devices and
systems. DO NOT operate the V
than V
5.0 LAYOUT AND GROUNDING
Proper grounding and proper routing of all signals are essential to ensure accurate conversion. Maintaining separate
analog and digital areas of the board, with the ADC12010
between these areas, is required to achieve specified performance.
The ground return for the data outputs (DR GND) carries the
ground current for the output drivers. The output current can
exhibit high transients that could add noise to the conversion
process. To prevent this from happening, the DR GND pins
should NOT be connected to system ground in close proximity to any of the ADC12010’s other ground pins.
Capacitive coupling between the typically noisy digital circuitry and the sensitive analog circuitry can lead to poor
performance. The solution is to keep the analog circuitry
separated from the digital circuitry, and to keep the clock line
as short as possible.
pin provides power for the output drivers and may
DR
pin at a voltage higher
.
D
DR
P-P
Digital circuits create substantial supply and ground current
transients. The logic noise thus generated could have significant impact upon system noise performance. The best
logic family to use in systems with A/D converters is one
which employs non-saturating transistor designs, or has low
noise characteristics, such as the 74LS, 74HC(T) and
74AC(T)Q families. The worst noise generators are logic
families that draw the largest supply current transients during clock or signal edges, like the 74F and the 74AC(T)
.
families.
The effects of the noise generated from the ADC output
switching can be minimized through the use of 47Ω to 100Ω
resistors in series with each data output line. Locate these
resistors as close to the ADC output pins as possible.
D
Since digital switching transients are composed largely of
high frequency components, total ground plane copper
weight will have little effect upon the logic-generated noise.
This is because of the skin effect. Total surface area is more
important than is total ground plane volume.
Generally, analog and digital lines should cross each other at
90˚ to avoid crosstalk. To maximize accuracy in high speed,
high resolution systems, however, avoid crossing analog and
digital lines altogether. It is important to keep clock lines as
short as possible and isolated from ALL other lines, including
other digital lines. Even the generally accepted 90˚ crossing
should be avoided with the clock line as even a little coupling
can cause problems at high frequencies. This is because
other lines can introduce jitter into the clock line, which can
lead to degradation of SNR. Also, the high speed clock can
introduce noise into the analog chain.
Best performance at high frequencies and at high resolution
is obtained with a straight signal path. That is, the signal path
through all components should form a straight line wherever
possible.
FIGURE 7. Example of a Suitable Layout
www.national.com 20
20051616
Applications Information (Continued)
Be especially careful with the layout of inductors. Mutual
inductance can change the characteristics of the circuit in
which they are used. Inductors should not be placed side by
side, even with just a small part of their bodies beside each
other.
The analog input should be isolated from noisy signal traces
to avoid coupling of spurious signals into the input. Any
external component (e.g., a filter capacitor) connected between the converter’s input pins and ground or to the reference input pin and ground should be connected to a very
clean point in the analog ground plane.
Figure 7 gives an example of a suitable layout. All analog
circuitry (input amplifiers, filters, reference components, etc.)
should be placed over the analog ground plane. All digital
circuitry and I/O lines should be placed in the digital area of
the board. Furthermore, all components in the reference
circuitry and the input signal chain that are connected to
ground should be connected together with short traces and
enter the ground plane at a single point. All ground connections should have a low inductance path to ground.
We do not recommend a split ground plane. Rather, using
wide power traces with analog and digital power traces
well-separated from each other, and keeping analog and
digital signal lines well-separated from each other will minimize noise while keeping EMI to tolerable levels.
6.0 DYNAMIC PERFORMANCE
To achieve the best dynamic performance, the clock source
driving the CLK input must be free of jitter. Isolate the ADC
clock from any digital circuitry with buffers, as with the clock
tree shown in Figure 8.
As mentioned in Section 5.0, it is good practice to keep the
ADC clock line as short as possible and to keep it well away
from any other signals. Other signals can introduce jitter into
the clock signal, which can lead to reduced SNR performance, and the clock can introduce noise into other lines.
Even lines with 90˚ crossings have capacitive coupling, so
try to avoid even these 90˚ crossings of the clock line.
20051617
FIGURE 8. Isolating the ADC Clock from other Circuitry
with a Clock Tree
7.0 COMMON APPLICATION PITFALLS Driving the inputs (analog or digital) beyond the power
supply rails. For proper operation, all inputs should not go
more than 100 mV beyond the supply rails (more than
100 mV below the ground pins or 100 mV above the supply
pins). Exceeding these limits on even a transient basis may
cause faulty or erratic operation. It is not uncommon for high
speed digital components (e.g., 74F and 74AC devices) to
exhibit overshoot or undershoot that goes above the power
supply or below ground. A resistor of about 50Ω to 100Ω in
series with any offending digital input, close to the signal
source, will eliminate the problem.
Do not allow input voltages to exceed the supply voltage,
even on a transient basis. Not even during power up or
power down.
Be careful not to overdrive the inputs of the ADC12010 with
a device that is powered from supplies outside the range of
the ADC12010 supply. Such practice may lead to conversion
inaccuracies and even to device damage.
Attempting to drive a high capacitance digital data bus.
The more capacitance the output drivers must charge for
each conversion, the more instantaneous digital current
flows through V
and DR GND. These large charging cur-
DR
rent spikes can couple into the analog circuitry, degrading
dynamic performance. Adequate bypassing and maintaining
separate analog and digital areas on the pc board will reduce
this problem.
Additionally, bus capacitance beyond the specified 25 pF/pin
will cause t
to increase, making it difficult to properly latch
OD
the ADC output data. The result could, again, be an apparent
reduction in dynamic performance.
The digital data outputs should be buffered (with 74ACQ541,
for example). Dynamic performance can also be improved
by adding series resistors at each digital output, close to the
ADC12010, which reduces the energy coupled back into the
converter output pins by limiting the output current. A reasonable value for these resistors is 47Ω to 100Ω.
Using an inadequate amplifier to drive the analog input.
As explained in Section 1.3, the capacitance seen at the
input alternates between 8 pF and 7 pF, depending upon the
phase of the clock. This dynamic load is more difficult to
drive than is a fixed capacitance.
If the amplifier exhibits overshoot, ringing, or any evidence of
instability, even at a very low level, it will degrade performance. A small series resistor and shunt capacitor at each
amplifier output (as shown in Figure 5) will improve performance. The LMH6702 and the LMH6628 have been successfully used to drive the analog inputs of the ADC12010.
Also, it is important that the signals at the two inputs have
exactly the same amplitude and be exactly 180
o
out of phase
with each other. Board layout, especially equality of the
length of the two traces to the input pins, will affect the
effective phase between these two signals. Remember that
an operational amplifier operated in the non-inverting configuration will exhibit more time delay than will the same
device operating in the inverting configuration.
Operating with the reference pins outside of the specified range. As mentioned in Section 1.2, V
should be in
REF
the range of
1.0V ≤ V
REF
≤ 2.4V
Operating outside of these limits could lead to performance
degradation.
Using a clock source with excessive jitter, using excessively long clock signal trace, or having other signals
coupled to the clock signal trace. This will cause the
sampling interval to vary, causing excessive output noise
and a reduction in SNR and SINAD performance.
ADC12010
www.national.com21
Physical Dimensions inches (millimeters) unless otherwise noted
32-Lead LQFP Package
Ordering Number ADC12010CIVY
NS Package Number VBE32A
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NATIONAL’S PRODUCTS ARE NOT AUTHORIZED FOR USE AS CRITICAL COMPONENTS IN LIFE SUPPORT
DEVICES OR SYSTEMS WITHOUT THE EXPRESS WRITTEN APPROVAL OF THE PRESIDENT AND GENERAL
COUNSEL OF NATIONAL SEMICONDUCTOR CORPORATION. As used herein:
1. Life support devices or systems are devices or
systems which, (a) are intended for surgical implant
ADC12010 12-Bit, 10 MSPS, 160 mW A/D Converter with Internal Sample-and-Hold
into the body, or (b) support or sustain life, and
whose failure to perform when properly used in
accordance with instructions for use provided in the
2. A critical component is any component of a life
support device or system whose failure to perform
can be reasonably expected to cause the failure of
the life support device or system, or to affect its
safety or effectiveness.
labeling, can be reasonably expected to result in a
significant injury to the user.
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Support Center
Email: new.feedback@nsc.com
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