Rainbow Electronics ADC11DL066 User Manual

ADC11DL066
Dual 11-Bit, 66 MSPS, 450 MHz Input Bandwidth A/D
Converter w/Internal Reference

ADC11DL066 Dual 11-Bit, 66 MSPS, 450 MHz Input Bandwidth A/D Converter w/Internal Reference

March 2004

General Description

The ADC11DL066 is a dual, low power monolithic CMOS
analog-to-digital converter capable of converting analog in­put signals into 11-bit digital words at 66 Megasamples per
second (MSPS), minimum. This converter uses a differential,
pipeline architecture with digital error correction and an on­chip sample-and-hold circuit to minimize die size and power
consumption while providing excellent dynamic performance
and a 450 MHz Full Power Bandwidth. Operating on a single

3.3V power supply, theADC11DL066 achieves 10.3 effective
bits and consumes just 686 mW at 66 MSPS, including the
reference current. The Power Down feature reduces power
consumption to 75 mW.

The differential inputs provide a full scale differential input
swing equal to 2 times V
ended input. Full use of the differential input is recom­mended for optimum performance. The digital outputs from
the two ADCs are available on separate 11-bit buses with an
output data format choice of offset binary or two’s comple­ment.

To ease interfacing to lower voltage systems, the digital
output driver power pins of the ADC11DL066 can be con­nected to a separate supply voltage in the range of 2.4V to
the digital supply voltage.

This device is available in the 64-lead TQFP package and
will operate over the industrial temperature range of −40˚C to
+85˚C. An evaluation board is available to ease the evalua­tion process.

with the possibility of a single-

REF

Features

n Single +3.3V supply operation
n Internal sample-and-hold
n Outputs 2.4V to 3.3V compatible
n Power down mode
n On-chip reference

Key Specifications

n Resolution 11 Bits
n DNL
n SNR (f
n SFDR (f
n Data Latency 6 Clock Cycles
n Power Consumption

— Operating 686 mW (typ)
— Power Down 75 mW (typ)

= 10 MHz) 64 dB (typ)

IN

= 10 MHz) 80 dB (typ)

IN

±

0.25 LSB (typ)

Applications

n Ultrasound and Imaging
n Instrumentation
n Communications Receivers
n Sonar/Radar
n xDSL
n Cable Modems
n DSP Front Ends

Connection Diagram

20077301

20040326

TRI-STATE®is a registered trademark of National Semiconductor Corporation.

© 2004 National Semiconductor Corporation DS200773 www.national.com

Ordering Information

ADC11DL066

Block Diagram

Industrial (−40˚C ≤ TA≤ +85˚C) Package

ADC11DL066CIVS 64 Pin TQFP

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Pin Descriptions and Equivalent Circuits

Pin No. Symbol Equivalent Circuit Description

ANALOG I/O

15

2

16

1

7V

A+

V

IN

B+

V

IN

A−

V

IN

B−

V

IN

REF

11 INT/EXT REF

Differential analog Inputs. With a 1.0V reference voltage the
differential full-scale input signal level is 2.0 V
input pin voltage centered on a common mode voltage, V
The negative input pins may be connected to V
single-ended operation, but a differential input signal is
required for best performance.

Reference input. This pin should be bypassed to AGND with
a 0.1 µF capacitor when an external reference is used. V
is 1.0V nominal and should be between 0.8V to 1.5V.

Reference source select pin. With a logic low at this pin the
internal 1.0V reference is selected and the V
not be driven. With a logic high on this pin an external
reference voltage should be applied to V

REF

input pin 7.

REF

P-P

CM

pin need

with each

for

CM

REF

ADC11DL066

.

13

5

14

4

12

6

DIGITAL I/O

60 CLK

22
41

59 PD

21 OF

V

RP

V

RP

V

RM

V

RM

V

RN

V

RN

OEA
OEB

A

B

A

B

A

B

These pins are high impedance reference bypass pins.
Bypass per Section 1.2. DO NOT LOAD these pins.

Digital clock input. The range of frequencies for this input is
as specified in the electrical tables with guaranteed
performance at 66 MHz. The input is sampled on the rising
edge of this input.

OEA and OEB are the output enable pins that, when low,
holds their respective data output pins in the active state.
When either of these pins is high, the corresponding outputs
are in a high impedance state.

PD is the Power Down input pin. When high, this input puts
the converter into the power down mode. When this pin is
low, the converter is in the active mode.

Output Format pin. A logic low on this pin causes output
data to be in offset binary format. A logic high on this pin
causes the output data to be in 2’s complement format.

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Pin Descriptions and Equivalent Circuits (Continued)

Pin No. Symbol Equivalent Circuit Description

ADC11DL066

25–29
34–39

43–47
52–57

ANALOG POWER

9, 18, 19,

62, 63

3, 8, 10, 17,

20, 61, 64

DIGITAL POWER

33, 48 V

32, 49 DGND The ground return for the digital supply.

24, 42 DGND

30, 51 V

23, 31, 40,

50, 58

DA0–DA10

Digital data output pins that make up the 11-bit conversion
results of their respective converters. DA0 and DB0 are the
LSBs, while DA10 and DB10 are the MSBs of the output
words. Output levels are TTL/CMOS compatible.

DB0–DB10

Positive analog supply pins. These pins should be connected

V

A

to a quiet +3.3V source and bypassed to AGND with 0.1 µF
capacitors located within 1 cm of these power pins, and with
a 10 µF capacitor.

AGND The ground return for the analog supply.

Positive digital supply pin. This pin should be connected to

D

the same quiet +3.3V source as is V
DGND with a 0.1 µF capacitor located within 1 cm of the
power pin and with a 10 µF capacitor.

These two pins are grounded internally and may be
grounded or left unconnected.

Positive digital supply pin for the ADC11DL066’s output
drivers. This pin should be connected to a voltage source of
+2.4V to V

DR

capacitor. If the supply for this pin is different from the
supply used for V

and be bypassed to DR GND with a 0.1 µF

D

and VD, it should also be bypassed with

A

a 10 µF tantalum capacitor. V
voltage on V

. All bypass capacitors should be located

D

within 1 cm of the supply pin.

The ground return for the digital supply for the
ADC11DL066’s output drivers. These pins should be

DR GND

connected to the system digital ground, but not be
connected in close proximity to the ADC11DL066’s DGND or
AGND pins. See Section 5 (Layout and Grounding) for more
details.

and be bypassed to

A

should never exceed the

DR

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ADC11DL066

Absolute Maximum Ratings (Notes 1,

2)

If Military/Aerospace specified devices are required,
please contact the National Semiconductor Sales Office/
Distributors for availability and specifications.

or V

A

+0.3V)

±

25 mA

±

50 mA

4.2V

V

A,VD,VDR

|V

| ≤ 100 mV

A–VD

Voltage on Any Input or Output Pin −0.3V to (V

Input Current at Any Pin (Note 3)

Package Input Current (Note 3)

Package Dissipation at T

= 25˚C See (Note 4)

A

D

Operating Ratings (Notes 1, 2)

Operating Temperature −40˚C ≤ T

Supply Voltage (V

Output Driver Supply (V

V

Input 0.8V to 1.5V

REF

CLK, PD, OE

Analog Input Pins 0V to (V

V

CM

|AGND–DGND| ≤100mV

) +3.0V to +3.6V

A,VD

) +2.4V to V

DR

−0.05V to (VD+ 0.05V)

ESD Susceptibility

Human Body Model (Note 5) 2500V

Machine Model (Note 5) 250V

Soldering Temperature,

Infrared, 10 sec. (Note 6) 235˚C

Storage Temperature −65˚C to +150˚C

Converter Electrical Characteristics

Unless otherwise specified, the following specifications apply for AGND = DGND = DR GND = 0V, VA=VD= +3.3V,

= +2.5V, PD = 0V, INT/EXT REF pin = +3.3V, V

V

DR

Boldface limits apply for TJ=T

MIN

to T

: all other limits TJ= 25˚C (Notes 7, 8, 9)

MAX

Symbol Parameter Conditions

STATIC CONVERTER CHARACTERISTICS

Resolution with No Missing Codes 11 Bits (min)

INL Integral Non Linearity (Note 11)

DNL Differential Non Linearity

PGE Positive Gain Error 0.4

NGE Negative Gain Error −0.1

TC GE Gain Error Tempco −40˚C ≤ T

V

TC
V

OFF

OFF

Offset Error (VIN+=VIN−) −0.18

Offset Error Tempco −40˚C ≤ TA≤ +85˚C 0.1 ppm/˚C

Under Range Output Code 0 0

Over Range Output Code 2047 2047

REFERENCE AND ANALOG INPUT CHARACTERISTICS

V

CM

C

IN

V

REF

Common Mode Input Voltage 1.0

VINInput Capacitance (each pin to
GND)

Reference Voltage (Note 13) 1.00

Reference Input Resistance 100 MΩ

= +1.0V, f

REF

A

VIN= 2.5 Vdc
+ 0.7 V

rms

= 66 MHz, fIN= 10 MHz, tr=tf= 2 ns, CL= 15 pF/pin.

CLK

Typical

(Note 10)

±

0.5

±

0.25

Limits

(Note 10)

±

1.6 LSB (max)

±

0.68 LSB (max)

±

4 %FS (max)

±

3.6 %FS (max)

≤ +85˚C 0.5 ppm/˚C

+1.3

-1.6

0.5 V (min)

1.8 V (max)

(CLK LOW) 8 pF

(CLK HIGH) 7 pF

0.8 V (min)

1.5 V (max)

≤ +85˚C

A

− 0.5V)

A

0.5V to 1.8V

Units

(Limits)

%FS (max)

%FS (min)

D

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Converter Electrical Characteristics (Continued)

Unless otherwise specified, the following specifications apply for AGND = DGND = DR GND = 0V, VA=VD= +3.3V,

= +2.5V, PD = 0V, INT/EXT REF pin = +3.3V, V

V

DR

Boldface limits apply for TJ=T

ADC11DL066

MIN

to T

: all other limits TJ= 25˚C (Notes 7, 8, 9)

MAX

Symbol Parameter Conditions

DYNAMIC CONVERTER CHARACTERISTICS

FPBW Full Power Bandwidth 0 dBFS Input, Output at −3 dB 450 MHz

SNR Signal-to-Noise Ratio

SINAD Signal-to-Noise and Distortion

ENOB Effective Number of Bits

THD Total Harmonic Distortion

H2 Second Harmonic

H3 Third Harmonic

SFDR Spurious Free Dynamic Range

INTER-CHANNEL CHARACTERISTICS

Channel — Channel Offset Match

Channel — Channel Channel gain
Match

Crosstalk

= +1.0V, f

REF

= 1 MHz, VIN= −0.5 dBFS 64 dB

f

IN

f

= 10 MHz, VIN= −0.5 dBFS 64 62 dB (min)

IN

f

= 33 MHz, VIN= −0.5 dBFS 62 dB

IN

= 1 MHz, VIN= −0.5 dBFS 63 dB

f

IN

f

= 10 MHz, VIN= −0.5 dBFS 63 62 dB (min)

IN

f

= 33 MHz, VIN= −0.5 dBFS 62 dB

IN

= 1 MHz, VIN= −0.5 dBFS 10.3 Bits

f

IN

f

= 10 MHz, VIN= −0,5 dBFS 10.3 10.0 Bits (min)

IN

f

= 33 MHz, VIN= −0,5 dBFS 10.1 Bits

IN

= 1 MHz, VIN= −0.5 dBFS −78 dB

f

IN

f

= 10 MHz, VIN= −0.5 dBFS −78 -69.7 dB (max)

IN

f

= 33 MHz, VIN= −0.5 dBFS −78 dB

IN

= 1 MHz, VIN= −0.5 dBFS −84 dB

f

IN

f

= 10 MHz, VIN= −0.5 dBFS −84 −73.5 dB (max)

IN

f

= 33 MHz, VIN= −0.5 dBFS −84 dB

IN

= 1 MHz, VIN= −0.5 dBFS −84 dB

f

IN

f

= 10 MHz, VIN= −0.5 dBFS −84 −73.3 dB (max)

IN

f

= 33 MHz, VIN= −0.5 dBFS −83 dB

IN

= 1 MHz, VIN= −0.5 dBFS 80 dB

f

IN

f

= 10 MHz, VIN= −0.5 dBFS 80 73.5 dB (min)

IN

f

= 33 MHz, VIN= −0.5 dBFS 74 dB

IN

10 MHz Tested, Channel;
20 MHz Other Channel

10 MHz Tested, Channel;
195 MHz Other Channel

= 66 MHz, fIN= 10 MHz, tr=tf= 2 ns, CL= 15 pF/pin.

CLK

Typical

(Note 10)

±

0.03 %FS

±

0.1 %FS

Limits

(Note 10)

80 dB

63 dB

Units

(Limits)

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DC and Logic Electrical Characteristics

Unless otherwise specified, the following specifications apply for AGND = DGND = DR GND = 0V, VA=VD= +3.3V, VDR=
+2.5V, PD = 0V, INT/EXT REF pin = 3.3V, V

face limits apply for TJ=T

MIN

to T

: all other limits TJ= 25˚C (Notes 7, 8, 9)

MAX

REF

= +1.0V, f

Symbol Parameter Conditions

CLK, PD, OE DIGITAL INPUT CHARACTERISTICS

V

V

I

I

C

IN(1)

IN(0)

IN(1)

IN(0)

IN

Logical “1” Input Voltage VD= 3.6V 2.0 V (min)

Logical “0” Input Voltage VD= 3.0V 1.0 V (max)

Logical “1” Input Current VIN= 3.3V 10 µA

Logical “0” Input Current VIN= 0V −10 µA

Digital Input Capacitance 5 pF

D0–D11 DIGITAL OUTPUT CHARACTERISTICS

V

V

I

OZ

+I

−I

C

OUT(1)

OUT(0)

SC

SC

OUT

Logical “1” Output Voltage I

Logical “0” Output Voltage I

TRI-STATE®Output Current

Output Short Circuit Source
Current

Output Short Circuit Sink Current V

= −0.5 mA

OUT

= 1.6 mA, VDR=3V 0.4 V (max)

OUT

= 2.5V or 3.3V 100 nA

V

OUT

V

= 0V −100 nA

OUT

= 0V −20 mA

V

OUT

OUT=VDR

Digital Output Capacitance 5 pF

POWER SUPPLY CHARACTERISTICS

I

A

I

D

I

DR

Analog Supply Current

Digital Supply Current

Digital Output Supply Current

Total Power Consumption

PSRR1 Power Supply Rejection Ratio

PSRR2 Power Supply Rejection Ratio

PD Pin = DGND, V
PD Pin = V

PD Pin = DGND
PD Pin = V

PD Pin = DGND, C
PD Pin = V

PD Pin = DGND, C
PD Pin = V

Rejection of Full-Scale Error with
VA= 3.0V vs. 3.6V

Rejection of Power Supply Noise with
10 MHz, 500 mV riding on V

= 66 MHz, fIN= 10 MHz, tr=tf= 2 ns, CL= 15 pF/pin. Bold-

CLK

Typical

(Note 10)

= 2.5V 2.3 V (min)

V

DR

V

=3V 2.7 V (min)

DR

Limits

(Note 10)

20 mA

DR

DR,fCLK

DR,fCLK

DR,fCLK

= 1.0V

REF

=0

= 0 pF (Note 14)

L

=0

= 0 pF (Note 15)

L

=0

197

14

11

8.7

<

0

686

75

237 mA (max)

35 mA (max)

2

898 mW (max)

56 dB

A

44 dB

(Limits)

ADC11DL066

Units

mA

mA

mA
mA

mW

AC Electrical Characteristics

Unless otherwise specified, the following specifications apply for AGND = DGND = DR GND = 0V, VA=VD= +3.3V, VDR=
+2.5V, PD = 0V, INT/EXT REF pin = 3.3V, V

face limits apply for TJ=T

MIN

to T

: all other limits TJ= 25˚C (Notes 7, 8, 9, 12)

MAX

REF

= +1.0V, f

Symbol Parameter Conditions

1

f

CLK

f

CLK

t

CH

t

CL

t

CONV

t

OD

t

AD

Maximum Clock Frequency 75 66 MHz (min)

2

Minimum Clock Frequency 15 MHz

Clock High Time 6.6 ns (min)

Clock Low Time 6.6 ns (min)

Conversion Latency 6

= 2.5V

V

Data Output Delay after Rising
CLK Edge

DR

V

= 3.3V

DR

Aperture Delay 2 ns

= 66 MHz, fIN= 10 MHz, tr=tf= 3 ns, CL= 15 pF/pin. Bold-

CLK

Typical

(Note 10)

Limits

(Note 10)

rising 6.6 9.0 ns (max)

falling 5.0 8.5 ns (max)

rising 5.4 9.0 ns (max)

falling 5.6 9.0 ns (max)

(Limits)

Cycles

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Units

Clock