Rainbow Electronics ADC1175-50 User Manual

ADC1175-50
8-Bit, 50 MSPS, 125 mW A/D Converter

General Description

The ADC1175-50 is a low power, 50 MSPS analog-to-digital
converter that digitizes signals to 8 bits while consuming just
125 mW (typ). The ADC1175-50 uses a unique architecture
that achieves 6.8 Effective Bits at 25 MHz input and 50 MHz
clock frequency. Output formatting is straight binary coding.

The excellent DC and AC characteristics of this device,
together with its low power consumption and +5V single
supply operation, make it ideally suited for many video and
imaging applications, including use in portable equipment.
Furthermore, the ADC1175-50 is resistant to latch-up and
the outputs are short-circuit proof. The top and bottom of the
ADC1175-50’sreference ladder is available for connections,
enabling a wide range of input possibilities. The low input
capacitance (7 pF, typical) makes this device easier to drive
than conventional flash converters and the power down
mode reduces power consumption to less than 5 mW.

TheADC1175-50 is offered in SOIC (EIAJ), TSSOP and LLP
(a molded lead frame-based chip-scale package.) It is de­signed to operate over the commercial temperature range of

−20˚C to +75˚C.

Features

n Internal Track-and-Hold function
n Single +5V operation
n Internal reference bias resistors

n Industry standard pinout
n Power-down mode (

Key Specifications

n Resolution 8 Bits
n Maximum Sampling Frequency 50 MSPS (min)
n THD 54 dB (typ)
n DNL 0.7 LSB (typ)
n ENOB
n Guaranteed No Missing Codes
n Differential Phase 0.5˚ (typ)
n Differential Gain 1.0% (typ)
n Power Consumption 125 mW (typ), 190 mW (max)

@

fIN= 25 MHz 6.8 Bits (typ)

(Excluding Reference Current)

Applications

n Digital Still Cameras
n CCD Imaging
n Electro-Optics
n Medical Imaging
n Communications
n Video Digitization
n Digital Television
n Multimedia

<

5 mW)

ADC1175-50 8-Bit, 50 MSPS, 125 mW A/D Converter

December 2000

Connection Diagram

24-pin SOLC and TSSOP

Top View

DS100896-1

24-pin LLP (CSP)

DS100896-34

Bottom View

© 2001 National Semiconductor Corporation DS100896 www.national.com

Ordering Information

ADC1175-50CIJM SOIC (EIAJ)
ADC1175-50CIJMX SOIC (EIAJ) (tape and reel)

ADC1175-50

ADC1175-50CIMT TSSOP
ADC1175-50CIMTX TSSOP (tape and reel)
ADC1175-50CILQ LLP (tape and reel - 1, 000 units)
ADC1175-50CILQX LLP (tape and reel - 4, 500 units)

Block Diagram

Pin Descriptions and Equivalent Circuits

Pin
No.

19

(17)

16

(14)

Symbol Equivalent Circuit Description

V

IN

V

RTS

DS100896-2

(LLP pins in parentheses)

Analog signal input. Conversion range is VRTto

.

V

RB

Reference Top Bias with internal pull up resistor.
Short this pin to V
ladder.

to self-bias the reference

RT

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Pin Descriptions and Equivalent Circuits (LLP pins in parentheses) (Continued)

ADC1175-50

Pin
No.

17

(15)

23

(21)

22

(20)

Symbol Equivalent Circuit Description

Analog input that is the high (top) side of the
reference ladder of the ADC. Nominal range is 1.0V

V

RT

to AV

, optimized value of 2.6V. Voltages on V

DD

and VRBinputs define the VINconversion range.
Bypass well. See Section 2.0 for more information.

Analog input that is the low (bottom) side of the
reference ladder of the ADC. Nominal range is 0.0V

V

RB

to 4.0V, with optimized value of 0.6V. Voltage on

and VRBinputs define the VINconversion

V

RT

range. Bypass well. See Section 2.0 for more
information.

Reference Bottom Bias with internal pull down

V

RBS

resistor. Short to V
ladder. Bypass well if not grounded. See Section

to self-bias the reference

RB

2.0 for more information.

RT

1

(23)

12

(10)

3 thru

10

(1 thru

8)

PD

CLK

D0–D7

CMOS/TTL compatible Digital input that, when high,
puts the ADC1175-50 into a power-down mode
where total power consumption is typically less than
5 mW. With this pin low, the device is in the normal
operating mode.

CMOS/TTL compatible digital clock input. VINis
sampled on the falling edge of CLK input.

Conversion data digital Output pins. D0 is the LSB,
D7 is the MSB. Valid data is output just after the
rising edge of the CLK input. These pins are in a
high impedance mode when the PD pin is low.

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Pin Descriptions and Equivalent Circuits (LLP pins in parentheses) (Continued)

Pin
No.

ADC1175-50

11,
13, 14
(9, 11,

12)

2, 24

(22,

24)

15, 18

(13,

16)

20, 21

(18,

19)

Symbol Equivalent Circuit Description

Positive digital supply pin. Connect to a clean, quiet

and DVDDshould have

DD

DV

voltage source of +5V. AV

DD

a common source and be separately bypassed with
a 10 µF capacitor and a 0.1 µF ceramic chip
capacitor. See Section 4.0 for more information.

The ground return for the digital supply. AVSSand

should be connected together close to the

DV

SS

DV

SS

ADC1175-50.
Positive analog supply pin. Connect to a clean,

quiet voltage source of +5V. AV

AV

DD

have a common source and be separately bypassed
with a 10 µF capacitor and a 0.1 µF ceramic chip
capacitor. See Section 4.0 for more information.

The ground return for the analog supply. AVSSand

should be connected together close to the

AV

SS

DV

SS

ADC1175-50 package.

and DVDDshould

DD

www.national.com 4

ADC1175-50

Absolute Maximum Ratings (Notes 1, 2)

If Military/Aerospace specified devices are required,
please contact the National Semiconductor Sales Office/
Distributors for availability and specifications.

Supply Voltage (AV
Voltage on Any Input or Output Pin −0.3V to +6.5V
Reference Voltage (V
CLK, PD Voltage Range −0.5 to (AVDD+0.5V)
Digital Output Voltage (V
Input Current at Any Pin (Note 3)
Package Input Current (Note 3)
Power Dissipation at T

,DVDD) 6.5V

DD

)AV

RT,VRB

OH,VOL

)V

DD

DD

±
±

= 25˚C See (Note 4)

A

to V

SS

to V

SS

25 mA
50 mA

ESD Susceptibility (Note 5)

Human Body Model 2000V
Machine Model 250V

Soldering Temperature, Infrared,

(10 sec.) (Note 6) 235˚C
Storage Temperature −65˚C to +150˚C
Short Circuit Duration

(Single High Output to Ground) 1 Second

Operating Ratings (Notes 1, 2)

Operating Temperature Range −20˚C ≤ T
Supply Voltage (AV

−DV

AV

DD

DD

Ground Difference |DV
Upper Reference Voltage (V

,DVDD) +4.75V to +5.25V

DD

–AVSS| 0V to 100 mV

SS

) 1.0V to V

RT

≤ +75˚C

A

<

Lower Reference Voltage (VRB) 0V to 4.0V

Voltage Range VRBto V

V

IN

Converter Electrical Characteristics

The following specifications apply for AVDD=DVDD= +5.0 VDC, PD = 0V, VRT= +2.6V, VRB= 0.6V, CL= 20 pF, f
50 MHz at 50% duty cycle. Boldface limits apply for T

A=TMIN

Symbol Parameter Conditions

to T

; all other limits TA= 25˚C (Notes 7, 8).

MAX

Typical

(Note 9)

Limits

(Note 9)

DC ACCURACY

INL Integral Non Linearity Error V
DNL Differential Non-Linearity

Resolution for No Missing
Codes

E

OT

E

OB

Top Offset Voltage −12 mV
Bottom Offset Voltage +10 mV

= 0.6V to 2.6V

IN

V

= 0.6V to 2.6V +0.7 +1.75 LSB (max)

IN

±

0.8

−0.7 −1.0 LSB (min)

±

1.95 LSB (max)

8 Bits

VIDEO ACCURACY

DP Differential Phase Error f
DG Differential Gain Error f

= 4.43 MHz Modulated Ramp 0.5 deg

IN

= 4.43 MHz Modulated Ramp 1.0 %

IN

ANALOG INPUT AND REFERENCE CHARACTERISTICS

V

V

IN

C

IN

R

IN

Input Range 2.0

VINInput Capacitance
RINInput Resistance

V

= 1.5V

IN

+0.7 Vrms

(CLK LOW) 4 pF
(CLK HIGH) 7 pF

>

1MΩ

RB

V

RT

BW Full Power Bandwidth 120 MHz
R

R
R

I

V

V

RT

REF

RB

REF

RT

RB

Top Reference Resistor 320 Ω
Reference Ladder Resistance VRTto V

RB

270

200
350

Bottom Reference Resistor 80 Ω

5.4 mA (min)

10.8 mA (max)

6.1 mA (min)

12.3 mA (max)

0.55

0.70

Reference Ladder Current

Reference Top Self Bias
Voltage

Reference Bottom Self Bias
Voltage

V

RT=VRTS,VRB=VRBS

V

RT=VRTS,VRB

=AV

VRTConnected to V
Connected to V

RBS

VRTConnected to V
Connected to V

RBS

SS

RTS,VRB

RTS,VRB

7

8

2.6

0.6

CLK

Units

(Limits)

V (min)

V (max)

Ω (min)

Ω (max)

V (min)

V (max)

V (min)

V (max)

=

0.5V

DD

RT

www.national.com5

Converter Electrical Characteristics (Continued)

The following specifications apply for AVDD=DVDD= +5.0 VDC, PD = 0V, VRT= +2.6V, VRB= 0.6V, CL= 20 pF, f
50 MHz at 50% duty cycle. Boldface limits apply for T

ADC1175-50

Symbol Parameter Conditions

A=TMIN

ANALOG INPUT AND REFERENCE CHARACTERISTICS

Connected to V

V

RT

V

RTS–VRBS

Self Bias Voltage Delta

Connected to V
V

Connected to V

RT

Connected to AV

V

RT–VRB

Reference Voltage Differential 2

CONVERTER DYNAMIC CHARACTERISTICS

f

= 4.4 MHz, f

IN

f

= 19.9 MHz, f

IN

ENOB Effective Number of Bits

SINAD Signal-to-Noise & Distortion

SNR Signal-to-Noise Ratio

SFDR Spurious Free Dynamic Range

THD Total Harmonic Distortion

f

= 1.3 MHz, f

IN

f

= 4.4 MHz, f

IN

f

= 24.9 MHz, f

IN

f

= 4.4 MHz, f

IN

f

= 19.9 MHz, f

IN

f

= 1.3 MHz, f

IN

f

= 4.4 MHz, f

IN

f

= 24.9 MHz, f

IN

f

= 4.4 MHz, f

IN

f

= 19.9 MHz, f

IN

f

= 1.3 MHz, f

IN

f

= 4.4 MHz, f

IN

f

= 24.9 MHz, f

IN

= 1.3 MHz 57 dB

f

IN

f

= 4.4 MHz 56 dB

IN

f

= 24.9 MHz 51 dB

IN

= 1.3 MHz −55 dB

f

IN

f

= 4.4 MHz −54 dB

IN

f

= 24.9 MHz −51 dB

IN

POWER SUPPLY CHARACTERISTICS

IA
ID

IA
ID

DD
DD

DD
DD

Analog Supply Current DVDD=AVDD= 5.25V 13 mA
Digital Supply Current DVDD=AVDD= 5.25V 11 mA

=AVDD= 5.25V,

DV

DD

=50MHz

+

Total Operating Current

f

CLK

DV

=AVDD= 5.25V,

DD

CLK Inactive (low)
Power Consumption PD pin low 125 190 mW (max)
Power Consumption PD pin high

CLK, PD DIGITAL INPUT CHARACTERISTICS

V

IH

V

IL

I

IH

I

IL

C

IN

Logical High Input Voltage 2.0 V (min)
Logical Low Input Voltage 0.8 V (max)
Logical High Input Current VIH=DVDD=AVDD= +5.25V
Logical Low Input Current VIL= 0V, DVDD=AVDD= +5.25V
Digital Input Capacitance 4 pF

DIGITAL OUTPUT CHARACTERISTICS

I

OH

I

OL

Output Current, Logic HIGH DVDD= 4.75V, VOH= 4.0V −1.1 mA (min)
Output Current, Logic LOW DVDD= 4.75V, VOL= 0.4V 1.8 mA (min)

to T

RTS,VRB

RBS

RTS,VRB

SS

= 40 MHz 7.2 6.7 Bits (min)

CLK

CLK

= 50 MHz 7.3 Bits

CLK

= 50 MHz 7.2 Bits

CLK

CLK

= 40 MHz 45 42 dB (min)

CLK

CLK

= 50 MHz 46 dB

CLK

= 50 MHz 45 dB

CLK

CLK

= 40 MHz 46 42.5 dB (min)

CLK

CLK

= 50 MHz 48 dB

CLK

= 50 MHz 45 dB

CLK

CLK

; all other limits TA= 25˚C (Notes 7, 8).

MAX

Typical

(Note 9)

Limits

(Note 9)

2

2.3 V

= 40 MHz 7.0 6.4 Bits (min)

= 50 MHz 6.8 6.1 Bits (min)

= 40 MHz 44 40 dB (min)

= 50 MHz 43 38.4 dB (min)

= 40 MHz 44 41 dB (min)

= 50 MHz 44 40 dB (min)

25 36 mA (max)

14 mA

<

5mW mW

CLK

Units

(Limits)

1.89

2.20

1.0

2.8

±

5 µA (max)

±

5 µA (max)

(V (min)
V (max)

V (min)

V (max)

=

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