Rainbow Electronics ADC1175 User Manual

ADC1175
8-Bit, 20MHz, 60mW A/D Converter

ADC1175 8-Bit, 20MHz, 60mW A/D Converter

March 2003

General Description

The ADC1175 is a low power, 20 Msps analog-to-digital
converter that digitizes signals to 8 bits while consuming just
60 mW of power (typ). The ADC1175 uses a unique archi­tecture that achieves 7.5 Effective Bits. Output formatting is
straight binary coding.

The excellent DC and AC characteristics of this device,
together with its low power consumption and +5V single
supply operation, make it ideally suited for many video,
imaging and communications applications, including use in
portable equipment. Furthermore, the ADC1175 is resistant
to latch-up and the outputs are short-circuit proof. The top
and bottom of the ADC1175’s reference ladder is available
for connections, enabling a wide range of input possibilities.

The ADC1175 is offered in SOIC (EIAJ) and TSSOP. It is
designed to operate over the commercial temperature range
of -20˚C to +75˚C.

Features

n Internal Sample-and-Hold Function
n Single +5V Operation
n Internal Reference Bias Resistors
n Industry Standard Pinout
n TRI-STATE Outputs

Key Specifications

j

Resolution 8 Bits

j

Maximum Sampling Frequency 20 Msps (min)

j

THD −55 dB (typ)

j

DNL 0.75 LSB (max)

j

ENOB 7.5 Bits (typ)

j

Guaranteed No Missing Codes

j

Differential Phase 0.5 Degree (typ)

j

Differential Gain 0.4% (typ)

j

Power Consumption

(excluding reference current)

60mW (typ)

Applications

n Video Digitization
n Digital Still Cameras
n Set Top Boxes
n Communications
n Medical Imaging
n Personal Computer Video Cameras
n Digital Television
n CCD Imaging
n Electro-Optics

Pin Configuration

ADC1175 Pin Configuration

10009201

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Ordering Information

ADC1175

Block Diagram

ADC1175CIJM SOIC (EIAJ)

ADC1175CIJMX SOIC (EIAJ) (tape & reel)

ADC1175CIMTC TSSOP

ADC1175CIMTCX TSSOP (tape & reel)

Pin Descriptions and Equivalent Circuits

Pin
No. Symbol Equivalent Circuit

19 V

16 V

IN

RTS

10009202

Description

Analog signal input. Conversion range is VRBto VRT.

Reference Top Bias with internal pull-up resistor.
Short this pin to V

to self bias the reference ladder.

RT

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Pin Descriptions and Equivalent Circuits (Continued)

ADC1175

Pin
No. Symbol Equivalent Circuit

17 V

23 V

22 V

RT

RB

RBS

1OE

Description

Analog Input that is the high (top) side of the
reference ladder of the ADC. Nominal range is 1.0V
to AV
V

. Voltage on VRTand VRBinputs define the

DD

conversion range. Bypass well. See Section 2.0

IN

for more information.

Analog Input that is the low (bottom) side of the
reference ladder of the ADC. Nominal range is 0V to

4.0V. Voltage on V

and VRBinputs define the V

RT

IN

conversion range. Bypass well. See Section 2.0 for
more information.

Reference Bottom Bias with internal pull down
resistor. Short to V

to self bias the reference

RB

ladder.

CMOS/TTL compatible Digital input that, when low,
enables the digital outputs of the ADC1175. When
high, the outputs are in a high impedance state.

12 CLK

3 thru

10

D0-D7

11, 13 DV

CMOS/TTL compatible digital clock Input. VINis
sampled on the falling edge of CLK input.

Conversion data digital Output pins. D0 is the LSB,
D7 is the MSB. Valid data is output just after the
rising edge of the CLK input. These pins are enabled
by bringing the OE pin low.

Positive digital supply pin. Connect to a clean, quiet
voltage source of +5V. AV

DD

a common source and be separately bypassed with a

and DVDDshould have

DD

10µF capacitor and a 0.1µF ceramic chip capacitor.
See Section 3.0 for more information.

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Pin Descriptions and Equivalent Circuits (Continued)

Pin

ADC1175

No. Symbol Equivalent Circuit

2, 24 DV

14, 15,

18

20, 21 AV

AV

SS

DD

SS

Description

The ground return for the digital supply. AVSSand

should be connected together close to the

DV

SS

ADC1175.

Positive analog supply pin. Connected to a clean,
quiet voltage source of +5V. AV

and DVDDshould

DD

have a common source and be separately bypassed
with a 10 µF capacitor and a 0.1 µF ceramic chip
capacitor. See Section 3.0 for more information.

The ground return for the analog supply. AVSSand

should be connected together close to the

DV

SS

ADC1175 package.

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ADC1175

Absolute Maximum Ratings (Note 1)

If Military/Aerospace specified devices are required,
please contact the National Semiconductor Sales Office/
Distributors for availability and specifications.

,DV

AV

DD

DD

Voltage on Any Pin −0.3V to 6.5V

V

RT,VRB

AVSSto AV

CLK, OE Voltage −0.5 to (AVDD+ 0.5V)

Digital Output Voltage DV

Input Current (Note 3)

SS

to DV

±

25mA

6.5V

DD

DD

Operating Ratings(Notes 1, 2)

Temperature Range −20˚C ≤ T

AV

,DV

DD

DD

AV

−DV

DD

|AV

V

RT

V

RB

V

RT-VRB

V

IN

DD

-DVSS| 0V to 100 mV

SS

Voltage Range VRBto V

+4.75V to +5.25V

≤ +75˚C

A

<

0.5V

1.0V to V

0V to 4.0V

1V to 2.8V

Package Input Current

±

(Note 3)

50mA

Package Dissipation at 25˚C (Note 4)

ESD Susceptibility (Note 5)

Human Body Model 2000V

Machine Model 200V

Soldering Temp., Infrared, 10
sec. (Note 6) 300˚C

Storage Temperature −65˚C to +150˚C

Converter Electrical Characteristics

The following specifications apply for AVDD=DVDD= +5.0VDC, OE = 0V, VRT= +2.6V, VRB= 0.6V, CL= 20 pF,
f

= 20MHz at 50% duty cycle. Boldface limits apply for TA=T

CLK

Symbol Parameter Conditions

DC Accuracy

INL Integral Non Linearity f

INL Integral Non Linearity f

DNL Differential Non Linearity f

DNL Differential Non Linearity f

CLK

CLK

CLK

CLK

= 20 MHz

= 30 MHz

= 20 MHz

= 30 MHz

Missing Codes 0 (max)

E

OT

E

OB

Top Offset −24 mV

Bottom Offset +37 mV

Video Accuracy

f

= 4.43 MHz sine wave,

DP Differential Phase Error

DG Differential Gain Error

in

= 17.7 MHz

f

CLK

f

= 4.43 MHz sine wave,

in

= 17.7 MHz

f

CLK

Analog Input and Reference Characteristics

V

IN

C

IN

R

IN

Input Range 2.0

VINInput Capacitance VIN= 1.5V + 0.7Vrms

RINInput Resistance

BW Analog Input Bandwidth 120 MHz

R

R

R

I

RT

REF

RB

REF

Top Reference Resistor 360 Ω

Reference Ladder Resistance VRTto V

RB

Bottom Reference Resistor 90 Ω

V

RT=VRTS,VRB=VRBS

Reference Ladder Current

V

RT=VRTS,VRB

=AV

SS

MIN

to T

; all other limits TA= 25˚C (Notes 7, 8)

MAX

(CLK LOW) 4

(CLK HIGH) 11

Typical

(Note 9)

±

0.5

±

1.0 LSB( max)

±

0.35

±

1.0 LSB( max)

Limits

(Note 9)

±

1.3 LSB( max)

±

0.75 LSB( max)

0.5 Degree

0.4 %

V

RB

V

RT

>

1MΩ

300

7

8

200 Ω(min)

400 Ω(max)

4.8 mA (min)

9.3 mA(max)

5.4 mA (min)

10.5 mA(max)

V(max)

Units

V(min)

pF

DD

RT

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Converter Electrical Characteristics (Continued)

The following specifications apply for AVDD=DVDD= +5.0VDC, OE = 0V, VRT= +2.6V, VRB= 0.6V, CL= 20 pF,
f

= 20MHz at 50% duty cycle. Boldface limits apply for TA=T

CLK

ADC1175

Symbol Parameter Conditions

V

RT

V

RB

V

RTS

V

RBS

V

RT-VRB

Reference Top Self Bias
Voltage

Reference Bottom Self Bias
Voltage

­Self Bias Voltage Delta

Reference Voltage Delta 2

VRTconnected to V
VRBconnected to V

connected to V

V

RT

V

connected to V

RB

V

connected to V

RT

connected to V

V

RB

V

connected to V

RT

connected to AV

V

RB

Power Supply Characteristics

IA

ID

IAV
IDV

DD

DD

DD

DD

Analog Supply Current DVDD=AVDD=5.25V 9.5 mA

Digital Supply Current DVDD=AVDD=5.25V 2.5 mA

=5.25V, f

=5.25V, f

=AVDD=5.25V, CLK Low

+

Total Operating Current

DV

DV

DV

DDAVDD

DDAVDD

DD

(Note 10)

Power Consumption

DVDD=AVDD=5.25V, f

DV

=AVDD=5.25V, f

DD

CLK, OE Digital Input Characteristics

V

IH

V

IL

I

IH

I

IL

C

IN

Logical High Input Voltage DVDD=AVDD= +5.25V 3.0 V (min)

Logical Low Input Voltage DVDD=AVDD= +5.25V 1.0 V (max)

Logical High Input Current VIH=DVDD=AVDD= +5.25V 5 µA

Logic Low Input Current VIL= 0V, DVDD=AVDD= +5.25V −5 µA

Logic Input Capacitance 5 pF

Digital Output Characteristics

I

I

I
I

OH

OL

OZH

OZL

High Level Output Current DVDD= 4.75V, VOH= 2.4V −1.1 mA (min)

Low Level Output Current DVDD= 4.75V, VOL= 0.4V 1.6 mA (max)

DV

= 5.25V

,

Tri-State®Leakage Current

DD

OE=DV

DD,VOL

=0VorVOH=DV

AC Electrical Characteristics

f

C1

f

C2

t

OD

Maximum Conversion Rate 30 20 MHz(min)

Minimum Conversion Rate 1 MHz

Output Delay CLK high to data valid 19 ns(max)

Pipeline Delay (Latency) 2.5

t

DS

t

AJ

t

OH

t

EN

t

DIS

ENOB Effective Number of Bits

Sampling (Aperture) Delay CLK low to acquisition of data 3 ns

Aperture Jitter 30 ps rms

Output Hold Time CLK high to data invalid 10 ns

OE Low to Data Valid Loaded as in Figure 2 11 ns

OE High to High Z State Loaded as in Figure 2 15 ns

f

= 1.31 MHz, VIN=FS-2LSB

IN

= 4.43 MHz, VIN=FS-2LSB

f

IN

= 9.9 MHz, VIN=FS-2LSB

f

IN

= 4.43 MHz, f

f

IN

CLK

RTS

RBS

RTS

RBS

RTS

RBS

RTS

SS

DD

= 30 MHz

MIN

to T

; all other limits TA= 25˚C (Notes 7, 8)

MAX

Typical

(Note 9)

2.6 V

0.6

,

,

= 20 MHz 12 17 mA

CLK

= 30 MHz 13

CLK

2

2.3 V

9.6 mA

= 20 MHz 60 85 mW

CLK

= 30 MHz 65 mW

CLK

±

20 µA

7.5

7.3

7.2

6.5

Limits

(Note 9)

Units

0.55 V(min)

0.65 V(max)

1.89

2.15

µAmin

µAmax

1.0 V(min)

2.8 V(max)

Clock

Cycles

7.0

Bits (min)

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