Rainbow Electronics ADC1173 User Manual

ADC1173
8-Bit, 3-Volt, 15MSPS, 33mW A/D Converter

ADC1173 8-Bit, 3-Volt, 15MSPS, 33mW A/D Converter

March 2003

General Description

The ADC1173 is a low power, 15 MSPS analog-to-digital
converter that digitizes signals to 8 bits while consuming just
33 mW of power (typ). The ADC1173 uses a unique archi­tecture that achieves 7.6 Effective Bits. Output formatting is
straight binary coding.

The excellent DC and AC characteristics of this device,
together with its low power consumption and +3V single
supply operation, make it ideally suited for many video,
imaging and communications applications, including use in
portable equipment. Furthermore, the ADC1173 is resistant
to latch-up and the outputs are short-circuit proof. The top
and bottom of the ADC1173’s reference ladder is available
for connections, enabling a wide range of input possibilities.

The ADC1173 is offered in SOIC (EIAJ) and TSSOP. It is
designed to operate over the commercial temperature range
of -40˚C to +75˚C.

Features

n Internal Sample-and-Hold Function
n Single +3V Operation
n Internal Reference Bias Resistors
n Industry Standard Pinout
n TRI-STATE

®

Outputs

Key Specifications

n Resolution 8 Bits
n Maximum Sampling Frequency 15 MSPS (min)
n THD −54 dB (typ)
n DNL
n ENOB at 3.58 MHz Input 7.6 Bits (typ)
n Guaranteed No Missing Codes
n Differential Phase 0.5 Degree (max)
n Differential Gain 1.5% (typ)
n Power Consumption 33mW (typ)
n (excluding reference current)

±

0.85 LSB (max)

Applications

n Video Digitization
n Digital Still Cameras
n Set Top Boxes
n Camcorders
n Personal Computer Video
n Digital Television
n CCD Imaging
n Electro-Optics

Pin Configuration

10089001

TRISTATE&®is a registered trademark of National Semiconductor Corporation.

© 2003 National Semiconductor Corporation DS100890 www.national.com

Ordering Information

ADC1173

Block Diagram

Industrial (−40˚C ≤ TA≤ +75˚C) Package

ADC1173CIJM SOIC (EIAJ)

ADC1173CIJMX SOIC (EIAJ) (tape & reel)

ADC1173CIMTC TSSOP

ADC1173CIMTCX TSSOP (tape & reel)

ADC1173EVAL Evaluation Board

Pin Descriptions and Equivalent Circuits

Pin
No. Symbol Equivalent Circuit

19 V

16 V

IN

RTS

10089002

Description

Analog signal input. Conversion range is VRBto VRT.

Reference Top Bias with internal pull-up resistor.
Short this pin to V

to self bias the reference ladder.

RT

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Pin Descriptions and Equivalent Circuits (Continued)

ADC1173

Pin
No. Symbol Equivalent Circuit

17 V

23 V

22 V

RT

RB

RBS

1OE

Description

Analog Input that is the high (top) side of the
reference ladder of the ADC. Nominal range is 1.0V
to AV
V

. Voltage on VRTand VRBinputs define the

DD

conversion range. Bypass well. See Section 2.0

IN

for more information.

Analog Input that is the low (bottom) side of the
reference ladder of the ADC. Nominal range is 0V to

2.0V. Voltage on V

and VRBinputs define the V

RT

IN

conversion range. Bypass well. See Section 2.0 for
more information.

Reference Bottom Bias with internal pull down
resistor. Short to V

to self bias the reference

RB

ladder.

CMOS/TTL compatible Digital input that, when low,
enables the digital outputs of the ADC1173. When
high, the outputs are in a high impedance state.

12 CLK

3 thru

10

D0-D7

11, 13 DV

CMOS/TTL compatible digital clock Input. VINis
sampled on the falling edge of CLK input.

Conversion data digital Output pins. D0 is the LSB,
D7 is the MSB. Valid data is output just after the
rising edge of the CLK input. These pins are enabled
by bringing the OE pin low.

Positive digital supply pin. Connect to a clean, quiet
voltage source of +3V. AV

DD

a common source and be separately bypassed with a

and DVDDshould have

DD

10µF capacitor and a 0.1µF ceramic chip capacitor.
See Section 3.0 for more information.

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Pin Descriptions and Equivalent Circuits (Continued)

Pin

ADC1173

No. Symbol Equivalent Circuit

2, 24 DV

14, 15,

18

20, 21 AV

AV

SS

DD

SS

Description

The ground return for the digital supply. AVSSand

should be connected together close to the

DV

SS

ADC1173.

Positive analog supply pin. Connected to a clean,
quiet voltage source of +3V. AV

and DVDDshould

DD

have a common source and be separately bypassed
with a 10 µF capacitor and a 0.1 µF ceramic chip
capacitor. See Section 3.0 for more information.

The ground return for the analog supply. AVSSand

should be connected together close to the

DV

SS

ADC1173 package.

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ADC1173

Absolute Maximum Ratings (Note 1)

If Military/Aerospace specified devices are required,
please contact the National Semiconductor Sales Office/
Distributors for availability and specifications.

,DV

AV

DD

DD

Voltage on Any Pin −0.3V to 6.5V

V

RT,VRB

CLK, OE Voltage −0.5 to (AVDD+ 0.5V)

Digital Output Voltage DV

Input Current (Note 3)

6.5V

AVDDto V

to DV

SS

±

25mA

SS

DD

Operating Ratings(Notes 1, 2)

Temperature Range −40˚C ≤ T

AV

,DV

DD

DD

|AV

-DVSS| 0V to 100 mV

SS

V

RT

V

RB

RT-RB

V

Voltage Range VRBto V

IN

+2.7V to +3.6V

≤ +75˚C

A

1.0V to AV

0V to 2.0V

1.0V to 2.8V

Package Input Current

±

(Note 3)

50mA

Package Dissipation at 25˚C (Note 4)

ESD Susceptibility (Note 5)

Human Body Model 2000V

Machine Model 200V

Soldering Temp., Infrared, 10
sec. (Note 6) 300˚C

Storage Temperature −65˚C to +150˚C

Converter Electrical Characteristics

The following specifications apply for AVDD=DVDD= +3.0VDC, OE = 0V, VRT= +2.0V, VRB= 0V, CL= 20 pF, f
at 50% duty cycle. Boldface limits apply for TA=T

Symbol Parameter Conditions

MIN

to T

; all other limits TA= 25˚C (Notes 7, 8)

MAX

Typical

(Note 9)

Limits Units

DC Accuracy

INL Integral Non Linearity

DNL Differential Non Linearity

±

0.5

±

0.4

±

1.3 LSB( max)

±

0.85 LSB( max)

Missing Codes 0 (max)

E

OT

E

OB

Top Offset −12 mV

Bottom Offset +1.0 mV

Video Accuracy

DP Differential Phase Error f

DG Differential Gain Error f

= 3.58 MHz sine wave 0.5 Degree

in

= 3.58 MHz sine wave 1.5 %

in

Analog Input and Reference Characteristics

V

V

IN

C

IN

R

IN

Input Range 2.0

VINInput Capacitance VIN= 1.5V + 0.7Vrms

Input Resistance

(CLK LOW) 4

(CLK HIGH) 11

>

1MΩ

RB

V

RT

BW Analog Input Bandwidth 120 MHz

R

R

R

I

RT

REF

RB

REF

Top Reference Resistor 360 Ω

Reference Ladder Resistance VRTto V

RB

300 200 Ω(min)

400 Ω(max)

Bottom Reference Resistor 90 Ω

V

RT=VRTS,VRB=VRBS

4.2

Reference Ladder Current

V

RT=VRTS,VRB

=AV

SS

4.8 mA

CLK

= 15MHz

V(min)

V(max)

pF

mA

DD

RT

V

RT

V

RB

Reference Top Self Bias
Voltage

Reference Bottom Self Bias
Voltage

VRTconnected to V
VRBconnected to V

connected to V

V

RT

V

connected to V

RB

RTS

RBS

RTS

RBS

1.56

0.36

1.45

1.65

0.32 V(min)

0.40 V(max)

V(min)

V(max)

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Converter Electrical Characteristics (Continued)

The following specifications apply for AVDD=DVDD= +3.0VDC, OE = 0V, VRT= +2.0V, VRB= 0V, CL= 20 pF, f
at 50% duty cycle. Boldface limits apply for TA=T

ADC1173

Symbol Parameter Conditions

V

connected to V

RT

connected to V

V

RTS

V

RBS

V

RT-VRB

­Self Bias Voltage Delta

Reference Voltage Delta 2

V

RB

V

connected to V

RT

connected to V

V

RB

Power Supply Characteristics

IA

ID

IAV
IDV

DD

DD

DD

DD

Analog Supply Current DVDD=AVDD= 3.6V 6.8 mA

Digital Supply Current DVDD=AVDD= 3.6V 2.3 mA

DV

+

Total Operating Current

DDAVDD

DV

=AVDD= 3.6V, CLK Low

DD

(Note 10)

Power Consumption DVDD=AVDD= 3.6V 33 41 mW

CLK, OE Digital Input Characteristics

V

IH

V

IL

I

IH

I

IL

C

IN

Logical High Input Voltage DVDD=AVDD= 3.6V 2.2 V (min)

Logical Low Input Voltage DVDD=AVDD= 3.6V 0.8 V (max)

Logical High Input Current VIH=DVDD=AVDD= 3.6V 5 µA

Logic Low Input Current VIL= 0V, DVDD=AVDD= 3.6V −5 µA

Logic Input Capacitance 5 pF

Digital Output Characteristics

= 2.7V, IOH= −360µA 2.4 V(min)

DV

V

V

I
I

OH

OL

OZH

OZL

High Level Output Voltage

Low Level Output Voltage DVDD= 2.7V, IOL= 1.6mA 0.32 0.6 V(max)

,

TRI-STATE®Leakage Current

DD

DV

= 2.7V, IOH= −1.1mA 2.1 1.9 V(min)

DD

DV

= 3.6V, OE = DVDD,

DD

V

OL

=0VorVOH=DV

AC Electrical Characteristics

f

C1

f

C2

t

−0 Output Delay CLK high to low data valid 28 ns(max)

OD

t

−1 Output Delay CLK low to high data valid 24 ns(max)

OD

Maximum Conversion Rate 20 15 MHz(min)

Minimum Conversion Rate 1 MHz

Pipeline Delay (Latency) 2.5

t

DS

t

AJ

t

OH

t

EN

t

DIS

ENOB Effective Number of Bits

SINAD Signal-to- Noise & Distortion

SNR Signal-to-Noise Ratio

Sampling (Aperture) Delay CLK low to acquisition of data 3 ns

Aperture Jitter 30 ps rms

Output Hold Time CLK high to data invalid 15 ns

OE Low to Data Valid Loaded as in Figure 2 22 ns

OE High to High Z State Loaded as in Figure 2 12 ns

f

= 1.31 MHz

IN

= 3.58 MHz

f

IN

= 7.5 MHz

f

IN

= 1.31 MHz

f

IN

= 3.58 MHz

f

IN

= 7.5 MHz

f

IN

= 1.31 MHz

f

IN

= 3.58 MHz

f

IN

= 7.5 MHz

f

IN

MIN

to T

; all other limits TA= 25˚C (Notes 7, 8)

MAX

Typical

(Note 9)

,

RTS

RBS

,

RTS

SS

Limits Units

1.2

1.1

1.3

1.38 V

1.0 V(min)

V

A

= 3.6V, 9.1 11.4 mA

5.8 mA

±

20 µA

DD

7.7

7.6

7.0 Bits (min)

7.4

49

47.7

43 dB(min)

46.5

49

48.7

44 dB(min)

48.0

CLK

= 15MHz

µAmin

µAmax

V(max)

Clock

Cycles

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Converter Electrical Characteristics (Continued)

The following specifications apply for AVDD=DVDD= +3.0VDC, OE = 0V, VRT= +2.0V, VRB= 0V, CL= 20 pF, f
at 50% duty cycle. Boldface limits apply for TA=T

Symbol Parameter Conditions

= 1.31 MHz

f

IN

= 3.58 MHz

SFDR Spurious Free Dynamic Range

THD Total Harmonic Distortion

Note 1: Absolute Maximum Ratings indicate limits beyond which damage to the device may occur. Operating Ratings indicate conditions for which the device is
functional, but do not guarantee specific performance limits. For guaranteed specifications and test conditions, see the Electrical Characteristics. The guaranteed
specifications apply only for the test conditions listed. Some performance characteristics may degrade when the device is not operated under the listed test
conditions.

Note 2: All voltages are measured with respect to GND = AV

Note 3: When the input voltage at any pin exceeds the power supplies (that is, less than AV

be limited to 25 mA. The 50 mA maximum package input current rating limits the number of pins that can safely exceed the power supplies with an input current of
25 mA to two.

Note 4: The absolute maximum junction temperatures (T
junction-to-ambient thermal resistance θ
TSSOP, θ
this part is 98˚C/W for the EIAJ SOIC). Note that the power dissipation of this device under normal operation will typically be about 49 mW (33 mW quiescent power
+ 13 mW reference ladder power+3mWdueto1TTLloan on each digital output. The values for maximum power dissipation listed above will be reached only when
the ADC1173 is operated in a severe fault condition (e.g. when input or output pins are driven beyond the power supply voltages, or the power supply polarity is
reversed). Obviously, such conditions should always be avoided.

Note 5: Human body model is 100 pF capacitor discharged through a 1.5kΩ resistor. Machine model is 220 pf discharged through ZERO Ω.

Note 6: See AN450, "Surface Mounting Methods and Their Effect on Product Reliability", or the section entitled "Surface Mount" found in any post 1986 National

Semiconductor Linear Data Book, for other methods of soldering surface mount devices.

Note 7: The analog inputs are protected as shown below. Input voltage magnitudes up to 6.5V or to 500 mV below GND will not damage this device. However, errors
in the A/D conversion can occur if the input goes above V
be ≤2.75V

is 92˚C/W, so PDMAX = 1,358 mW at 25˚C and 815 mW at the maximum operating ambient temperature of 75˚C. (Typical thermal resistance, θJA,of

JA

to ensure accurate conversions.

DC

, and the ambient temperature, TA, and can be calculated using the formula PDMAX=(TJmax - TA)/θJA. In the 24-pin

JA

f

IN

= 7.5 MHz

f

IN

= 1.31 MHz

f

IN

= 3.58 MHz

f

IN

= 7.5 MHz

f

IN

SS

max) for this device is 150˚C. The maximum allowable power dissipation is dictated by TJmax, the

J

or below GND by more than 50 mV. As an example, if AVDDis 2.7VDC, the full-scale input voltage must

DD

to T

MIN

=DVSS= 0V, unless otherwise specified.

; all other limits TA= 25˚C (Notes 7, 8)

MAX

or DVSS, or greater than AVDDor DVDD), the current at that pin should

SS

Typical

(Note 9)

65
55
51

−62

−54

−51

Limits Units

CLK

= 15MHz

ADC1173

dB

dB

10089010

Note 8: To guarantee accuracy, it is required that AVDDand DVDDbe well bypassed. Each supply pin must be decoupled with separate bypass capacitors.

Note 9: Typical figures are at T

Level).

Note 10: At least two clock cycles must be presented to the ADC1173 after power up. See Section 4.0 for details.

= 25˚C, and represent most likely parametric norms. Test limits are guaranteed to National’s AOQL (Average Outgoing Quality

J

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