ADC10D040
Dual 10-Bit, 40 MSPS, 267 mW A/D Converter
ADC10D040 Dual 10-Bit, 40 MSPS, 267 mW A/D Converter
September 2003
General Description
The ADC10D040 is a dual low power, high performance
CMOS analog-to-digital converter that digitizes signals to 10
bits resolution at sampling rates up to 45 MSPS while consuming a typical 267 mW from a single 3.3V supply. No
missing codes is guaranteed over the full operating temperature range. The unique two stage architecture achieves 9.4
Effective Bits over the entire Nyquist band at 40 MHz sample
rate. An output formatting choice of straight binary or 2’s
complement coding and a choice of two gain settings eases
the interface to many systems. Also allowing great flexibility
of use is a selectable 10-bit multiplexed or 20-bit parallel
output mode. An offset correction feature minimizes the offset error.
To ease interfacing to most low voltage systems, the digital
output power pins of the ADC10D040 can be tied to a
separate supply voltage of 1.5V to 3.6V, making the outputs
compatible with other low voltage systems. When not converting, power consumption can be reduced by pulling the
PD (Power Down) pin high, placing the converter into a low
power state where it typically consumes less than 1 mW and
from which recovery is less than 1 ms. Bringing the STBY
(Standby) pin high places the converter into a standby mode
where power consumption is about 30 mW and from which
recovery is 800 ns.
The ADC10D040’s speed, resolution and single supply operation make it well suited for a variety of applications,
including high speed portable applications.
Operating over the industrial (−40˚ ≤ T
ture range, the ADC10D040 is available in a 48-pin TQFP. An
evaluation board is available to ease the design effort.
≤ +85˚C) tempera-
A
Features
n Internal sample-and-hold
n Internal Reference Capability
n Dual gain settings
n Offset correction
n Selectable straight binary or 2’s complement output
n Multiplexed or parallel output bus
n Single +3.0V to 3.6V operation
n Power down and standby modes
n 3V TTL Logic input/output compatible
Key Specifications
n Resolution 10 Bits
n Conversion Rate 40 MSPS
n ENOB 9.4 Bits (typ)
n DNL 0.35 LSB (typ)
n Conversion Latency Parallel Outputs 2.5 Clock Cycles
— Multiplexed Outputs, I Data Bus 2.5 Clock Cycles
— Multiplexed Outputs, Q Data Bus 3 Clock Cycles
n PSRR 90 dB
n Power Consumption— Normal Operation 267 mW (typ)
— Power Down Mode
— Fast Recovery Standby Mode 30 mW (typ)
<
1 mW (typ)
Applications
n Digital Video
n CCD Imaging
n Portable Instrumentation
n Communications
n Medical Imaging
n Ultrasound
© 2003 National Semiconductor Corporation DS200297 www.national.com
Connection Diagram
ADC10D040
Ordering Information
Industrial Temperature Range
TOP VIEW
(−40˚C ≤ T
ADC10D040CIVS TQFP
ADC10D040EVAL Evaluation Board
≤ +85˚C)
A
NS Package
20029701
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Block Diagram
ADC10D040
Pin Descriptions and Equivalent Circuits
Pin No. Symbol Equivalent Circuit Description
48
47
37
38
1V
I+
I−
Q+
Q−
REF
Analog inputs to “I” ADC. With V
is 1.15V to 1.85V with GAIN pin low, or 0.8V to 2.2V with
GAIN pin high.
Analog inputs to “Q” ADC. With V
range is 1.15V to 1.85V with GAIN pin low, or 0.8V to 2.2V
with GAIN pin high.
Analog Reference Voltage input. The voltage at this pin
should be in the range of 0.6V to 1.6V. With 1.4V at this pin
and the GAIN pin low, the full scale differential inputs are
1.4 V
. With 1.4V at this pin and the GAIN pin high, the full
P-P
scale differential inputs are 2.8 V
bypassed with a minimum 1 µF capacitor.
REF
REF
P-P
20029702
= 1.4V, conversion range
= 1.4V, conversion
. This pin should be
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Pin Descriptions and Equivalent Circuits (Continued)
Pin No. Symbol Equivalent Circuit Description
ADC10D040
This is an analog output which can be used as a reference
source and/or to set the common mode voltage of the input. It
45 V
43 V
44 V
CMO
RP
RN
should be bypassed with a minimum of 1 µF low ESR
capacitor in parallel with a 0.1 µF capacitor. This pin has a
nominal output voltage of 1.5V and hasa1mAoutput source
capability.
Top of the reference ladder. Do not drive this pin. Bypass
this pin with a 10 µF low ESR capacitor and a 0.1 µF
capacitor.
Bottom of the reference ladder. Do not drive this pin.
Bypass this pin with a 10 µF low ESR capacitor and a 0.1 µF
capacitor.
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Pin Descriptions and Equivalent Circuits (Continued)
Pin No. Symbol Equivalent Circuit Description
33 CLK
2OS
31 OC
32 OF
34 STBY
35 PD
36 GAIN
8 thru 27 I0–I9 and Q0–Q9
28 I/Q
40, 41 V
A
Digital clock input for both converters. The analog inputs are
sampled on the falling edge of this clock input.
Output Bus Select. With this pin at a logic high, both the “I”
and the “Q” data are present on their respective 10-bit output
buses (Parallel mode of operation). When this pin is at a logic
low, the “I” and “Q” data are multiplexed onto the “I” output
bus and the “Q” output lines all remain at a logic low
(multiplexed mode).
Offset Correct pin. A low-to-high transition on this pin initiates
an independent offset correction sequence for each converter,
which takes 34 clock cycles to complete. During this time 32
conversions are taken and averaged. The result is subtracted
from subsequent conversions. Each input pair should have 0V
differential value during this entire 34 clock period.
Output Format pin. When this pin is LOW the output format is
Straight Binary. When this pin is HIGH the output format is 2’s
complement. This pin may be changed asynchronously, but
this will result in errors for one or two conversions.
Standby pin. The device operates normally with a logic low on
this and the PD (Power Down) pin. With this pin at a logic
high and the PD pin at a logic low, the device is in the
standby mode where it consumes just 30 mW of power. It
takes just 800 ns to come out of this mode after the STBY pin
is brought low.
Power Down pin that, when high, puts the converter into the
Power Down mode where it consumes just 1 mW of power. It
takes less than 1 ms to recover from this mode after the PD
pin is brought low. If both the STBY and PD pins are high
simultaneously, the PD pin dominates.
This pin sets the internal signal gain at the inputs to the
ADCs. With this pin low the full scale differential input
peak-to-peak signal is equal to V
REF
full scale differential input peak-to-peak signal is equal to 2 x
.
V
REF
3V TTL/CMOS-compatible Digital Output pins that provide the
conversion results of the I and Q inputs. I0 and Q0 are the
LSBs, I9 and Q9 are the MSBs. Valid data is present just
after the rising edge of the CLK input in the Parallel mode. In
the multiplex mode, I-channel data is valid on I0 through I9
when the I/Q output is high and the Q-channel data is valid
on I0 through I9 when the I/Q output is low.
Output data valid signal. In the multiplexed mode, this pin
transitions from low to high when the data bus transitions
from Q-data to I-data, and from high to low when the data bus
transitions from I-data to Q-data. In the Parallel mode, this pin
transitions from low to high as the output data changes.
Positive analog supply pin. This pin should be connected to a
quiet voltage source of +3.0V to +3.6V. V
have a common supply and be separately bypassed with
10 µF to 50 µF capacitors in parallel with 0.1 µF capacitors.
. With this pin high the
and VDshould
A
ADC10D040
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Pin Descriptions and Equivalent Circuits (Continued)
Pin No. Symbol Equivalent Circuit Description
ADC10D040
4V
6, 30 V
3, 39, 42,
46
5 DGND
7, 29 DR GND The ground return of the digital output drivers.
D
DR
AGND
Digital supply pin. This pin should be connected to a quiet
voltage source of +3.0V to +3.6V. V
common supply and be separately bypassed with 10 µF to 50
µF capacitors in parallel with 0.1 µF capacitors.
Digital output driver supply pins. These pins should be
connected to a voltage source of +1.5V to V
bypassed with 10 µF to 50 µF capacitors in parallel with 0.1
µF capacitors.
The ground return for the analog supply. AGND and DGND
should be connected together close to the ADC10D040
package.
The ground return for the digital supply. AGND and DGND
should be connected together close to the ADC10D040
package.
and VDshould have a
A
and be
D
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ADC10D040
Absolute Maximum Ratings (Notes 1,
2)
If Military/Aerospace specified devices are required,
please contact the National Semiconductor Sales Office/
Distributors for availability and specifications.
Positive Supply Voltages 3.8V
Voltage on Any Pin −0.3V to (V
Input Current at Any Pin (Note 3)
Package Input Current (Note 3)
Package Dissipation at T
= 25˚C See (Note 4)
A
ESD Susceptibility (Note 5)
Human Body Model 2500V
Machine Model 250V
or VD+0.3V)
A
±
25 mA
±
50 mA
Operating Ratings (Notes 1, 2)
Operating Temperature Range −40˚C ≤ T
V
Supply Voltage +3.0V to +3.6V
A,VD
V
Supply Voltage +1.5V to V
DR
VINDifferential Voltage Range
GAIN = Low
GAIN = High
VCMInput Common Mode Range
GAIN = Low V
GAIN = High V
V
Voltage Range 0.6V to 1.8V
REF
Digital Input Pins Voltage
Range −0.3V to (V
Soldering Temperature,
Infrared, 10 sec. (Note 6) 235˚C
Storage Temperature −65˚C to +150˚C
Converter Electrical Characteristics
The following specifications apply for VA=VD= +3.3 VDC,VDR= +2.5 VDC,V
(a.c. coupled) = FSR = 1.4 V
rected. Boldface limits apply for T
P-P,CL
= 15 pF, f
A=TMIN
= 40 MHz, 50% Duty Cycle, RS=50Ω,trc=t
CLK
to T
: all other limits TA= 25˚C (Note 7).
MAX
Symbol Parameter Conditions
STATIC CONVERTER CHARACTERISTICS
INL Integral Non-Linearity
DNL Differential Non-Linearity
Resolution with No Missing Codes 10 Bits
Without Offset Correction −3.3
V
OFF
Offset Error
With Offset Correction +0.4
GE Gain Error −4
DYNAMIC CONVERTER CHARACTERISTICS
= 4.43 MHz, VIN= FSR −0.1 dB 9.5 Bits
f
IN
f
ENOB Effective Number of Bits
SINAD
Signal-to-Noise Plus Distortion
Ratio
SNR Signal-to-Noise Ratio
THD Total Harmonic Distortion
HS2 Second Harmonic
HS3 Third Harmonic
= 10.4 MHz, VIN= FSR −0.1 dB, TA= 25˚C 9.5 9.1 Bits (min)
IN
f
= 19.7 MHz, VIN= FSR −0.1 dB 9.4 Bits
IN
= 4.43 MHz, VIN= FSR −0.1 dB 59 dB
f
IN
f
= 10.4 MHz, VIN= FSR −0.1 dB, TA= 25˚C 59 56.3 dB (min)
IN
f
= 19.7 MHz, VIN= FSR −0.1 dB 58 dB
IN
= 4.43 MHz, VIN= FSR −0.1 dB 60 dB
f
IN
f
= 10.4 MHz, VIN= FSR −0.1 dB, TA= 25˚C 60 57.3 dB (min)
IN
f
= 19.7 MHz, VIN= FSR −0.1 dB 59 dB
IN
= 4.43 MHz, VIN= FSR −0.1 dB −70 dB
f
IN
f
= 10.4 MHz, VIN= FSR −0.1 dB, TA= 25˚C −69 −61 dB (min)
IN
f
= 19.7 MHz, VIN= FSR −0.1 dB −67 dB
IN
= 4.43 MHz, VIN= FSR −0.1 dB −86 dB
f
IN
f
= 10.4 MHz, VIN= FSR −0.1 dB −83 dB
IN
f
= 19.7 MHz, VIN= FSR −0.1 dB −81 dB
IN
= 4.43 MHz, VIN= FSR −0.1 dB −73 dB
f
IN
f
= 10.4 MHz, VIN= FSR −0.1 dB −73 dB
IN
f
= 19.7 MHz, VIN= FSR −0.1 dB −72 dB
IN
= 1.4 VDC, GAIN = OF = 0V, OS = 3.3V, V
REF
Typical
(Note 8)
/4 to (VA–V
REF
/2 to (VA–V
REF
<
4 ns, NOT offset cor-
fc
Limits
(Note 9)
±
±
0.65
0.35
±
1.9 LSB (max)
+1.2
−1.0
+7
−12
+1.5
−0.5
+5
−12
≤ +85˚C
A
D
±
V
/2
REF
±
V
REF
/4)
REF
/2)
REF
+0.3V)
A
IN
Units
(Limits)
LSB (max)
LSB (min)
LSB (max)
LSB (min)
LSB (max)
LSB (min)
%FS (max)
%FS (min)
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Converter Electrical Characteristics (Continued)
The following specifications apply for VA=VD= +3.3 VDC,VDR= +2.5 VDC,V
(a.c. coupled) = FSR = 1.4 V
rected. Boldface limits apply for T
ADC10D040
P-P,CL
= 15 pF, f
A=TMIN
= 40 MHz, 50% Duty Cycle, RS=50Ω,trc=t
CLK
to T
: all other limits TA= 25˚C (Note 7).
MAX
Symbol Parameter Conditions
= 4.43 MHz, VIN= FSR −0.1 dB 72 dB
f
IN
f
SFDR Spurious Free Dynamic Range
IMD Intermodulation Distortion
Overrange Output Code (V
Underrange Output Code (V
= 10.4 MHz, VIN= FSR −0.1 dB 72 dB
IN
f
= 19.7 MHz, VIN= FSR −0.1 dB 70 dB
IN
<
f
8.5 MHz, VIN= FSR −6.1 dB
IN1
<
f
9.5 MHz, VIN= FSR −6.1 dB
IN2
IN+−VIN−
IN+−VIN−
)>1.5V 1023
)<−1.5V 0
FPBW Full Power Bandwidth 140 MHz
INTER-CHANNEL CHARACTERISTICS
Crosstalk
Channel - Channel Aperture Delay
Match
1 MHz input to tested channel, 10.3 MHz input
to other channel
f
= 8 MHz 8.5 ps
IN
Channel - Channel Gain Matching 0.1 %FS
REFERENCE AND ANALOG CHARACTERISTICS
V
C
R
V
I
REF
V
TC
V
Analog Differential Input Range
IN
Analog Input Capacitance (each
IN
input)
Analog Differential Input
IN
Resistance
Reference Voltage 1.4
REF
Reference Input Current
Common Mode Voltage Output
CMO
Common Mode Voltage
Temperature Coefficient
CMO
Gain Pin = AGND 1.4 V
Gain Pin = V
A
Clock High 6 pF
Clock Low 3 pF
1 mA load to ground
(sourcing current)
DIGITAL INPUT CHARACTERISTICS
V
V
I
IH
I
IL
Logical “1” Input Voltage VD= +3.0V 2.0 V (min)
IH
Logical “0” Input Voltage VD= +3.6V 0.5 V (max)
IL
Logical “1” Input Current VIH=V
D
Logical “0” Input Current VIL= DGND
DIGITAL OUTPUT CHARACTERISTICS
V
V
+I
−I
Logical “1” Output Voltage VDR= +2.5V, I
OH
Logical “0” Output Voltage VDR= +2.5V, I
OL
Output Short Circuit Source
SC
Current
Output Short Circuit Sink Current V
SC
=0V
V
OUT
OUT=VDR
= −0.5 mA
OUT
= 1.6 mA 0.4 V (max)
OUT
Parallel Mode −4.7 mA
Multiplexed Mode −9 mA
Parallel Mode 4.7 mA
Multiplexed Mode 9 mA
POWER SUPPLY CHARACTERISTICS
PD = LOW, STBY = LOW, d.c. input 70 80 mA (max)
I
A
Analog Supply Current
PD = LOW, STBY = HIGH 10 mA
PD = HIGH, STBY = LOW or HIGH 0.1 mA
= 1.4 VDC, GAIN = OF = 0V, OS = 3.3V, V
REF
<
4 ns, NOT offset cor-
fc
Typical
(Note 8)
Limits
(Note 9)
71 dB
−72 dB
2.8 V
13.5 kΩ
0.6 V (min)
1.6 V (max)
<
1µA
1.5
1.35 V (min)
1.6 V (max)
30 ppm/˚C
<
1µA
>
−1 µA
V
DR
−0.2V
IN
Units
(Limits)
P-P
P-P
V (min)
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Converter Electrical Characteristics (Continued)
The following specifications apply for VA=VD= +3.3 VDC,VDR= +2.5 VDC,V
(a.c. coupled) = FSR = 1.4 V
rected. Boldface limits apply for T
P-P,CL
= 15 pF, f
A=TMIN
= 40 MHz, 50% Duty Cycle, RS=50Ω,trc=t
CLK
to T
: all other limits TA= 25˚C (Note 7).
MAX
Symbol Parameter Conditions
PD = LOW, STBY = LOW, d.c. input 9 10 mA (max)
I
D
Digital Supply Current
PD = LOW, STBY = HIGH 0.1 mA
PD = HIGH, STBY = LOW or HIGH 0.1 mA
I
DR
Digital Output Driver Supply
Current (Note 10)
PD = STBY = LOW, dc input 1.9 2.5 mA (max)
PD = LOW, STBY = LOW, d.c. input 267 305 mW (max)
PD Power Consumption
PD = LOW, STBY = LOW, 1 MHz Input 270 mW
PD = LOW, STBY = HIGH 30 mW
PD = HIGH, STBY = LOW or HIGH 0.6 mW
PSRR1 Power Supply Rejection Ratio
PSRR2 Power Supply Rejection Ratio
Change in Full Scale with 3.0V to 3.6V Supply
Change
Rejection at output with 10.3 MHz, 250 mV
Riding on VAand V
D
= 1.4 VDC, GAIN = OF = 0V, OS = 3.3V, V
REF
P-P
AC Electrical Characteristics OS = Low (Multiplexed Mode)
The following specifications apply for VA=VD= +3.3 VDC,VDR= +2.5VDC,V
(a.c. coupled) = FSR = 1.4 V
rected. Boldface limits apply for T
P-P,CL
= 15 pF, f
A=TMIN
= 40 MHz, 50% Duty Cycle, RS=50Ω,trc=t
CLK
to T
: all other limits TA= 25˚C (Note 7)
MAX
Symbol Parameter Conditions
1
f
CLK
f
CLK
Maximum Clock Frequency 45 40 MHz (min)
2
Minimum Clock Frequency 20 MHz
Duty Cycle 50
Pipeline Delay (Latency)
I Data 2.5 Clock Cycles
Q Data 3.0 Clock Cycles
t
t
t
r,tf
OC
OD
Output Rise and Fall Times 5 ns
Offset Correction Pulse Width 10 ns (min)
Output Delay from CLK Edge to
Data Valid
t
DIQ
t
SKEW
t
AD
t
AJ
t
VALID
t
WUPD
I/Q Output Delay 13 ns
I/Q to Data Skew
Sampling (Aperture) Delay 2.2 ns
Aperture Jitter
Data Valid Time 7.5 ns
Overrange Recovery Time
Differential V
0V
step from 1.5V to
IN
PD Low to 1/2 LSB Accurate
Conversion (Wake-Up Time)
t
WUSB
STBY Low to 1/2 LSB Accurate
Conversion (Wake-Up Time)
= 1.4 VDC, GAIN = OF = 0V, OS = 0V, V
REF
Typical
(Note 8)
13 19 ns (max)
±
200 ps
<
50 ns
<
800 ns
ADC10D040
<
4 ns, NOT offset cor-
fc
Typical
(Note 8)
Limits
(Note 9)
90 dB
52 dB
<
4 ns, NOT offset cor-
fc
Limits
(Note 9)
45
55
(Limits)
% (min)
% (max)
10 ps (rms)
1ms
IN
Units
(Limits)
IN
Units
www.national.com9
AC Electrical Characteristics OS = High (Parallel Mode)
The following specifications apply for VA=VD= +3.3 VDC,VDR= +2.5VDC,V
(a.c. coupled) = FSR = 1.0 V
V
IN
rected. Boldface limits apply for T
ADC10D040
P-P,CL
A=TMIN
= 15 pF, f
to T
= 40 MHz, 50% Duty Cycle, RS=50Ω,trc=t
CLK
: all other limits TA= 25˚C (Note 7)
MAX
Symbol Parameter Conditions
1
f
f
CLK
CLK
Maximum Clock Frequency 45 40 MHz (min)
2
Minimum Clock Frequency 20 MHz
Duty Cycle 50
Pipeline Delay (Latency) 2.5
t
t
t
r,tf
OC
OD
Output Rise and Fall Times 9 ns
OC Pulse Width 10 ns
Output Delay from CLK Edge to
Data Valid
t
DIQ
t
AD
t
AJ
t
VALID
t
WUPD
I/Q Output Delay 13 ns
Sampling (Aperture) Delay 2.2 ns
Aperture Jitter
Data Valid Time 16 ns
Overrange Recovery Time
Differential V
0V
step from 1.5V to
IN
PD Low to 1/2 LSB Accurate
Conversion (Wake-Up Time)
t
WUSB
STBY Low to 1/2 LSB Accurate
Conversion (Wake-Up Time)
Note 1: Absolute Maximum Ratings indicate limits beyond which damage to the device may occur. Operating Ratings indicate conditions for which the device is
functional, but do not guarantee specific performance limits. For guaranteed specifications and test conditions, see the Electrical Characteristics. The guaranteed
specifications apply only for the test conditions listed. Some performance characteristics may degrade when the device is not operated under the listed test
conditions.
Note 2: All voltages are measured with respect to GND = AGND = DGND = 0V, unless otherwise specified.
Note 3: When the input voltage at any pin exceeds the power supplies (V
maximum package input current rating limits the number of pins that can safely exceed the power supplies with an input current of 25 mA to two.
Note 4: The absolute maximum junction temperature (T
junction-to-ambient thermal resistance (θ
TQFP, θ
device under normal operation will typically be about 307 mW (267 mW quiescent power + 40 mW due to 1 LVTTL load on each digital output). The values for
maximum power dissipation listed above will be reached only when the ADC10D040 is operated in a severe fault condition (e.g. when input or output pins are driven
beyond the power supply voltages, or the power supply polarity is reversed). Obviously, such conditions should always be avoided.
Note 5: Human body model is 100 pF capacitor discharged through a 1.5 kΩ resistor. Machine model is 220 pF discharged through 0Ω.
Note 6: See AN450, “Surface Mounting Methods and Their Effect on Product Reliability”, or the section entitled “Surface Mount” found in any post 1986 National
Semiconductor Linear Data Book, for other methods of soldering surface mount devices.
Note 7: The inputs are protected as shown below. Input voltage magnitude up to 300 mV beyond the supply rails will not damage this device. However, errors in
the A/D conversion can occur if the input goes beyond the limits given in these tables.
is 76˚C/W, so PDMAX = 1,645 mW at 25˚C and 855 mW at the maximum operating ambient temperature of 85˚C. Note that the power dissipation of this
JA
), and the ambient temperature (TA), and can be calculated using the formula PDMAX=(TJmax - TA)/θJA. In the 48-pin
JA
max) for this device is 150˚C. The maximum allowable power dissipation is dictated by TJmax, the
J
IN
<
GND or V
>
VAor VD), the current at that pin should be limited to 25 mA. The 50 mA
IN
= 1.4 VDC, GAIN = OF = 0V, OS = +3.3V,
REF
Typical
(Note 8)
<
4 ns, NOT offset cor-
fc
Limits
(Note 9)
45
55
16 22 ns (max)
<
10 ps (rms)
50 ns
<
1ms
800 ns
Units
(Limits)
% (min)
% (max)
Clock
Cycles
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AC Electrical Characteristics OS = High (Parallel Mode) (Continued)
20029706
Note 8: Typical figures are at TJ= 25˚C, and represent most likely parametric norms.
Note 9: Test limits are guaranteed to National’s AOQL (Average Outgoing Quality Level). Performance is guaranteed only at V
of 50%. The limits for V
clock low and high levels of 0.3V and V
Note 10: I
voltage, V
power supply voltage, C
is the current consumed by the switching of the output drivers and is primarily determined by the load capacitance on the output pins, the supply
DR
, and the rate at which the outputs are switching (which is signal dependent). IDR=VDR(COxfO+C1xf1+...+C9xf9) where VDRis the output driver
DR
and clock duty cycle specify the range over which reasonable performance is expected. Tests are performed and limits guaranteed with
REF
is the total capacitance on the output pin, and fnis the average frequency at which that pin is toggling.
n
−0.3V, respectively.
D
= 1.4V and a clock duty cycle
REF
ADC10D040
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Timing Diagrams
ADC10D040
ADC10D040 Timing Diagram for Multiplexed Mode
20029708
ADC10D040 Timing Diagram for Parallel Mode
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20029707
Timing Diagrams (Continued)
ADC10D040
20029709
FIGURE 1. AC Test Circuit
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Specification Definitions
APERTURE (SAMPLING) DELAY is that time required after
the fall of the clock input for the sampling switch to open. The
Sample/Hold circuit effectively stops capturing the input sig-
ADC10D040
nal and goes into the “hold” mode t
low.
APERTURE JITTER is the variation in aperture delay from
sample to sample. Aperture jitter shows up as input noise.
CLOCK DUTY CYCLE is the ratio of the time that the clock
waveform is high to the total time of one clock period.
CROSSTALK is coupling of energy from one channel into
the other channel.
DIFFERENTIAL NON-LINEARITY (DNL) is the measure of
the maximum deviation from the ideal step size of 1 LSB.
Measured at 40 MSPS with a ramp input.
EFFECTIVE NUMBER OF BITS (ENOB, or EFFECTIVE
BITS) is another method of specifying Signal-to-Noise and
Distortion Ratio, or SINAD. ENOB is defined as (SINAD −
1.76)/6.02 and says that the converter is equivalent to a
perfect ADC of this (ENOB) number of bits.
FULL POWER BANDWIDTH (FPBW) is the frequency at
which the magnitude of the reconstructed output fundamental drops 3 dB below its 1 MHz value.
GAIN ERROR is the difference between the ideal and actual
differences between the input levels at which the first and
last code transitions occur. That is, how far this difference is
from Full Scale.
INTEGRAL NON LINEARITY (INL) is a measure of the
maximum deviation of each individual code from a line
drawn from negative full scale (
transition) through positive full scale (
code transition). The deviation of any given code from this
straight line is measured from the center of that code value.
The end point test method is used. Measured at 40 MSPS
with a ramp input.
INTERMODULATION DISTORTION (IMD) is the creation of
spectral components that are not present in the input as a
result of two sinusoidal frequencies being applied to the ADC
input at the same time. It is defined as the ratio of the power
in the second and third order intermodulation products to the
total power in one of the original frequencies. IMD is usually
expressed in dB.
LSB (LEAST SIGNIFICANT BIT) is the bit that has the
smallest value of weight of all bits. This value is
*
V
m
REF
where “m” is the reference scale factor and “n” is the ADC
resolution, which is 10 in the case of the ADC10D040. The
value of “m” is determined by the logic level at the gain pin
and has a value of 1 when the gain pin is at a logic low and
a value of 2 when the gain pin is at a logic high.
MISSING CODES are those output codes that are skipped
and will never appear at the ADC outputs. These codes
cannot be reached with any input value.
after the clock goes
AD
1
⁄2LSB below the first code
1
⁄2LSB above the last
n
/2
MSB (MOST SIGNIFICANT BIT) is the bit that has the
largest value or weight. Its value is one half of full scale.
OFFSET ERROR is a measure of how far the mid-scale
transition point is from the ideal zero voltage input.
OUTPUT DELAY is the time delay after the rising edge of
the input clock before the data update is present at the
output pins.
OVERRANGE RECOVERY TIME is the time required after
the differential input voltages goes from 1.5V to 0V for the
converter to recover and make a conversion with its rated
accuracy.
PIPELINE DELAY (LATENCY) is the number of clock cycles
between initiation of conversion and when that data is presented to the output driver stage. New data is available at
every clock cycle, but the data output lags the input by the
Pipeline Delay plus the Output Delay.
POWER SUPPLY REJECTION RATIO (PSRR) can be one
of two specifications. PSRR1 (DC PSRR) is the ratio of the
change in full scale gain error that results from a power
supply voltage change from 3.0V to 3.6V. PSRR2 (AC
PSRR) is measured with a 10 MHz, 250 mV
signal riding
P-P
upon the power supply and is the ratio of the signal amplitude on the power supply pins to the amplitude of that
frequency at the output. PSRR is expressed in dB.
SIGNAL TO NOISE RATIO (SNR) is the ratio, expressed in
dB, of the rms value of the fundamental signal at the output
to the rms value of the sum of all other spectral components
below one-half the sampling frequency, not including harmonics or d.c.
SIGNAL TO NOISE PLUS DISTORTION (S/(N+D) or SINAD) is the ratio, expressed in dB, of the rms value of the
fundamental signal at the output to the rms value of all of the
other spectral components below half the clock frequency,
including harmonics but excluding d.c.
SPURIOUS FREE DYNAMIC RANGE (SFDR) is the difference, expressed in dB, between the rms values of the fundamental signal at the output and the peak spurious signal,
where a spurious signal is any signal present in the output
spectrum that is not present at the input.
TOTAL HARMONIC DISTORTION (THD) is the ratio, expressed in dB, of the total of the first nine harmonic levels at
the output to the level of the fundamental at the output. THD
is calculated as
where f1is the RMS power of the fundamental (output)
frequency and f
through f10are the RMS power of the first
2
9 harmonic frequencies in the output spectrum.
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ADC10D040
Typical Performance Characteristics V
unless otherwise specified
Typical INL INL vs. V
20029782
INL vs. V
REF
= 3.3V, VDR= 2.5V, f
A=VD
CLK
INL vs. f
= 40 MHz, fIN= 10.4 MHz,
A
20029783
CLK
20029784
INL vs. Clock Duty Cycle INL vs. Temperature
20029786
20029785
20029787
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Typical Performance Characteristics V
unless otherwise specified (Continued)
= 3.3V, VDR= 2.5V, f
A=VD
= 40 MHz, fIN= 10.4 MHz,
CLK
ADC10D040
Typical DNL DNL vs. V
20029788
DNL vs. V
REF
DNL vs. f
A
20029789
CLK
SNR, SINAD & SFDR vs. V
20029790
A
20029794
DISTORTION vs. V
20029791
A
20029795
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ADC10D040
Typical Performance Characteristics V
unless otherwise specified (Continued)
DNL vs. Clock Duty Cycle DNL vs. Temperature
20029792 20029793
SNR, SINAD & SFDR vs. V
REF
= 3.3V, VDR= 2.5V, f
A=VD
= 40 MHz, fIN= 10.4 MHz,
CLK
DISTORTION vs. V
REF
SNR, SINAD & SFDR vs. f
CLK
20029796
20029798
DISTORTION vs. f
20029797
CLK
20029799
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Typical Performance Characteristics V
unless otherwise specified (Continued)
= 3.3V, VDR= 2.5V, f
A=VD
= 40 MHz, fIN= 10.4 MHz,
CLK
ADC10D040
SNR, SINAD & SFDR vs. f
IN
200297A0
DISTORTION vs. f
IN
SNR, SINAD & SFDR vs. Temperature DISTORTION vs. Temperature
200297A1
CROSSTALK vs. f
200297A3
IN
200297A5
CROSSTALK vs. Temperature
200297A4
200297A6
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ADC10D040
Typical Performance Characteristics V
unless otherwise specified (Continued)
Total Power vs. TEMP Spectral Response at f
200297A7 200297A8
IMD Response fIN= 8.5 MHz, 9.5 MHz
= 3.3V, VDR= 2.5V, f
A=VD
= 40 MHz, fIN= 10.4 MHz,
CLK
= 10.4 MHz
IN
200297A9
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Functional Description
Using a subranging architecture, the ADC10D040 achieves
9.4 effective bits over the entire Nyquist band at 40 MSPS
while consuming just 267 mW. The use of an internal
ADC10D040
sample-and-hold amplifier (SHA) not only enables this sustained dynamic performance, but also lowers the converter’s
input capacitance and reduces the number of external components required.
Analog signals at the “I” and “Q” inputs that are within the
voltage range set by V
ten bits at up to 45 MSPS. V
providing a differential peak-to-peak input range of 0.6 V
to 1.6 V
with the GAIN pin at a logic low, or a differential
P-P
input range of 1.2 V
logic high. Differential input voltages less than −V
the GAIN pin low, or less than −V
will cause the output word to indicate a negative full scale.
Differential input voltages greater than V
pin low, or greater than V
cause the output word to indicate a positive full scale.
Both “I” and “Q” channels are sampled simultaneously on the
falling edge of the clock input, while the timing of the data
output depends upon the mode of operation.
In the parallel mode, the “I” and “Q” output busses contain
the conversion result for their respective inputs. The “I” and
“Q” channel data are present and valid at the data output
pins t
after the rising edge of the input clock. In the
OD
multiplexed mode, “I” channel data is available at the digital
outputs t
after the rise of the clock edge, while the “Q”
OD
channel data is available at the I0 through I9 digital outputs
after the fall of the clock. However, a delayed I/Q output
t
OD
signal should be used to latch the output for best, most
consistent results.
Data latency in the parallel mode is 2.5 clock cycles. In the
multiplexed mode data latency is 2.5 clock cycles for the “I”
channel and 3.0 clock cycles for the “Q” channel. The
ADC10D040 will convert as long as the clock signal is
present and the PD and STBY pins are low.
Throughout this discussion,V
input voltage of the ADC10D040 while V
Common Mode output voltage.
and the GAIN pin are digitized to
REF
P-P
has a range of 0.6V to 1.6V,
REF
to 3.2 V
REF
with the GAIN pin at a
P-P
with the GAIN pin high
REF
/2 with the GAIN
REF
with the GAIN pin high, will
refers to the Common Mode
CM
CMO
P-P
/2 with
REF
refers to its
are not sensitive to the common-mode voltage and can be
anywhere within the supply rails (ground to V
) with little or
A
no performance degradation, as long as the signal swing at
the individual input pins is no more than 300 mV beyond the
supply rails.
Single-ended drive is not recommended as it can result in
degraded dynamic performance and faulty operation. If
single-ended input drive is absolutely required, it is recommended that a sample rate above 30 MSPS be used. If the
desired sample rate is lower than this, operate the
ADC10D040 at a multiple of the desired rate and decimate
the output (use every "n"th sample).
For single-ended drive, operate the ADC10D040 with the
GAIN pin at a logic low, connect one pin of the input pair to
1.5V (V
) through a resistor of 1k to 10 k Ohms, bypassing
CM
this input pin to ground witha1uFcapacitor. Drive the other
input pin of the input pair with 1.0 V
centered around 1.5V.
P-P
Because of the larger signal swing at one input for singleended operation, distortion performance will not be as good
as with a differential input signal. Alternatively, single-ended
to differential conversion with a transformer provides a quick,
easy solution for those applications not requiring response to
d.c. and low frequencies. See Figure 3. The 36Ω resistors
and 56 pF capacitor values are chosen to provide a cutoff
frequency near the clock frequency to compensate for the
effects of input sampling. A lower time constant should be
used for undersampling applications.
Applications Information
1.0 THE ANALOG SIGNAL INPUTS
Each of the analog inputs of the ADC10D040 consists of a
switch (transmission gate) followed by a switched capacitor
amplifier. The capacitance seen at each input pin changes
with the clock level, appearing as about 2 pF when the clock
is low, and about 5 pF when the clock is high. This switching
action causes analog input current spikes that work with the
input source impedance to produce voltage spikes.
The LMH6702 and the CLC428 dual op amp have been
found to be a good amplifiers to drive the ADC10D040
because of their wide bandwidth and low distortion. They
also have good Differential Gain and Differential Phase performance.
Care should be taken to avoid driving the input beyond the
supply rails, even momentarily, as during power-up.
The ADC10D040 is designed for differential input signals for
best performance. With a 1.4V reference and the GAIN pin
at a logic low, differential input signals up to 1.4 V
digitized. See Figure 2. For differential signals, the input
common mode is expected to be about 1.5V, but the inputs
www.national.com 20
P-P
are
20029769
FIGURE 2. The ADC10D040 is designed for use with
differential signals of 1.4 V
with a common mode
P-P
voltage of 1.5V. The signal swing should not cause any
pin to experience a swing more than 300 mV beyond
the supply rails.
2.0 REFERENCE INPUTS
The V
and VRNpins should each be bypassed witha5µF
RP
(or larger) tantalum or electrolytic capacitor and a 0.1 µF
ceramic capacitor. Use these pins only for bypassing. DO
NOT connect anything else to these pins.
Figure 4 shows a simple reference biasing scheme with
minimal components. While this circuit will suffice for many
applications, the value of the reference voltage will depend
upon the supply voltage.
The circuit of Figure 5 is an improvement over the circuit of
Figure 4 because the reference voltage is independent of
supply voltage. This reduces problems of reference voltage
Applications Information (Continued)
variability. The reference voltage at the V
bypassed to AGND witha5µF(orlarger) tantalum or
pin should be
REF
The circuit of Figure 6 may be used if it is desired to obtain
a precise reference voltage not available with a fixed reference source. The 604Ω and 1.40k resistors can be replaced
with a potentiometer, if desired.
electrolytic capacitor and a 0.1 µF ceramic capacitor.
20029770
FIGURE 3. Use of an input transformer for single-ended to differential conversion can simplify circuit design for
single-ended signals.
ADC10D040
FIGURE 4. Simple Reference Biasing
20029771
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Applications Information (Continued)
ADC10D040
FIGURE 5. Improved Low Component Count Reference Biasing
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20029772
Applications Information (Continued)
ADC10D040
FIGURE 6. Setting An Accurate Reference Voltage
20029773
www.national.com23
Applications Information (Continued)
ADC10D040
FIGURE 7. The V
The V
output can be used as the ADC reference source
CMO
output pin may be used as an internal reference source if its output is not loaded excessively.
CMO
as long as care is taken to prevent excessive loading of this
pin. However, the V
output was not designed to be a
CMO
precision reference and has move variability than does a
precision reference. Refer to V
, Common Mode Voltage
CMO
Output, in the Electrical Characteristics table. Since the reference input of the ADC10D040 is buffered, there is virtually
no loading on the V
output by the V
CMO
pin. While the
REF
ADC10D040 will work with a 1.5V reference voltage, it is fully
specified for a 1.4V reference. To use the V
ence voltage at 1.4V, the 1.5V V
output needs to be
CMO
CMO
for a refer-
divided down. The divider resistor values need to be carefully chosen to prevent excessive V
7. While the average temperature coefficient of V
loading. See Figure
CMO
CMO
is 30
ppm/˚C, that temperature coefficient can be broken down to
a typical 70 ppm/˚C between −40˚C and +25˚C and a typical
−11 ppm/˚C between +25˚C and +85˚C.
www.national.com 24
20029774
2.1 Reference Voltage
The reference voltage should be within the range specified in
the Operating Ratings table (0.6V to 1.6V). A reference
voltage that is too low could result in a noise performance
that is less than desired because the quantization level falls
below other noise sources. On the other hand, a reference
voltage that is too high means that an input signal that
produces a full scale output uses such a large input range
that the input stage is less linear, resulting in a degradation
of distortion performance. Also, for large reference voltages,
the internal ladder buffer runs out of head-room, leading to a
reduction of gain in that buffer and causing gain error degradation.
The Reference bypass pins V
and VRNare output com-
RP
pensated and should each be bypassed with a parallel combination ofa5µF(minimum) and 0.1 µF capacitors.
Applications Information (Continued)
2.2 V
The V
bias for the differential input pins of the ADC10D040. It can
also be used as a voltage reference source. Care should be
taken, however, to avoid loading this pin with more than 1
mA. A load greater than this could result in degraded long
term and temperature stability of this voltage. The V
is output compensated and should be bypassed with a
1 µF/0.1 µF combination, minimum. See 2.0 REFERENCE
INPUTS for more information on using the V
reference source.
3.0 DIGITAL INPUT PINS
The seven digital input pins are used to control the function
of the ADC10D040.
3.1 The Adc Clock (CLK) Input
The clock (CLK) input is common to both A/D converters.
This pin is CMOS/LVTTL compatible with a threshold of
about V
formance is guaranteed with a 40 MHz clock, it typically will
function well with low-jitter clock frequencies from 20 MHz to
45 MHz. The analog inputs I = (I+) – (I−) and Q = (Q+) –
(Q−) are simultaneously sampled on the falling edge of this
input to ensure the best possible aperture delay match between the two channels.
3.1.1 Low Sample Rate Considerations
While the ADC10D040 will typically function well with sample
rates below 20 MSPS, it is important to note that it is possible
for some production lots not to perform well below 20 MSPS.
To ensure adequate performance over lot to lot and over
temperature extremes, we recommend not operating the
ADC10D040 at sample rates below 20 MSPS.
3.1.2 Clock Termination
The clock source should be series terminated to match the
clock source impedance with the characteristic impedance of
the clock line, Z
the ADC clock pin with a series RC to ground. This series
network should be located near the ADC10D040 clock pin
but on the far side of that pin as seen from the clock source.
The resistor value should equal the characteristic impedance, Z
value such thatCxZ
propagation of the clock signal from its source to the ADC
clock pin. The typical propagation rate on a board of FR4
material is about 150 ps/inch. The rise and fall times of the
clock supplied to the ADC clock pin should be no more than
4 ns.
3.2 Output Bus Select (OS) Pin
The Output Bus Select (OS) pin determines whether the
ADC10D040 is in the parallel or multiplexed mode of operation. A logic high at this pin puts the device into the parallel
mode of operation where “I” and “Q” data appear at their
respective output buses. A logic low at this pin puts the
device into the multiplexed mode of operation where the “I”
and “Q” data are multiplexed onto the “I” output bus and the
“Q” output lines all remain at a logic low.
Output
CMO
output pin is intended to provide a common mode
CMO
output as a
CMO
/2. Although the ADC10D040 is tested and its per-
A
. It may also be necessary to a.c. terminate
O
, of the clock line and the capacitor should have a
O
≥ 4xtPD, where tPDis the time of
O
CMO
pin
3.3 Offset Correct (OC) Pin
The Offset Correct (OC) pin is used to initiate an offset
correction sequence. This procedure should be done after
power up and need not be performed again unless power to
the ADC10D040 is interrupted. An independent offset correction sequence for each converter is initiated when there is
a low-to-high transition at the OC pin. This sequence takes
34 clock cycles to complete, during which time 32 conversions are taken and averaged. The result is subtracted from
subsequent conversions. Because the offset correction is
performed digitally at the output of the ADC, the output range
of the ADC is reduced by the offset amount.
Each input pair should have a 0V differential voltage value
during this entire 34 clock period, but the “I” and “Q” input
common mode voltages do not have to be equal to each
other. Because of the uncertainty as to exactly when the
correction sequence starts, it is best to allow 35 clock periods for this sequence.
3.4 Output Format (OF) Pin
The Output Format (OF) pin provides a choice of straight
binary or 2’s complement output formatting. With this pin at a
logic low, the output format is straight binary. With this pin at
a logic high, the output format is 2’s complement.
3.5 Standby (STBY) Pin
The Standby (STBY) pin may be used to put the
ADC10D040 into a low power mode where it consumes just
30 mW and can quickly be brought to full operation. The
device operates normally with a logic low on this and the PD
pins.
While in the Standby mode the data outputs contain the
results of the last conversion before going into this Mode.
3.6 Power Down (PD) Pin
The Power Down (PD) pin puts the device into a low-power
“sleep” state where it consumes less than 1 mW when the
PD pin is at a logic high. Power consumption is reduced
more when the PD pin is high than when the STBY pin is
high, but recovery to full operation is much quicker from the
standby state than it is from the power down state. When the
STBY and PD pins are both high, the ADC10D040 is in the
power down mode.
While in the Power Down mode the data outputs contain the
results of the last conversion before going into this mode.
3.7 GAIN Pin
The GAIN pin sets the internal signal gain of the “I” and “Q”
inputs. With this pin at a logic low, the full scale differential
peak-to-peak input signal is equal to V
. With the GAIN
REF
pin at a logic high, the full scale differential peak-to-peak
input signal is equal to 2 times V
REF
.
4.0 INPUT/OUTPUT RELATIONSHIP ALTERNATIVES
The GAIN pin of the ADC10D040 offers input range selection, while the OF pin offers a choice of straight binary or 2’s
complement output formatting.
The relationship between the GAIN, OF, analog inputs and
the output code are as defined in Table 1. Keep in mind that
the input signals must not exceed the power supply rails.
ADC10D040
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Applications Information (Continued)
TABLE 1. ADC10D040 Input/Output Relationships
ADC10D040
GAIN OF I+ / Q+ I− / Q− Output Code
00V
00V
00V
01V
01V
01V
10V
10V
10V
11V
11V
11V
CM
CM
CM
CM
CM
CM
CM
CM
+ 0.25*V
CM
− 0.25*V
+ 0.25*V
CM
− 0.25*V
+ 0.5*V
CM
− 0.5*V
+ 0.5*V
CM
− 0.5*V
REF
REF
REF
REF
REF
REF
REF
REF
VCM− 0.25*V
V
CM
VCM+ 0.25*V
VCM− 0.25*V
V
CM
VCM+ 0.25*V
VCM− 0.5*V
V
CM
VCM+ 0.5*V
VCM− 0.5*V
V
CM
VCM+ 0.5*V
REF
REF
REF
REF
REF
REF
REF
REF
11 1111 1111
10 0000 0000
00 0000 0000
01 1111 1111
00 0000 0000
10 0000 0000
11 1111 1111
10 0000 0000
00 0000 0000
01 1111 1111
00 0000 0000
10 0000 0000
5.0 POWER SUPPLY CONSIDERATIONS
A/D converters draw sufficient transient current to corrupt
their own power supplies if not adequately bypassed. A
10 µF to 50 µF tantalum or aluminum electrolytic capacitor
should be placed within half an inch (1.2 centimeters) of the
A/D power pins, with a 0.1 µF ceramic chip capacitor placed
as close as possible to each of the converter’s power supply
pins. Leadless chip capacitors are preferred because they
have low lead inductance.
While a single voltage source should be used for the analog
and digital supplies of the ADC10D040, these supply pins
should be well isolated from each other to prevent any digital
noise from being coupled to the analog power pins. A choke
is recommended between the V
and VDsupply lines. V
A
DR
should have a separate supply from VAand VDto avoid
noise coupling into the input. Be sure to bypass V
The V
pin is completely isolated from the other supply
DR
.
DR
pins. Because of this isolation, a separate supply can be
used for these pins. This V
supply can be significantly
DR
lower than the three volts used for the other supplies, easing
the interface to lower voltage digital systems. Using a lower
voltage for this supply can also reduce the power consumption and noise associated with the output drivers.
The converter digital supply should not be the supply that is
used for other digital circuitry on the board. It should be the
same supply used for the ADC10D040 analog supply.
As is the case with all high speed converters, the
ADC10D040 should be assumed to have little high frequency power supply rejection.A clean analog power source
should be used.
No pin should ever have a voltage on it that is more than
300 mV in excess of the supply voltages or below ground,
not even on a transient basis. This can be a problem upon
application of power to a circuit and upon turn off of the
power source. Be sure that the supplies to circuits driving the
CLK, or any other digital or analog inputs do not come up
any faster than does the voltage at the ADC10D040 power
pins.
6.0 LAYOUT AND GROUNDING
Proper routing of all signals and proper ground techniques
are essential to ensure accurate conversion. Separate analog and digital ground planes may be used if adequate care
is taken with signal routing, but may result in EMI/RFI. A
single ground plane with proper component placement will
yield good results while minimizing EMI/RFI.
Analog and digital ground current paths should not coincide
with each other as the common impedance will cause digital
noise to be added to analog signals. Accordingly, traces
carrying digital signals should be kept as far away from
traces carrying analog signals as is possible. Power should
be routed with traces rather than the use of a power plane.
The analog and digital power traces should be kept well
away from each other. All power to the ADC10D040, except
, should be considered analog. The DR GND pin should
V
DR
be considered a digital ground and not be connected to the
ground plane in close proximity with the other ground pins of
the ADC10D040.
Each bypass capacitor should be located as close to the
appropriate converter pin as possible and connected to the
pin and the appropriate ground plane with short traces. The
analog input should be isolated from noisy signal traces to
avoid coupling of spurious signals into the input. Any external component (e.g., a filter capacitor) connected between
the converter’s input and ground should be connected to a
very clean point in the ground return.
The clock line should be properly terminated, as discussed
in Section 3.1, and be as short as possible.
Figure 8 gives an example of a suitable layout and bypass
capacitor placement. All analog circuitry (input amplifiers,
filters, reference components, etc.) and interconnections
should be placed in an area reserved for analog circuitry. All
digital circuitry and I/O lines should be placed in an area
reserved for digital circuitry. Violating these rules can result
in digital noise getting into the analog circuitry, which will
degrade accuracy and dynamic performance (THD, SNR,
SINAD).
www.national.com 26
Applications Information (Continued)
FIGURE 8. An Acceptable Layout Pattern
ADC10D040
20029775
7.0 DYNAMIC PERFORMANCE
The ADC10D040 is a.c. tested and its dynamic performance
is guaranteed. To meet the published specifications, the
clock source driving the CLK input must be free of jitter. For
best dynamic performance, isolating the ADC clock from any
digital circuitry should be done with adequate buffers, as with
a clock tree. See Figure 9.
20029776
FIGURE 9. Isolating the ADC Clock from Digital
Circuitry
8.0 COMMON APPLICATION PITFALLS Driving the inputs (analog or digital) beyond the power
supply rails. For proper operation, no input should go more
than 300 mV beyond the supply pins, Exceeding these limits
on even a transient basis can cause faulty or erratic operation. It is not uncommon for high speed digital circuits (e.g.,
74F and 74AC devices) to exhibit overshoot and undershoot
that goes a few hundred millivolts beyond the supply rails. A
resistor of 50Ω to 100Ω in series with the offending digital
input, close to the source, will usually eliminate the problem.
Care should be taken not to overdrive the inputs of the
ADC10D040 (or any device) with a device that is powered
from supplies outside the range of the ADC10D040 supply.
Such practice may lead to conversion inaccuracies and even
to device damage.
Attempting to drive a high capacitance digital data bus.
The more capacitance the output drivers have to charge for
each conversion, the more instantaneous digital current is
required from V
and DR GND. These large charging cur-
DR
rent spikes can couple into the analog section, degrading
dynamic performance. Adequate bypassing and attention to
board layout will reduce this problem. Buffering the digital
data outputs (with a 74ACTQ841, for example) may be
necessary if the data bus to be driven is heavily loaded.
Dynamic performance can also be improved by adding series resistors of 47Ω to 56Ω at each digital output, close to
the ADC output pins.
Using a clock source with excessive jitter. This will cause
the sampling interval to vary, causing excessive output noise
and a reduction in SNR and SINAD performance. The use of
simple gates with RC timing as a clock source is generally
inadequate.
Using the same voltage source for V
tal logic. As mentioned in Section 5.0, V
same power source used by V
A
nents, but should be decoupled from V
and external digi-
D
should use the
D
and other analog compo-
.
A
www.national.com27
Physical Dimensions inches (millimeters) unless otherwise noted
NOTES UNLESS OTHERWISE SPECIFIED
1. STANDARD LEAD FINISH
7.62 MICROMETERS MINIMUM SOLDER PLATING (85/15)
THICKNESS ON ALLOY 42/COPPER.
2. DIMENSION DOES NOT INCLUDE MOLD PROTRUSION.
MAXIMUM ALLOWABLE MOLD PROTRUSION 0.15 mm PER SIDE.
3. REFERENCE JEDEC REGISTRATION MS-026, VARIATION ABC,
DATED FEBRUARY 1999.
48-Lead TQFP Package
ADC10D040 Dual 10-Bit, 40 MSPS, 267 mW A/D Converter
Ordering Number ADC10D040CIVS
NS Package Number VBA48A
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