Rainbow Electronics ADC10D040 User Manual

ADC10D040
Dual 10-Bit, 40 MSPS, 267 mW A/D Converter

ADC10D040 Dual 10-Bit, 40 MSPS, 267 mW A/D Converter

September 2003

General Description

The ADC10D040 is a dual low power, high performance
CMOS analog-to-digital converter that digitizes signals to 10
bits resolution at sampling rates up to 45 MSPS while con­suming a typical 267 mW from a single 3.3V supply. No
missing codes is guaranteed over the full operating tempera­ture range. The unique two stage architecture achieves 9.4
Effective Bits over the entire Nyquist band at 40 MHz sample
rate. An output formatting choice of straight binary or 2’s
complement coding and a choice of two gain settings eases
the interface to many systems. Also allowing great flexibility
of use is a selectable 10-bit multiplexed or 20-bit parallel
output mode. An offset correction feature minimizes the off­set error.

To ease interfacing to most low voltage systems, the digital
output power pins of the ADC10D040 can be tied to a
separate supply voltage of 1.5V to 3.6V, making the outputs
compatible with other low voltage systems. When not con­verting, power consumption can be reduced by pulling the
PD (Power Down) pin high, placing the converter into a low
power state where it typically consumes less than 1 mW and
from which recovery is less than 1 ms. Bringing the STBY
(Standby) pin high places the converter into a standby mode
where power consumption is about 30 mW and from which
recovery is 800 ns.

The ADC10D040’s speed, resolution and single supply op­eration make it well suited for a variety of applications,
including high speed portable applications.

Operating over the industrial (−40˚ ≤ T
ture range, the ADC10D040 is available in a 48-pin TQFP. An
evaluation board is available to ease the design effort.

≤ +85˚C) tempera-

A

Features

n Internal sample-and-hold
n Internal Reference Capability
n Dual gain settings
n Offset correction
n Selectable straight binary or 2’s complement output
n Multiplexed or parallel output bus
n Single +3.0V to 3.6V operation
n Power down and standby modes
n 3V TTL Logic input/output compatible

Key Specifications

n Resolution 10 Bits
n Conversion Rate 40 MSPS
n ENOB 9.4 Bits (typ)
n DNL 0.35 LSB (typ)
n Conversion Latency Parallel Outputs 2.5 Clock Cycles

— Multiplexed Outputs, I Data Bus 2.5 Clock Cycles
— Multiplexed Outputs, Q Data Bus 3 Clock Cycles

n PSRR 90 dB
n Power Consumption— Normal Operation 267 mW (typ)

— Power Down Mode
— Fast Recovery Standby Mode 30 mW (typ)

<

1 mW (typ)

Applications

n Digital Video
n CCD Imaging
n Portable Instrumentation
n Communications
n Medical Imaging
n Ultrasound

© 2003 National Semiconductor Corporation DS200297 www.national.com

Connection Diagram

ADC10D040

Ordering Information

Industrial Temperature Range

TOP VIEW

(−40˚C ≤ T

ADC10D040CIVS TQFP

ADC10D040EVAL Evaluation Board

≤ +85˚C)

A

NS Package

20029701

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Block Diagram

ADC10D040

Pin Descriptions and Equivalent Circuits

Pin No. Symbol Equivalent Circuit Description

48
47

37
38

1V

I+
I−

Q+
Q−

REF

Analog inputs to “I” ADC. With V
is 1.15V to 1.85V with GAIN pin low, or 0.8V to 2.2V with
GAIN pin high.

Analog inputs to “Q” ADC. With V
range is 1.15V to 1.85V with GAIN pin low, or 0.8V to 2.2V
with GAIN pin high.

Analog Reference Voltage input. The voltage at this pin
should be in the range of 0.6V to 1.6V. With 1.4V at this pin
and the GAIN pin low, the full scale differential inputs are

1.4 V

. With 1.4V at this pin and the GAIN pin high, the full

P-P

scale differential inputs are 2.8 V
bypassed with a minimum 1 µF capacitor.

REF

REF

P-P

20029702

= 1.4V, conversion range

= 1.4V, conversion

. This pin should be

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Pin Descriptions and Equivalent Circuits (Continued)

Pin No. Symbol Equivalent Circuit Description

ADC10D040

This is an analog output which can be used as a reference
source and/or to set the common mode voltage of the input. It

45 V

43 V

44 V

CMO

RP

RN

should be bypassed with a minimum of 1 µF low ESR
capacitor in parallel with a 0.1 µF capacitor. This pin has a
nominal output voltage of 1.5V and hasa1mAoutput source
capability.

Top of the reference ladder. Do not drive this pin. Bypass
this pin with a 10 µF low ESR capacitor and a 0.1 µF
capacitor.

Bottom of the reference ladder. Do not drive this pin.
Bypass this pin with a 10 µF low ESR capacitor and a 0.1 µF
capacitor.

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Pin Descriptions and Equivalent Circuits (Continued)

Pin No. Symbol Equivalent Circuit Description

33 CLK

2OS

31 OC

32 OF

34 STBY

35 PD

36 GAIN

8 thru 27 I0–I9 and Q0–Q9

28 I/Q

40, 41 V

A

Digital clock input for both converters. The analog inputs are
sampled on the falling edge of this clock input.

Output Bus Select. With this pin at a logic high, both the “I”
and the “Q” data are present on their respective 10-bit output
buses (Parallel mode of operation). When this pin is at a logic
low, the “I” and “Q” data are multiplexed onto the “I” output
bus and the “Q” output lines all remain at a logic low
(multiplexed mode).

Offset Correct pin. A low-to-high transition on this pin initiates
an independent offset correction sequence for each converter,
which takes 34 clock cycles to complete. During this time 32
conversions are taken and averaged. The result is subtracted
from subsequent conversions. Each input pair should have 0V
differential value during this entire 34 clock period.

Output Format pin. When this pin is LOW the output format is
Straight Binary. When this pin is HIGH the output format is 2’s
complement. This pin may be changed asynchronously, but
this will result in errors for one or two conversions.

Standby pin. The device operates normally with a logic low on
this and the PD (Power Down) pin. With this pin at a logic
high and the PD pin at a logic low, the device is in the
standby mode where it consumes just 30 mW of power. It
takes just 800 ns to come out of this mode after the STBY pin
is brought low.

Power Down pin that, when high, puts the converter into the
Power Down mode where it consumes just 1 mW of power. It
takes less than 1 ms to recover from this mode after the PD
pin is brought low. If both the STBY and PD pins are high
simultaneously, the PD pin dominates.

This pin sets the internal signal gain at the inputs to the
ADCs. With this pin low the full scale differential input
peak-to-peak signal is equal to V

REF

full scale differential input peak-to-peak signal is equal to 2 x

.

V

REF

3V TTL/CMOS-compatible Digital Output pins that provide the
conversion results of the I and Q inputs. I0 and Q0 are the
LSBs, I9 and Q9 are the MSBs. Valid data is present just
after the rising edge of the CLK input in the Parallel mode. In
the multiplex mode, I-channel data is valid on I0 through I9
when the I/Q output is high and the Q-channel data is valid
on I0 through I9 when the I/Q output is low.

Output data valid signal. In the multiplexed mode, this pin
transitions from low to high when the data bus transitions
from Q-data to I-data, and from high to low when the data bus
transitions from I-data to Q-data. In the Parallel mode, this pin
transitions from low to high as the output data changes.

Positive analog supply pin. This pin should be connected to a
quiet voltage source of +3.0V to +3.6V. V
have a common supply and be separately bypassed with
10 µF to 50 µF capacitors in parallel with 0.1 µF capacitors.

. With this pin high the

and VDshould

A

ADC10D040

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Pin Descriptions and Equivalent Circuits (Continued)

Pin No. Symbol Equivalent Circuit Description

ADC10D040

4V

6, 30 V

3, 39, 42,

46

5 DGND

7, 29 DR GND The ground return of the digital output drivers.

D

DR

AGND

Digital supply pin. This pin should be connected to a quiet
voltage source of +3.0V to +3.6V. V
common supply and be separately bypassed with 10 µF to 50
µF capacitors in parallel with 0.1 µF capacitors.

Digital output driver supply pins. These pins should be
connected to a voltage source of +1.5V to V
bypassed with 10 µF to 50 µF capacitors in parallel with 0.1
µF capacitors.

The ground return for the analog supply. AGND and DGND
should be connected together close to the ADC10D040
package.

The ground return for the digital supply. AGND and DGND
should be connected together close to the ADC10D040
package.

and VDshould have a

A

and be

D

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ADC10D040

Absolute Maximum Ratings (Notes 1,

2)

If Military/Aerospace specified devices are required,
please contact the National Semiconductor Sales Office/
Distributors for availability and specifications.

Positive Supply Voltages 3.8V

Voltage on Any Pin −0.3V to (V

Input Current at Any Pin (Note 3)

Package Input Current (Note 3)

Package Dissipation at T

= 25˚C See (Note 4)

A

ESD Susceptibility (Note 5)

Human Body Model 2500V

Machine Model 250V

or VD+0.3V)

A

±

25 mA

±

50 mA

Operating Ratings (Notes 1, 2)

Operating Temperature Range −40˚C ≤ T

V

Supply Voltage +3.0V to +3.6V

A,VD

V

Supply Voltage +1.5V to V

DR

VINDifferential Voltage Range

GAIN = Low

GAIN = High

VCMInput Common Mode Range

GAIN = Low V

GAIN = High V

V

Voltage Range 0.6V to 1.8V

REF

Digital Input Pins Voltage

Range −0.3V to (V

Soldering Temperature,

Infrared, 10 sec. (Note 6) 235˚C

Storage Temperature −65˚C to +150˚C

Converter Electrical Characteristics

The following specifications apply for VA=VD= +3.3 VDC,VDR= +2.5 VDC,V
(a.c. coupled) = FSR = 1.4 V
rected. Boldface limits apply for T

P-P,CL

= 15 pF, f

A=TMIN

= 40 MHz, 50% Duty Cycle, RS=50Ω,trc=t

CLK

to T

: all other limits TA= 25˚C (Note 7).

MAX

Symbol Parameter Conditions

STATIC CONVERTER CHARACTERISTICS

INL Integral Non-Linearity

DNL Differential Non-Linearity

Resolution with No Missing Codes 10 Bits

Without Offset Correction −3.3

V

OFF

Offset Error

With Offset Correction +0.4

GE Gain Error −4

DYNAMIC CONVERTER CHARACTERISTICS

= 4.43 MHz, VIN= FSR −0.1 dB 9.5 Bits

f

IN

f

ENOB Effective Number of Bits

SINAD

Signal-to-Noise Plus Distortion
Ratio

SNR Signal-to-Noise Ratio

THD Total Harmonic Distortion

HS2 Second Harmonic

HS3 Third Harmonic

= 10.4 MHz, VIN= FSR −0.1 dB, TA= 25˚C 9.5 9.1 Bits (min)

IN

f

= 19.7 MHz, VIN= FSR −0.1 dB 9.4 Bits

IN

= 4.43 MHz, VIN= FSR −0.1 dB 59 dB

f

IN

f

= 10.4 MHz, VIN= FSR −0.1 dB, TA= 25˚C 59 56.3 dB (min)

IN

f

= 19.7 MHz, VIN= FSR −0.1 dB 58 dB

IN

= 4.43 MHz, VIN= FSR −0.1 dB 60 dB

f

IN

f

= 10.4 MHz, VIN= FSR −0.1 dB, TA= 25˚C 60 57.3 dB (min)

IN

f

= 19.7 MHz, VIN= FSR −0.1 dB 59 dB

IN

= 4.43 MHz, VIN= FSR −0.1 dB −70 dB

f

IN

f

= 10.4 MHz, VIN= FSR −0.1 dB, TA= 25˚C −69 −61 dB (min)

IN

f

= 19.7 MHz, VIN= FSR −0.1 dB −67 dB

IN

= 4.43 MHz, VIN= FSR −0.1 dB −86 dB

f

IN

f

= 10.4 MHz, VIN= FSR −0.1 dB −83 dB

IN

f

= 19.7 MHz, VIN= FSR −0.1 dB −81 dB

IN

= 4.43 MHz, VIN= FSR −0.1 dB −73 dB

f

IN

f

= 10.4 MHz, VIN= FSR −0.1 dB −73 dB

IN

f

= 19.7 MHz, VIN= FSR −0.1 dB −72 dB

IN

= 1.4 VDC, GAIN = OF = 0V, OS = 3.3V, V

REF

Typical

(Note 8)

/4 to (VA–V

REF

/2 to (VA–V

REF

<

4 ns, NOT offset cor-

fc

Limits

(Note 9)

±

±

0.65

0.35

±

1.9 LSB (max)

+1.2

−1.0

+7

−12

+1.5

−0.5

+5

−12

≤ +85˚C

A

D

±

V

/2

REF

±

V

REF

/4)

REF

/2)

REF

+0.3V)

A

IN

Units

(Limits)

LSB (max)

LSB (min)

LSB (max)

LSB (min)

LSB (max)

LSB (min)

%FS (max)

%FS (min)

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Converter Electrical Characteristics (Continued)

The following specifications apply for VA=VD= +3.3 VDC,VDR= +2.5 VDC,V
(a.c. coupled) = FSR = 1.4 V
rected. Boldface limits apply for T

ADC10D040

P-P,CL

= 15 pF, f

A=TMIN

= 40 MHz, 50% Duty Cycle, RS=50Ω,trc=t

CLK

to T

: all other limits TA= 25˚C (Note 7).

MAX

Symbol Parameter Conditions

= 4.43 MHz, VIN= FSR −0.1 dB 72 dB

f

IN

f

SFDR Spurious Free Dynamic Range

IMD Intermodulation Distortion

Overrange Output Code (V

Underrange Output Code (V

= 10.4 MHz, VIN= FSR −0.1 dB 72 dB

IN

f

= 19.7 MHz, VIN= FSR −0.1 dB 70 dB

IN

<

f

8.5 MHz, VIN= FSR −6.1 dB

IN1

<

f

9.5 MHz, VIN= FSR −6.1 dB

IN2

IN+−VIN−

IN+−VIN−

)>1.5V 1023

)<−1.5V 0

FPBW Full Power Bandwidth 140 MHz

INTER-CHANNEL CHARACTERISTICS

Crosstalk

Channel - Channel Aperture Delay
Match

1 MHz input to tested channel, 10.3 MHz input
to other channel

f

= 8 MHz 8.5 ps

IN

Channel - Channel Gain Matching 0.1 %FS

REFERENCE AND ANALOG CHARACTERISTICS

V

C

R

V

I

REF

V

TC
V

Analog Differential Input Range

IN

Analog Input Capacitance (each

IN

input)

Analog Differential Input

IN

Resistance

Reference Voltage 1.4

REF

Reference Input Current

Common Mode Voltage Output

CMO

Common Mode Voltage
Temperature Coefficient

CMO

Gain Pin = AGND 1.4 V

Gain Pin = V

A

Clock High 6 pF

Clock Low 3 pF

1 mA load to ground
(sourcing current)

DIGITAL INPUT CHARACTERISTICS

V

V

I

IH

I

IL

Logical “1” Input Voltage VD= +3.0V 2.0 V (min)

IH

Logical “0” Input Voltage VD= +3.6V 0.5 V (max)

IL

Logical “1” Input Current VIH=V

D

Logical “0” Input Current VIL= DGND

DIGITAL OUTPUT CHARACTERISTICS

V

V

+I

−I

Logical “1” Output Voltage VDR= +2.5V, I

OH

Logical “0” Output Voltage VDR= +2.5V, I

OL

Output Short Circuit Source

SC

Current

Output Short Circuit Sink Current V

SC

=0V

V

OUT

OUT=VDR

= −0.5 mA

OUT

= 1.6 mA 0.4 V (max)

OUT

Parallel Mode −4.7 mA

Multiplexed Mode −9 mA

Parallel Mode 4.7 mA

Multiplexed Mode 9 mA

POWER SUPPLY CHARACTERISTICS

PD = LOW, STBY = LOW, d.c. input 70 80 mA (max)

I

A

Analog Supply Current

PD = LOW, STBY = HIGH 10 mA

PD = HIGH, STBY = LOW or HIGH 0.1 mA

= 1.4 VDC, GAIN = OF = 0V, OS = 3.3V, V

REF

<

4 ns, NOT offset cor-

fc

Typical

(Note 8)

Limits

(Note 9)

71 dB

−72 dB

2.8 V

13.5 kΩ

0.6 V (min)

1.6 V (max)

<

1µA

1.5

1.35 V (min)

1.6 V (max)

30 ppm/˚C

<

1µA

>

−1 µA

V

DR

−0.2V

IN

Units

(Limits)

P-P

P-P

V (min)

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Converter Electrical Characteristics (Continued)

The following specifications apply for VA=VD= +3.3 VDC,VDR= +2.5 VDC,V
(a.c. coupled) = FSR = 1.4 V
rected. Boldface limits apply for T

P-P,CL

= 15 pF, f

A=TMIN

= 40 MHz, 50% Duty Cycle, RS=50Ω,trc=t

CLK

to T

: all other limits TA= 25˚C (Note 7).

MAX

Symbol Parameter Conditions

PD = LOW, STBY = LOW, d.c. input 9 10 mA (max)

I

D

Digital Supply Current

PD = LOW, STBY = HIGH 0.1 mA

PD = HIGH, STBY = LOW or HIGH 0.1 mA

I

DR

Digital Output Driver Supply
Current (Note 10)

PD = STBY = LOW, dc input 1.9 2.5 mA (max)

PD = LOW, STBY = LOW, d.c. input 267 305 mW (max)

PD Power Consumption

PD = LOW, STBY = LOW, 1 MHz Input 270 mW

PD = LOW, STBY = HIGH 30 mW

PD = HIGH, STBY = LOW or HIGH 0.6 mW

PSRR1 Power Supply Rejection Ratio

PSRR2 Power Supply Rejection Ratio

Change in Full Scale with 3.0V to 3.6V Supply
Change

Rejection at output with 10.3 MHz, 250 mV
Riding on VAand V

D

= 1.4 VDC, GAIN = OF = 0V, OS = 3.3V, V

REF

P-P

AC Electrical Characteristics OS = Low (Multiplexed Mode)

The following specifications apply for VA=VD= +3.3 VDC,VDR= +2.5VDC,V
(a.c. coupled) = FSR = 1.4 V
rected. Boldface limits apply for T

P-P,CL

= 15 pF, f

A=TMIN

= 40 MHz, 50% Duty Cycle, RS=50Ω,trc=t

CLK

to T

: all other limits TA= 25˚C (Note 7)

MAX

Symbol Parameter Conditions

1

f

CLK

f

CLK

Maximum Clock Frequency 45 40 MHz (min)

2

Minimum Clock Frequency 20 MHz

Duty Cycle 50

Pipeline Delay (Latency)

I Data 2.5 Clock Cycles

Q Data 3.0 Clock Cycles

t

t

t

r,tf

OC

OD

Output Rise and Fall Times 5 ns

Offset Correction Pulse Width 10 ns (min)

Output Delay from CLK Edge to
Data Valid

t

DIQ

t

SKEW

t

AD

t

AJ

t

VALID

t

WUPD

I/Q Output Delay 13 ns

I/Q to Data Skew

Sampling (Aperture) Delay 2.2 ns

Aperture Jitter

Data Valid Time 7.5 ns

Overrange Recovery Time

Differential V
0V

step from 1.5V to

IN

PD Low to 1/2 LSB Accurate
Conversion (Wake-Up Time)

t

WUSB

STBY Low to 1/2 LSB Accurate
Conversion (Wake-Up Time)

= 1.4 VDC, GAIN = OF = 0V, OS = 0V, V

REF

Typical

(Note 8)

13 19 ns (max)

±

200 ps

<

50 ns

<

800 ns

ADC10D040

<

4 ns, NOT offset cor-

fc

Typical

(Note 8)

Limits

(Note 9)

90 dB

52 dB

<

4 ns, NOT offset cor-

fc

Limits

(Note 9)

45
55

(Limits)

% (min)

% (max)

10 ps (rms)

1ms

IN

Units

(Limits)

IN

Units

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