Rainbow Electronics ADC10D020 User Manual

ADC10D020
Dual 10-Bit, 20 MSPS, 150 mW A/D Converter

ADC10D020 Dual 10-Bit, 20 MSPS, 150 mW A/D Converter

April 2002

General Description

The ADC10D020 is a dual low power, high performance
CMOS analog-to-digital converter that digitizes signals to 10
bits resolution at sampling rates up to 30 MSPS while con­suming a typical 150 mW from a single 3.0V supply. No
missing codesisguaranteed over the full operating tempera­ture range. The unique two stage architecture achieves 9.5
Effective Bits over the entire Nyquist band at 20 MHz sample
rate. An output formatting choice of straight binary or 2’s
complement coding and a choice of two gain settings eases
the interface to many systems. Also allowing great flexibility
of use is a selectable 10-bit multiplexed or 20-bit parallel
output mode. An offset correction feature minimizes the off­set error.

To ease interfacing to most low voltage systems, the digital
output power pins of the ADC10D020 can be tied to a
separate supply voltage of 1.5V to 3.6V, making the outputs
compatible with other low voltage systems. When not con­verting, power consumption can be reduced by pulling the
PD (Power Down) pin high, placing the converter into a low
power state where it typically consumes less than 1 mW and
from which recovery is less than 1 ms. Bringing the STBY
(Standby) pin high places the converter into a standby mode
where power consumption is about 27 mW and from which
recovery is 800 ns.

The ADC10D020’s speed, resolution and single supply op­eration makes it well suited for a variety of applications,
including high speed portable applications.

Operating over the industrial (−40˚ ≤ T
ture range, theADC10D020 is available in a 48-pinTQFP.An
evaluation board is available to ease the design effort.

≤ +85˚C) tempera-

A

Features

n Internal sample-and-hold
n Internal reference capability
n Dual gain settings
n Offset correction
n Selectable straight binary or 2’s complement output
n Multiplexed or parallel output bus
n Single +2.7V to 3.6V operation
n Power down and standby modes

Key Specifications

n Resolution 10 Bits
n Conversion Rate 20 MSPS
n ENOB 9.5 Bits (typ)
n DNL 0.35 LSB (typ)
n Conversion Latency Parallel Outputs 2.5 Clock Cycles

— Multiplexed Outputs, I Data Bus 2.5 Clock Cycles
— Multiplexed Outputs, Q Data Bus 3 Clock Cycles

n PSRR 90 dB
n Power Consumption—Normal Operation 150 mW (typ)

— Power Down Mode
— Fast Recovery Standby Mode 27 mW (typ)

<

1 mW (typ)

Applications

n Digital Video
n CCD Imaging
n Portable Instrumentation
n Communications
n Medical Imaging
n Ultrasound

© 2002 National Semiconductor Corporation DS200255 www.national.com

Connection Diagram

ADC10D020

Ordering Information

Industrial Temperature Range

TOP VIEW

(−40˚C ≤ T

ADC10D020CIVS TQFP

ADC10D020EVAL Evaluation Board

≤ +85˚C)

A

NS Package

20025501

www.national.com 2

Block Diagram

ADC10D020

20025502

www.national.com3

Pin Descriptions and Equivalent Circuits

Pin No. Symbol Equivalent Circuit Description

ADC10D020

48
47

I+
I−

Analog inputs to “I” ADC. Nominal conversion range is 1.25V
to 1.75V with GAIN pin low, or 1.0V to 2.0V with GAIN pin
high.

37
38

1V

45 V

43 V

Q+
Q−

REF

CMO

RP

Analog inputs to “Q” ADC. Nominal conversion range is 1.25V
to 1.75V with GAIN pin low, or 1.0V to 2.0V with GAIN pin
high.

Analog Reference Voltage input. The voltage at this pin
should be in the range of 0.8V to 1.5V. With 1.0V at this pin

low

and the GAIN pin

. With 1.0V at this pin and the GAIN pin

1V

P-P

scale differential inputs are 2 V

, the full scale differential inputs are

high

, the full

. This pin should be

P-P

bypassed with a minimum 1 µF capacitor.

This is an analog output which can be used as a reference
source and/or to set the common mode voltage of the input. It
should be bypassed with a minimum of 1 µF low ESR
capacitor in parallel with a 0.1 µF capacitor. This pin has a
nominal output voltage of 1.5V and hasa1mAoutput source
capability.

Top of the reference ladder. Do not drive this pin. Bypass
this pin with a 10 µF low ESR capacitor and a 0.1 µF
capacitor.

44 V

www.national.com 4

RN

Bottom of the reference ladder. Do not drive this pin.
Bypass this pin with a 10 µF low ESR capacitor and a 0.1 µF
capacitor.

Pin Descriptions and Equivalent Circuits (Continued)

Pin No. Symbol Equivalent Circuit Description

33 CLK

2OS

31 OC

32 OF

34 STBY

35 PD

36 GAIN

8 thru 27 I0–I9 and Q0–Q9

28 I/Q

40, 41 V

A

Digital clock input for both converters. The analog inputs are
sampled on the falling edge of this clock input.

Output Bus Select. With this pin at a logic high, both the “I”
and the “Q” data are present on their respective 10-bit output
buses (Parallel mode of operation). When this pin is at a logic
low, the “I” and “Q” data are multiplexed onto the “I” output
bus and the “Q” output lines all remain at a logic low
(multiplexed mode).

Offset Correct pin. A low-to-high transition on this pin initiates
an independent offset correction sequence for each converter,
which takes 34 clock cycles to complete. During this time 32
conversions are taken and averaged. The result is subtracted
from subsequent conversions. Each input pair should have 0V
differential value during this entire 34 clock period.

Output Format pin. When this pin is LOW the output format is
Straight Binary. When this pin is HIGH the output format is 2’s
complement. This pin may be changed asynchronously, but
this will result in errors for one or two conversions.

Standby pin. The device operates normally with a logic low on
this and the PD (Power Down) pin. With this pin at a logic
high and the PD pin at a logic low, the device is in the
standby mode where it consumes just 27 mW of power. It
takes just 800 ns to come out of this mode after the STBY pin
is brought low.

Power Down pin that, when high, puts the converter into the
Power Down mode where it consumes less than 1 mW of
power. It takes less than 1 ms to recover from this mode after
the PD pin is brought low. If both the STBY and PD pins are
high simultaneously, the PD pin dominates.

This pin sets the internal signal gain at the inputs to the
ADCs. With this pin low the full scale differential input
peak-to-peak signal is equal to V

REF

full scale differential input peak-to-peak signal is equal to 2 x

.

V

REF

3V TTL/CMOS-compatible Digital Output pins that provide the
conversion results of the I and Q inputs. I0 and Q0 are the
LSBs, I9 and Q9 are the MSBs. Valid data is present just after
the rising edge of the CLK input in the Parallel mode. In the
multiplexed mode, I-channel data is valid on I0 through I9
when the I/Q output is high and the Q-channel data is valid
on I0 through I9 when the I/Q output is low.

Output data valid signal. In the multiplexed mode, this pin
transitions from low to high when the data bus transitions
from Q-data to I-data, and from high to low when the data bus
transitions from I-data to Q-data. In the Parallel mode, this pin
transitions from low to high as the output data changes.

Positive analog supply pin. This pin should be connected to a
quiet voltage source of +2.7V to +3.6V. V
have a common supply and be separately bypassed with
10 µF to 50 µF capacitors in parallel with 0.1 µF capacitors.

. With this pin high the

and VDshould

A

ADC10D020

www.national.com5

Pin Descriptions and Equivalent Circuits (Continued)

Pin No. Symbol Equivalent Circuit Description

ADC10D020

4V

6, 30 V

3, 39, 42,

46

5 DGND

7, 29 DR GND The ground return of the digital output drivers.

D

DR

AGND

Digital supply pin. This pin should be connected to a quiet
voltage source of +2.7V to +3.6V. V
common supply and be separately bypassed with 10 µF to 50
µF capacitors in parallel with 0.1 µF capacitors.

Digital output driver supply pins. These pins should be
connected to a voltage source of +1.5V to V
bypassed with 10 µF to 50 µF capacitors in parallel with 0.1
µF capacitors.

The ground return for the analog supply. AGND and DGND
should be connected together close to the ADC10D020
package.

The ground return for the digital supply. AGND and DGND
should be connected together close to the ADC10D020
package.

and VDshould have a

A

and be

D

www.national.com 6

ADC10D020

Absolute Maximum Ratings (Notes 1,

2)

If Military/Aerospace specified devices are required,
please contact the National Semiconductor Sales Office/
Distributors for availability and specifications.

Positive Supply Voltages 3.8V
Voltage on Any Pin −0.3V to (V
Input Current at Any Pin (Note 3)
Package Input Current (Note 3)
Package Dissipation at T

= 25˚C See (Note 4)

A

ESD Susceptibility (Note 5)

Human Body Model 2500V
Machine Model 250V

or VD+0.3V)

A

±

25 mA

±

50 mA

Operating Ratings (Notes 1, 2)

Operating Temperature Range −40˚C ≤ T
V

Supply Voltage +2.7V to +3.6V

A,VD

V

Supply Voltage +1.5V to V

DR

VINDifferential Voltage Range

GAIN = Low
GAIN = High

VCMInput Common Mode Range

GAIN = Low V
GAIN = High V

V

Voltage Range 0.8V to 1.5V

REF

Digital Input Pins Voltage

Range −0.3V to (V

Soldering Temperature,

Infrared, 10 sec. (Note 6) 235˚C

Storage Temperature −65˚C to +150˚C

Converter Electrical Characteristics

The following specifications apply for VA=VD=VDR= +3.0 VDC,V
coupled) = FSR = 1.0 V

Boldface limits apply for T

P-P,CL

A=TMIN

= 15 pF, f

to T

= 20 MHz, 50% Duty Cycle, RS=50Ω,trc=t

CLK

: all other limits TA= 25˚C (Note 7).

MAX

Symbol Parameter Conditions

STATIC CONVERTER CHARACTERISTICS
INL Integral Non-Linearity

DNL Differential Non-Linearity

Resolution with No Missing Codes 10 Bits

Without Offset Correction −5

V

OFF

Offset Error

With Offset Correction +0.5

GE Gain Error −4
DYNAMIC CONVERTER CHARACTERISTICS

= 1.0 MHz, VIN= FSR −0.1 dB 9.5 Bits

f

IN

f

= 4.7 MHz, VIN= FSR −0.1 dB 9.5 9.0 Bits(min)

ENOB Effective Number of Bits

SINAD

Signal-to-Noise Plus Distortion
Ratio

SNR Signal-to-Noise Ratio

THD Total Harmonic Distortion

IN

f

= 9.5 MHz, VIN= FSR −0.1 dB 9.5 Bits

IN

f

= 19.5 MHz, VIN= FSR −0.1 dB 9.5 Bits

IN

= 1.0 MHz, VIN= FSR −0.1 dB 59 dB

f

IN

f

= 4.7 MHz, VIN= FSR −0.1 dB 59 56 dB(min)

IN

f

= 9.5 MHz, VIN= FSR −0.1 dB 59 dB

IN

f

= 19.5 MHz, VIN= FSR −0.1 dB 59 dB

IN

= 1.0 MHz, VIN= FSR −0.1 dB 59 dB

f

IN

f

= 4.7 MHz, VIN= FSR −0.1 dB 59 56 dB(min)

IN

f

= 9.5 MHz, VIN= FSR −0.1 dB 59 dB

IN

f

= 19.5 MHz, VIN= FSR −0.1 dB 59 dB

IN

= 1.0 MHz, VIN= FSR −0.1 dB −73 dB

f

IN

f

= 4.7 MHz, VIN= FSR −0.1 dB −73 −62 dB(min)

IN

f

= 9.5 MHz, VIN= FSR −0.1 dB −73 dB

IN

f

= 19.5 MHz, VIN= FSR −0.1 dB −73 dB

IN

= 1.0 VDC, GAIN = OF = 0V, OS = 3.0V, VIN(ac

REF

<

4 ns, NOT offset corrected.

fc

Typical

(Note 8)

±

0.65

±

0.35

A

±

/4 to (VA–V

REF

/2 to (VA–V

REF

A

Limits

(Note 9)

±

1.8 LSB(max)

+1.2

−1.0

+10

−16

+1.5

−0.5
+6

−14

(Limits)

LSB(max)

LSB(min)

LSB(max)

LSB(min)

LSB(max)

LSB(min)

%FS(max)

%FS(min)

≤ +85˚C

V

REF

±

V

REF

/4)

REF

/2)

REF

+0.3V)

Units

D

/2

www.national.com7

Converter Electrical Characteristics (Continued)

The following specifications apply for VA=VD=VDR= +3.0 VDC,V
coupled) = FSR = 1.0 V

Boldface limits apply for T

ADC10D020

P-P,CL

A=TMIN

= 15 pF, f

to T

= 20 MHz, 50% Duty Cycle, RS=50Ω,trc=t

CLK

: all other limits TA= 25˚C (Note 7).

MAX

Symbol Parameter Conditions

= 1.0 MHz, VIN= FSR −0.1 dB −84 dB

f

IN

f

= 4.7 MHz, VIN= FSR −0.1 dB −92 dB

HS2 Second Harmonic

HS3 Third Harmonic

SFDR Spurious Free Dynamic Range

IMD Intermodulation Distortion

Overrange Output Code (V
Underrange Output Code (V

IN

f

= 9.5 MHz, VIN= FSR −0.1 dB −87 dB

IN

f

= 19.5 MHz, VIN= FSR −0.1 dB −87 dB

IN

= 1.0 MHz, VIN= FSR −0.1 dB −80 dB

f

IN

f

= 4.7 MHz, VIN= FSR −0.1 dB −78 dB

IN

f

= 9.5 MHz, VIN= FSR −0.1 dB −78 dB

IN

f

= 19.5 MHz, VIN= FSR −0.1 dB −78 dB

IN

= 1.0 MHz, VIN= FSR −0.1 dB 76 dB

f

IN

f

= 4.7 MHz, VIN= FSR −0.1 dB 75 dB

IN

f

= 9.5 MHz, VIN= FSR −0.1 dB 75 dB

IN

f

= 19.5 MHz, VIN= FSR −0.1 dB 74 dB

IN

<

f

4.9 MHz, VIN= FSR −6.1 dB

IN1

<

5.1 MHz, VIN= FSR −6.1 dB

f

IN2

IN+−VIN−
IN+−VIN−

)>1.1V 1023

)<−1.1V 0
FPBW Full Power Bandwidth 140 MHz
INTER-CHANNEL CHARACTERISTICS

Crosstalk
Channel - Channel Aperture Delay

Match

1 MHz input to tested channel, 4.75 MHz input
to other channel

= 8 MHz 8.5 ps

f

IN

Channel - Channel Gain Matching 0.03 %FS

REFERENCE AND ANALOG CHARACTERISTICS
V

IN

C

IN

R

IN

V

REF

I

REF

V

CMO

TC
V

CMO

Analog Differential Input Range
Analog Input Capacitance (each

input)
Analog Differential Input

Resistance
Reference Voltage 1.0
Reference Input Current
Common Mode Voltage Output
Common Mode Voltage

Temperature Coefficient

Gain Pin = AGND 1 V
Gain Pin = V

A

Clock High 6 pF
Clock Low 3 pF

1 mA load to ground
(sourcing current)

DIGITAL INPUT CHARACTERISTICS
V

IH

V

IL

I

IH

I

IL

Logical “1” Input Voltage VD= +2.7V 2.0 V(min)
Logical “0” Input Voltage VD= +3.6V 0.5 V(max)
Logical “1” Input Current VIH=V

D

Logical “0” Input Current VIL= DGND

DIGITAL OUTPUT CHARACTERISTICS
V

OH

V

OL

Logical “1” Output Voltage VDR= +2.7V, I
Logical “0” Output Voltage VDR= +2.7V, I

= −0.5 mA

OUT

= 1.6 mA 0.4 V(max)

OUT

= 1.0 VDC, GAIN = OF = 0V, OS = 3.0V, VIN(ac

REF

<

4 ns, NOT offset corrected.

fc

Typical

(Note 8)

Limits

(Note 9)

65 dB

−90 dB

2V

27 kΩ

0.8 V(min)

1.5 V(max)

<

1µA

1.5

1.35 V(min)

1.6 V(max)

20 ppm/˚C

<

1µA

>

−1 µA

V

DR

−0.3V

Units

(Limits)

P-P
P-P

V(min)

www.national.com 8

Converter Electrical Characteristics (Continued)

The following specifications apply for VA=VD=VDR= +3.0 VDC,V
coupled) = FSR = 1.0 V

Boldface limits apply for T

P-P,CL

A=TMIN

= 15 pF, f

to T

= 20 MHz, 50% Duty Cycle, RS=50Ω,trc=t

CLK

: all other limits TA= 25˚C (Note 7).

MAX

Symbol Parameter Conditions

+I

−I

Output Short Circuit Source

SC

Current
Output Short Circuit Sink Current V

SC

=0V

V

OUT

OUT=VDR

POWER SUPPLY CHARACTERISTICS

PD = LOW, STBY = LOW, dc input 47.6 55 mA(max)

I

A+ID

Core Supply Current

PD = LOW, STBY = HIGH 8.8 mA
PD = HIGH, STBY = LOW or HIGH 0.22 mA

I

DR

Digital Output Driver Supply
Current (Note 10)

PD = LOW, STBY = LOW, dc input 1.3 1.4 mA(max)
PD = LOW, STBY = HIGH 0.1 mA
PD = HIGH, STBY = LOW or HIGH 0.1 mA
PD = LOW, STBY = LOW, dc input 150 169 mW(max)

PWR Power Consumption

PD = LOW, STBY = LOW, 1 MHz Input 178 mW
PD = LOW, STBY = HIGH 27 mW
PD = HIGH, STBY = LOW or HIGH

PSRR1 Power Supply Rejection Ratio

PSRR2 Power Supply Rejection Ratio

Change in Full Scale with 2.7V to 3.6V Supply
Change

Rejection at output with 20 MHz, 250 mV
Riding on VAand V

REF

Parallel Mode −7 mA
Multiplexed Mode −14 mA
Parallel Mode 7 mA
Multiplexed Mode 14 mA

D

= 1.0 VDC, GAIN = OF = 0V, OS = 3.0V, VIN(ac

<

4 ns, NOT offset corrected.

fc

Typical

(Note 8)

<

Limits

(Note 9)

Units

(Limits)

1mW

90 dB

P-P

52 dB

ADC10D020

AC Electrical Characteristics OS = Low (Multiplexed Mode)

The following specifications apply for VA=VD=VDR= +3.0VDC,V
coupled) = FSR = 1.0 V

Boldface limits apply for T

P-P,CL

A=TMIN

= 15 pF, f

to T

= 20 MHz, 50% Duty Cycle, RS=50Ω,trc=t

CLK

: all other limits TA= 25˚C (Note 7)

MAX

Symbol Parameter Conditions

1

f
f

CLK
CLK

Maximum Clock Frequency 30 20 MHz(min)

2

Minimum Clock Frequency 1 MHz
Duty Cycle 50
Pipeline Delay (Latency)

I Data 2.5 Clock Cycles
Q Data 3.0 Clock Cycles

t

r,tf

t

OC

t

OD

Output Rise and Fall Times 4 ns
Offset Correction Pulse Width 10 ns(min)
Output Delay from CLK Edge to

Data Valid

t

DIQ

t

SKEW

t

AD

t

AJ

t

VALID

t

WUPD

I/Q Output Delay 13 ns
I/Q to Data Delay
Sampling (Aperture) Delay 2.4 ns
Aperture Jitter
Data Valid Time 21 ns

Overrange Recovery Time

Differential V
0V

IN

PD Low to 1/2 LSB Accurate
Conversion (Wake-Up Time)

= 1.0 VDC, GAIN = OF = 0V, OS = 0V, VIN(ac

REF

<

4 ns, NOT offset corrected.

fc

Typical

(Note 8)

13 18 ns(max)

±

200 ps

<

10 ps(rms)

step from 1.5V to

50 ns

<

1ms

Limits

(Note 9)

30
70

Units

(Limits)

%(min)

%(max)

www.national.com9

AC Electrical Characteristics OS = Low (Multiplexed Mode) (Continued)

The following specifications apply for VA=VD=VDR= +3.0VDC,V
coupled) = FSR = 1.0 V

Boldface limits apply for T

ADC10D020

P-P,CL

A=TMIN

= 15 pF, f

to T

= 20 MHz, 50% Duty Cycle, RS=50Ω,trc=t

CLK

: all other limits TA= 25˚C (Note 7)

MAX

Symbol Parameter Conditions

t

WUSB

STBY Low to 1/2 LSB Accurate
Conversion (Wake-Up Time)

= 1.0 VDC, GAIN = OF = 0V, OS = 0V, VIN(ac

REF

<

4 ns, NOT offset corrected.

fc

Typical

(Note 8)

Limits

(Note 9)

800 ns

AC Electrical Characteristics OS = High (Parallel Mode)

The following specifications apply for VA= +3.0 VDC,VD= +3.0 VDC,VDR= +3.0VDC,V
= 3.0V, V
offset corrected. Boldface limits apply for T

(ac coupled) = FSR = 1.0 V

IN

P-P,CL

A=TMIN

= 15 pF, f

to T

= 20 MHz, 50% Duty Cycle, RS=50Ω,trc=t

CLK

: all other limits TA= 25˚C (Note 7)

MAX

Symbol Parameter Conditions

1

f
f

CLK
CLK

Maximum Clock Frequency 30 20 MHz(min)

2

Minimum Clock Frequency 1 MHz
Duty Cycle 50
Pipeline Delay (Latency) 2.5 Conv Cycles

t

r,tf

t

oc

t

OD

Output Rise and Fall Times 7 ns
OC Pulse Width 10 ns
Output Delay from CLK Edge to

Data Valid

t

DIQ

t

AD

t

AJ

t

VALID

t

WUPD

I/Q Output Delay 13 ns
Sampling (Aperture) Delay 2.4 ns
Aperture Jitter
Data Valid Time 43 ns

Overrange Recovery Time

Differential V
0V

step from 1.5V to

IN

PD Low to 1/2 LSB Accurate
Conversion (Wake-Up Time)

t

WUSB

STBY Low to 1/2 LSB Accurate
Conversion (Wake-Up Time)

Note 1: Absolute Maximum Ratings indicate limits beyond which damage to the device may occur. Operating Ratings indicate conditions for which the device is
functional, but do not guarantee specific performance limits. For guaranteed specifications and test conditions, see the Electrical Characteristics. The guaranteed
specifications apply only for the test conditions listed. Some performance characteristics may degrade when the device is not operated under the listed test
conditions.

Note 2: All voltages are measured with respect to GND = AGND = DGND = 0V, unless otherwise specified.
Note 3: When the input voltage at any pin exceeds the power supplies (V

maximum package input current rating limits the number of pins that can safely exceed the power supplies with an input current of 25 mA to two.
Note 4: The absolute maximum junction temperature (T

junction-to-ambient thermal resistance (θ
TQFP, θ
device under normal operation will typically be about 170 mW (150 mW quiescent power + 20 mW due to 1 LVTTL load on each digital output). The values for
maximum power dissipation listed above will be reached only when theADC10D020 is operated in a severe fault condition (e.g. when input or output pins are driven
beyond the power supply voltages, or the power supply polarity is reversed). Obviously, such conditions should always be avoided.

Note 5: Human body model is 100 pF capacitor discharged through a 1.5 kΩ resistor. Machine model is 220 pF discharged through 0Ω.
Note 6: See AN450, “Surface Mounting Methods and Their Effect on Product Reliability”, or the section entitled “Surface Mount” found in any post 1986 National

Semiconductor Linear Data Book, for other methods of soldering surface mount devices.
Note 7: The inputs are protected as shown below. Input voltage magnitude up to 300 mV beyond the supply rails will not damage this device. However, errors in

the A/D conversion can occur if the input goes beyond the limits given in these tables.

is 76˚C/W, so PDMAX = 1,645 mW at 25˚C and 855 mW at the maximum operating ambient temperature of 85˚C. Note that the power dissipation of this

JA

), and the ambient temperature (TA), and can be calculated using the formula PDMAX=(TJmax - TA)/θJA. In the 48-pin

JA

max) for this device is 150˚C. The maximum allowable power dissipation is dictated by TJmax, the

J

IN

<

GND or V

>

VAor VD), the current at that pin should be limited to 25 mA. The 50 mA

IN

= 1.0 VDC, GAIN = OF = 0V, OS

REF

Typical

(Note 8)

(Note 9)

Limits

<

fc

30
70

15 21 ns(max)

<

10 ps(rms)

50 ns

<

1ms

800 ns

Units

(Limits)

4 ns, NOT

Units

(Limits)

%(min)

%(max)

www.national.com 10