ADC10731/ADC10732/ADC10734/ADC10738
10-Bit Plus Sign Serial I/O A/D Converters
with Mux, Sample/Hold and Reference
December 1994
ADC10731/ADC10732/ADC10734/ADC10738 10-Bit Plus Sign Serial I/O
A/D Converters with Mux, Sample/Hold and Reference
General Description
This series of CMOS 10-bit plus sign successive approximation A/D converters features versatile analog input multiplexers, sample/hold and a 2.5V band-gap reference. The
1-, 2-, 4-, or 8-channel multiplexers can be software configured for single-ended or differential mode of operation.
An input sample/hold is implemented by a capacitive reference ladder and sampled-data comparator. This allows the
analog input to vary during the A/D conversion cycle.
In the differential mode, valid outputs are obtained even
when the negative inputs are greater than the positive because of the 10-bit plus sign output data format.
The serial I/O is configured to comply with the NSC
MICROWIRE
terface to the COPS
TM
serial data exchange standard for easy in-
TM
and HPCTMfamilies of controllers,
and can easily interface with standard shift registers and
microprocessors.
Applications
Y
Medical instruments
Y
Portable and remote instrumentation
Y
Test equipment
ADC10738 Simplified Block Diagram
Features
Y
0V to 5V analog input range with single 5V power
supply
Y
Serial I/O (MICROWIRE compatible)
Y
1-, 2-, 4-, or 8-channel differential or single-ended
multiplexer
Y
Software or hardware power down
Y
Analog input sample/hold function
Y
Ratiometric or absolute voltage referencing
Y
No zero or full scale adjustment required
Y
No missing codes over temperature
Y
TTL/CMOS input/output compatible
Y
Standard DIP and SO packages
Key Specifications
Y
Resolution 10 bits plus sign
Y
Single supply 5V
Y
Power dissipation 37 mW (Max)
Ð In powerdown mode 18 mW
Y
Conversion time 5 ms (Max)
Y
Sampling rate 74 kHz (Max)
Y
Band-gap reference 2.5Vg2% (Max)
TL/H/11390– 1
COPSTM, HPCTMand MICROWIRETMare trademarks of National Semiconductor Corporation.
C
1995 National Semiconductor Corporation RRD-B30M75/Printed in U. S. A.
TL/H/11390
Connection Diagrams for Dual-In-Line and SO Packages
Top View
TL/H/11390– 2
See NS Package Number N16E or M16B
TL/H/11390– 3
Top View
See NS Package Number N20A or M20B
Connection Diagram for the SSOP Package
TL/H/11390– 34
See NS Package Number MSA20
Top View
See NS Package Number N20A or M20B
Top View
See NS Package Number N24A or M24B
Ordering Information
Industrial Temperature Range
b
40§CsT
ADC10731CIN N16E
ADC10731CIWM M16B
ADC10732CIN N20A
ADC10732CIWM M20B
ADC10734CIMSA MSA20
ADC10734CIN N20A
ADC10734CIWM M20B
ADC10738CIN N24A
ADC10738CIWM M24B
s
a
85§C
A
TL/H/11390– 4
TL/H/11390– 5
Package
2
Absolute Maximum Ratings (Notes1&3)
If Military/Aerospace specified devices are required,
please contact the National Semiconductor Sales
Office/Distributors for availability and specifications.
Supply Voltage (V
Total Reference Voltage (V
Voltage at Inputs and Outputs V
Input Current at Any Pin (Note 4) 30 mA
Package Input Current (Note 4) 120 mA
Package Dissipation at T
ESD Susceptability (Note 6)
Human Body Model 2500V
Machine Model 150V
Soldering Information
N packages (10 seconds) 260
SO Package (Note 7)
Vapor Phase (60 seconds) 215
Infrared (15 seconds) 220
Storage Temperature
a
a
e
e
AV
DVa) 6.5V
a
b
–V
REF
e
25§C (Note 5) 500 mW
A
) 6.5V
REF
a
a
0.3V tob0.3V
§
§
§
b
40§Ctoa150§C
Operating Ratings (Notes 2 and 3)
Operating Temperature Range T
ADC10731CIN, ADC10731CIWM,
ADC10732CIN, ADC10732CIWM,
ADC10734CIN, ADC10734CIWM,
ADC10734CIMSA, ADC10738CIN,
C
C
C
ADC10738CIWM
Supply Voltage (V
a
V
REF
b
V
REF
V
REF(VREF
a
e
AV
a
b
–V
)
REF
s
s
T
MIN
b
DVa)
AV
AV
40§CsT
a
a
a
50 mV tob50 mV
a
a
50 mV tob50 mV
a
e
T
A
MAX
s
a
85§C
A
4.5V toa5.5V
a
0.5V to V
a
Electrical Characteristics
The following specifications apply for V
Signed Characteristics, V
limits apply for T
b
IN
e
e
T
A
J
a
a
e
to T
AV
MAX
e
GND for Unsigned Characteristics and f
T
MIN
a
e
ea
DV
; all other limits T
5.0 VDC,V
Symbol Parameter Conditions
SIGNED STATIC CONVERTER CHARACTERISTICS
Resolution with No Missing Codes 10aSign Bits
TUE Total Unadjusted Error (Note 13)
INL Positive and Negative Integral
Linearity Error
Positive and Negative
Full-Scale Error
Offset Error
Power Supply Sensitivity
Offset Error V
a
Full-Scale Error
b
Full-Scale Error
DC Common Mode Error (Note 14) V
a
ea
a
e
IN
5.0VtV
5.0Vg10%
V
IN
t
IN
Multiplexer Channel to
Channel Matching
A
b
e
0V
CLK
e
T
J
VINwhere
a
e
2.5 VDC,V
REF
e
2.5 MHz unless otherwise specified. Boldface
ea
25§C. (Notes 8, 9 and 10)
REF
b
e
GND, V
IN
Typical Limits Units
(Note 11) (Note 12) (Limits)
g
2.0 LSB(max)
g
1.25 LSB(max)
g
1.5 LSB(max)
g
1.5 LSB(max)
g
0.2
g
0.2
g
0.1
g
0.1
g
0.1 LSB
g
1.0 LSB(max)
g
1.0 LSB(max)
g
0.75 LSB(max)
g
0.33 LSB(max)
b
e
2.5V for
3
Electrical Characteristics (Continued)
The following specifications apply for V
Signed Characteristics, V
limits apply for T
b
IN
e
e
T
A
J
a
a
e
to T
AV
MAX
e
GND for Unsigned Characteristics and f
T
MIN
a
e
ea
DV
; all other limits T
5.0 VDC,V
e
A
Symbol Parameter Conditions
UNSIGNED STATIC CONVERTER CHARACTERISTICS
Resolution with No Missing Codes 10 Bits
a
TUE Total Unadjusted Error (Note 13) V
INL Integral Linearity Error V
Full-Scale Error V
Offset Error V
Power Supply Sensitivity
Offset Error V
Full-Scale Error V
DC Common Mode Error (Note 14) V
Multiplexer Channel to Channel Matching V
REF
REF
REF
REF
a
REF
a
IN
where
REF
a
a
a
ea
a
e
a
a
e
e
e
e
e
e
4.096V
4.096V
4.096V
4.096V
5.0Vg10%
4.096V
V
IN
5.0VtV
4.096V
DYNAMIC SIGNED CONVERTER CHARACTERISTICS
S/(NaD) Signal-to-Noise Plus Distortion Ratio V
ENOB Effective Number of Bits V
THD Total Harmonic Distortion V
IMD Intermodulation Distortion V
Full-Power Bandwidth V
Multiplexer Channel to Channel Crosstalk f
IN
and f
IN
and f
IN
and f
IN
and f
IN
S/(N
IN
e
e
e
e
e
e
IN
IN
IN
IN
a
15 kHz
4.85 VPP,
4.85 VPP,
4.85 VPP,
4.85 VPP,
4.85 VPP, where
e
1 kHz to 15 kHz
e
1 kHz to 15 kHz
e
1 kHz to 15 kHz
e
1 kHz to 15 kHz
D) Decreases 3 dB
a
e
2.5 VDC,V
e
2.5 MHz unless otherwise specified. Boldface
25§C. (Notes 8, 9 and 10) (Continued)
T
CLK
J
REF
ea
REF
b
e
GND, V
Typical Limits Units
(Note 11) (Note 12) (Limits)
g
0.75 LSB
g
0.50 LSB
g
g
g
0.1 LSB
g
0.1 LSB
b
e
V
IN
t
0V
IN
g
0.1 LSB
g
0.1 LSB
67 dB
10.8 Bits
b
78 dB
b
85 dB
380 kHz
b
80 dB
b
e
2.5V for
IN
1.25 LSB(max)
1.25 LSB(max)
4
Electrical Characteristics (Continued)
The following specifications apply for V
Signed Characteristics, V
limits apply for T
b
IN
e
e
T
A
J
a
a
e
to T
AV
MAX
e
GND for Unsigned Characteristics and f
T
MIN
a
e
ea
DV
; all other limits T
5.0 VDC,V
e
A
Symbol Parameter Conditions
DYNAMIC UNSIGNED CONVERTER CHARACTERISTIC
a
S/(NaD) Signal-to-Noise Plus Distortion Ratio V
Effective Bits V
THD Total Harmonic Distortion V
IMD Intermodulation Distortion V
Full-Power Bandwidth V
Multiplexer Channel to Channel Crosstalk f
e
4.096V,
REF
e
V
4.0 VPP, and 60 dB
IN
e
f
1 kHz to 15 kHz
IN
a
e
4.096V,
REF
e
V
4.0 VPP, and 9.8 Bits
IN
e
f
1 kHz to 15 kHz
IN
a
e
4.096V,
REF
e
V
4.0 VPP, and
IN
e
f
1 kHz to 15 kHz
IN
a
e
4.096V,
REF
e
V
4.0 VPP, and
IN
e
f
1 kHz to 15 kHz
IN
e
4.0 VPP,
IN
a
e
V
where S/(N
IN
V
4.096V, 380 kHz
REF
REF
e
15 kHz,
a
e
a
4.096V
D) decreases 3 dB
REFERENCE INPUT AND MULTIPLEXER CHARACTERISTICS
Reference Input Resistance 7 kX
C
REF
Reference Input Capacitance 70 pF
MUX Input Voltage
C
IM
MUX Input Capacitance 47 pF
Off Channel Leakage Current (Note 15) On Channele5V and
e
Off Channel
On Channel
Off Channel
e
e
0V
0V and
5V
On Channel Leakage Current (Note 15) On Channele5V and
Off Channel
e
0V
On Channele0V and
e
Off Channel
5V
a
e
2.5 VDC,V
REF
e
2.5 MHz unless otherwise specified. Boldface
CLK
ea
T
25§C. (Notes 8, 9 and 10) (Continued)
J
REF
b
e
GND, V
Typical Limits Units
(Note 11) (Note 12) (Limits)
b
70 dB
b
73 dB
b
80 dB
a
AV
b
0.4
b
0.4 3.0 mA(max)
0.4 3.0 mA(max)
b
0.4
b
b
e
2.5V for
IN
5.0 kX(min)
9.5 kX(max)
b
50 mV(min)
a
50 mV (max)
3.0 mA(max)
3.0 mA(max)
5
Electrical Characteristics (Continued)
The following specifications apply for V
Signed Characteristics, V
limits apply for T
Symbol Parameter Conditions
b
IN
e
e
T
A
J
a
a
e
to T
AV
MAX
e
GND for Unsigned Characteristics and f
T
MIN
a
e
ea
DV
; all other limits T
5.0 VDC,V
a
e
REF
CLK
e
ea
T
A
J
2.5 VDC,V
e
2.5 MHz unless otherwise specified. Boldface
25§C. (Notes 8, 9 and 10) (Continued)
REF
b
e
GND, V
Typical Limits Units
(Note 11) (Note 12) (Limits)
REFERENCE CHARACTERISTICS
V
Out Reference Output Voltage 2.5Vg0.5% 2.5Vg2% V(max)
REF
DV
/DTV
REF
DV
/DILLoad Regulation, Sourcing 0 mAsI
REF
DV
/DILLoad Regulation, Sinking 0 mAsI
REF
Out Temperature Coefficient
REF
Line Regulation 5Vg10%
I
SC
Short Circuit Current V
Noise Voltage 10 Hz to 10 kHz, C
DV
/Dt Long-term Stability
REF
t
SU
Start-Up Time C
s
a
4mA
L
s
b
1mA
L
Oute0V 13 22 mA(max)
REF
e
100 mF5 mV
L
e
100 mF 100 ms
L
g
40 ppm/§C
g
0.003
g
0.2
g
0.3
g
120 ppm/kHr
g
0.05 %/mA(max)
g
0.6 %/mA(max)
g
2.5 mV(max)
DIGITAL AND DC CHARACTERISTICS
a
V
IN(1)
V
IN(0)
I
IN(1)
I
IN(0)
V
OUT(1)
V
OUT(0)
I
OUT
a
I
b
I
a
I
D
SC
SC
Logical ‘‘1’’ Input Voltage V
Logical ‘‘0’’ Input Voltage V
Logical ‘‘1’’ Input Current V
Logical ‘‘0’’ Input Current V
Logical ‘‘1’’ Output Voltage V
Logical ‘‘0’’ Output Voltage V
TRI-STATE Output Current V
Output Short Circuit Source V
Current
Output Short Circuit Sink Current V
Digital Supply Current CSeHIGH, Power Up 0.9 1.3 mA(max)
(Note 17) CS
e
5.5V 2.0 V(min)
a
e
4.5V 0.8 V(max)
e
5.0V 0.005
IN
e
0V
IN
a
e
4.5V, I
a
e
V
4.5V, I
a
e
4.5V, I
e
OUT
e
V
OUT
e
OUT
e
V
OUT
e
HIGH, Power Down 0.2 0.4 mA(max)
e
CS
HIGH, Power Down, 0.5 50 mA(max)
eb
OUT
OUT
OUT
360 mA 2.4 V(min)
eb
10 mA 4.5 V(min)
e
1.6 mA 0.4 V(min)
0V
5V
a
e
0V, V
a
4.5V
e
4.5V 30 15 mA(min)
b
0.005
b
a
b
0.1
0.1
30
a
2.5 mA(max)
b
2.5 mA(max)
b
3.0 mA(max)
a
3.0 mA(max)
b
15 mA(min)
and CLK Off
a
I
A
I
REF
Analog Supply Current CSeHIGH, Power Up 2.7 6.0 mA(max)
(Note 17) CS
Reference Input Current V
e
HIGH, Power Down 3 15 mA(max)
a
ea
CS
REF
2.5V and
e
HIGH, Power Up
0.6 mA(max)
b
e
2.5V for
IN
6
Electrical Characteristics (Continued)
The following specifications apply for V
Signed Characteristics, V
limits apply for T
b
IN
e
e
T
A
J
a
a
e
to T
AV
MAX
e
GND for Unsigned Characteristics and f
T
MIN
a
e
ea
DV
; all other limits T
5.0 VDC,V
CLK
e
T
A
J
REF
ea
Symbol Parameter Conditions
AC CHARACTERISTICS
f
CLK
Clock Frequency 3.0 2.5 MHz(max)
Clock Duty Cycle 40 %(min)
t
C
t
A
t
SCS
t
SDI
t
HDI
t
AT
t
AC
t
DSARS
t
HDO
t
AD
t1H,t
t
DCS
t
CS(H)
t
CS(L)
t
SC
t
PD
t
PC
C
IN
C
OUT
Conversion Time 12 12 Clock
Acquisition Time 4.5 4.5 Clock
CS Set-Up Time, Set-Up Time from Falling Edge of 14 30 ns(min)
CS to Rising Edge of Clock
DI Set-Up Time, Set-Up Time from Data Valid on
DI to Rising Edge of Clock
DI Hold Time, Hold Time of DI Data from Rising
Edge of Clock to Data not Valid on DI
DO Access Time from Rising Edge of CLK When
CS
is ‘‘Low’’ during a Conversion
DO or SARS Access Time from CS, Delay from
Falling Edge of CS
to Data Valid on DO or SARS
Delay from Rising Edge of Clock to Falling Edge of
SARS when CS
is ‘‘Low’’
DO Hold Time, Hold Time of Data on DO after
Falling Edge of Clock
DO Access Time from Clock, Delay from Falling
Edge of Clock to Valid Data of DO
Delay from Rising Edge of CS to DO or SARS
0H
TRI-STATE
Delay from Falling Edge of Clock to Falling Edge of
CS
CS ‘‘HIGH’’ Time for A/D Reset after Reading of
Conversion Result
ADC10731 Minimum CS ‘‘Low’’ Time to Start a
Conversion
Time from End of Conversion to CS Going ‘‘Low’’ 5 CLK 5 CLK cycle(min)
Delay from Power-Down command to 10% of
Operating Current
Delay from Power-Up Command to Ready to Start
a New Conversion
Capacitance of Logic Inputs 7 pF
Capacitance of Logic Outputs 12 pF
a
e
2.5 VDC,V
e
2.5 MHz unless otherwise specified. Boldface
REF
b
e
GND, V
b
e
IN
25§C. (Note 16)
Typical Limits Units
(Note 11) (Note 12) (Limits)
5 kHz(min)
60 %(max)
5 5 ms(max)
2 2 ms(max)
b
(1 t
14 ns)
CLK
(1 t
b
30 ns)
CLK
16 25 ns(min)
2 25 ns(min)
30 50 ns(min)
30 70 ns(max)
100 200 ns(max)
20 35 ns(max)
40 80 ns(max)
40 50 ns(max)
20 30 ns(min)
1 CLK 1 CLK cycle(min)
1 CLK 1 CLK cycle(min)
1 ms
10
2.5V for
Cycles
Cycles
(max)
ms
7
Electrical Characteristics (Continued)
Note 1: Absolute Maximum Ratings indicate limits beyond which damage to the device may occur.
Note 2: Operating Ratings indicate conditions for which the device is functional, but do not guarantee specific performance limits. For guaranteed specifcations and
test conditions, see the Electrical Characteristics. The guaranteed specifications apply only for the test conditions listed. Some performance characteristics may
degrade when the device is not operated under the listed test conditions.
Note 3: All voltages are measured with respect to GND, unless otherwise specified.
Note 4: When the input voltage (V
The 120 mA maximum package input current rating limits the number of pins that can safely exceed the power supplies with an input current of 30 mA to four.
Note 5: The maximum power dissipation must be derated at elevated temperatures and is dictated by T
allowable power dissipation at any temperature is P
device, T
e
150§C. The typical thermal resistance (iJA) of these Paris when board mounted can be found in the following table:
Jmax
) at any pin exceeds the power supplies (V
IN
e
b
(T
D
Jmax
Part Number Thermal Resistance Package Type
ADC10731CIN 82§C/W N16E
ADC10731CIWM 90
ADC10732CIN 47
ADC10732CIWM 80
ADC10734CIMSA 134
ADC10734CIN 47
ADC10734CIWM 80§C/W M20B
ADC10738CIN 60
ADC10738CIWM 75
Note 6: The human body model is a 100 pF capacitor discharged through a 1.5 kX resistor into each pin. The machine model is a 200 pF capacitor discharged
directly into each pin.
Note 7: See AN-450 ‘‘Surface Mounting Methods and Their Effect on Product Reliability’’ or the section titied ‘‘Surtace Mount’’ found in any post 1986 National
Semiconductor Linear Data Book for other methods of soldering surtace mount devices.
Note 8: Two on-ohip diodes are tied to each analog input as shown below. They will forward-conduct for analog input voltages one diode drop below ground or one
diode drop greater than V
especially at elevated temperatures, which will cause errors In the conversion result. The specification allows 50 mV forward bias of either diode; this means that as
long as the analog V
corrupt the reading of a selected channel. If AV
a
supply. Be careful during testing at low Valevels (a4.5V), as high level analog inputs (a5V) can cause an input diode to conduct,
does not exceed the supply voltage by more than 50 mV, the output code will be oorrect. Exceeding this range on an unselected channel will
IN
a
and DVaare minimum (4.5 VDC) and full scale must be
k
IN
TA)/iJAor the number given In the Absolute Maximum Ratings, whichever is lower. For this
C/W M16B
§
C/W N20A
§
C/W M20B
§
C/W MSA20
§
C/W N20A
§
C/W N24A
§
C/W M24B
§
GND or V
l
AVaor DVa), the current at that pln should be limited to 30 mA.
IN
, iJAand the ambient temperature, TA. The maximum
Jmax
s
a
4.55 VDC.
Note 9: No connection exists between AVaand DVaon the chip.
To guarantee accuracy, it is required that the AV
a
and DVabe connected together to a power supply with separate bypass filter at eacn Vapin.
TL/H/11390– 6
Note 10: One LSB is referenced to 10 bits of resolution.
e
Note 11: Typicals are at T
Note 12: Tested limits are guaranteed to National’s AOQL (Average Outgolng Quality Level).
e
T
25§C and represent most likely pararmetric norm.
J
A
Note 13: Total unadjusted error includes offset, full-scale, linearity, multiplexer, and hold step errors.
Note 14: The DC common-mode error is measured in the differential multiplexer mode with the assigned positive and negative input channels shorted together.
Note 15: Channel leakage current is measured after the channel selection.
Note 16: All the timing specifications are tested at the TTL logic levels, V
to 1.4V.
Note 17: The voltage applied to the digital inputs will affect the current drain during power down. These devices are tested with CMOS logic levels (logic Low
and logic High
e
5V). TTL levels increase the current, during power down, to about 300 mA.
e
0.8V for a falling edge and V
IL
e
2.0V for a rising. TRl-STATE voltage level is forced
IH
e
8
0V
Electrical Characteristics (Continued)
FIGURE 1A. Transter Characteristic
FIGURE 1B. Simplified Error Curve vs Output Code
TL/H/11390– 8
TL/H/11390– 26
9
Leakage Current Test Circuit
Typical Performance Characteristics
TL/H/11390– 9
Analog Supply Current (I
vs Temperature
Digital Supply Current (I
vs Clock Frequency
a
)
A
a
)
D
Analog Supply Current (I
vs Clock Frequency
Offset Error
vs Reference Voltage
a
)
A
Digital Supply Current (I
vs Temperature
a
)
D
Offset Error
vs Temperature
TL/H/11390– 33
10
Typical Performance Characteristics (Continued)
Linearity Error
vs Clock Frequency
10-Bit Unsigned
Signal-to-Noise
vs Input Signal Level
a
THD Ratio
Linearity Error
vs Reference Voltage
Spectral Response with
34 kHz Sine Wave
Typical Reference Performance Characteristics
Load Regulation Line Regulation (3 Typical Parts)
Linearity Error
vs Temperature
Power Bandwidth Response
with 380 kHz Sine Wave
TL/H/11390– 23
Output Drift
vs Temperature
Available
Output Current
vs Supply Voltage
11
TL/H/11390– 24
TRI-STATE Test Circuits and Waveforms
Timing Diagrams
TL/H/11390– 10
TL/H/11390– 12
FIGURE 2. DI Timing
TL/H/11390– 11
TL/H/11390– 13
TL/H/11390– 14
FIGURE 3. DO Timing
12
TL/H/11390– 15
Timing Diagrams (Continued)
FIGURE 4. Delayed DO Timing
FIGURE 5. Hardware Power Up/Down Sequence
TL/H/11390– 16
TL/H/11390– 17
FIGURE 6. Software Power Up/Down Sequence
13
TL/H/11390– 18
Timing Diagrams (Continued)
Note: If CS is low during power up of the power supply voltages (AVaand DVa) then CS needs to go high for t
invalid.
FIGURE 7. ADC10731 CS Low during Conversion
. The data output after the first conversion is
CS(H)
TL/H/11390– 19
14
Timing Diagrams (Continued)
TL/H/11390– 20
. The data output after the first conversion is not valid.
CS(H)
) then CS needs to go high for t
a
and DV
a
FIGURE 8. ADC10732, ADC10734 and ADC10738 CS Low during Conversion
Note: If CS is low during power up of the power supply voltages (AV
15
Timing Diagrams (Continued)
TL/H/11390– 21
. The data output after the first conversion is not valid.
CS(H)
) then CS needs to go high for t
a
and DV
a
FIGURE 9. ADC10731 Using CS to Delay Output of Data afer a Conversion has Completed
Note: If CS is low during power up of the power supply voltages (AV
16
Timing Diagrams (Continued)
TL/H/11390– 22
. The data output after the first conversion is not valid.
CS(H)
) then CS needs to go high for t
a
and DV
a
FIGURE 10. ADC10732, ADC10734 and ADC10738 Using CS to Delay Output of Data after a Conversion has Completed
Note: If CS is low during power up of the power supply voltages (AV
17
TABLE I. ADC10738 Multiplexer Address Assignment
MUX Address Channel Number
MA0 MA1 MA2 MA3 MA4
SING/ ODD/
PU
DIFF SIGN
SEL1 SEL0
11 000
11 001
11 010
11 011
11 100
11 101
11 110
11 111
10 000
10 001
10 010
10 011
10 100
10 101
10 110
10 111
CH0 CH1 CH2 CH3 CH4 CH5 CH6 CH7 COM
ab
ab
ab
ab
ab
ab
ab
ab
ab
ab
ab
ab
ba
ba
ba
ba
0 X X X X Power Down (All Channels Disconnected)
TABLE II. ADC10734 Multiplexer Address Assignment
MUX Address Channel Number
MA0 MA1 MA2 MA3 MA4
PU
SING/ ODD/
DIFF SIGN
SEL1 SEL0
11 000
11 001
11 100
11 101
10 000
10 001
10 100
10 101
CH0 CH1 CH2 CH3 COM
ab
ab
ab
ab
ab
ab
ba
ba
0 X X X X Power Down (All Channels Disconnected)
MUX
MODE
Single-Ended
Differential
MUX
MODE
Single-Ended
Differential
TABLE III. ADC10732 Multiplexer Address Assignment
MUX Address Channel Number
MA0 MA1 MA2 MA3 MA4
PU
SlNG/ ODD/
DIFF SIGN
SEL1 SEL0
11 0 00
11 1 00
10 0 00
10 1 00
CH0 CH1 COM
ab
ab
ab
ba
Single-Ended
Differential
0 X X X X Power Down (All Channels Disconnected)
18
MUX
MODE
Pin Descriptions
CLK The clock applied to this input controls the suc-
DI This is the serial data input pin. The data applied
DO The data output pin. The A/D conversion result
CS
PD This is the power down input pin. When a logic
SARS This is the successive approximation register
cessive approximation conversion time interval,
the acquisition time and the rate at which the
serial data exchange occurs. The rising edge
loads the information on the DI pin into the multiplexer address shift register. This address controls which channel of the analog input multiplexer (MUX) is selected. The falling edge shifts
the data resulting from the A/D conversion out
on DO. CS
enables or disables the above functions. The clock frequency applied to this input
can be between 5 kHz and 3 MHz.
to this pln is shifted by CLK into the multiplexer
address register. Tables I through III show the
multiplexer address assignment.
(DB0-SIGN) are clocked out by the failing edge
of CLK on this pin.
This is the chip select input pin. When a logic
low is applied to this pin, the rising edge of CLK
shifts the data on DI into the address register.
This low also brings DO out of TRI-STATE after
a conversion has been completed.
high is applied to this pin the A/D is powered
down. When a low is applied the A/D is powered up.
status output pin. When CS
TRI-STATE. With CS
is high this pin is in
low this pin is active high
when a conversion is in progress and active low
at all other times.
CH0–CH7 These are the analog inputs of the MUX. A
channel input is selected by the address information at the DI pin, which is loaded on the rising edge of CLK into the address register (see
Tables I – III).
The voltage applied to these inputs should not
exceed AV
a
or go below GND by more than
50 mV. Exceeding this range on an unselected
channel will corrupt the reading of a selected
channel.
COM This pin is another analog input pln. It can be
used as a ‘‘pseudo ground’’ when the analog
multiplexer is single-ended.
a
V
REF
V
REF
AVa,
DV
This is the positive analog voltage reference input. In order to malntaln accuracy, the voltage
range V
REF(VREF
0.5 V
to 5.0 VDCand the voltage at V
DC
cannot exceed AV
b
The negative voltage reference input. In order to
maintain accuracy, the voltage at this pin must
not go below GND
a
50 mV.
a
These are the analog and digital power supply
e
V
a
a
50 mV.
b
50 mV or exceed AV
REF
a
b
–V
)is
REF
REF
pins. These pins should be tied to the same
power supply and bypassed separately. The operating voltage range of AV
4.5 V
to 5.5 VDC.
DC
a
and DVais
DGND This is the digital ground pin.
AGND This is the analog ground pin.
a
a
19
Applications Hints
The ADC10731/2/4/8 use successive approximation to
digitize an analog input voltage. The DAC portion of the A/D
converters uses a capacitive array and a resistive ladder
structure. The structure of the DAC allows a very simple
switching scheme to provide a versatile analog input multiplexer. This structure also provides a sample/hold. The
ADC10731/2/4/8 have a 2.5V CMOS bandgap reference.
The serial digital I/O interfaces to MICROWIRE and
MICROWIRE
1.0 DIGITAL INTERFACE
There are two modes of operation. The fastest throughput
rate is obtained when CS
The timing diagrams in
of the devices in this mode. CS
least t
to reset the internal logic.
tion of the devices when CS
ADC10731/2/4/8 is converting. CS
ing the conversion and kept high indefinitely to delay the
output data. This mode simplifies the interface to other devices while the ADC10731/2/4/8 is busy converting.
1.1 Getting Started with a Conversion
The ADC10731/2/4/8 need to be initialized after the power
supply voltage is applied. If CS
age is applied then CS
t
CS(H)
version is not valid.
1.2 Software and Hardware Power Up/Down
These devices have the capability of software or hardware
power down.
hardware and software power up/down. In the case of hardware power down note that CS
after PD is taken low. When PD is high the device is powered down. The total quiescent current, when powered
down, is typically 200 mA with the clock at 2.5 MHz and
3 mA with the clock off. The actual voltage level applied to a
digital input will effect the power consumption of the
a
.
is kept low during a conversion.
Figures 7
(1 CLK) between conversions. This is necessary
CS(H)
(1 clock period). The data output after the first con-
Figures 5
needs to be taken high for at least
and6show the timing diagrams for
and8show the operation
must be taken high for at
Figures 9
and10show the opera-
is taken high while the
may be taken high dur-
is low when the supply volt-
needs to be high for t
device during power down. CMOS logic levels will give the
least amount of current drain (3 mA). TTL logic levels will
increase the total current drain to 200 mA.
These devices have resistive reference ladders which draw
600 mA with a 2.5V reference voltage. The internal band
gap reference voltage shuts down when power down is activated. If an external reference voltage is used, it will have to
be shut down to minimize the total current drain of the device.
2.0 ARCHITECTURE
Before a conversion is started, during the analog input sampling period, (t
As the comparator is being zeroed the channel assigned to
be the positive input is connected to the A/D’s input capacitor. (The assignment procedure is explained in the Pin Descriptions section.) This charges the input 32C capacitor of
the DAC to the positive analog input voltage. The switches
shown in the DAC portion of
ing/acquisition period. The voltage at the input and output
of the comparator are at equilibrium at this time. When the
conversion is started, the comparator feedback switches
are opened and the 32C input capacitor is then switched to
the assigned negative input voltage. When the comparator
feedback switch opens, a fixed amount of charge is trapped
on the common plates of the capacitors. The voltage at the
input of the comparator moves away from equilibrium when
the 32C capacitor is switched to the assigned negative input
voltage, causing the output of the comparator to go high
(‘‘1’’) or low (‘‘0’’). The SAR next goes through an algorithm,
controlled by the output state of the comparator, that redistributes the charge on the capacitor array by switching the
voltage on one side of the capacitors in the array. The ob-
PC
jective of the SAR algorithm is to return the voltage at the
input of the comparator as close as possible to equilibrium.
The switch position information at the completion of the
successive approximation routine is a direct representation
of the digital output. This data is then available to be shifted
on the DO pin.
), the sampled data comparator is zeroed.
A
Figure 11
are set for this zero-
20
Applications Hints (Continued)
TL/H/11390– 28
FIGURE 11. Detailed Diagram of the ADC10738 DAC and Analog Multiplexer Stages
21
Applications Hints (Continued)
3.0 APPLICATIONS INFORMATION
3.1 Multiplexer Configuration
The design of these converters utilizes a sampled-data
comparator structure, which allows a differential analog input to be converted by the successive approximation routine.
The actual voltage converted is always the difference between an assigned ‘‘
minal. The polarity of each input terminal or pair of input
terminals being converted indicates which line the converter
expects to be the most positive.
A unique input multiplexing scheme has been utilized to provide multiple analog channels. The input channels can be
software configured into three modes: differential, singleended, or pseudo-differential.
modes using the 4-channel MUX of the ADC10734. The
eight inputs of the ADC10738 can also be configured in any
of the three modes. The single-ended mode has CH0–CH3
assigned as the positive input with COM serving as the negative input. In the differential mode, the ADC10734 channel
inputs are grouped in pairs, CH0 with CH1 and CH2 with
CH3. The polarity assignment of each channel in the pair is
interchangeable. Finally, in the pseudo-differential mode
CH0–CH3 are positive inputs referred to COM which is now
a pseudo-ground. This pseudo-ground input can be set to
any potential within the input common-mode range of the
converter. The analog signal conditioning required in transducer-based data acquisition systems is significantly simplified with this type of input flexibility. One converter package
can now handle ground-referred inputs and true differential
inputs as well as signals referred to a specific voltage.
The analog input voltages for each channel can range from
50 mV below GND to 50 mV above V
without degrading conversion accuracy. If the voltage on an
unselected channel exceeds these limits it may corrupt the
reading of the selected channel.
3.2 Reference Considerations
The voltage difference between the V
puts defines the analog input voltage span (the difference
between V
and 1024 negative possible output codes apply.
IN
The value of the voltage on the V
can be anywhere between AV
long as V
ADC10731/2/4/8 can be used in either ratiometric applications or in systems requiring absolute accuracy. The reference pins must be connected to a voltage source capable
of driving the minimum reference input resistance of 5 k X.
The internal 2.5V bandgap reference in the
ADC10731/2/4/8 is available as an output on the V
pin. To ensure optimum performance this output needs to
be bypassed to ground with 100 mF aluminum electrolytic or
tantalum capacitor. The reference output can be unstable
with capacitive loads greater than 100 pF and less than
100 mF. Any capacitive loading less than 100 pF and
greater than 100 mF will not cause oscillation. Lower
a
’’ input terminal and a ‘‘b’’ input ter-
Figure 12
illustrates the three
a
a
e
e
DV
a
and V
REF
REF
AV
b
(Max) and VIN(Min)) over which 1023 positive
a
is greater than V
REF
a
REF
a
a
50 mV andb50 mV, so
or V
REF
REF
b
b
. The
REF
inputs
Out
output noise can be obtained by increasing the output capacitance. A 100 mF capacitor will yield a typical noise floor
of 200 nV/
tiplexer modes allow for more flexibility in the analog input
Hz. The pseudo-differential and differential mul-
0
voltage range since the ‘‘zero’’ reference voltage is set by
the actual voltage applied to the assigned negative input
pin.
In a ratiometric system
(Figure 13a)
, the analog input voltage is proportional to the voltage used for the A/D reference. This voltage may also be the system power supply, so
a
V
can also be tied to AVa. This technique relaxes the
REF
stability requirements of the system reference as the analog
input and A/D reference move together maintaining the
same output code for a given input condition.
For absolute accuracy
(Figure 13b)
, where the analog input
varies between very specific voltage limits, the reference pin
can be biased with a time- and temperature-stable voltage
source that has excellent initial accuracy. The LM4040,
LM4041 and LM185 references are suitable for use with the
ADC10731/2/4/8.
a
The minimum value of V
be quite small (see Typical Performance Characteristics) to
REF(VREF
e
V
REF
–V
REF
b
) can
allow direct conversion of transducer outputs providing less
than a 5V output span. Particular care must be taken with
regard to noise pickup, circuit layout and system error voltage sources when operating with a reduced span due to the
increased sensitivity of the converter (1 LSB equals V
1024).
REF
/
3.3 The Analog Inputs
Due to the sampling nature of the analog inputs, at the clock
edges short duration spikes of current will be seen on the
selected assigned negative input. Input bypass capacitors
should not be used if the source resistance is greater than
a
1kXsince they will average the AC current and cause an
effective DC current to flow through the analog input source
resistance. An op amp RC active lowpass filter can provide
both impedance buffering and noise filtering should a high
impedance signal source be required. Bypass capacitors
in-
may be used when the source impedance is very low without any degradation in performance.
In a true differential input stage, a signal that is common to
a
both ‘‘
’’ and ‘‘b’’ inputs is canceled. For the
ADC10731/2/4/8, the positive input of a selected channel
pair is only sampled once before the start of a conversion
during the acquisition time (t
be stable during the complete conversion sequence be-
). The negative input needs to
A
cause it is sampled before each decision in the SAR sequence. Therefore, any AC common-mode signal present
on the analog inputs will not be completely canceled and
will cause some conversion errors. For a sinusoid commonmode signal this error is:
V
ERROR
(max)eV
(2 q fCM)(tC)
PEAK
where fCMis the frequency of the common-mode signal,
V
is its peak voltage value, and tCis the A/D’s conver-
PEAK
sion time (t
mon-mode signal to generate a (/4 LSB error (0.61 mV) with
e
12/f
C
). For example, for a 60 Hz com-
CLK
a 4.8 ms conversion time, its peak value would have to be
approximately 337 mV.
22
Applications Hints (Continued)
4 Single-Ended 2 Differential
FIGURE 12. Analog Input Multiplexer Options
a. Ratiometric Using the Internal Reference
4 Psuedo-
Differential
2 Single-Ended
and 1 Differential
TL/H/11390– 27
b. Absolute Using a 4.096V Span
FIGURE 13. Different Reference Configurations
23
TL/H/11390– 29
TL/H/11390– 30
Applications Hints (Continued)
3.4 Optional Adjustments
3.4.1 Zero Error
The zero error of the A/D converter relates to the location
of the first riser of the transfer function (see
can be measured by grounding the minus input and applying
a small magnitude voltage to the plus input. Zero error is the
difference between actual DC input voltage which is necessary to just cause an output digital code transition from
000 0000 0000 to 000 0000 0001 and the ideal (/2 LSB
value ((/2 LSB
e
1.22 mV for V
REF
The zero error of the A/D does not require adjustment. If
the minimum analog input voltage value, V
ground, the effective ‘‘zero’’ voltage can be adjusted to a
convenient value. The converter can be made to output an
all zeros digital code for this minimum input voltage by biasing any minus input to V
differential or pseudo-differential input channel configura-
(Min). This is useful for either the
IN
tions.
3.4.2 Full-Scale
The full-scale adjustment can be made by applying a differential input voltage which is 1(/2 LSB down from the desired
analog full-scale voltage range and then adjusting the V
voltage (V
changing from 011 1111 1110 to 011 1111 1111. In bipolar
REF
a
e
V
REF
b
–V
) for a digital output code
REF
signed operation this only adjusts the positive full scale error.
3.4.3 Adjusting for an Arbitrary Analog Input
Voltage Range
If the analog zero voltage of the A/D is shifted away from
ground (for example, to accommodate an analog input signal which does not go to ground), this new zero reference
should be properly adjusted first. A plus input voltage which
equals this desired zero reference plus (/2 LSB is applied to
selected plus input and the zero reference voltage at the
corresponding minus input should then be adjusted to just
obtain the 000 0000 0000 to 000 0000 0001 code transition.
The full-scale adjustment should be made[with the proper
minus input voltage applied]by forcing a voltage to the plus
input which is given by:
V
(a)fsadjeV
IN
where V
V
MIN
range. Both V
(V
REF
vide a code change from 011 1111 1110 to 011 1111 1111.
equals the high end of the analog input range,
MAX
equals the low end (the offset zero) of the analog
MAX
a
e
b
V
REF
Note, when using a pseudo-differential or differential multiplexer mode where V
a
the V
and GND range, the individual values of V
b
V
do not matter, only the difference sets the analog
REF
input voltage span. This completes the adjustment proce-
b
1.5
and V
V
REF
MAX
MIN
REF
Ð
are ground referred. The V
b
) voltage is then adjusted to pro-
a
and V
REF
dure.
Figure 1
ea
2.500V).
IN
b
(V
MAX
n
2
b
are placed within
) and
(Min), is not
V
)
MIN
(
REF
REF
REF
and
3.5 The Input Sample and Hold
The ADC10731/2/4/8’s sample/hold capacitor is implemented in the capacitor array. After the channel address is
loaded, the array is switched to sample the selected positive
analog input. The sampling period for the assigned positive
input is maintained for the duration of the acquisition time
(t
) 4.5 clock cycles.
A
This acquisition window of 4.5 clock cycles is available to
allow the voltage on the capacitor array to settle to the positive analog input voltage. Any change in the analog voltage
on a selected positive input before or after the acquisition
window will not effect the A/D conversion result.
In the simplest case, the array’s acquisition time is determined by the R
stray input capacitance C
and stray (C
resistance the analog input can be modeled as an RC network as shown in
(3 kX) of the multiplexer switches, the
ON
) capacitance (48 pF). For a large source
S2
(3.5 pF) and the total array (CL)
S1
Figure 14
. The values shown yield an
acquisition time of about 1.1 ms for 10-bit unipolar or 10-bit
plus sign accuracy with a zero-to-full-scale change in the
input voltage. External source resistance and capacitance
will lengthen the acquisition time and should be accounted
for. Slowing the clock will lengthen the acquisition time,
thereby allowing a larger external source resistance.
FIGURE 14. Analog Input Model
TL/H/11390– 25
The signal-to-noise ratio of an ideal A/D is the ratio of the
RMS value of the full scale input signal amplitude to the
value of the total error amplitude (including noise) caused
by the transfer function of the ideal A/D. An ideal 10-bit plus
sign A/D converter with a total unadjusted error of 0 LSB
would have a signal-to-(noise
a
distortion) ratio of about 68
dB, which can be derived from the equation:
aD)e
S/(N
6.02(n)a1.8
where S/(NaD) is in dB and n is the number of bits.
24
Applications Hints (Continued)
(R1aR2)//R3s1k
Note 1: Diodes are 1N914.
Note 2: The protection diodes should be able to withstand the output current of the op amp under current limit.
FIGURE 15. Protecting the Analog Inputs
FIGURE 16. Zero-Shift and Span-Adjust for Signed or Unsigned, Single-Ended
Multiplexer Assignment, Signed Analog Input Range of 0.5V
*1% resistors
s
V
IN
TL/H/11390– 31
TL/H/11390– 32
s
4.5V
25
26
Physical Dimensions inches (millimeters)
Order Number ADC10731CIWM
NS Package Number M16B
Order Number ADC10732CIWM and ADC10734CIWM
NS Package Number M20B
27
Physical Dimensions inches (millimeters) (Continued)
Order Number ADC10738CIWM
NS Package Number M24B
Order Number ADC10734CIMSA
NS Package Number MSA20
28
Physical Dimensions inches (millimeters) (Continued)
Order Number ADC10731CIN
NS Package Number N16E
Order Number ADC10732CIN and ADC10734CIN
NS Package Number N20A
29
Physical Dimensions inches (millimeters) (Continued)
Order Number ADC10738CIN
NS Package Number N24A
A/D Converters with Mux, Sample/Hold and Reference
LIFE SUPPORT POLICY
ADC10731/ADC10732/ADC10734/ADC10738 10-Bit Plus Sign Serial I/O
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SEMICONDUCTOR CORPORATION. As used herein:
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systems which, (a) are intended for surgical implant support device or system whose failure to perform can
into the body, or (b) support or sustain life, and whose be reasonably expected to cause the failure of the life
failure to perform, when properly used in accordance support device or system, or to affect its safety or
with instructions for use provided in the labeling, can effectiveness.
be reasonably expected to result in a significant injury
to the user.
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