ADC10731/ADC10732/ADC10734/ADC10738
10-Bit Plus Sign Serial I/O A/D Converters
with Mux, Sample/Hold and Reference
December 1994
ADC10731/ADC10732/ADC10734/ADC10738 10-Bit Plus Sign Serial I/O
A/D Converters with Mux, Sample/Hold and Reference
General Description
This series of CMOS 10-bit plus sign successive approximation A/D converters features versatile analog input multiplexers, sample/hold and a 2.5V band-gap reference. The
1-, 2-, 4-, or 8-channel multiplexers can be software configured for single-ended or differential mode of operation.
An input sample/hold is implemented by a capacitive reference ladder and sampled-data comparator. This allows the
analog input to vary during the A/D conversion cycle.
In the differential mode, valid outputs are obtained even
when the negative inputs are greater than the positive because of the 10-bit plus sign output data format.
The serial I/O is configured to comply with the NSC
MICROWIRE
terface to the COPS
TM
serial data exchange standard for easy in-
TM
and HPCTMfamilies of controllers,
and can easily interface with standard shift registers and
microprocessors.
Applications
Y
Medical instruments
Y
Portable and remote instrumentation
Y
Test equipment
ADC10738 Simplified Block Diagram
Features
Y
0V to 5V analog input range with single 5V power
supply
Y
Serial I/O (MICROWIRE compatible)
Y
1-, 2-, 4-, or 8-channel differential or single-ended
multiplexer
Y
Software or hardware power down
Y
Analog input sample/hold function
Y
Ratiometric or absolute voltage referencing
Y
No zero or full scale adjustment required
Y
No missing codes over temperature
Y
TTL/CMOS input/output compatible
Y
Standard DIP and SO packages
Key Specifications
Y
Resolution10 bits plus sign
Y
Single supply5V
Y
Power dissipation37 mW (Max)
Ð In powerdown mode18 mW
Y
Conversion time5 ms (Max)
Y
Sampling rate74 kHz (Max)
Y
Band-gap reference2.5Vg2% (Max)
TL/H/11390– 1
COPSTM, HPCTMand MICROWIRETMare trademarks of National Semiconductor Corporation.
C
1995 National Semiconductor CorporationRRD-B30M75/Printed in U. S. A.
TL/H/11390
Connection Diagrams for Dual-In-Line and SO Packages
If Military/Aerospace specified devices are required,
please contact the National Semiconductor Sales
Office/Distributors for availability and specifications.
Supply Voltage (V
Total Reference Voltage (V
Voltage at Inputs and OutputsV
Input Current at Any Pin (Note 4)30 mA
Package Input Current (Note 4)120 mA
Package Dissipation at T
ESD Susceptability (Note 6)
Human Body Model2500V
Machine Model150V
Soldering Information
N packages (10 seconds)260
SO Package (Note 7)
Vapor Phase (60 seconds)215
Infrared (15 seconds)220
The following specifications apply for V
Signed Characteristics, V
limits apply for T
b
IN
e
e
T
A
J
a
a
e
to T
AV
MAX
e
GND for Unsigned Characteristics and f
T
MIN
a
e
ea
DV
; all other limits T
5.0 VDC,V
SymbolParameterConditions
SIGNED STATIC CONVERTER CHARACTERISTICS
Resolution with No Missing Codes10aSignBits
TUETotal Unadjusted Error (Note 13)
INLPositive and Negative Integral
Linearity Error
Positive and Negative
Full-Scale Error
Offset Error
Power Supply Sensitivity
Offset ErrorV
a
Full-Scale Error
b
Full-Scale Error
DC Common Mode Error (Note 14)V
a
ea
a
e
IN
5.0VtV
5.0Vg10%
V
IN
t
IN
Multiplexer Channel to
Channel Matching
A
b
e
0V
CLK
e
T
J
VINwhere
a
e
2.5 VDC,V
REF
e
2.5 MHz unless otherwise specified. Boldface
ea
25§C. (Notes 8, 9 and 10)
REF
b
e
GND, V
IN
TypicalLimitsUnits
(Note 11)(Note 12)(Limits)
g
2.0LSB(max)
g
1.25LSB(max)
g
1.5LSB(max)
g
1.5LSB(max)
g
0.2
g
0.2
g
0.1
g
0.1
g
0.1LSB
g
1.0LSB(max)
g
1.0LSB(max)
g
0.75LSB(max)
g
0.33LSB(max)
b
e
2.5V for
3
Electrical Characteristics (Continued)
The following specifications apply for V
Signed Characteristics, V
limits apply for T
b
IN
e
e
T
A
J
a
a
e
to T
AV
MAX
e
GND for Unsigned Characteristics and f
T
MIN
a
e
ea
DV
; all other limits T
5.0 VDC,V
e
A
SymbolParameterConditions
UNSIGNED STATIC CONVERTER CHARACTERISTICS
Resolution with No Missing Codes10Bits
a
TUETotal Unadjusted Error (Note 13)V
INLIntegral Linearity ErrorV
Full-Scale ErrorV
Offset ErrorV
Power Supply Sensitivity
Offset ErrorV
Full-Scale ErrorV
DC Common Mode Error (Note 14)V
Multiplexer Channel to Channel MatchingV
REF
REF
REF
REF
a
REF
a
IN
where
REF
a
a
a
ea
a
e
a
a
e
e
e
e
e
e
4.096V
4.096V
4.096V
4.096V
5.0Vg10%
4.096V
V
IN
5.0VtV
4.096V
DYNAMIC SIGNED CONVERTER CHARACTERISTICS
S/(NaD)Signal-to-Noise Plus Distortion RatioV
ENOBEffective Number of BitsV
THDTotal Harmonic DistortionV
IMDIntermodulation DistortionV
Full-Power BandwidthV
Multiplexer Channel to Channel Crosstalkf
IN
and f
IN
and f
IN
and f
IN
and f
IN
S/(N
IN
e
e
e
e
e
e
IN
IN
IN
IN
a
15 kHz
4.85 VPP,
4.85 VPP,
4.85 VPP,
4.85 VPP,
4.85 VPP, where
e
1 kHz to 15 kHz
e
1 kHz to 15 kHz
e
1 kHz to 15 kHz
e
1 kHz to 15 kHz
D) Decreases 3 dB
a
e
2.5 VDC,V
e
2.5 MHz unless otherwise specified. Boldface
25§C. (Notes 8, 9 and 10) (Continued)
T
CLK
J
REF
ea
REF
b
e
GND, V
TypicalLimitsUnits
(Note 11)(Note 12)(Limits)
g
0.75LSB
g
0.50LSB
g
g
g
0.1LSB
g
0.1LSB
b
e
V
IN
t
0V
IN
g
0.1LSB
g
0.1LSB
67dB
10.8Bits
b
78dB
b
85dB
380kHz
b
80dB
b
e
2.5V for
IN
1.25LSB(max)
1.25LSB(max)
4
Electrical Characteristics (Continued)
The following specifications apply for V
Signed Characteristics, V
limits apply for T
b
IN
e
e
T
A
J
a
a
e
to T
AV
MAX
e
GND for Unsigned Characteristics and f
T
MIN
a
e
ea
DV
; all other limits T
5.0 VDC,V
e
A
SymbolParameterConditions
DYNAMIC UNSIGNED CONVERTER CHARACTERISTIC
a
S/(NaD) Signal-to-Noise Plus Distortion RatioV
Effective BitsV
THDTotal Harmonic DistortionV
IMDIntermodulation DistortionV
Full-Power BandwidthV
Multiplexer Channel to Channel Crosstalk f
e
4.096V,
REF
e
V
4.0 VPP, and60dB
IN
e
f
1 kHz to 15 kHz
IN
a
e
4.096V,
REF
e
V
4.0 VPP, and9.8Bits
IN
e
f
1 kHz to 15 kHz
IN
a
e
4.096V,
REF
e
V
4.0 VPP, and
IN
e
f
1 kHz to 15 kHz
IN
a
e
4.096V,
REF
e
V
4.0 VPP, and
IN
e
f
1 kHz to 15 kHz
IN
e
4.0 VPP,
IN
a
e
V
where S/(N
IN
V
4.096V,380kHz
REF
REF
e
15 kHz,
a
e
a
4.096V
D) decreases 3 dB
REFERENCE INPUT AND MULTIPLEXER CHARACTERISTICS
Reference Input Resistance7kX
C
REF
Reference Input Capacitance70pF
MUX Input Voltage
C
IM
MUX Input Capacitance47pF
Off Channel Leakage Current (Note 15)On Channele5V and
e
Off Channel
On Channel
Off Channel
e
e
0V
0V and
5V
On Channel Leakage Current (Note 15)On Channele5V and
Off Channel
e
0V
On Channele0V and
e
Off Channel
5V
a
e
2.5 VDC,V
REF
e
2.5 MHz unless otherwise specified. Boldface
CLK
ea
T
25§C. (Notes 8, 9 and 10) (Continued)
J
REF
b
e
GND, V
TypicalLimitsUnits
(Note 11)(Note 12)(Limits)
b
70dB
b
73dB
b
80dB
a
AV
b
0.4
b
0.43.0mA(max)
0.43.0mA(max)
b
0.4
b
b
e
2.5V for
IN
5.0kX(min)
9.5kX(max)
b
50mV(min)
a
50 mV(max)
3.0mA(max)
3.0mA(max)
5
Electrical Characteristics (Continued)
The following specifications apply for V
Signed Characteristics, V
limits apply for T
SymbolParameterConditions
b
IN
e
e
T
A
J
a
a
e
to T
AV
MAX
e
GND for Unsigned Characteristics and f
T
MIN
a
e
ea
DV
; all other limits T
5.0 VDC,V
a
e
REF
CLK
e
ea
T
A
J
2.5 VDC,V
e
2.5 MHz unless otherwise specified. Boldface
25§C. (Notes 8, 9 and 10) (Continued)
REF
b
e
GND, V
TypicalLimitsUnits
(Note 11)(Note 12)(Limits)
REFERENCE CHARACTERISTICS
V
OutReference Output Voltage2.5Vg0.5%2.5Vg2%V(max)
REF
DV
/DTV
REF
DV
/DILLoad Regulation, Sourcing0 mAsI
REF
DV
/DILLoad Regulation, Sinking0 mAsI
REF
Out Temperature Coefficient
REF
Line Regulation5Vg10%
I
SC
Short Circuit CurrentV
Noise Voltage10 Hz to 10 kHz, C
DV
/DtLong-term Stability
REF
t
SU
Start-Up TimeC
s
a
4mA
L
s
b
1mA
L
Oute0V1322mA(max)
REF
e
100 mF5mV
L
e
100 mF100ms
L
g
40ppm/§C
g
0.003
g
0.2
g
0.3
g
120ppm/kHr
g
0.05%/mA(max)
g
0.6%/mA(max)
g
2.5mV(max)
DIGITAL AND DC CHARACTERISTICS
a
V
IN(1)
V
IN(0)
I
IN(1)
I
IN(0)
V
OUT(1)
V
OUT(0)
I
OUT
a
I
b
I
a
I
D
SC
SC
Logical ‘‘1’’ Input VoltageV
Logical ‘‘0’’ Input VoltageV
Logical ‘‘1’’ Input CurrentV
Logical ‘‘0’’ Input CurrentV
Logical ‘‘1’’ Output VoltageV
Logical ‘‘0’’ Output VoltageV
TRI-STATE Output CurrentV
Output Short Circuit SourceV
Current
Output Short Circuit Sink CurrentV
Digital Supply CurrentCSeHIGH, Power Up0.91.3mA(max)
(Note 17)CS
e
5.5V2.0V(min)
a
e
4.5V0.8V(max)
e
5.0V0.005
IN
e
0V
IN
a
e
4.5V, I
a
e
V
4.5V, I
a
e
4.5V, I
e
OUT
e
V
OUT
e
OUT
e
V
OUT
e
HIGH, Power Down0.20.4mA(max)
e
CS
HIGH, Power Down,0.550mA(max)
eb
OUT
OUT
OUT
360 mA2.4V(min)
eb
10 mA4.5V(min)
e
1.6 mA0.4V(min)
0V
5V
a
e
0V, V
a
4.5V
e
4.5V3015mA(min)
b
0.005
b
a
b
0.1
0.1
30
a
2.5mA(max)
b
2.5mA(max)
b
3.0mA(max)
a
3.0mA(max)
b
15mA(min)
and CLK Off
a
I
A
I
REF
Analog Supply CurrentCSeHIGH, Power Up2.76.0mA(max)
(Note 17)CS
Reference Input CurrentV
e
HIGH, Power Down315mA(max)
a
ea
CS
REF
2.5V and
e
HIGH, Power Up
0.6mA(max)
b
e
2.5V for
IN
6
Electrical Characteristics (Continued)
The following specifications apply for V
Signed Characteristics, V
limits apply for T
b
IN
e
e
T
A
J
a
a
e
to T
AV
MAX
e
GND for Unsigned Characteristics and f
T
MIN
a
e
ea
DV
; all other limits T
5.0 VDC,V
CLK
e
T
A
J
REF
ea
SymbolParameterConditions
AC CHARACTERISTICS
f
CLK
Clock Frequency3.02.5MHz(max)
Clock Duty Cycle40%(min)
t
C
t
A
t
SCS
t
SDI
t
HDI
t
AT
t
AC
t
DSARS
t
HDO
t
AD
t1H,t
t
DCS
t
CS(H)
t
CS(L)
t
SC
t
PD
t
PC
C
IN
C
OUT
Conversion Time1212Clock
Acquisition Time4.54.5Clock
CS Set-Up Time, Set-Up Time from Falling Edge of1430ns(min)
CS to Rising Edge of Clock
DI Set-Up Time, Set-Up Time from Data Valid on
DI to Rising Edge of Clock
DI Hold Time, Hold Time of DI Data from Rising
Edge of Clock to Data not Valid on DI
DO Access Time from Rising Edge of CLK When
CS
is ‘‘Low’’ during a Conversion
DO or SARS Access Time from CS, Delay from
Falling Edge of CS
to Data Valid on DO or SARS
Delay from Rising Edge of Clock to Falling Edge of
SARS when CS
is ‘‘Low’’
DO Hold Time, Hold Time of Data on DO after
Falling Edge of Clock
DO Access Time from Clock, Delay from Falling
Edge of Clock to Valid Data of DO
Delay from Rising Edge of CS to DO or SARS
0H
TRI-STATE
Delay from Falling Edge of Clock to Falling Edge of
CS
CS ‘‘HIGH’’ Time for A/D Reset after Reading of
Conversion Result
ADC10731 Minimum CS ‘‘Low’’ Time to Start a
Conversion
Time from End of Conversion to CS Going ‘‘Low’’5 CLK5 CLKcycle(min)
Delay from Power-Down command to 10% of
Operating Current
Delay from Power-Up Command to Ready to Start
a New Conversion
Capacitance of Logic Inputs7pF
Capacitance of Logic Outputs12pF
a
e
2.5 VDC,V
e
2.5 MHz unless otherwise specified. Boldface
REF
b
e
GND, V
b
e
IN
25§C. (Note 16)
TypicalLimitsUnits
(Note 11)(Note 12)(Limits)
5kHz(min)
60%(max)
55ms(max)
22ms(max)
b
(1 t
14 ns)
CLK
(1 t
b
30 ns)
CLK
1625ns(min)
225ns(min)
3050ns(min)
3070ns(max)
100200ns(max)
2035ns(max)
4080ns(max)
4050ns(max)
2030ns(min)
1 CLK1 CLKcycle(min)
1 CLK1 CLKcycle(min)
1ms
10
2.5V for
Cycles
Cycles
(max)
ms
7
Electrical Characteristics (Continued)
Note 1: Absolute Maximum Ratings indicate limits beyond which damage to the device may occur.
Note 2: Operating Ratings indicate conditions for which the device is functional, but do not guarantee specific performance limits. For guaranteed specifcations and
test conditions, see the Electrical Characteristics. The guaranteed specifications apply only for the test conditions listed. Some performance characteristics may
degrade when the device is not operated under the listed test conditions.
Note 3: All voltages are measured with respect to GND, unless otherwise specified.
Note 4: When the input voltage (V
The 120 mA maximum package input current rating limits the number of pins that can safely exceed the power supplies with an input current of 30 mA to four.
Note 5: The maximum power dissipation must be derated at elevated temperatures and is dictated by T
allowable power dissipation at any temperature is P
device, T
e
150§C. The typical thermal resistance (iJA) of these Paris when board mounted can be found in the following table:
Jmax
) at any pin exceeds the power supplies (V
IN
e
b
(T
D
Jmax
Part NumberThermal ResistancePackage Type
ADC10731CIN82§C/WN16E
ADC10731CIWM90
ADC10732CIN47
ADC10732CIWM80
ADC10734CIMSA134
ADC10734CIN47
ADC10734CIWM80§C/WM20B
ADC10738CIN60
ADC10738CIWM75
Note 6: The human body model is a 100 pF capacitor discharged through a 1.5 kX resistor into each pin. The machine model is a 200 pF capacitor discharged
directly into each pin.
Note 7: See AN-450 ‘‘Surface Mounting Methods and Their Effect on Product Reliability’’ or the section titied ‘‘Surtace Mount’’ found in any post 1986 National
Semiconductor Linear Data Book for other methods of soldering surtace mount devices.
Note 8: Two on-ohip diodes are tied to each analog input as shown below. They will forward-conduct for analog input voltages one diode drop below ground or one
diode drop greater than V
especially at elevated temperatures, which will cause errors In the conversion result. The specification allows 50 mV forward bias of either diode; this means that as
long as the analog V
corrupt the reading of a selected channel. If AV
a
supply. Be careful during testing at low Valevels (a4.5V), as high level analog inputs (a5V) can cause an input diode to conduct,
does not exceed the supply voltage by more than 50 mV, the output code will be oorrect. Exceeding this range on an unselected channel will
IN
a
and DVaare minimum (4.5 VDC) and full scale must be
k
IN
TA)/iJAor the number given In the Absolute Maximum Ratings, whichever is lower. For this
C/WM16B
§
C/WN20A
§
C/WM20B
§
C/WMSA20
§
C/WN20A
§
C/WN24A
§
C/WM24B
§
GND or V
l
AVaor DVa), the current at that pln should be limited to 30 mA.
IN
, iJAand the ambient temperature, TA. The maximum
Jmax
s
a
4.55 VDC.
Note 9: No connection exists between AVaand DVaon the chip.
To guarantee accuracy, it is required that the AV
a
and DVabe connected together to a power supply with separate bypass filter at eacn Vapin.
TL/H/11390– 6
Note 10: One LSB is referenced to 10 bits of resolution.
e
Note 11: Typicals are at T
Note 12: Tested limits are guaranteed to National’s AOQL (Average Outgolng Quality Level).
e
T
25§C and represent most likely pararmetric norm.
J
A
Note 13: Total unadjusted error includes offset, full-scale, linearity, multiplexer, and hold step errors.
Note 14: The DC common-mode error is measured in the differential multiplexer mode with the assigned positive and negative input channels shorted together.
Note 15: Channel leakage current is measured after the channel selection.
Note 16: All the timing specifications are tested at the TTL logic levels, V
to 1.4V.
Note 17: The voltage applied to the digital inputs will affect the current drain during power down. These devices are tested with CMOS logic levels (logic Low
and logic High
e
5V). TTL levels increase the current, during power down, to about 300 mA.
e
0.8V for a falling edge and V
IL
e
2.0V for a rising. TRl-STATE voltage level is forced
IH
e
8
0V
Electrical Characteristics (Continued)
FIGURE 1A. Transter Characteristic
FIGURE 1B. Simplified Error Curve vs Output Code
TL/H/11390– 8
TL/H/11390– 26
9
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