ADC1061 10-Bit High-Speed mP-Compatible
A/D Converter with Track/Hold Function
ADC1061 10-Bit High-Speed mP-Compatible A/D Converter with Track/Hold Function
December 1994
General Description
Using a modified half-flash conversion technique, the 10-bit
ADC1061 CMOS analog-to-digital converter offers very fast
conversion times yet dissipates a maximum of only 235 mW.
The ADC1061 performs a 10-bit conversion in two lowerresolution ‘‘flashes’’, thus yielding a fast A/D without the
cost, power dissipation, and other problems associated with
true flash approaches.
The analog input voltage to the ADC1061 is tracked and
held by an internal sampling circuit. Input signals at frequencies from DC to greater than 160 kHz can therefore be digitized accurately without the need for an external sampleand-hold circuit.
For ease of interface to microprocessors, the ADC1061 has
Features
Y
1.8 ms maximum conversion time to 10 bits
Y
Low power dissipation: 235 mW (maximum)
Y
Built-in track-and-hold
Y
No external clock required
Y
Singlea5V supply
Y
No missing codes over temperature
Applications
Y
Waveform digitizers
Y
Disk drives
Y
Digital signal processor front ends
Y
Mobile telecommunications
been designed to appear as a memory location or I/O port
without the need for external interface logic.
Simplified Block and Connection Diagrams
Dual-In-Line Package
TL/H/10559– 2
Top View
TL/H/10559– 1
Order Number
Ordering Information
Industrial (b40§CsT
ADC1061CIJ J20A
s
85§C) Package
A
ADC1061CIJ, ADC1061CIN,
ADC1061CIWM or ADC1061CMJ
See NS Package J20A,
M20B or N20A
ADC1061CIN N20A
ADC1061CIWM M20B
Military (b55§CsT
s
125§C) Package
A
ADC1061CMJ J20A
TRI-STATEÉis a registered trademark of National Semiconductor Corporation.
C
1995 National Semiconductor Corporation RRD-B30M75/Printed in U. S. A.
TL/H/10559
Absolute Maximum Ratings (Notes1&2)
If Military/Aerospace specified devices are required,
please contact the National Semiconductor Sales
Office/Distributors for availability and specifications.
Supply Voltage (V
Voltage at any Input or Output
Input Current at Any Pin (Note 3) 5 mA
Package Input Current (Note 3) 20 mA
Power Dissipation (Note 4) 875 mW
ESD Susceptibility (Note 5) 1500V
a
e
AV
CC
e
DVCC)
b
0.3V to V
b
0.3V toa6V
a
a
0.3V
Soldering Information (Note 6)
N Package (10 seconds) 260
J Package (10 seconds) 300
SO Package (Note 6):
Vapor Phase (60 seconds) 215
Infrared (15 seconds) 220
Junction Temperature, T
J
Storage Temperature Range
b
a
150§C
65§Ctoa150§C
Operating Ratings (Notes1&2)
s
s
T
Temperature Range T
ADC1061CIJ, ADC1061CIN,
ADC1061CIWM
ADC1061CMJ
b
40§CsT
b
55§CsT
MIN
Supply Voltage Range 4.5V to 5.5V
T
A
MAX
s
a
85§C
A
s
a
125§C
A
C
§
C
§
C
§
C
§
Converter Characteristics
The following specifications apply for V
limits apply for T
e
e
T
A
J
a
ea
T
to T
MIN
5V, V
; all other limits T
MAX
REF(a)
e
5V, and V
e
A
Symbol Parameter Conditions
Resolution 10 Bits
Total Unadjusted Error
Integral Linearity Error
Differential Linearity Error
Offset Error
Fullscale Error
R
REF
R
REF
V
REF(a)
V
REF(b)
V
REF(a)
V
REF(b)
V
IN
V
IN
Reference Resistance 0.65 0.4 kX (Min)
Reference Resistance 0.65 0.9 kX (Max)
V
Input Voltage V
REF(a)
V
Input Voltage GNDb0.05 V (Min)
REF(b)
V
Input Voltage V
REF(a)
V
Input Voltage V
REF(b)
Input Voltage V
Input Voltage GNDb0.05 V (Min)
Analog Input Leakage Current CSeVa,V
CSeVa,V
Power Supply Sensitivity V
a
V
REF
e
5Vg5%
e
IN
IN
4.75V
REF(b)
e
T
25§C.
J
a
e
V
e
GND 0.01
e
GND unless otherwise specified. Boldface
Typical Limit Units
(Note 7) (Note 8) (Limit)
g
1.0
g
0.3
g
0.1
g
0.5
g
2.0 LSB (Max)
g
1.5 LSB (Max)
g
1.0 LSB (Max)
g
1.0 LSB (Max)
g
1.0 LSB (Max)
a
a
0.05 V (Max)
REF(b)
REF(b)
a
a
0.05 V (Max)
V (Min)
V (Max)
0.01 3 mA (Max)
b
3 mA (Max)
g
0.125
g
0.5 LSB
2
DC Electrical Characteristics
The following specifications apply for V
limits apply for T
e
e
T
A
J
a
ea
T
to T
MIN
5V, V
; all other limits T
MAX
REF(a)
e
5V, and V
e
A
T
Symbol Parameter Conditions
a
V
IN(1)
V
IN(0)
I
IN(1)
I
IN(0)
V
OUT(1)
V
OUT(0)
I
OUT
DI
CC
AI
CC
Logical ‘‘1’’ Input Voltage V
Logical ‘‘0’’ Input Voltage V
Logical ‘‘1’’ Input Current V
Logical ‘‘0’’ Input Current V
Logical ‘‘1’’ Output Voltage V
Logical ‘‘0’’ Output Voltage V
TRI-STATEÉOutput Current V
DVCCSupply Current CSeWReRDe0 0.1 2 mA (Max)
AVCCSupply Current CSeWReRDe03045 mA (Max)
e
5.25V 2.0 V (Min)
a
e
4.75V 0.8 V (Max)
e
5V 0.005 1.0 mA (Max)
IN(1)
e
0V
IN(0)
a
e
4.75V I
V
V
a
a
OUT
OUT
OUT
e
4.75V I
OUT
e
4.75V I
OUT
e
5V 0.1 50 mA (Max)
e
0V
e
REF(b)
e
25§C.
J
GND unless otherwise specified. Boldface
Typical Limit Units
(Note 7) (Note 8) (Limits)
b
0.005
eb
360 mA 2.4 V (Min)
eb
10 mA 4.5 V (Min)
e
1.6 mA 0.4 V (Max)
b
0.1
b
1.0 mA (Max)
b
50 mA (Max)
AC Electrical Characteristics
The following specifications apply for V
specified. Boldface limits apply for T
a
ea
e
T
A
e
MIN
e
t
to T
f
MAX
20 ns, V
REF(a)
; all other limits T
r
5V, t
e
T
J
Symbol Parameter Conditions
t
CONV
t
CRD
t
ACC1
t
ACC2
t
SH
t1H,t
t
INTH
t
ID
t
P
Conversion Time from Rising Edge Mode 1
of S
/H to Falling Edge of INT
Conversion Time for MODE 2 Mode 2
(RD Mode)
Access Time (Delay from Falling Mode 1; C
Edge of RD
to Output Valid)
Access Time (Delay from Falling Mode 2; C
Edge of RD
to Output Valid)
Minimum Sample Time
TRI-STATE Control (Delay from Rising R
0H
Edge of RD to High-Z State)
Delay from Rising Edge of RD
to Rising Edge of INT
Delay from INT to Output Valid C
Delay from End of Conversion
to Next Conversion
e
L
e
L
(Figure 1)
; (Note 9) 250 ns (Max)
e
L
e
L
e
1k, C
L
100 pF 20 50 ns (Max)
SR Slew Rate for Correct
Track-and-Hold Operation
100 pF
100 pF
10 pF
e
5V, and V
A
e
e
T
J
REF(b)
25§C.
e
GND unless otherwise
Typical Limit Units
(Note 7) (Note 8) (Limits)
1.2 1.8 ms (Max)
1.8 2.4 ms (Max)
20 50 ns (Max)
a
t
50 ns (Max)
CRD
20 50 ns (Max)
10 50 ns (Max)
10 20 ns (Max)
2.5 V/ms
3
AC Electrical Characteristics (Continued)
The following specifications apply for V
specified. Boldface limits apply for T
Symbol Parameter Conditions
C
VIN
C
OUT
C
IN
Note 1: Absolute Maximum Ratings indicate limits beyond which damage to the device may occur. Operating Ratings indicate conditions for which the device is
functional, but do not guarantee specific performance limits. For guaranteed specifications and test conditions, see the Electrical Characteristics. The guaranteed
specifications apply only for the test conditions listed. Some performance characteristics may degrade when the device is not operated under the listed test
conditions.
Note 2: All voltages are measured with respect to GND, unless otherwise specified.
Note 3: When the input voltage (V
to 5 mA or less. The 20 mA package input current limits the number of pins that can safely exceed the power supplies with an input of 5 mA to four.
Note 4: The maximum power dissipation must be derated at elevated temperatures and is dictated by T
allowable power dissipation at any temperature is P
device, T
JMAX
C/W for the small outline (WM) package.
and 65
§
Note 5: Human body model, 100 pF discharged through a 1.5 kX resistor.
Note 6: See AN-450 ‘‘Surface Mounting Methods and Their Effect on Product Reliability’’ or the section titled ‘‘Surface Mount’’ found in a current National
Semiconductor Linear Data Book for other methods of soldering surface mount devices.
Note 7: Typicals are at 25
Note 8: Limits are guaranteed to National’s AOQL (Average Outgoing Quality Level).
Note 9: Accuracy may degrade if tSH is shorter than the value specified.
Analog Input Capacitance 35 pF
Logic Output Capacitance 5 pF
Logic Input Capacitance 5 pF
) at any pin exceeds the power supply rails (V
IN
e
150§C, and the typical thermal resistance (iJA) when board mounted is 47§C/W for the plastic (N) package, 85§C/W for the ceramic (J) package,
C and represent most likely parametric norm.
§
a
ea
e
T
A
e
5V, t
e
J
e
t
to T
f
MAX
20 ns, V
; all other limits T
r
T
MIN
REF(a)
e
5V, and V
e
A
e
REF(b)
e
T
25§C.
J
GND unless otherwise
Typical Limit Units
(Note 7) (Note 8)
k
IN
e
b
(T
D
TA)/iJAor the number given in the Absolute Maximum Ratings, whichever is lower. For this
JMAX
Vbor V
l
Va) the absolute value of current at that pin should be limited
IN
, iJAand the ambient temperature, TA. The maximum
JMAX
TRI-STATE Test Circuits and Waveforms
TL/H/10559– 3
TL/H/10559– 5
TL/H/10559– 4
TL/H/10559– 6
4
Timing Diagrams
FIGURE 1. Mode 1. The conversion time (t
CONV
FIGURE 2. Mode 2 (RD Mode). The conversion time (t
the sampling time, and is determined by the internal timer.
) is determined by the internal timer.
) includes
CRD
TL/H/10559– 7
TL/H/10559– 8
5
Typical Performance Characteristics
Zero (Offset) Error
vs Reference Voltage
Linearity Error vs
Reference Voltage
Mode 1 Conversion Time
TL/H/10559– 9
vs Temperature
TL/H/10559– 11
Pin Descriptions
Symbol Function
DV
, These are the digital and analog positive
CC
AV
CC
(1, 6) always be connected to the same
INT
(2) This is the active low interrupt output.
/H (3) This is the Sample/Hold control input.
S
RD
(4) This is the active low Read control input.
supply voltage inputs. They should
voltage source, but are brought out
separately to allow for separate bypass
capacitors. Each supply pin should be
bypassed with a 0.1 mF ceramic
capacitor in parallel with a 10 mF
tantalum capacitor.
INT
goes low at the end of each
conversion, and returns to a high state
following the rising edge of RD
.
When this pin is forced low, it causes
the analog input signal to be sampled
and initiates a new conversion.
When this pin is low, any data present in
the ADC1061’s output registers will be
placed on the data bus. In Mode 2, the
Read signal must be low until INT
low. Until INT
goes low, the data at the
output pins will be incorrect.
goes
Mode 2 Conversion Time
TL/H/10559– 10
vs Temperature
TL/H/10559– 12
Symbol Function
CS
(5) This is the active low Chip Select control
input. This pin enables the S
/H and RD
inputs.
, These are the reference voltage inputs.
V
b
REF
V
a
REF
(7, 9) between GND
They may be placed at any voltage
b
50 mV, but V
V
. An input voltage equal to
b
REF
V
produces an output code of 0,
b
REF
and an input voltage equal to V
must be greater than
a
REF
50 mV and V
CC
1LSB produces an output code of 1023.
(8) This is the analog input pin. The
V
IN
impedance of the source should be less
than 500X for best accuracy and
conversion speed. To avoid damage to
the ADC1061, V
allowed to extend beyond the power
should not be
IN
supply voltages by more than 300 mV
unless the drive current is limited. For
accurate conversions, V
extend more than 50 mV beyond the
should not
IN
supply voltages.
REF
a
b
a
6
Pin Descriptions (Continued)
Symbol Function
GND (10) This is the power supply ground pin. The
ground pin should be connected to a
‘‘clean’’ ground reference point.
DB0–DB9 These are the TRI-STATE output pins.
(11-20)
Functional Description
The ADC1061 digitizes an analog input signal to 10 bits accuracy by performing two lower-resolution ‘‘flash’’ conversions. The first flash conversion provides the six most significant bits (MSBs) of data, and the second flash conversion
provides the four least significant bits (LSBs).
Figure 3
is a simplified block diagram of the converter. Near
the center of the diagram is a string of resistors. At the
bottom of the string of resistors are 16 resistors, each of
which has a value 1/1024th the resistance of the whole
resistor string. These lower 16 resistors (the LSB Ladder)
therefore have a voltage drop of 16/1024, or 1/64th of the
total reference voltage (V
The remainder of the resistor string is made up of eight
groups of eight resistors connected in series. These comprise the MSB Ladder. Each section of the MSB Ladder
has 1/8th of the total reference voltage across it, and each
of the MSB resistors has 1/64th of the total reference voltage across it. Tap points across all of these resistors can be
REF
b
VREFb) across them.
a
connected, in groups, to the sixteen comparators at the
right of the diagram.
On the left side of the diagram is a string of seven resistors
connected between V
compare the input voltage with the tap voltages on the re-
REF
b
V
a
. Six comparators
b
REF
sistor string to provide an estimate of the input voltage. This
estimate is then used to control the multiplexer that connects the MSB Ladder to the sixteen comparators on the
right. Note that the comparators on the left needn’t be very
accurate; they simply provide an estimate of the input voltage. Only the sixteen comparators on the right and the six
on the left are necessary to perform the initial six-bit flash
conversion, instead of the 64 comparators that would be
required using conventional half-flash methods.
To perform a conversion, the estimator compares the input
voltage with the tap voltages on the seven resistors on the
left. The estimator decoder then determines which MSB
Ladder tap points will be connected to the sixteen comparators on the right. For example, assume that the estimator
determines that V
The estimator decoder will instruct the comparator mux to
is between 11/16 and 13/16 of VREF.
IN
connect the 16 comparators to the taps on the MSB Ladder
between 10/16 and 14/16 of VREF. The 16 comparators
will then perform the first flash conversion. Note that since
the comparators are connected to Ladder voltages that extend beyond the range indicated by the estimator circuit,
errors in the estimator as large as (/16 of the reference voltage (64 LSBs) will be corrected. This first flash conversion
produces the six most significant bits of data.
FIGURE 3. Block Diagram of the Modified Half-Flash Converter Architecture
7
TL/H/10559– 13
Functional Description (Continued)
The remaining four LSBs may now be determined using the
same sixteen comparators that were used for the first flash
conversion. The MSB Ladder tap voltage just below the input voltage (as determined by the first flash) is subtracted
from the input voltage and compared with the tap points on
the sixteen LSB Ladder resistors. The result of this second
flash conversion is then decoded, and the full 10-bit result is
latched.
Note that the sixteen comparators used in the first flash
conversion are reused for the second flash. Thus, the halfflash conversion techniques used in the ADC1061 needs
only a small fraction of the number of comparators that
would be required for a traditional flash converter, and far
fewer than would be used in a conventional half-flash approach. This allows the ADC1061 to perform high-speed
conversions without excessive power drain.
Applications Information
1.0 Modes of Operation
The ADC1061 has two basic digital interface modes. These
are illustrated in
Figure 1
and
Figure 2
.
MODE 1
In this mode, the S
S
/H is pulled low for a minimum of 250 ns. This causes the
comparators in the ‘‘coarse’’ flash converter to become active. When S
sion is latched and the ‘‘fine’’ conversion begins. After approximately 1.2 ms (1.8 ms maximum), INT
ing that the conversion results are latched and can be read
by pulling RD
or RD
.CSis internally ‘‘ANDed’’ with the sample and read
control signals; the input voltage is sampled when CS
S
/H are low, and is read when CS and RD are low.
MODE 2
In Mode 2, also called ‘‘RD mode’’, the S
are tied together. A conversion is initiated by pulling both
pins low. The ADC1061 samples the input voltage and
causes the coarse comparators to become active. An internal timer then terminates the coarse conversion and begins
the fine conversion.
About 1.8 ms (2.4 ms maximum) after S
pulled low, INT
complete. Approximately 20 ns later the data appearing on
the TRI-STATE output pins will be valid. Note that data will
appear on these pins throughout the conversion, but will be
valid only after INT
/H pin controls the start of conversion.
/H goes high, the result of the coarse conver-
goes low, indicat-
low. Note that CS must be low to enable S/H
and
/H and RD pins
/H and RD are
goes low, indicating that the conversion is
goes low.
FIGURE 4. Typical connection. Note the multiple bypass capacitors on the reference
and power supply pins. If V
ground using multiple capacitors (see 5.0 ‘‘Power Supply Considerations’’).
b
is not grounded, it should also be bypassed to
REF
8
TL/H/10559– 14
2.0 Reference Considerations
The ADC1061 has two reference inputs. These inputs,
V
and V
a
REF
to full-scale range of the input signal. The reference inputs
can be connected to span the entire supply voltage range
e
(V
b
REF
or they can be connected to different voltages (as long as
they are between ground and V
are required. Reducing the overall V
5V increases the sensitivity of the converter (e.g., if V
2V, then 1LSBe1.953 mV). Note, however, that linearity
, are fully differential and define the zero
b
REF
0V, V
e
VCC) for ratiometric applications,
a
REF
) when other input spans
CC
REF
span to less than
REF
and offset errors become larger when lower reference voltages are used. See the Typical Performance Curves for
more information. Reference voltages less than 2V are not
recommended.
In most applications, V
ground, but it is often useful to have an input span that is
will simply be connected to
b
REF
offset from ground. This situation is easily accommodated
by the reference configuration used in the ADC1061.
V
can be connected to a voltage other than ground as
b
REF
long as the reference for this pin is capable of sinking current. If V
bypass it with multiple capacitors.
is connected to a voltage other than ground,
b
REF
Since the resistance between the two reference inputs can
be as low as 400X, the voltage source driving the reference
inputs should have low output impedance. Any noise on either reference input is a potential cause of conversion errors, so each of these pins must be supplied with a clean,
low noise voltage source. Each reference pin should normally be bypassed with a 10 mF tantalum and a 0.1 mF
ceramic capacitor. More bypassing may be necessary in
some systems.
The choice of reference voltage source will depend on the
requirements of the system. In ratiometric data acquisition
systems with a power supply-referenced sensor, the reference inputs are normally connected to V
no reference other than the power supply is necessary. In
and GND, and
CC
absolute measurement systems requiring 10-bit accuracy, a
reference with better than 0.1% accuracy will be necessary.
3.0 The Analog Input
The ADC1061 samples the analog input voltage once every
conversion cycle. When this happens, the input is briefly
connected to an impedance approximately equal to 600X in
series with 35 pF. Short-duration current spikes can therefore be observed at the analog input during normal operation. These spikes are normal and do not degrade the convertor’s performance.
Note that large source impedances can slow the charging of
the sampling capacitors and degrade conversion accuracy.
Therefore, only signal sources with output impedances less
than 500X should be used if rated accuracy is to be
achieved at the minimum sample time. If the sampling time
is increased, the source impedance can be larger. If a signal
source has a high output impedance, its output should be
buffered with an operational amplifier. The operational amplifier’s output should be well-behaved when driving a
switched 35 pF/600X load. Any ringing or voltage shifts at
the op amp’s output during the sampling period can result in
conversion errors.
Correct conversion results will be obtained for input volt-
e
ages greater than GND
50 mV. Do not allow the signal source to drive the analog
input pin more than 300 mV higher than AV
more than 300 mV lower than GND. If the analog input pin is
b
50 mV and less than V
CC
a
a
and DVCC,or
forced beyond these voltages, the current flowing through
the pin should be limited to 5 mA or less to avoid permanent
damage to the ADC1061.
4.0 Inherent Sample-and-Hold
Because the ADC1061 samples the input signal once during
each conversion, it is capable of measuring relatively fast
input signals without the help of an external sample-hold. In
a conventional successive-approximation A/D converter,
regardless of speed, the input signal must be stable to bet-
g
ter than
(/2 LSB during each conversion cycle or significant errors will result. Consequently, even for many relatively slow input signals, the signals must be externally sampled
and held constant during each conversion.
The ADC1061 can perform accurate conversions of input
signals at frequencies from DC to greater than 160 kHz
without the need for external sampling circuitry.
5.0 Power Supply Considerations
The ADC1061 is designed to operate from aa5V (nominal)
power supply. There are two supply pins, AV
These pins allow separate external bypass capacitors for
the analog and digital portions of the circuit. To guarantee
accurate conversions, the two supply pins should be connected to the same voltage source, and each should be
bypassed with a 0.1 mF ceramic capacitor in parallel with a
10 mF tantalum capacitor. Depending on the circuit board
layout and other system considerations, more bypassing
may be necessary.
It is important to ensure that none of the ADC1061’s input or
output pins are ever driven to a voltage more than 300 mV
above AV
these voltage limits are exceeded, the overdrive current into
and DVCC, or more than 300 mV below GND. If
CC
or out of any pin on the ADC1061 must be limited to less
than 5 mA, and no more than 20 mA of overdrive current (all
overdriven pins combined) should flow. In systems with multiple power supplies, this may require careful attention to
power supply sequencing. The ADC1061’s power supply
pins should be at the proper voltage before signals are applied to any of the other pins.
and DVCC.
CC
9
6.0 Layout and Grounding
In order to ensure fast, accurate conversions from the
ADC1061, it is necessary to use appropriate circuit board
layout techniques. The analog ground return path should be
low-impedance and free of noise from other parts of the
system. Noise from digital circuitry can be especially troublesome, so digital grounds should always be separate from
analog grounds. For best performance, separate ground
planes should be provided for the digital and analog parts of
the system.
All bypass capacitors should be located as close to the converter as possible and should connect to the converter and
to ground with short traces. The analog input should be isolated from noisy signal traces to avoid having spurious signals couple to the input. Any external component (e.g., a
filter capacitor) connected across the converter’s input
should be connected to a very clean ground return point.
Grounding the component at the wrong point will result in
reduced conversion accuracy.
10
Physical Dimensions inches (millimeters)
Order Number ADC1061CIJ or ADC1061CMJ
NS Package Number J20A
Order Number ADC1061CIWM
NS Package Number M20B
11
Physical Dimensions inches (millimeters) (Continued) Lit.
Order Number ADC1061CIN
NS Package Number N20A
Ý
101004
LIFE SUPPORT POLICY
NATIONAL’S PRODUCTS ARE NOT AUTHORIZED FOR USE AS CRITICAL COMPONENTS IN LIFE SUPPORT
DEVICES OR SYSTEMS WITHOUT THE EXPRESS WRITTEN APPROVAL OF THE PRESIDENT OF NATIONAL
SEMICONDUCTOR CORPORATION. As used herein:
1. Life support devices or systems are devices or 2. A critical component is any component of a life
systems which, (a) are intended for surgical implant support device or system whose failure to perform can
into the body, or (b) support or sustain life, and whose be reasonably expected to cause the failure of the life
failure to perform, when properly used in accordance support device or system, or to affect its safety or
with instructions for use provided in the labeling, can effectiveness.
be reasonably expected to result in a significant injury
to the user.
ADC1061 10-Bit High-Speed mP-Compatible A/D Converter with Track/Hold Function
National Semiconductor National Semiconductor National Semiconductor National Semiconductor National Semiconductores National Semiconductor
Corporation GmbH Japan Ltd. Hong Kong Ltd. Do Brazil Ltda. (Australia) Pty, Ltd.
2900 Semiconductor Drive Livry-Gargan-Str. 10 Sumitomo Chemical 13th Floor, Straight Block, Rue Deputado Lacorda Franco Building 16
P.O. Box 58090 D-82256 F4urstenfeldbruck Engineering Center Ocean Centre, 5 Canton Rd. 120-3A Business Park Drive
Santa Clara, CA 95052-8090 Germany Bldg. 7F Tsimshatsui, Kowloon Sao Paulo-SP Monash Business Park
Tel: 1(800) 272-9959 Tel: (81-41) 35-0 1-7-1, Nakase, Mihama-Ku Hong Kong Brazil 05418-000 Nottinghill, Melbourne
TWX: (910) 339-9240 Telex: 527649 Chiba-City, Tel: (852) 2737-1600 Tel: (55-11) 212-5066 Victoria 3168 Australia
National does not assume any responsibility for use of any circuitry described, no circuit patent licenses are implied and National reserves the right at any time without notice to change said circuitry and specifications.
Fax: (81-41) 35-1 Ciba Prefecture 261 Fax: (852) 2736-9960 Telex: 391-1131931 NSBR BR Tel: (3) 558-9999
Tel: (043) 299-2300 Fax: (55-11) 212-1181 Fax: (3) 558-9998
Fax: (043) 299-2500
Loading...