Rainbow Electronics ADC1061 User Manual

ADC1061 10-Bit High-Speed mP-Compatible
A/D Converter with Track/Hold Function

ADC1061 10-Bit High-Speed mP-Compatible A/D Converter with Track/Hold Function

December 1994

General Description

Using a modified half-flash conversion technique, the 10-bit
ADC1061 CMOS analog-to-digital converter offers very fast
conversion times yet dissipates a maximum of only 235 mW.
The ADC1061 performs a 10-bit conversion in two lower­resolution ‘‘flashes’’, thus yielding a fast A/D without the
cost, power dissipation, and other problems associated with
true flash approaches.

The analog input voltage to the ADC1061 is tracked and
held by an internal sampling circuit. Input signals at frequen­cies from DC to greater than 160 kHz can therefore be digi­tized accurately without the need for an external sample­and-hold circuit.

For ease of interface to microprocessors, the ADC1061 has

Features

Y

1.8 ms maximum conversion time to 10 bits

Y

Low power dissipation: 235 mW (maximum)

Y

Built-in track-and-hold

Y

No external clock required

Y

Singlea5V supply

Y

No missing codes over temperature

Applications

Y

Waveform digitizers

Y

Disk drives

Y

Digital signal processor front ends

Y

Mobile telecommunications

been designed to appear as a memory location or I/O port
without the need for external interface logic.

Simplified Block and Connection Diagrams

Dual-In-Line Package

TL/H/10559– 2

Top View

TL/H/10559– 1

Order Number

Ordering Information

Industrial (b40§CsT

ADC1061CIJ J20A

s

85§C) Package

A

ADC1061CIJ, ADC1061CIN,

ADC1061CIWM or ADC1061CMJ

See NS Package J20A,

M20B or N20A

ADC1061CIN N20A

ADC1061CIWM M20B

Military (b55§CsT

s

125§C) Package

A

ADC1061CMJ J20A

TRI-STATEÉis a registered trademark of National Semiconductor Corporation.

C

1995 National Semiconductor Corporation RRD-B30M75/Printed in U. S. A.

TL/H/10559

Absolute Maximum Ratings (Notes1&2)

If Military/Aerospace specified devices are required,
please contact the National Semiconductor Sales
Office/Distributors for availability and specifications.

Supply Voltage (V

Voltage at any Input or Output

Input Current at Any Pin (Note 3) 5 mA

Package Input Current (Note 3) 20 mA

Power Dissipation (Note 4) 875 mW

ESD Susceptibility (Note 5) 1500V

a

e

AV

CC

e

DVCC)

b

0.3V to V

b

0.3V toa6V

a

a

0.3V

Soldering Information (Note 6)

N Package (10 seconds) 260
J Package (10 seconds) 300
SO Package (Note 6):

Vapor Phase (60 seconds) 215
Infrared (15 seconds) 220

Junction Temperature, T

J

Storage Temperature Range

b

a

150§C

65§Ctoa150§C

Operating Ratings (Notes1&2)

s

s

T

Temperature Range T

ADC1061CIJ, ADC1061CIN,
ADC1061CIWM
ADC1061CMJ

b

40§CsT

b

55§CsT

MIN

Supply Voltage Range 4.5V to 5.5V

T

A

MAX

s

a

85§C

A

s

a

125§C

A

C

§

C

§

C

§

C

§

Converter Characteristics

The following specifications apply for V

limits apply for T

e

e

T

A

J

a

ea

T

to T

MIN

5V, V

; all other limits T

MAX

REF(a)

e

5V, and V

e

A

Symbol Parameter Conditions

Resolution 10 Bits

Total Unadjusted Error

Integral Linearity Error

Differential Linearity Error

Offset Error

Fullscale Error

R

REF

R

REF

V

REF(a)

V

REF(b)

V

REF(a)

V

REF(b)

V

IN

V

IN

Reference Resistance 0.65 0.4 kX (Min)

Reference Resistance 0.65 0.9 kX (Max)

V

Input Voltage V

REF(a)

V

Input Voltage GNDb0.05 V (Min)

REF(b)

V

Input Voltage V

REF(a)

V

Input Voltage V

REF(b)

Input Voltage V

Input Voltage GNDb0.05 V (Min)

Analog Input Leakage Current CSeVa,V

CSeVa,V

Power Supply Sensitivity V

a

V

REF

e

5Vg5%

e

IN

IN

4.75V

REF(b)

e

T

25§C.

J

a

e

V

e

GND 0.01

e

GND unless otherwise specified. Boldface

Typical Limit Units

(Note 7) (Note 8) (Limit)

g

1.0

g

0.3

g

0.1

g

0.5

g

2.0 LSB (Max)

g

1.5 LSB (Max)

g

1.0 LSB (Max)

g

1.0 LSB (Max)

g

1.0 LSB (Max)

a

a

0.05 V (Max)

REF(b)

REF(b)

a

a

0.05 V (Max)

V (Min)

V (Max)

0.01 3 mA (Max)

b

3 mA (Max)

g

0.125

g

0.5 LSB

2

DC Electrical Characteristics

The following specifications apply for V

limits apply for T

e

e

T

A

J

a

ea

T

to T

MIN

5V, V

; all other limits T

MAX

REF(a)

e

5V, and V

e

A

T

Symbol Parameter Conditions

a

V

IN(1)

V

IN(0)

I

IN(1)

I

IN(0)

V

OUT(1)

V

OUT(0)

I

OUT

DI

CC

AI

CC

Logical ‘‘1’’ Input Voltage V

Logical ‘‘0’’ Input Voltage V

Logical ‘‘1’’ Input Current V

Logical ‘‘0’’ Input Current V

Logical ‘‘1’’ Output Voltage V

Logical ‘‘0’’ Output Voltage V

TRI-STATEÉOutput Current V

DVCCSupply Current CSeWReRDe0 0.1 2 mA (Max)

AVCCSupply Current CSeWReRDe03045 mA (Max)

e

5.25V 2.0 V (Min)

a

e

4.75V 0.8 V (Max)

e

5V 0.005 1.0 mA (Max)

IN(1)

e

0V

IN(0)

a

e

4.75V I

V

V

a

a

OUT

OUT

OUT

e

4.75V I

OUT

e

4.75V I

OUT

e

5V 0.1 50 mA (Max)

e

0V

e

REF(b)

e

25§C.

J

GND unless otherwise specified. Boldface

Typical Limit Units

(Note 7) (Note 8) (Limits)

b

0.005

eb

360 mA 2.4 V (Min)

eb

10 mA 4.5 V (Min)

e

1.6 mA 0.4 V (Max)

b

0.1

b

1.0 mA (Max)

b

50 mA (Max)

AC Electrical Characteristics

The following specifications apply for V
specified. Boldface limits apply for T

a

ea

e

T

A

e

MIN

e

t

to T

f

MAX

20 ns, V

REF(a)

; all other limits T

r

5V, t

e

T

J

Symbol Parameter Conditions

t

CONV

t

CRD

t

ACC1

t

ACC2

t

SH

t1H,t

t

INTH

t

ID

t

P

Conversion Time from Rising Edge Mode 1
of S

/H to Falling Edge of INT

Conversion Time for MODE 2 Mode 2
(RD Mode)

Access Time (Delay from Falling Mode 1; C
Edge of RD

to Output Valid)

Access Time (Delay from Falling Mode 2; C
Edge of RD

to Output Valid)

Minimum Sample Time

TRI-STATE Control (Delay from Rising R

0H

Edge of RD to High-Z State)

Delay from Rising Edge of RD
to Rising Edge of INT

Delay from INT to Output Valid C

Delay from End of Conversion
to Next Conversion

e

L

e

L

(Figure 1)

; (Note 9) 250 ns (Max)

e

L

e

L

e

1k, C

L

100 pF 20 50 ns (Max)

SR Slew Rate for Correct

Track-and-Hold Operation

100 pF

100 pF

10 pF

e

5V, and V

A

e

e

T

J

REF(b)

25§C.

e

GND unless otherwise

Typical Limit Units

(Note 7) (Note 8) (Limits)

1.2 1.8 ms (Max)

1.8 2.4 ms (Max)

20 50 ns (Max)

a

t

50 ns (Max)

CRD

20 50 ns (Max)

10 50 ns (Max)

10 20 ns (Max)

2.5 V/ms

3

AC Electrical Characteristics (Continued)

The following specifications apply for V
specified. Boldface limits apply for T

Symbol Parameter Conditions

C

VIN

C

OUT

C

IN

Note 1: Absolute Maximum Ratings indicate limits beyond which damage to the device may occur. Operating Ratings indicate conditions for which the device is
functional, but do not guarantee specific performance limits. For guaranteed specifications and test conditions, see the Electrical Characteristics. The guaranteed
specifications apply only for the test conditions listed. Some performance characteristics may degrade when the device is not operated under the listed test
conditions.

Note 2: All voltages are measured with respect to GND, unless otherwise specified.

Note 3: When the input voltage (V

to 5 mA or less. The 20 mA package input current limits the number of pins that can safely exceed the power supplies with an input of 5 mA to four.

Note 4: The maximum power dissipation must be derated at elevated temperatures and is dictated by T
allowable power dissipation at any temperature is P
device, T

JMAX

C/W for the small outline (WM) package.

and 65

§

Note 5: Human body model, 100 pF discharged through a 1.5 kX resistor.

Note 6: See AN-450 ‘‘Surface Mounting Methods and Their Effect on Product Reliability’’ or the section titled ‘‘Surface Mount’’ found in a current National

Semiconductor Linear Data Book for other methods of soldering surface mount devices.

Note 7: Typicals are at 25

Note 8: Limits are guaranteed to National’s AOQL (Average Outgoing Quality Level).

Note 9: Accuracy may degrade if tSH is shorter than the value specified.

Analog Input Capacitance 35 pF

Logic Output Capacitance 5 pF

Logic Input Capacitance 5 pF

) at any pin exceeds the power supply rails (V

IN

e

150§C, and the typical thermal resistance (iJA) when board mounted is 47§C/W for the plastic (N) package, 85§C/W for the ceramic (J) package,

C and represent most likely parametric norm.

§

a

ea

e

T

A

e

5V, t

e

J

e

t

to T

f

MAX

20 ns, V

; all other limits T

r

T

MIN

REF(a)

e

5V, and V

e

A

e

REF(b)

e

T

25§C.

J

GND unless otherwise

Typical Limit Units

(Note 7) (Note 8)

k

IN

e

b

(T

D

TA)/iJAor the number given in the Absolute Maximum Ratings, whichever is lower. For this

JMAX

Vbor V

l

Va) the absolute value of current at that pin should be limited

IN

, iJAand the ambient temperature, TA. The maximum

JMAX

TRI-STATE Test Circuits and Waveforms

TL/H/10559– 3

TL/H/10559– 5

TL/H/10559– 4

TL/H/10559– 6

4