ADC1031/ADC1034/ADC1038 10-Bit Serial
I/O A/D Converters with Analog Multiplexer
and Track/Hold Function
General Description
The ADC1031, ADC1034 and ADC1038 are 10-bit successive approximation A/D converters with serial I/O. The serial input, for the ADC1034 and ADC1038, controls a singleended analog multiplexer that selects one of 4 input channels (ADC1034) or one of 8 input channels (ADC1038). The
ADC1034 and ADC1038 serial output data can be configured into a left- or right-justified format.
An input track/hold is implemented by a capacitive reference ladder and sampled-data comparator. This allows the
analog input to vary during the A/D conversion cycle.
Separate serial I/O and conversion clock inputs are provided to facilitate the interface to various microprocessors.
Applications
Y
Engine control
Y
Process control
Y
Instrumentation
Y
Test equipment
TRI-STATEÉis a registered trademark of National Semiconductor Corporation.
TM
MICROWIRE
is a trademark of National Semiconductor Corporation.
Features
Y
Serial I/O (MICROWIRETMcompatible)
Y
Separate asynchronous converter clock and serial data
I/O clock
Y
Analog input track/hold function
Y
Ratiometric or absolute voltage referencing
Y
No zero or full scale adjustment required
Y
0V to 5V analog input range with single 5V power
supply
Y
TTL/MOS input/output compatible
Y
No missing codes
Key Specifications
Y
Resolution10 bits
Y
Total unadjusted error
Y
Single supply5Vg5%
Y
Power dissipation20 mW (max)
Y
Max. conversion time (f
Y
Serial data exchange time (f
C
January 1995
g
1 LSB (max)
e
3 MHz)13.7 ms (max)
e
1 MHz)10 ms (max)
S
ADC1031/ADC1034/ADC1038 10-Bit Serial I/O A/D Converters
with Analog Multiplexer and Track/Hold Function
Connection Diagrams
Dual-In-Line and SO Packages
Top View
ADC1031 In NS Package N08E
Ordering Information
C
1995 National Semiconductor CorporationRRD-B30M75/Printed in U. S. A.
TL/H/10556– 4
Top View
ADC1034 In NS Packages
J16A, M16B or N16E
s
Industrialb40§CsT
a
85§CPackage
A
ADC1031CINN08E
ADC1034CINN16E
ADC1034CIWMM16B
ADC1038CINN20A
ADC1038CIWMM20B
s
Militaryb55§CsT
a
125§CPackage
A
ADC1034CMJJ16A
ADC1038CMJJ20A
TL/H/10556
TL/H/10556– 3
TL/H/10556– 2
Top View
ADC1038 In NS Packages
J20A, M20B or N20A
Absolute Maximum Ratings (Notes1&3)
If Military/Aerospace specified devices are required,
please contact the National Semiconductor Sales
Office/Distributors for availability and specifications.
Supply Voltage (V
Voltage at Inputs and Outputs
Input Current at Any Pin (Note 4)
Package Input Current (Note 4)
Package Dissipation
e
at T
A
ESD Susceptability (Note 6)2000V
Soldering Information
N Package (10 sec.)260
J Package (10 sec.)300
SO Package (Note 7):
Vapor Phase (60 sec.)215
Infrared (15 sec.)220
Storage Temperature
)6.5V
CC
b
0.3V to V
CC
a
g
g
20 mA
0.3V
5mA
25§C (Note 5)500 mW
b
65§Ctoa150§C
§
§
§
§
Operating Ratings (Notes2&3)
Temperature RangeT
ADC1031CIN,
ADC1034CIN,
ADC1034CIWM,
ADC1038CIN,
ADC1038CIWM
ADC1034CMJ, ADC1038CMJ
Supply Voltage (VCC)4.75 VDCto 5.25 V
Reference Voltage
(V
REF
a
e
b
V
REF
V
REF
C
C
C
C
b
b
)2.0 VDCto V
MIN
b
40§CsT
55§CsT
s
s
T
T
A
MAX
s
a
85§C
A
s
a
125§C
A
DC
a
0.05V
CC
Electrical Characteristics
The following specifications apply for V
specified. Boldface limits apply for T
ea
5.0V, V
CC
e
e
T
A
T
J
MIN
REF
to T
MAX
ea
4.6V, f
; all other limits T
SymbolParameterConditions
CONVERTER AND MULTIPLEXER CHARACTERISTICS
Total UnadjustedCIN, CIWM, CMJ(Note 10)
Error
Differential Linearity10Bits (min)
R
REF
V
REF
V
IN
Reference Input Resistance8kX
Reference Voltage(V
Analog Input Voltage(Note 11)(V
On Channel Leakage CurrentOn Channele5VDC,5.0200nA (max)
Off Channel
e
0V
DC
(Note 12)On Channele0VDC,5.0
Off Channele5V
DC
Off Channel Leakage CurrentOn Channele5VDC,5.0
Off Channel
e
0V
DC
(Note 12)On Channele0VDC,5.0200nA (max)
DC
e
5V
DC
s
s
V
CC
Off Channel
Power SupplyZero Error4.75 V
Sensitivity
Full Scale Error
S
5.25 V
e
700 kHz, and f
e
A
T
J
e
3 MHz unless otherwise
C
e
25§C.
TypicalLimitUnits
(Note 8)(Note 9)(Limits)
g
11kX (max)
a
CC
a
CC
b
(GND
500nA (max)
b
b
500nA (max)
b
b
500nA (max)
500nA (max)
g
DC
1/4LSB (max)
g
1/4LSB (max)
1LSB (max)
5kX (min)
0.05)V (max)
0.05)V (max)
0.05)V (min)
200nA (max)
200nA (max)
2
Electrical Characteristics (Continued)
The following specifications apply for V
specified. Boldface limits apply for T
ea
5.0V, V
CC
e
e
T
A
T
J
MIN
REF
to T
MAX
ea
4.6V, f
; all other limits T
S
SymbolParameterConditions
DIGITAL AND DC CHARACTERISTICS
V
IN(1)
V
IN(0)
I
IN(1)
I
IN(0)
V
OUT(1)
V
OUT(0)
I
OUT
I
SOURCE
I
SINK
I
CC
Logical ‘‘1’’ Input VoltageV
Logical ‘‘0’’ Input VoltageV
Logical ‘‘1’’ Input CurrentV
Logical ‘‘0’’ Input CurrentV
Logical ‘‘1’’ Output VoltageV
Logical ‘‘0’’ Output VoltageV
TRI-STATE Output CurrentV
Output Source CurrentV
Output Sink CurrentV
Supply CurrentCSeHIGH, V
e
5.25 V
I
OUT
V
CC
CC
IN
IN
CC
I
OUT
I
OUT
CC
OUT
OUT
OUT
OUT
e
e
DC
e
4.75 V
DC
5.0 V
DC
0V
DC
e
4.75 V
DC
eb
360 mA2.4V (min)
eb
10 mA4.5V (min)
e
4.75 V
DC
e
1.6 mA
e
0V
e
5V0.013mA (max)
e
0V
e
V
CC
Open1.53mA (max)
REF
AC CHARACTERISTICS
f
f
T
t
t
t
t1H,t0HDelay from OE or CS RisingR
t
t
Conversion Clock (C
C
Frequency4.03.0MHz (max)
Serial Data Clock (S
S
Frequency (Note 13)f
Conversion TimeNot Including MUX Addressing and41 (1/fC)
C
Analog Sampling TimeAfter Address is Latched,CSeLow4.5 (1/fS)
CA
Access Time Delay from CS or OEOEe‘‘0’’
ACC
Falling Edge to DO Data Valid
Set-up Time of CS Falling
SET-UP
Edge to S
Rising Edge
CLK
Edge to DO TRI-STATE
DI Hold Time from S
HDI
DI Set-up Time to S
SDI
)0.7MHz (min)
CLK
)f
CLK
e
3 MHz, R/Le‘‘0’’183kHz (min)
C
e
3 MHz, R/Le‘‘1’’622kHz (min)
C
e
f
3 MHz, R/Le‘‘0’’ or R/Le‘‘1’’21.0MHz (max)
C
Analog Input Sampling Times
e
L
Rising Edge050ns (min)
CLK
Rising Edge50100ns (min)
CLK
3kX,C
e
100 pF
L
e
700 kHz, and f
e
A
e
3 MHz unless otherwise
C
e
T
25§C.
J
TypicalLimitUnits
(Note 8) (Note 9)(Limits)
2.0V (min)
0.8V (max)
0.0052.5mA (max)
b
0.005b2.5mA (max)
0.4V (max)
b
0.01
b
14
b
b
168.0mA (min)
a
200 ns
a
200 ns
100200ns (max)
75150ns (min)
100120ns (max)
3mA (max)
6.5mA (min)
(max)
(max)
3
Electrical Characteristics (Continued)
The following specifications apply for V
specified. Boldface limits apply for T
SymbolParameterConditions
ea
5.0V, V
CC
e
e
T
A
T
J
MIN
REF
to T
MAX
ea
4.6V, f
; all other limits T
S
e
700 kHz, and f
e
A
e
3 MHz unless otherwise
C
e
T
25§C.
J
TypicalLimitUnits
(Note 8)(Note 9)(Limits)
AC CHARACTERISTICS (Continued)
t
HDO
t
DDO
t
RDO
t
FDO
C
DO Hold Time from S
Delay from S
Edge to DO Data Valid
CLK
Falling EdgeR
CLK
FallingR
DO Rise TimeR
DO Fall TimeR
IN
Input CapacitanceAnalog Inputs (CH0 – CH7)50pF
e
30 kX,C
L
e
30 kX,C
L
e
30 kX,TRI-STATE to High3575ns (max)
L
e
C
100 pF
L
e
30 kX,TRI-STATE to Low3575ns (max)
L
e
C
100 pF
L
e
100 pF7010ns (min)
L
e
100 pF
L
150250ns (max)
Low to High75150ns (max)
High to Low75150ns (max)
All Other Inputs7.5pF
Note 1: Absolute Maximum Ratings indicate limits beyond which damage to the device may occur.
Note 2: Operating Ratings indicate conditions for which the device is functional, but do not guarantee specific performance limits. For guaranteed specifications
and test conditions, see the Electrical Characteristics. The guaranteed specifications apply only for the test conditions listed. Some performance characteristics
may degrade when the device is not operated under the listed test conditions.
Note 3: All voltages are measured with respect to AGND and DGND, unless otherwise specified.
Note 4: When the input voltage (V
20 mA maximum package input current rating limits the number of pins that can safely exceed the power supplies with an input current of 5 mA to four pins.
Note 5: The maximum power dissipation must be derated at elevated temperatures and is dictated by T
allowable power dissipation at any temperature is P
device, T
suffixes 52
46
Note 6: Human body model, 100 pF capacitor discharged through a 1.5 kX resistor.
Note 7: See AN450 ‘‘Surface Mounting Methods and Their Effect on Product Reliability’’ or
soldering surface mount devices.
Note 8: Typicals are at T
Note 9: Limits are guaranteed to National’s AOQL (Average Outgoing Quality Level).
Note 10: Total unadjusted error includes offset, full-scale, linearity, multiplexer, and hold step errors.
Note 11: Two on-chip diodes are tied to each analog input. They will forward-conduct for analog input voltages one diode drop below ground or one diode drop
greater than V
elevated temperatures, which will cause errors for analog inputs near full-scale. The spec allows 50 mV forward bias of either diode; this means that as long as the
analog V
reading of a selected channel. To achieve an absolute 0 V
temperature variations, initial tolerance and loading.
Note 12: Channel leakage current is measured after the channel selection.
Note 13: In order to synchronize the serial data exchange properly, SARS needs to go low after completion of the serial I/O data exchange. If this does not occur
the output shift register will be reset and the correct output data lost. The minimum limit for S
justified, and can be determined by the following equations:
e
125§C. The typical thermal resistance (iJA) of these parts when board mounted follow: ADC1031 with CIN suffixes 71§C/W, ADC1034 with CMJ
Jmax
C/W, ADC1034 with CIN suffixes 54§C/W, ADC1034 with CIWM suffixes 70§C/W, ADC1038 with CMJ suffixes 53§C/W, ADC1038 with CIN suffixes
§
C/W, ADC1038 with CIWM suffixes 64§C/W.
§
supply. Be careful during testing at low VCClevels (4.5V), as high level analog inputs (5V) can cause an input diode to conduct, especially at
CC
does not exceed the supply voltage by more than 50 mV, the output code will be correct. Exceeding this range on an unselected channel will corrupt the
IN
) at any pin exceeds the power supplies (V
IN
e
b
(T
D
Jmax
e
25§C and represent most likely parametric norm.
J
to5VDCinput voltage range will therefore require a minimum supply voltage of 4.950 VDCover
DC
l
(8.5/41) (fC) with right-justification (R/Le‘‘1’’) and f
f
S
TA)/iJAor the number given in the Absolute Maximum Ratings, whichever is lower. For this
k
IN
DGND, or V
l
S
l
VCC) the current at that pin should be limited to 5 mA. The
IN
, iJAand the ambient temperature, TA. The maximum
Jmax
Linear Databook
will depend on C
CLK
(2.5/41) (fC) with left-justification (R/Le‘‘0’’).
section ‘‘Surface Mount’’ for other methods of
frequency and whether right-justified or left-
CLK
4
Typical Performance Characteristics
Power Supply Current
(ICC)vsC
CLK
Linearity Error vs
Frequency
C
CLK
Power Supply Current (ICC)
vs Ambient Temperature
Linearity Error vs
Ambient Temperature
Zero Error vs
Reference Voltage
Reference Current (I
vs Ambient Temperature
REF
Linearity Error vs
Reference Voltage
)
TL/H/10556– 5
5
Test Circuits
t1H,t
0H
Timing Diagrams
DO High to Low State
DI Data Input Timing
TL/H/10556– 6
TL/H/10556– 9
DO except ‘‘TRI-STATE’’
TL/H/10556– 7
DO Low to High State
TL/H/10556– 10
DO Data Output Timing
Leakage Current
TL/H/10556– 8
DO ‘‘TRI-STATE’’ Rise
and Fall Times
TL/H/10556– 11
TL/H/10556– 12
TL/H/10556– 13
6
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