Rainbow Electronics ADC10064 User Manual

December 1994

ADC10061/ADC10062/ADC10064 10-Bit 600 ns A/D Converter with Input Multiplexer and Sample/Hold

ADC10061/ADC10062/ADC10064 10-Bit 600 ns A/D Converter

with Input Multiplexer and Sample/Hold

General Description

Using an innovative, patented multistep* conversion technique, the 10-bit ADC10061, ADC10062, and ADC10064 CMOS analog-to-digital converters offer sub-microsecond conversion times yet dissipate a maximum of only 235 mW. The ADC10061, ADC10062, and ADC10064 perform a 10-bit conversion in two lower-resolution ‘‘flashes’’, thus yielding a fast A/D without the cost, power dissipation, and other problems associated with true flash approaches. The ADC10061 is pin-compatible with the ADC1061 but much faster, thus providing a convenient upgrade path for the ADC1061.

The analog input voltage to the ADC10061, ADC10062, and ADC10064 is sampled and held by an internal sampling circuit. Input signals at frequencies from dc to over 200 kHz can therefore be digitized accurately without the need for an external sample-and-hold circuit.

The ADC10062 and ADC10064 include a ‘‘speed-up’’ pin. Connecting an external resistor between this pin and ground reduces the typical conversion time to as little as 350 ns with only a small increase in linearity error.

For ease of interface to microprocessors, the ADC10061, ADC10062, and ADC10064 have been designed to appear as a memory location or I/O port without the need for external interface logic.

Ordering Information

ADC10061

s

Industrial (b40§CsT

ADC10061BIN, ADC10061CIN N20A Molded DIP ADC10061BIWM, ADC10061CIWM M20B Small Outline

a

85§C) Package

A

Features

Y

Built-in sample-and-hold

Y

Singlea5V supply

Y

1, 2, or 4-input multiplexer options

Y

No external clock required

Y

Speed adjust pin for faster conversions (ADC10062 and ADC10064). See ADC10662/4 for high speed guaranteed performance.

Key Specifications

Y

Conversion time to 10 bits 600 ns typical,

900 ns max over temperature

Y

Sampling Rate 800 kHz

Y

Low power dissipation 235 mW (max)

Y

Total unadjusted error

Y

No missing codes over temperature

g

1.0 LSB (max)

Applications

Y

Digital signal processor front ends

Y

Instrumentation

Y

Disk drives

Y

Mobile telecommunications

ADC10064

s

Industrial (b40§CsT

ADC10064BIN, ADC10064CIN N28B Molded DIP ADC10064BIWM, ADC10064CIWM M28B Small Outline

a

85§C) Package

A

s

Military (b55§CsT

a

125§C) Package

A

ADC10061CMJ/883 J20A Cerdip

Military (b55§CsT

ADC10064CMJ/883 J28A Cerdip

s

a

125§C) Package

A

ADC10062

s

Industrial (b40§CsT

a

85§C) Package

A

ADC10062BIN, ADC10062CIN N24A Molded DIP ADC10062BIWM, ADC10062CIWM M24B Small Outline

s

Military (b55§CsT

a

125§C) Package

A

ADC10062CMJ/883 J24A Cerdip

*U.S. Patent Number 4918449

TRI-STATEÉis a registered trademark of National Semiconductor Corporation.

C

1995 National Semiconductor Corporation RRD-B30M75/Printed in U. S. A.

TL/H/11020

Absolute Maximum Ratings (Notes 1, 2)

If Military/Aerospace specified devices are required, please contact the National Semiconductor Sales Office/Distributors for availability and specifications.

Supply Voltage (V

Voltage at Any Input or Output

Input Current at Any Pin (Note 3) 5 mA

Package Input Current (Note 3) 20 mA

Power Dissipation (Note 4) 875 mW

ESD Susceptability (Note 5) 2000V

Soldering Information (Note 6)

N Package (10 Sec) 260 J Package (10 Sec) 300 SO Package:

Vapor Phase (60 Sec) 215 Infrared (15 Sec) 220

Storage Temperature Range

Junction Temperature 150§C

a

e

AV

CC

e

DVCC)

b

0.3V toa6V

b

0.3V to V

b

65§Ctoa150§C

a

0.3V

Operating Ratings (Notes 1, 2)

s

T

Temperature Range T

ADC10061BIN, ADC10061BIWM,

MIN

ADC10061CIN, ADC10061CIWM, ADC10062BIN, ADC10062BIWM, ADC10062CIN, ADC10062CIWM, ADC10064BIN, ADC10064BIWM, ADC10064CIN, ADC10064CIWM ADC10061CMJ/883, ADC10062CMJ/883, ADC10064CMJ/883

b

40§CsT

b

55§CsT

Supply Voltage Range 4.5V to 5.5V

C

§

C

§

C

§

C

§

T

A

MAX

s

a

85§C

A

s

a

125§C

A

Converter Characteristics

The following specifications apply for V unless otherwise specified. Boldface limits apply for T

a

ea

5V, V

REF(a)

A

e

ea

T

J

e

5V, V

T

Min

Symbol Parameter Conditions

Resolution 10 Bits

Integral Linearity Error BIN, BIWM Suffixes

CIN, CIWM, CMJ Suffixes

e

R

18 kX

SA

Offset Error

Full-Scale Error

Total Unadjusted Error BIN, BIWM Suffixes

CIN, CIWM, CMJ Suffixes All Suffixes, R

e

SA

Missing Codes 0 (max)

a

Power Supply Sensitivity V

THD Total Harmonic Distortion f

SNR Signal-to-Noise Ratio f

Effective Number of Bits f

R

REF

R

REF

V

REF(a)VREF(a)

V

REF(b)VREF(b)

V

REF(a)VREF(a)

V

REF(b)VREF(b)

V

IN

V

IN

Reference Resistance 650 400 X (min)

Reference Resistance 650 900 X (max)

Input Voltage V

Input Voltage GNDb0.05 V (min)

Input Voltage V

Input Voltage GNDb0.05 V (min)

OFF Channel Input Leakage Current CSeVa,V ON Channel Input Leakage Current CS

e

5Vg5%, V

a

e

V

5Vg10%, V

e

10 kHz, 4.85 V

IN

e

f

160 kHz, 4.85 V

IN

e

10 kHz, 4.85 V

IN

e

f

160 kHz, 4.85 V

IN

e

10 kHz, 4.85 V

IN

e

f

160 kHz, 4.85 V

IN

e

Va,V

REF

e

V

IN

e

V

IN

REF(b)

to T

18 kX

REF

P-P

a

e

; all other limits T

Max

e

4.5V

e

4.5V

GND, and Speed Adjust pin unconnected

e

ea

T

A

25§C.

J

Typical Limit Units

(Note 7) (Notes 8, 10) (Limit)

g

0.6/g1.1 LSB (max)

g

0.5 LSB

g

0.5 LSB

g

(/16 LSB

1.0/g1.5 LSB (max)

g

1 LSB (max)

g

1 LSB (max)

g

1.0/g1.5 LSB (max)

g

1.5/g2.0 LSB (max)

g

*/8 LSB (max)

0.06 %

0.08 %

61 dB 60 dB

9.6 Bits

9.4 Bits

a

0.05 V (max)

REF(b)

REF(a)

a

0.05 V (max)

V (min)

V (max)

0.01 3 mA (max)

g

1

b

3 mA (max)

2

DC Electrical Characteristics

The following specifications apply for V otherwise specified. Boldface limits apply for T

a

ea

5V, V

A

REF(a)

e

T

e

5V V

e

T

MIN

to T

J

Symbol Parameter Conditions

a

V

IN(1)

V

IN(0)

I

IN(1)

I

IN(0)

V

OUT(1)

V

OUT(0)

I

OUT

DI

CC

AI

CC

Logical ‘‘1’’ Input Voltage V

Logical ‘‘0’’ Input Voltage V

Logical ‘‘1’’ Input Current V

Logical ‘‘0’’ Input Current V

Logical ‘‘1’’ Output Voltage V

Logical ‘‘0’’ Output Voltage V

TRI-STATEÉOutput Current V

DVCCSupply Current CSeS/HeRDe0, R

AVCCSupply Current CSeS/HeRDe0, R

e

5.5V 2.0 V (min)

a

e

4.5V 0.8 V (max)

e

5V 0.005 3.0 mA (max)

IN(1)

0V

IN(0)

a

V

a

OUT

e e

e

4.5V, I

e e

eb

OUT

eb

OUT

e

1.6 mA 0.4 V (max)

OUT

5V 0.1 50 mA (max) 0V

CSeS/HeRDe0, R

e

S/HeRDe0, R

CS

e

REF(b)

GND, and Speed Adjust pin unconnected unless

; all other limits T

MAX

e

ea

T

A

25§C.

J

Typical Limit Units

(Note 7) (Notes 8, 10) (Limits)

b

0.005

b

3.0 mA (max)

360 mA 2.4 V (min) 10 mA 4.25 V (min)

b

0.1

e %

SA

e

18 kX 1.0 mA (max)

SA

e %

SA

e

18 kX 30 mA (max)

SA

1.0 2 mA (max)

30 45 mA (max)

b

50 mA (max)

AC Electrical Characteristics

The following specifications apply for V unconnected unless otherwise specified. Boldface limits apply for T

a

25§C.

a

ea

5V, t

e

t

f

20 ns, V

r

Symbol Parameter Conditions

t

CONV

t

CRD

Mode 1 Conversion Time BIN, BIWM, CIN, from Rising Edge of S to Falling Edge of INT

/H CIWM Suffixes 600 750/900 ns (max)

CMJ Suffixes 600 1000 ns (max)

e

R

18k 375 ns

SA

Mode 2 Conversion Time BIN, BIWM, CIN,

CIWM Suffixes 850 1400 ns (max) CMJ Suffixes 850 1500 ns (max)

e

SA

e

L

e

L

; (Note 9) 250 ns (max)

e

1k, C

L

t

ACC1

t

ACC2

t

SH

t1H,t

Mode 2, R

Access Time (Delay from Falling Mode 1; C Edge of RD

to Output Valid)

Access Time (Delay from Falling Mode 2; C Edge of RD to Output Valid)

Minimum Sample Time

0H

TRI-STATE Control (Delay R from Rising Edge of RD

(Figure 1)

e

L

to High-Z State)

t

INTH

t

P

Delay from Rising Edge of RD C to Rising Edge of INT

Delay from End of Conversion to Next Conversion

e

100 pF

L

REF(a)

e

A

e

5V, V

e

T

J

MIN

REF(b)

to T

e

GND, and Speed Adjust pin

; all other limits T

MAX

A

Typical Limit Units

(Note 7) (Notes 8, 10) (Limits)

18k 530 ns

100 pF

30 60 ns (max)

900 t

a

50 ns (max)

CRD

10 pF

30 60 ns (max)

25 50 ns (max)

50 ns (max)

e

T

J

3

AC Electrical Characteristics (Continued)

The following specifications apply for V unconnected unless otherwise specified. Boldface limits apply for T

a

25§C.

Symbol Parameter Conditions

t

MS

t

MH

C

VIN

C

OUT

C

IN

Note 1: Absolute Maximum Ratings indicate limits beyond which damage to the device may occur. Operating Ratings indicate conditions for which the device is functional. These ratings do not guarantee specific performance limits, however. For guaranteed specifications and test conditions, see the Electrical Characteristics. The guaranteed specifications apply only for the test conditions listed. Some performance characteristics may degrade when the device is not operated under the listed test conditons.

Note 2: All voltages are measured with respect to GND, unless otherwise specified.

Note 3: When the input voltage (V

to 5 mA or less. The 20 mA package input current limits the number of pins that can safely exceed the power supplies with an input current of 5 mA to four.

Note 4: The maximum power dissipation must be derated at elevated temperatures and is dictated by T allowable power dissipation at any temperature is P cases, the maximum derated power dissipation will be reached only during fault conditions. For these devices, T from the tables below:

Suffix iJA(§C/W)

CMJ 54

BIN, CIN 70

BIWM, CIWM 85

Note 5: Human body model, 100 pF discharged through a 1.5 kX resistor.

Note 6: See AN-450 ‘‘Surface Mounting Methods and Their Effect on Product Reliability’’ or the section titled ‘‘Surface Mount’’ found in a current National

Semiconductor Linear Data Book for other methods of soldering surface mount devices.

Note 7: Typicals are at

Note 8: Limits are guaranteed to National’s AOQL (Average Outgoing Quality Level).

Note 9: Accuracy may degrade if t

Note 10: A military RETS electrical test specification is available on request. At time of printing, the ADC10061CMJ/883, ADC10062CMJ/883, and

ADC10064CMJ/883 RETS specification complies fully with the boldface limits in this column.

Multiplexer Control Setup Time 10 75 ns (max)

Multiplexer Hold Time 10 40 ns (max)

Analog Input Capacitance 35 pF (max)

Logic Output Capacitance 5 pF (max)

Logic Input Capacitance 5 pF (max)

) at any pin exceeds the power supply rails (V

IN

ADC10061

a

25§C and represent must likely parametric norm.

is shorter than the value specified. See curves of Accuracy vs tSH.

SH

a

ea

e

D

e

5V, t

r

b

(T

TA)/iJAor the number given in the Absolute Maximum Ratings, whichever is lower. In most

JMAX

Suffix iJA(§C/W)

CMJ 48

BIN, CIN 60

BIWM, CIWM 82

e

t

20 ns, V

f

k

IN

ADC10062

REF(a)

A

GND or V

e

5V, V

e

T

J

MIN

REF(b)

to T

e

GND, and Speed Adjust pin

; all other limits T

MAX

Typical Limit Units

(Note 7) (Note 8) (Limits)

l

Va) the absolute value of current at that pin should be limited

IN

, iJAand the ambient temperature, TA. The maximum

JMAX

for a board-mounted device can be found

JMAX

ADC10064

Suffix iJA(§C/W)

CMJ 44

BIN, CIN 53

BIWM, CIWM 78

e

T

A

J

e

4

Typical Performance Characteristics

Zero (Offset) Error vs Reference Voltage

Digital Supply Current vs Temperature

Conversion Time vs Speed-Up Resistor (ADC10062 and ADC10064 Only)

Linearity Error vs Reference Voltage

Conversion Time vs Temperature

Conversion Time vs Speed-Up Resistor (ADC10062 and ADC10064 Only)

Analog Supply Current vs Temperature

Conversion Time vs Temperature

Spectral Response with 100 kHz Sine Wave Input

5

TL/H/11020– 2

Typical Performance Characteristics (Continued)

Signal-to-Noise vs Signal Frequency

Linearity Change vs Speed-Up Resistor (ADC10062 and ADC10064 Only)

a

THD Ratio

Linearity Change vs Speed-Up Resistor (ADC10062 and ADC10064 Only)

Linearity Error Change vs Sample Time

TL/H/11020– 4

6