Rainbow Electronics ADC10040 User Manual
ADC10040
10-Bit, 40 MSPS, 3V, 55.5 mW A/D Converter
ADC10040 10-Bit 40 MSPS 3V, 55 mW A/D Converter
November 2004
General Description
The ADC10040 is a monolithic CMOS analog-to-digital converter capable of converting analog input signals into 10-bit
digital words at 40 Megasamples per second (MSPS). This
converter uses a differential, pipeline architecture with digital
error correction and an on-chip sample-and-hold circuit to
provide a complete conversion solution, and to minimize
power consumption, while providing excellent dynamic performance. A unique sample-and-hold stage yields a fullpower bandwidth of 400 MHz. Operating on a single 3.0V
power supply, this device consumes just 55.5 mW at
40 MSPS, including the reference current. The Standby
feature reduces power consumption to just 13.5 mW.
The differential inputs provide a full scale selectable input
swing of 2.0 V
single-ended input. Full use of the differential input is recommended for optimum performance. An internal +1.2V precision bandgap reference is used to set the ADC full-scale
range, and also allows the user to supply a buffered referenced voltage for those applications requiring increased accuracy. The output data format is 10-bit offset binary, or two’s
complement.
This device is available in the 28-lead TSSOP package and
will operate over the industrial temperature range of −40˚C to
+85˚C.
P-P
, 1.5 V
P-P
, 1.0 V
, with the possibility of a
P-P
Features
n Single +3.0V operation
n Selectable 2.0 V
swing
n 400 MHz −3 dB input bandwidth
n Low power consumption
n Standby mode
n On-chip reference and sample-and-hold amplifier
n Offset binary or two’s complement data format
n Separate adjustable output driver supply to
accommodate 2.5V and 3.3V logic families
n 28-pin TSSOP package
P-P
, 1.5 V
, or 1.0 V
P-P
full-scale input
P-P
Key Specifications
n Resolution 10 Bits
n Conversion Rate 40 MSPS
n Full Power Bandwidth 400 MHz
n DNL
n SNR (f
n SFDR (f
n Data Latency 6 Clock Cycles
n Supply Voltage +3.0V
n Power Consumption, 40 MHz 55.5 mW
= 11 MHz) 59.6 dB (typ)
IN
= 11 MHz) −80 dB (typ)
IN
±
0.3 LSB (typ)
Applications
n Ultrasound and Imaging
n Instrumentation
n Cellular Based Stations/Communications Receivers
n Sonar/Radar
n xDSL
n Wireless Local Loops
n Data Acquisition Systems
n DSP Front Ends
Connection Diagram
20077801
© 2004 National Semiconductor Corporation DS200778 www.national.com
Ordering Information
ADC10040
Block Diagram
Industrial (−40˚C ≤ TA≤ +85˚C) NS Package
ADC10040CIMT 28 Pin TSSOP
ADC10040CIMTX 28 Pin TSSOP Tape & Reel
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20077802
Pin Descriptions and Equivalent Circuits
Pin No. Symbol Equivalent Circuit Description
ANALOG I/O
Inverting analog input signal. With a 1.2V reference the
12 V
−
IN
full-scale input signal level is 1.0 V
(pin 4) for single-ended operation.
V
COM
. This pin may be tied to
P-P
ADC10040
13 V
6V
7V
4V
8V
IN
REF
REFT
COM
REFB
+
Non-inverting analog input signal. With a 1.2V reference the
full-scale input signal level is 1.0 V
Reference input. This pin should be bypassed to V
0.1 µF monolithic capacitor. V
.
P-P
is 1.20V nominal. This pin
REF
SSA
with a
may be driven by a 1.20V external reference if desired. Do
not load this pin.
V
REFT
and V
are high impedance reference bypass pins
REFB
only. Connect a 0.1 µF capacitor from each of these pins to
. These pins should not be loaded. V
V
SSA
bypassed with a 0.1 µF capacitor to V
to set the input common voltage V
CM
SSA.VCOM
.
should also be
COM
may be used
DIGITAL I/O
1 CLK
15 DF
28 STBY
5
IRS (Input Range
Select)
Digital clock input. The range of frequencies for this input is
20 MHz to 40 MHz. The input is sampled on the rising edge
of this input.
DF = “1” Two’s Complement
DF = “0” Offset Binary
This is the standby pin. When high, this pin sets the converter
into standby mode. When this pin is low, the converter is in
active mode.
IRS=“V
IRS=“V
DDA
SSA
” 2.0 V
” 1.5 V
IRS = “Floating” 1.0 V
If using both V
IN
input range
P-P
input range
P-P
input range
P-P
+ and VIN- pins, (or differential mode), then
the peak-to-peak voltage refers to the differential voltage
+-VIN-).
(V
IN
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Pin Descriptions and Equivalent Circuits (Continued)
Pin No. Symbol Equivalent Circuit Description
ADC10040
16–20,
23–27
ANALOG POWER
2, 9, 10 V
3, 11, 14 V
DIGITAL POWER
22 V
21 V
D0–D9
DDA
SSA
DDIO
SSIO
Digital output data. D0 is the LSB and D9 is the MSB of the
binary output word.
Positive analog supply pins. These pins should be connected
to a quiet 3,0V source and bypassed to analog ground with a
0.1 µF monolithic capacitor located within 1 cm of these pins.
A 4.7 µF capacitor should also be used in parallel.
Ground return for the analog supply.
Positive digital supply pins for the ADC10040’s output drivers.
This pin should be bypassed to digital ground with a 0.1 µF
monolithic capacitor located within 1 cm of this pin. A 4.7 µF
capacitor should also be used in parallel. The voltage on this
pin should never exceed the voltage on V
by more than
DDA
300 mV.
The ground return for the digital supply for the output drivers.
This pin should be connected to the digital ground, but not
near the analog ground.
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ADC10040
Absolute Maximum Ratings (Notes 1,
2)
If Military/Aerospace specified devices are required,
please contact the National Semiconductor Sales Office/
Distributors for availability and specifications.
V
DDIO
DDA
+0.3V
±
25 mA
±
50 mA
3.9V
or
V
DDA,VDDIO
Voltage on Any Pin to GND −0.3V to V
Input Current on Any Pin
Package Input Current (Note 3)
Package Dissipation at T = 25˚C See (Note 4)
Operating Ratings
Operating Temperature Range −40˚C ≤ TA≤ +85˚C
V
(Supply Voltage) +2.7V to +3.6V
DDA
V
(Output Driver Supply
DDIO
Voltage) +2.5V to V
V
REF
|V
SSA–VSSIO
NOTE: Absolute maximum ratings are limiting values, to be applied individually, and beyond which the serviceability of the circuit may be impaired.
Functional operability under any of these conditions is not necessarily implied. Exposure to maximum ratings for extended periods may affect device
reliability.
| ≤ 100 mV
1.20V
ESD Susceptibility
Human Body Model (Note 5) 2500V
Machine Model (Note 5) 250V
Soldering Temperature
Infrared, 10 sec. (Note 6) 235˚C
Storage Temperature −65˚C to +150˚C
Converter Electrical Characteristics
Unless otherwise specified, the following specifications apply for V
=2V
V
IN
apply for T
, STBY = 0V, V
P-P
A=TMIN
to T
= 1.20V, (External Supply) f
REF
: all other limits TA= 25˚C.
MAX
SSA=VSSIO
= 40 MHz, 50% Duty Cycle, CL= 10 pF/pin. Boldface limits
CLK
Symbol Parameter Conditions Min Typ Max Units
STATIC CONVERTER CHARACTERISTICS
No Missing Codes Guaranteed 10 Bits
F
= 250 kHz, −0 dB Full
INL Integral Non-Linearity (Note 11)
DNL Differential Non-Linearity
GE Gain Error
OE Offset Error (V
+=VIN−) −1.4 0.12 +1.6 %FS
IN
IN
Scale
F
= 250 kHz, −0 dB Full
IN
Scale
Positive Error −1.5 +0.4 +1.9 %FS
Negative Error −1.5 −0.01 +1.9 %FS
Under Range Output Code 0
Over Range Output Code 1023
FPBW Full Power Bandwidth 400 MHz
REFERENCE AND INPUT CHARACTERISTICS
V
CM
Common Mode Input Voltage 0.5 1.5 V
Output Voltage for use as an
V
COM
input common mode voltage
(Note 16)
V
REF
V
REFTC
Reference Voltage 1.2 V
Reference Voltage Temperature
Coefficient
POWER SUPPLY CHARACTERISTICS
I
VDDA
I
VDDIO
Analog Supply Current
Digital Supply Current
PWR Power Consumption
STBY = 1 4.5 6.0 mA
STBY = 0 18 25 mA
STBY=1,f
STBY=0,f
=0Hz 0 mA
IN
=0Hz 0.6 0.8 mA
IN
STBY = 1 13.5 18 mW
STBY = 0 55.5 77 mW
= 0V, V
−1.0
−0.9
DDA
= +3.0V, V
±
0.3 +1.0 LSB
±
0.3 +0.9 LSB
DDIO
= +2.5V,
1.45
±
80 ppm/˚C
V
DDA
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DC and Logic Electrical Characteristics Unless otherwise specified, the following specifications
apply for V
= 40 MHz, 50% Duty Cycle, CL= 10 pF/pin. Boldface limits apply for TA=T
f
CLK
ADC10040
SSA=VSSIO
= 0V, V
Symbol Parameter Conditions Min Typ Max Units
CLK, DF, STBY, SENSE
Logical “1” Input Voltage 2 V
Logical “0” Input Voltage 0.8 V
Logical “1” Input Current +10 µA
Logical “0” Input Current −10 µA
D0–D9 OUTPUT CHARACTERISTICS
Logical “1” Output Voltage I
Logical “0” Output Voltage I
DYNAMIC CONVERTER CHARACTERISTICS
ENOB Effective Number of Bits
SNR Signal-to-Noise Ratio
SINAD Signal-to-Noise Ratio + Distortion
2nd HD 2nd Harmonic
3rd HD 3rd Harmonic
THD
SFDR
Total Harmonic Distortion (First 6
Harmonics)
Spurious Free Dynamic Range
(Excluding 2nd and 3rd Harmonic)
DDA
= +3.0V, V
= +2.5V, VIN=2V
DDIO
, STBY = 0V, V
P-P
MIN
= −0.5 mA V
OUT
= 1.6 mA 0.4 V
OUT
f
= 11 MHz 9.4, 9.3 9.6 Bits
IN
f
= 19 MHz 9.4, 9.3 9.6 Bits
IN
f
= 11 MHz 58.7, 58.1 59.6 dB
IN
f
= 19 MHz 58.6, 58 59.5 dB
IN
f
= 11 MHz 58.6, 58 59.5 dB
IN
f
= 19 MHz 58.5, 57.8 59.4 dB
IN
f
= 11 MHz −75.9,
IN
fIN= 19 MHz −74.4,
= 11 MHz −69.5,
f
IN
fIN= 19 MHz −68.8,
= 11 MHz −69.5,
f
IN
= 19 MHz −68.8,
f
.IN
fIN= 11 MHz −75.8,
= 19 MHz −75.7,
f
IN
= 1.20V, (Externally Supplied)
REF
to T
DDIO
: all other limits TA= 25˚C
MAX
−0.2 V
−74.7
−73
−67.5
−66.7
−67.5
−66.7
−74.5
−74.3
−89 dBc
−86 dBc
−78 dBc
−77 dBc
−78 dB
−77 dB
−80 dBc
−80 dBc
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