ADC08L060
8-Bit, 10 MSPS to 60 MSPS, 0.65 mW/MSPS A/D
Converter with Internal Sample-and-Hold
July 2004
ADC08L060 8-Bit, 10 MSPS to 60 MSPS, 0.65 mW/MSPS A/D Converter with Internal
Sample-and-Hold
General Description
The ADC08L060 is a low-power, 8-bit, monolithic analog-todigital converter with an on-chip track-and-hold circuit. Optimized for low cost, low power, small size and ease of use,
this product operates at conversion rates of 10 MSPS to
60 MSPS while consuming just 0.65 mW per MHz of clock
frequency, or 39 mW at 60 MSPS. Raising the PD pin puts
the ADC08L060 into a Power Down mode where it consumes about 1 mW.
The unique architecture achieves 7.6 Effective Bits. The
ADC08L060 is resistant to latch-up and the outputs are
short-circuit proof. The top and bottom of the ADC08L060s
reference ladder are available for connections, enabling a
wide range of input possibilities. The digital outputs are
TTL/CMOS compatible with a separate output power supply
pin to support interfacing with 1.8V to 3V logic. The digital
inputs (CLK and PD) are TTL/CMOS compatible.
The ADC08L060 is offered in a 24-lead plastic package
(TSSOP) and is specified over the industrial temperature
range of −40˚C to +85˚C. An evaluation board is available to
assist in the evaluation of the ADC08L060.
Features
n Single-ended input
n Internal sample-and-hold function
n Low voltage (single +3V) operation
n Small package
n Power-down feature
Key Specifications
n Resolution 8 bits
n Conversion rate 60 MSPS
n DNL
n INL +0.5/−0.2 LSB (typ)
n SNR (10.1 MHz) 48 dB (typ)
n ENOB (10.1 MHz) 7.6 bits (typ)
n THD (10.1 MHz) −57 dB (typ)
n Latency 5 Clock Cycles
n No missing codes Guaranteed
n Power Consumption
— Operating 0.65 mW/MSPS (typ)
— Power Down Mode 1.0 mW (typ)
±
0.25 LSB (typ)
Applications
n Digital Imaging
n Set-top boxes
n Portable Instrumentation
n Communication Systems
n X-ray imaging
n Viterbi decoders
Pin Configuration
20041701
© 2004 National Semiconductor Corporation DS200417 www.national.com
Ordering Information
ADC08L060
Block Diagram
Order Number (−40˚C ≤ TA≤ +85˚C) Package
ADC08L060CIMT TSSOP
ADC08L060CIMTX TSSOP (tape and reel)
ADC08L060EVAL Evaluation Board
20041702
www.national.com 2
Pin Descriptions and Equivalent Circuits
Pin No. Symbol Equivalent Circuit Description
ADC08L060
6V
3V
9V
10 V
IN
RT
RM
RB
23 PD
24 CLK
Analog signal input. Conversion range is VRBto VRT.
Analog Input that is the high (top) side of the reference
ladder of the ADC. Nominal range is 0.5V to V
and VRBinputs define the VINconversion range.
on V
RT
. Voltage
A
Bypass well. See Section 2.0 for more information.
Mid-point of the reference ladder. This pin should be
bypassed to a quiet point in the analog ground plane with
a 0.1 µF capacitor.
Analog Input that is the low side (bottom) of the
reference ladder of the ADC. Nominal range is 0.0V to
– 0.5V). Voltage on VRTand VRBinputs define the
(V
RT
conversion range. Bypass well. See Section 2.0 for
V
IN
more information.
Power Down input. When this pin is high, the converter is
in the Power Down mode and the data output pins hold
the last conversion result.
CMOS/TTL compatible digital clock Input. V
is sampled
IN
on the rising edge of CLK input.
13 thru 16
and
D0–D7
19 thru 22
7V
IN
GND Reference ground for the single-ended analog input, VIN.
Conversion data digital Output pins. D0 is the LSB, D7 is
the MSB. Valid data is output after the rising edge of the
CLK input.
Positive analog supply pin. Connect to a quiet voltage
1, 4, 12 V
A
source of +3V. V
ceramic chip capacitor for each pin, plus one
should be bypassed with a 0.1 µF
A
10 µF capacitor. See Section 3.0 for more information.
18 V
DR
Power supply for the output drivers. If connected to VA,
decouple well from V
.
A
17 DR GND The ground return for the output driver supply.
2, 5, 8, 11 AGND The ground return for the analog supply.
www.national.com3
Absolute Maximum Ratings
(Notes 1, 2)
If Military/Aerospace specified devices are required,
ADC08L060
please contact the National Semiconductor Sales Office/
Distributors for availability and specifications.
Supply Voltage (V
Driver Supply Voltage (V
Voltage on Any Input or Output Pin −0.3V to V
Reference Voltage (VRT,VRB)V
CLK, PD Voltage Range −0.05V to
Input Current at Any Pin (Note 3)
Package Input Current (Note 3)
Power Dissipation at T
) 3.8V
A
)V
DR
A
(V
= 25˚C See (Note 4)
A
+0.3V
A
to AGND
+ 0.05V)
A
±
25 mA
±
50 mA
A
Operating Ratings (Notes 1, 2)
Operating Temperature Range −40˚C ≤ T
Supply Voltage, V
A
Driver Supply Voltage, V
Output Driver Voltage, V
DR
DR
+2.4V to +3.6V
Ground Difference |GND − DR GND| 0V to 300 mV
Upper Reference Voltage (V
Lower Reference Voltage (V
V
Voltage Range VRBto V
IN
) 0.5V to (VA−0.3V)
RT
) 0Vto(VRT−0.5V)
RB
Package Thermal Resistance
Package θ
24-Lead TSSOP 92˚C/W
JA
ESD Susceptibility (Note 5)
Human Body Model
Machine Model
2500V
200V
Soldering Temperature, Infrared,
10 seconds (Note 6) 235˚C
Storage Temperature −65˚C to +150˚C
Converter Electrical Characteristics
The following specifications apply for VA=VDR= +3.0VDC,VRT= +1.9V, VRB= 0.3V, CL= 10 pF, f
cycle. Boldface limits apply for T
J=TMIN
to T
Symbol Parameter Conditions
: all other limits TJ= 25˚C (Notes 7, 8)
MAX
Typical
(Note 9)
DC ACCURACY
INL Integral Non-Linearity
DNL Differential Non-Linearity
+0.5
−0.2
±
0.25
Missing Codes 0 (max)
FSE Full Scale Error 3.0
V
OFF
Zero Scale Offset Error 19 27 mV (max)
ANALOG INPUT AND REFERENCE CHARACTERISTICS
V
IN
C
IN
R
IN
Input Voltage 1.6
VINInput Capacitance
RINInput Resistance
V
= 0.75V +0.5
IN
Vrms
(CLK LOW) 3 pF
(CLK HIGH) 4 pF
>
1MΩ
BW Full Power Bandwidth 270 MHz
V
RT
V
RB
R
REF
I
ref
Top Reference Voltage 1.9
Bottom Reference Voltage 0.3
Reference Ladder Resistance VRTto V
Reference Ladder Current VRTto V
RB
RB
720
2.2
CLK, PD DIGITAL INPUT CHARACTERISTICS
V
IH
V
IL
I
IH
Logical High Input Voltage VDR=VA= 3.6V 2.0 V (min)
Logical Low Input Voltage VDR=VA= 2.7V 0.8 V (max)
Logical High Input Current VIH=VDR=VA= 3.6V 10 nA
= 60 MHz at 50% duty
CLK
Limits
(Note 9)
+1.9
−1.35
±
0.90 LSB (max)
±
13 mV (max)
V
RB
V
RT
V
A
0.5 V (min)
− 0.5 V (max)
V
RT
0 V (min)
590 Ω (min)
1070 Ω (max)
1.5 mA (min)
2.7 mA (max)
≤ +85˚C
A
+2.4V to V
1.8V to V
Units
(Limits)
LSB (max)
LSB (min)
V (min)
V (max)
V (max)
A
A
RT
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Converter Electrical Characteristics (Continued)
The following specifications apply for VA=VDR= +3.0VDC,VRT= +1.9V, VRB= 0.3V, CL= 10 pF, f
cycle. Boldface limits apply for T
J=TMIN
to T
Symbol Parameter Conditions
I
IL
C
IN
Logical Low Input Current VIL= 0V, VDR=VA= 2.7V −50 nA
Logic Input Capacitance 3 pF
DIGITAL OUTPUT CHARACTERISTICS
V
OH
V
OL
High Level Output Voltage VA=VDR= 2.7V, IOH= −400 µA 2.6 2.4 V (min)
Low Level Output Voltage VA=VDR= 2.7V, IOL= 1.0 mA 0.4 0.5 V (max)
DYNAMIC PERFORMANCE
ENOB Effective Number of Bits
SINAD Signal-to-Noise & Distortion
SNR Signal-to-Noise Ratio
SFDR Spurious Free Dynamic Range
THD Total Harmonic Distortion
HD2 2nd Harmonic Distortion
HD3 3rd Harmonic Distortion
IMD Intermodulation Distortion
POWER SUPPLY CHARACTERISTICS
I
A
DRI
I
A
DRI
+
Analog Supply Current
Output Driver Supply Current
D
Total Operating Current
D
PC Power Consumption
PSRR
Power Supply Rejection Ratio
1
PSRR2Power Supply Rejection Ratio
AC ELECTRICAL CHARACTERISTICS
f
C1
f
C2
t
CL
t
CH
Maximum Conversion Rate 80 60 MHz (min)
Minimum Conversion Rate 10 MHz
Minimum Clock Low Time 0.62 ns (min)
Minimum Clock High Time 0.62 ns (min)
DC Clock Duty Cycle
t
OH
Output Hold Time CLK to Data Invalid 5.2 ns
: all other limits TJ= 25˚C (Notes 7, 8)
MAX
Typical
(Note 9)
f
= 10.1 MHz, VIN= FS − 0.25 dB 7.6 6.9 Bits (min)
IN
f
= 29 MHz, VIN= FS − 0.25 dB 7.4 Bits
IN
f
= 10.1 MHz, VIN= FS − 0.25 dB 47.4 43.3 dB (min)
IN
f
= 29 MHz, VIN= FS − 0.25 dB 46.1 dB
IN
f
= 10.1 MHz, VIN= FS − 0.25 dB 48 44.5 dB (min)
IN
f
= 29 MHz, VIN= FS − 0.25 dB 47.2 dB
IN
f
= 10.1 MHz, VIN= FS − 0.25 dB 59.1 dBc
IN
f
= 29 MHz, VIN= FS − 0.25 dB 54.5 dBc
IN
f
= 10.1 MHz, VIN= FS − 0.25 dB −56.9 dBc
IN
f
= 29 MHz, VIN= FS − 0.25 dB −53.3 dBc
IN
f
= 10.1 MHz, VIN= FS − 0.25 dB -61.1 dBc
IN
f
= 29 MHz, VIN= FS − 0.25 dB −54.9 dBc
IN
f
= 10.1 MHz, VIN= FS − 0.25 dB −64.2 dBc
IN
f
= 29 MHz, VIN= FS − 0.25 dB −63.1 dBc
IN
f
= 11 MHz, VIN= FS − 6.25 dB
1
= 12 MHz, VIN= FS − 6.25 dB
f
2
−55 dBc
DC Input 13 15.9 mA (max)
f
= 10 MHz, VIN=FS−3dB 14 mA
IN
DC Input 0.04 0.2 mA (max)
f
= 10 MHz, VIN=FS−3dB 4.2 mA
IN
DC Input 13 16.1 mA (max)
f
= 10 MHz, VIN= FS − 3 dB, PD =
IN
Low
18.2 mA
CLK Low, PD = Hi 0.33 mA
DC Input 39 48.3 mW (max)
f
= 10 MHz, VIN= FS − 3 dB, PD =
IN
Low
53
CLK Low, PD = Hi 1 mW
FSE change with 2.7V to 3.3V change
in V
A
SNR reduction with 200 mV at 1MHz
on supply
−51 dB
45 dB
95
ADC08L060
= 60 MHz at 50% duty
CLK
Limits
(Note 9)
5
Units
(Limits)
mW
%(min)
%(max)
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Converter Electrical Characteristics (Continued)
The following specifications apply for VA=VDR= +3.0VDC,VRT= +1.9V, VRB= 0.3V, CL= 10 pF, f
cycle. Boldface limits apply for T
J=TMIN
to T
ADC08L060
Symbol Parameter Conditions
: all other limits TJ= 25˚C (Notes 7, 8)
MAX
Typical
(Note 9)
DYNAMIC PERFORMANCE
t
OD
Output Delay CLK to Data Transition 7.1
Pipeline Delay (Latency) 5 Clock Cycles
t
AD
t
AJ
Note 1: Absolute Maximum Ratings indicate limits beyond which damage to the device may occur. Operating Ratings indicate conditions for which the device is
functional, but do not guarantee specific performance limits. For guaranteed specifications and test conditions, see the Electrical Characteristics. The guaranteed
specifications apply only for the test conditions listed. Some performance characteristics may degrade when the device is not operated under the listed test
conditions.
Note 2: All voltages are measured with respect to GND = AGND = DR GND = 0V, unless otherwise specified.
Note 3: When the input voltage at any pin exceeds the power supplies (that is, less thanAGND or DR GND, or greater than V
be limited to 25 mA. The 50 mA maximum package input current rating limits the number of pins that can safely exceed the power supplies with an input current of
25 mA to two.
Note 4: The absolute maximum junction temperature (T
junction-to-ambient thermal resistance (θ
for maximum power dissipation will be reached only when this device is operated in a severe fault condition (e.g., when input or output pins are driven beyond the
power supply voltages, or the power supply polarity is reversed). Obviously, such conditions should always be avoided.
Note 5: Human body model is 100 pF capacitor discharged through a 1.5 kΩ resistor. Machine model is 220 pF discharged through ZERO Ohms.
Note 6: See AN-450, “Surface Mounting Methods and Their Effect on Product Reliability”.
Note 7: The analog inputs are protected as shown below. Input voltage magnitudes up to V
However, errors in the A/D conversion can occur if the input goes above V
voltage must be ≤2.8V
Sampling (Aperture) Delay CLK Rise to Acquisition of Data 2.6 ns
Aperture Jitter 2 ps rms
max) for this device is 150˚C. The maximum allowable power dissipation is dictated by TJmax, the
), and the ambient temperature (TA), and can be calculated using the formula PDMAX = (TJmax − TA)/θJA. The values
JA
to ensure accurate conversions.
DC
J
+ 300 mV or to 300 mV below GND will not damage this device.
or below GND by more than 100 mV. For example, if VAis 2.7VDCthe full-scale input
DR
A
= 60 MHz at 50% duty
CLK
Limits
(Note 9)
5.0 ns (min)
9.4 ns (max)
or VDR), the current at that pin should
A
Units
(Limits)
20041707
Note 8: To guarantee accuracy, it is required that VAand VDRbe well bypassed. Each supply pin must be decoupled with separate bypass capacitors.
Note 9: Typical figures are at T
Level).
Note 10: I
voltage, V
driver power supply voltage, C
is the current consumed by the switching of the output drivers and is primarily determined by the load capacitance on the output pins, the supply
DR
, and the rate at which the outputs are switching (which is signal dependent), IDR=VDR(COxfO+C1xf1+…+C71xf7) where VDRis the output
DR
= 25˚C, and represent most likely parametric norms. Test limits are guaranteed to National’s AOQL (Average Outgoing Quality
J
is the total capacitance on any given output pin, and fnis the average frequency at which that pin is toggling.
n
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Specification Definitions
APERTURE (SAMPLING) DELAY is that time required after
the rise of the clock input for the sampling switch to open.
The Sample/Hold circuit effectively stops capturing the input
signal and goes into the “hold” mode t
high.
APERTURE JITTER is the variation in aperture delay from
sample to sample. Aperture jitter shows up as input noise.
CLOCK DUTY CYCLE is the ratio of the time that the clock
wave form is at a logic high to the total time of one clock
period.
DIFFERENTIAL NON-LINEARITY (DNL) is the measure of
the maximum deviation from the ideal step size of 1 LSB.
Measured at 60 MSPS with a ramp input.
EFFECTIVE NUMBER OF BITS (ENOB, or EFFECTIVE
BITS) is another method of specifying Signal-to-Noise and
Distortion Ratio, or SINAD. ENOB is defined as (SINAD –
1.76) / 6.02 and says that the converter is equivalent to a
perfect ADC of this (ENOB) number of bits.
FULL POWER BANDWIDTH is a measure of the frequency
at which the reconstructed output fundamental drops 3 dB
below its low frequency value for a full scale input.
FULL-SCALE ERROR is a measure of how far the last code
transition is from the ideal 1
1
⁄2LSB below VRTand is defined
as:
+ 1.5 LSB – V
V
max
where V
is the voltage at which the transition to the
max
maximum (full scale) code occurs.
INTEGRAL NON-LINEARITY (INL) is a measure of the
deviation of each individual code from a line drawn from zero
1
⁄2LSB below the first code transition) through positive
scale (
full scale (
1
⁄2LSB above the last code transition). The deviation of any given code from this straight line is measured
from the center of that code value. The end point test method
is used. Measured at 60 MSPS with a ramp input.
INTERMODULATION DISTORTION (IMD) is the creation of
additional spectral components as a result of two sinusoidal
frequencies being applied to the ADC input at the same time.
it is defined as the ratio of the power in the second and third
order intermodulation products to the power in one of the
original frequencies. IMD is usually expressed in dBFS.
LSB (LEAST SIGNIFICANT BIT) is the bit that has the
smallest value or weight of all bits. This value is
(V
RT−VRB
where “n” is the ADC resolution, which is 8 in the case of the
ADC08L060.
MISSING CODES are those output codes that are skipped
and will never appear at the ADC outputs. These codes
cannot be reached with any input value.
MSB (MOST SIGNIFICANT BIT) is the bit that has the
largest value or weight. Its value is one half of full scale.
OUTPUT DELAY is the time delay after the rising edge of
the input clock before the data update is present at the
output pins.
OUTPUT HOLD TIME is the length of time that the output
data is valid after the rise of the input clock.
PIPELINE DELAY (LATENCY) is the number of clock cycles
between initiation of conversion and when that data is pre-
after the clock goes
AD
RT
n
)/2
sented to the output driver stage. New data is available at
every clock cycle, but the data lags the conversion by the
Pipeline Delay plus the Output Delay.
POWER SUPPLY REJECTION RATIO (PSRR) is a measure of how well the ADC rejects a change in the power
supply voltage. For the ADC08L060, PSRR1 is the ratio of
the change in Full-Scale Error that results from a change in
the d.c. power supply voltage, expressed in dB. PSRR2 is a
measure of how well an a.c. signal riding upon the power
supply is rejected and is here defined as
where SNR0 is the SNR measured with no noise or signal on
the supply lines and SNR1 is the SNR measured with a
1 MHz, 200 mV
signal riding upon the supply lines.
P-P
SIGNAL TO NOISE RATIO (SNR) is the ratio, expressed in
dB, of the rms value of the input signal at the output to the
rms value of the sum of all other spectral components below
one-half the sampling frequency, not including harmonics or
d.c.
SIGNAL TO NOISE PLUS DISTORTION (S/(N+D) or
SINAD) is the ratio, expressed in dB, of the rms value of the
input signal at the output to the rms value of all of the other
spectral components below half the clock frequency, including harmonics but excluding d.c.
SPURIOUS FREE DYNAMIC RANGE (SFDR) is the difference, expressed in dB, between the rms values of the input
signal at the output and the peak spurious signal, where a
spurious signal is any signal present in the output spectrum
that is not present at the input.
TOTAL HARMONIC DISTORTION (THD) is the ratio expressed in dB, of the rms total of the first nine harmonic
levels at the output to the level of the fundamental at the
output. THD is calculated as
where Af1is the RMS power of the fundamental (output)
frequency and A
through A
f2
are the RMS power of the
f10
first 9 harmonic frequencies in the output spectrum.
ZERO SCALE OFFSET ERROR is the error in the input
voltage required to cause the first code transition. It is defined as
V
OFF=VZT−VRB
where VZTis the first code transition input voltage.
2nd HARMONIC DISTORTION (2nd HARM) is the differ-
ence, expressed in dB, between the rms power in the output
fundamental frequency and the power in its 2nd harmonic at
the output.
3rd HARMONIC DISTORTION (3rd HARM) is the difference, expressed in dB, between the rms power in the output
fundamental frequency and the power in its 3rd harmonic at
the output.
ADC08L060
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Timing Diagram
ADC08L060
20041710
FIGURE 1. ADC08L060 Timing Diagram
Typical Performance Characteristics
wise stated
INL INL vs. Temperature
20041753
INL vs. Supply Voltage, V
A
VA=VDR= 3V, f
= 60 MHz, fIN= 10 MHz, unless other-
CLK
20041712
INL vs. Sample Rate
20041713 20041714
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ADC08L060
Typical Performance Characteristics V
stated (Continued)
INL vs. Clock Duty Cycle DNL
20041715
DNL vs. Temperature DNL vs. Supply Voltage, V
A=VDR
= 3V, f
= 60 MHz, fIN= 10 MHz, unless otherwise
CLK
20041754
A
20041717 20041718
DNL vs. Sample Rate DNL vs. Clock Duty Cycle
20041719 20041720
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Typical Performance Characteristics V
stated (Continued)
A=VDR
= 3V, f
= 60 MHz, fIN= 10 MHz, unless otherwise
CLK
ADC08L060
SNR, SINAD and SFDR vs. Temperature SNR, SINAD and SFDR vs. Supply Voltage, V
20041721 20041722
SNR, SINAD and SFDR vs. Sample Rate SNR, SINAD and SFDR vs. Input Frequency
A
20041723 20041724
SNR, SINAD and SFDR vs. Clock Duty Cycle Distortion vs. Temperature
20041725
20041726
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ADC08L060
Typical Performance Characteristics V
stated (Continued)
Distortion vs. Supply Voltage, V
Distortion vs. Input Frequency Distortion vs. Clock Duty Cycle
A
20041727 20041728
A=VDR
= 3V, f
= 60 MHz, fIN= 10 MHz, unless otherwise
CLK
Distortion vs. Sample Rate
20041729 20041730
Power Consumption (Active) vs.
Sample Rate (f
IN
= d.c.)
20041731
Power Consumption (Active) vs.
Sample Rate (fIN= d.c.)
20041738
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Typical Performance Characteristics V
stated (Continued)
A=VDR
= 3V, f
= 60 MHz, fIN= 10 MHz, unless otherwise
CLK
ADC08L060
Power Consumption (Active) vs.
Sample Rate (f
= 1 MHz)
IN
20041739 20041740
Power Consumption (Active) vs.
Sample Rate (fIN= 1 MHz)
Spectral Response@fIN= 10 MHz Spectral Response@fIN=29MHz
20041755 20041757
Spectral Response@fIN= 75 MHz Spectral Response@fIN= 98.9 MHz
20041756 20041758
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Functional Description
The ADC08L060 uses a unique architecture that achieves
over 7 effective bits at input frequencies up to and beyond
Nyquist.
The analog input signal that is within the voltage range set by
and VRBis digitized to eight bits. Input voltages below
V
RT
will cause the output word to consist of all zeroes. Input
V
RB
voltages above V
all ones.
Incorporating a switched capacitor bandgap, the
ADC08L060 exhibits a power consumption that is proportional to frequency, limiting power consumption to what is
needed at the clock rate that is used. This and its excellent
performance over a wide range of clock frequencies makes
it an ideal choice as a single ADC for many 8-bit needs.
Data is acquired at the rising edge of the clock and the digital
equivalent of that data is available at the digital outputs 5
clock cycles plus t
long as an adequate clock signal is present at pin 24. The
will cause the output word to consist of
RT
later. The ADC08L060 will convert as
OD
device is in the active state when the Power Down pin (PD)
is low. When the PD pin is high, the device is in the power
down mode, where the output pins hold the last conversion
before the PD pin went high and the device consumes about
1.4 mW. Holding the clock input low will further reduce the
power consumption in the power down mode to about 1 mW
Applications Information
1.0 REFERENCE INPUTS
The reference inputs V
the reference ladder, respectively. Input signals between
these two voltages will be digitized to 8 bits. External voltages applied to the reference input pins should be within the
range specified in the Operating Ratings table. Any device
used to drive the reference pins should be able to source
sufficient current into the V
from the V
pin to keep these voltages stable.
RB
and VRBare the top and bottom of
RT
pin and sink sufficient current
RT
ADC08L060
20041732
FIGURE 2. Simple, low component count reference biasing. Because of the ladder and external resistor tolerances,
the reference voltage of this circuit can vary too much for some applications.
The reference bias circuit of Figure 2 is very simple and the
performance is adequate for many applications. However,
circuit tolerances will lead to a wide reference voltage range.
Better reference stability can be achieved by driving the
reference pins with low impedance sources.
The circuit of Figure 3 will allow a more accurate setting of
the reference voltages. The lower amplifier must have bipolar supplies as its output voltage must go negative to force
to any voltage below the VBEof the PNP transistor. Of
V
RB
course, the divider resistors at the amplifier input could be
changed to suit your reference voltage needs, or the divider
can be replaced with potentiometers for precise settings.
The bottom of the ladder (V
ground if the minimum input signal excursion is 0V. Be sure
that the driving source can source sufficient current into the
pin and sink enough current from the VRBpin to keep
V
RT
these pins stable.
The LMC662 amplifier shown was chosen for its low offset
voltage and low cost. V
more positive than V
The V
pin is the center of the reference ladder and should
RM
RB
be bypassed to a quiet point in the analog ground plane with
a 0.1 µF capacitor. DO NOT allow this pin to float.
) may simply be returned to
RB
should always be at least 0.5V
RT
to minimize noise.
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Applications Information (Continued)
ADC08L060
FIGURE 3. Driving the reference to force desired values requires driving with a low impedance source.
2.0 THE ANALOG INPUT
The analog input of the ADC08L060 is a switch followed by
an integrator. The input capacitance changes with the clock
level, appearing as 3 pF when the clock is low, and 4 pF
when the clock is high. The sampling nature of the analog
input causes current spikes that result in voltage spikes at
the analog input pin. Any circuit used to drive the analog
input must be able to drive that input and to settle within the
clock low time. The LMH6702 has been found to be a good
amplifier to drive the ADC08L060.
Figure 4 shows an example of an input circuit using the
LMH6702. Any input amplifier should incorporate some gain
as operational amplifiers exhibit better phase margin and
transient response with gains above 2 or 3 than with unity
gain. If an overall gain of less than 3 is required, attenuate
the input and operate the amplifier at a higher gain, as
shown in Figure 4.
The RC at the amplifier output filters the clock rate energy
that comes out of the analog input due to the input sampling
circuit. The optimum time constant for this circuit depends
not only upon the amplifier and ADC, but also on the circuit
layout and board material. A resistor value should be chosen
between 10Ω and 47Ω and the capacitor value chose according to the formula
This will provide optimum SNR performance. Best THD performance is realized when the capacitor and resistor values
are both zero. To optimize SINAD, reduce the capacitor
value until SINAD performance is optimized. That is, until
SNR = −THD. This value will usually be in the range of 20&
to 65% of the value calculated with the above formula. An
accurate calculation is not possible because of the board
material and layout dependence.
The circuit of Figure 4 has both gain and offset adjustments.
If you eliminate these adjustments normal circuit tolerances
may result in signal clipping unless care is exercised in the
worst case analysis of component tolerances and the input
signal excursion is appropriately limited to account for the
worst case conditions.
20041733
www.national.com 14
Applications Information (Continued)
ADC08L060
FIGURE 4. The input amplifier should incorporate some gain for best performance (see text).
3.0 POWER SUPPLY CONSIDERATIONS
A/D converters draw sufficient transient current to corrupt
their own power supplies if not adequately bypassed. A
10 µF tantalum or aluminum electrolytic capacitor should be
placed within an inch (2.5 cm) of the A/D power pins, with a
0.1 µF ceramic chip capacitor placed within one centimeter
of the converter’s power supply pins. Leadless chip capacitors are preferred because they have low lead inductance.
While a single voltage source is recommended for the V
and VDRsupplies of the ADC08L060, these supply pins
should be well isolated from each other to prevent any digital
noise from being coupled into the analog portions of the
ADC. A choke or 27Ω resistor is recommended between
these supply lines with adequate bypass capacitors close to
the supply pins.
As is the case with all high speed converters, the
ADC08L060 should be assumed to have little power supply
rejection. None of the supplies for the converter should be
the supply that is used for other digital circuitry in any system
with a lot of digital power being consumed. The ADC supplies should be the same supply used for other analog
circuitry.
No pin should ever have a voltage on it that is in excess of
the supply voltage or below ground by more than 300 mV,
not even on a transient basis. This can be a problem upon
application of power and power shut-down. Be sure that the
supplies to circuits driving any of the input pins, analog or
digital, do not come up any faster than does the voltage at
the ADC08L060 power pins.
20041734
4.0 THE DIGITAL INPUT PINS
The ADC08L060 has two digital input pins: The PD pin and
the Clock pin.
4.1 The PD Pin
The Power Down (PD) pin, when high, puts the ADC08L060
into a low power mode where power consumption is reduced
to 1.4 mW with the clock running, or to about 1 mW with the
A
clock held low. Output data is valid and accurate about 1
microsecond after the PD pin is brought low.
The digital output pins retain the last conversion output code
when either the clock is stopped or the PD pin is high.
4.2 The ADC08L060 Clock
Although the ADC08L060 is tested and its performance is
guaranteed with a 60 MHz clock, it typically will function well
with clock frequencies from 10 MHz to 80 MHz.
4.2.1 Clock Duty Cycle
The low and high times of the clock signal can affect the
performance of any A/D Converter. Because achieving a
precise duty cycle is difficult, the ADC08L060 is designed to
maintain performance over a range of duty cycles. While it is
specified and performance is guaranteed with a 50% clock
duty cycle and 60 Msps, ADC08L060 performance is typically maintained with clock high and low times of 0.83 ns,
corresponding to a clock duty cycle range of 5% to 95% with
a 60 MHz clock. Note that minimum low and high times may
not be simultaneously asserted.
www.national.com15
Applications Information (Continued)
4.2.2 Clock Line Termination The CLOCK line should be series terminated at the clock
ADC08L060
source in the characteristic impedance of that line. If the
clock line is longer than
where tris the clock rise time and t
of the signal along the trace. The CLOCK pin should be a.c.
terminated with a series RC to ground such that the resistor
value is equal to the characteristic impedance of the clock
line and the capacitor value is
where “L” is the line length in inches and ZOis the characteristic impedance of the clock line. Typical t
150 ps/inch on FR-4 board material. For FR-4 board material, the value of C becomes
This termination should be located as close as possible to,
but within one centimeter of, the ADC08L060 clock pin.
5.0 LAYOUT AND GROUNDING
Proper grounding and proper routing of all signals are essential to ensure accurate conversion. A combined analog
and digital ground plane should be used.
Since digital switching transients are composed largely of
high frequency components, total ground plane copper
weight will have little effect upon the logic-generated noise
because of the skin effect. Total surface area is more important than is total ground plane volume. Capacitive coupling
between the typically noisy digital circuitry and the sensitive
analog circuitry can lead to poor performance that may seem
impossible to isolate and remedy. The solution is to keep the
analog circuitry well separated from the digital circuitry.
High power digital components should not be located on or
near a straight line between the ADC or any linear component and the power supply area as the resulting common
return current path could cause fluctuation in the analog
input “ground” return of the ADC.
Keeping analog and digital return (ground) currents separate
from each other will improve system noise performance. Two
methods may be used to do this. Use of traces rather than a
solid plane to route power to all components will accomplish
this because return currents follow the path of the outgoing
currents. However, the advantage of the distributed capacitance of a power plane and a ground plane is lost. Analog
and digital power should be routed as far from each other as
is practical. The analog power trace should also be routed
away from digital areas of the board.
The use of power and ground planes in adjacent layers will
provide distributed capacitance for a low impedance power
distribution system and better system noise performance.
The use of separate analog and digital power planes, both in
the same PC board layer, and the use of a single, non-split
ground plane will keep analog and digital currents separated
is the propagation rate
prop
PROP
is about
from each other. Of course, locate all analog circuitry and
traces over the analog power plane and the digital circuitry
and traces over the digital power plane. To minimize RFI/
EMI, give proper attention to any lines crossing the analog/
digital power plane boundary.
Noise performance is also enhanced by driving a single gate
with each ADC output pin and locating the gate as close as
possible to the ADC output. Inserting a 47Ω resistor in series
with the ADC digital output pins will also help reduce ADC
noise. Be sure to keep the resistors as close to the ADC
output pins as possible. Eliminating ground plane copper
beneath the ADC output lines can also help ADC noise
performance, but could produce unacceptable radiation from
the board.
Analog and digital circuitry should be kept well away from
each other. Especially troublesome is high power digital
components such as processors and large PLDs. Switch
mode power supplies, including capacitive DC-DC converters, can cause noise problems with high speed ADCs. Keep
such components well away from ADCs and low level analog
signal areas. Such components should be located as close
to the power supply as possible and should not be in the path
of analog signal or power supply currents.
Digital circuits create substantial supply and ground current
transients. The noise thus generated could have significant
impact upon system noise performance. The best logic family to use in systems with A/D converters is one that employs
non-saturating transistor designs, or has low noise characteristics, like the 74LS and the 74AC(T)Q families. The worst
noise generators are logic families that draw the largest
supply current transients during clock or signal edges, like
the 74HC, 74F and 74AC(T) families.
Since digital switching transients are composed largely of
high frequency components, total ground plane copper
weight will have little effect upon logic-generated noise. This
is because of the skin effect. Total surface area is more
important than is total ground plane volume.
Clock lines should be isolated from ALL other lines, analog
AND digital. Even the generally accepted 90˚ crossing
should be avoided as even a little coupling can cause problems at high frequencies. Best performance at high frequencies is obtained with a straight signal path.
20041736
FIGURE 5. Layout Example
www.national.com 16
Applications Information (Continued)
The analog input should be isolated from noisy signal traces
to avoid coupling of spurious signals into the input. Any
external component (e.g., a filter capacitor) connected between the converter’s input and ground should be connected
to a very clean point in the ground plane.
Figure 5 gives an example of a suitable layout. All analog
circuitry (input amplifiers, filters, reference components, etc.)
should be placed together away from any digital components.
6.0 DYNAMIC PERFORMANCE
The ADC08L060 is a.c. tested and its dynamic performance
is guaranteed. To meet the published specifications, the
clock source driving the CLK input should exhibit less than
10 ps (rms) of jitter. For best a.c. performance, isolating the
ADC clock from any digital circuitry should be done with
adequate buffers, as with a clock tree. See Figure 6.
It is good practice to keep the ADC clock line as short as
possible and to keep it well away from any other signals.
Other signals can introduce jitter into the clock signal. The
clock signal can also introduce noise into the analog path.
20041737
FIGURE 6. Isolating the ADC Clock from Digital
Circuitry
7.0 COMMON APPLICATION PITFALLS Driving the inputs (analog or digital) beyond the power
supply rails. For proper operation, all inputs should not go
more than 300 mV below the ground pins or 300 mV above
the supply pins. Exceeding these limits on even a transient
basis may cause faulty or erratic operation. It is not uncommon for high speed digital circuits (e.g., 74F and 74AC
devices) to exhibit undershoot that goes more than a volt
below ground. A 51Ω resistor in series with the offending
digital input will usually eliminate the problem.
Care should be taken not to overdrive the inputs of the
ADC08L060. Such practice may lead to conversion inaccuracies and even to device damage.
Attempting to drive a high capacitance digital data bus.
The more capacitance the output drivers must charge for
each conversion, the more instantaneous digital current is
required from V
and DR GND. These large charging cur-
DR
rent spikes can couple into the analog section, degrading
dynamic performance. Buffering the digital data outputs (with
a 74F541, for example) may be necessary if the data bus
capacitance exceeds 5 pF. Dynamic performance can also
be improved by adding 100Ω series resistors at each digital
output, reducing the energy coupled back into the converter
input pins.
Using an inadequate amplifier to drive the analog input.
As explained in Section 2.0, the capacitance seen at the
input alternates between 3 pF and 4 pF with the clock. This
dynamic capacitance is more difficult to drive than is a fixed
capacitance, and should be considered when choosing a
driving device.
Driving the V
pin or the VRBpin with devices that can
RT
not source or sink the current required by the ladder. As
mentioned in Section 1.0, care should be taken to see that
any driving devices can source sufficient current into the V
RT
pin and sink sufficient current from the VRBpin. If these pins
are not driven with devices than can handle the required
current, these reference pins will not be stable, resulting in a
reduction of dynamic performance.
Using a clock source with excessive jitter, using an
excessively long clock signal trace, or having other
signals coupled to the clock signal trace. This will cause
the sampling interval to vary, causing excessive output noise
and a reduction in SNR performance. The use of simple
gates with RC timing is generally inadequate as a clock
source.
ADC08L060
www.national.com17
Physical Dimensions inches (millimeters)
unless otherwise noted
Sample-and-Hold
NOTES: UNLESS OTHERWISE SPECIFIED
REFERENCE JEDEC REGISTRATION mo-153, VARIATION AD, DATED 7/93.
LIFE SUPPORT POLICY
NATIONAL’S PRODUCTS ARE NOT AUTHORIZED FOR USE AS CRITICAL COMPONENTS IN LIFE SUPPORT
DEVICES OR SYSTEMS WITHOUT THE EXPRESS WRITTEN APPROVAL OF THE PRESIDENT AND GENERAL
COUNSEL OF NATIONAL SEMICONDUCTOR CORPORATION. As used herein:
1. Life support devices or systems are devices or
ADC08L060 8-Bit, 10 MSPS to 60 MSPS, 0.65 mW/MSPS A/D Converter with Internal
BANNED SUBSTANCE COMPLIANCE
National Semiconductor certifies that the products and packing materials meet the provisions of the Customer Products
Stewardship Specification (CSP-9-111C2) and the Banned Substances and Materials of Interest Specification
(CSP-9-111S2) and contain no ‘‘Banned Substances’’ as defined in CSP-9-111S2.
24-Lead Package TC
Order Number ADC08L060CIMT
NS Package Number MTC24
systems which, (a) are intended for surgical implant
into the body, or (b) support or sustain life, and
whose failure to perform when properly used in
accordance with instructions for use provided in the
labeling, can be reasonably expected to result in a
significant injury to the user.
2. A critical component is any component of a life
support device or system whose failure to perform
can be reasonably expected to cause the failure of
the life support device or system, or to affect its
safety or effectiveness.
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Support Center
Email: new.feedback@nsc.com
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www.national.com
National does not assume any responsibility for use of any circuitry described, no circuit patent licenses are implied and National reserves the right at any time without notice to change said circuitry and specifications.
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