Rainbow Electronics ADC08D1000 User Manual
ADVANCE INFORMATION
January 2005
ADC08D1000
High Performance, Low Power, Dual 8-Bit, 1 GSPS A/D
Converter
High Performance, Low Power, Dual 8-Bit, 1 GSPS A/D Converter
General Description
NOTE: This product is currently in development. – ALL
specifications are design targets and are subject to
change.
The ADC08D1000 is a dual, low power, high performance
CMOS analog-to-digital converter that digitizes signals to 8
bits resolution at sampling rates up to 1.3 GSPS. Consuming
a typical 1.6 Watts at 1 GSPS from a single 1.9 Volt supply,
this device is guaranteed to have no missing codes over the
full operating temperature range. The unique folding and
interpolating architecture, the fully differential comparator
design, the innovative design of the internal sample-andhold amplifier and the self-calibration scheme enable a very
flat response of all dynamic parameters beyond Nyquist,
producing a high 7.5 ENOB with a 500 MHz input signal and
a 1 GHz sample rate while providing a 10
formatting is offset binary and the LVDS digital outputs are
compliant with IEEE 1596.3-1996, with the exception of a
reduced common mode voltage of 0.8V.
Each converter has a 1:2 demultiplexer that feeds two LVDS
buses and reduces the output data rate on each bus to half
the sampling rate. The two converters can be interleaved
and used as a single 2 GSPS ADC.
The converter typically consumes less than 20 mW in the
Power Down Mode and is available in a 128-lead, thermally
enhanced exposed pad LQFP and operates over the industrial (-40˚C ≤ T
≤ +85˚C) temperature range.
A
-18
B.E.R. Output
Features
n Internal Sample-and-Hold
n Single +1.9V
n Choice of SDR or DDR output clocking
n Interleave Mode for 2x Sampling Rate
n Multiple ADC Synchronization Capability
n Guaranteed No Missing Codes
n Serial Interface for Extended Control
n Fine Adjustment of Input Full-Scale Range and Offset
n Duty Cycle Corrected Sample Clock
±
0.1V Operation
Key Specifications
n Resolution 8 Bits
n Max Conversion Rate 1 GSPS (min)
n Bit Error Rate 10
n ENOB
n DNL
n Power Consumption
@
500 MHz Input 7.5 Bits (typ)
±
— Operating 1.6 W (typ)
— Power Down Mode 20 mW (typ)
-18
(typ)
0.25 LSB (typ)
Applications
n Direct RF Down Conversion
n Digital Oscilloscopes
n Satellite Set-top boxes
n Communications Systems
n Test Instrumentation
Block Diagram
20097453
© 2005 National Semiconductor Corporation DS200974 www.national.com
Ordering Information
ADC08D1000
Pin Configuration
Extended Commercial Temperature
<
<
T
Range (-40˚C
ADC08D1000CIYB 128-Pin Exposed Pad LQFP
ADC08D1000EVAL Evaluation Board
A
+85˚C)
NS Package
* Exposed pad on back of package must be soldered to ground plane to ensure rated performance.
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20097401
Pin Descriptions and Equivalent Circuits
Pin Functions
Pin No. Symbol Equivalent Circuit Description
Output Voltage Amplitude and Serial Interface Clock. Tie this
pin high for normal differential DCLK and data amplitude.
3 OutV / SCLK
OutEdge / DDR
4
/ SDATA
15 DCLK_RST
26
29
PD
PDQ
30 CAL
14 FSR/ECE
127
CalDly / DES /
SCS
Ground this pin for a reduced differential output amplitude and
reduced power consumption. See Section 1.1.6. When the
extended control mode is enabled, this pin functions as the
SCLK input which clocks in the serial data. See Section 1.3
DCLK Edge Select, Double Data Rate Enable and Serial Data
Input. This input sets the output edge of DCLK+ at which the
output data transitions. (See Section 1.1.5.2). When this pin is
floating or connected to 1/2 the supply voltage, DDR clocking
is enabled. When the extended control mode is enabled, this
pin functions as the (SDATA) input. See Section 1.2 for
details on the extended control mode.
DCLK Reset. A positive pulse on this pin is used to reset and
synchronize the DCLK outs of multiple converters. See
Section 1.5 for detailed description.
Power Down Pins. A logic high on the PD pin puts the entire
device into the Power Down Mode. A logic high on the PDQ
pin puts only the "Q" ADC into the Power Down mode.
Calibration Cycle Initiate. A minimum 80 input clock cycles
logic low followed by a minimum of 80 input clock cycles high
on this pin initiates the self calibration sequence. See Section
2.4.2.
Full Scale Range Select and Extended Control Enable. In
non-extended control mode, a logic low on this pin sets the
full-scale differential input range to 650 mV
this pin sets the full-scale differential input range to 860
. See Section 1.1.4. To enable the extended control
mV
P-P
mode, whereby the serial interface and control registers are
employed, allow this pin to float or connect it to a voltage
equal to V
/2. See Section 1.2 for information on the
A
extended control mode.
Calibration Delay, Dual Edge Sampling and Serial Interface
Chip Select. With a logic high or low on pin 14, this pin
functions as Calibration Delay and sets the number of input
clock cycles after power up before calibration begins (See
Section 1.1.1). With pin 14 floating, this pin acts as the enable
pin for the serial interface input and the CalDly value
becomes "0" (short delay with no provision for a long
power-up calibration delay). When this pin is floating or
connected to a voltage equal to V
Sampling) mode is selected where the "I" input is sampled at
twice the input clock rate and the "Q" input is ignored. See
Section 1.1.5.1.
. A logic high on
P-P
/2, DES (Dual Edge
A
ADC08D1000
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Pin Descriptions and Equivalent Circuits (Continued)
Pin Functions
Pin No. Symbol Equivalent Circuit Description
ADC08D1000
18
19
11
10
.
22
23
7V
31 V
CLK+
CLK-
V
IN
V
IN
.
V
IN
V
IN
CMO
BG
I+
I−
Q+
Q−
126 CalRun
LVDS Clock input pins for the ADC. The differential clock
signal must be a.c. coupled to these pins. The input signal is
sampled on the falling edge of CLK+. See Section 2.3.
Analog signal inputs to the ADC. The differential full-scale
input range is 650 mV
when the FSR pin is high.
mV
P-P
when the FSR pin is low, or 860
P-P
Common Mode Voltage. The voltage output at this pin is
required to be the common mode input voltage at V
− when d.c. coupling is used. This pin should be grounded
V
IN
+ and
IN
when a.c. coupling is used at the analog inputs. This pin is
capable of sourcing or sinking 100µA. See Section 2.2.
Bandgap output voltage capable of 100 µA source/sink.
Calibration Running indication. This pin is at a logic high when
calibration is running.
32 R
34
35
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EXT
Tdiode_P
Tdiode_N
External bias resistor connection. Nominal value is 3.3k-Ohms
±
0.1%) to ground. See Section 1.1.1.
(
Temperature Diode Positive (Anode) and Negative (Cathode)
for die temperature measurements. See Section 2.6.2.
Pin Descriptions and Equivalent Circuits (Continued)
Pin Functions
Pin No. Symbol Equivalent Circuit Description
83/78
84/77
85/76
86/75
89/72
90/71
91/70
92/69
93/68
94/67
95/66
96/65
100/61
101/60
102/59
103/58
104/57
105/56
106/55
107/54
111/50
112/49
113/48
114/47
115/46
116/45
117/44
118/43
122/39
123/38
124/37
125/36
DI7− / DQ7−
DI7+ / DQ7+
DI6− / DQ6−
DI6+ / DQ6+
DI5− / DQ5−
DI5+ / DQ5+
DI4− / DQ4−
DI4+ / DQ4+
DI3− / DQ3−
DI3+ / DQ3+
DI2− / DQ2−
DI2+ / DQ2+
DI1− / DQ1−
DI1+ / DQ1+
DI0− / DQ0−
DI0+ / DQ0+
DId7− / DQd7−
DId7+ / DQd7+
DId6− / DQd6−
DId6+ / DQd6+
DId5− / DQd5−
DId5+ / DQd5+
DId4− / DQd4−
DId4+ / DQd4+
DId3− / DQd3−
DId3+ / DQd3+
DId2− / DQd2−
DId2+ / DQd2+
DId1− / DQd1−
DId1+ / DQd1+
DId0− / DQd0−
DId0+ / DQd0+
I and Q channel LVDS Data Outputs that are not delayed in
the output demultiplexer. Compared with the DId and DQd
outputs, these outputs represent the later time samples.
These outputs should always be terminated with a 100Ω
differential resistor.
I and Q channel LVDS Data Outputs that are delayed by one
CLK cycle in the output demultiplexer. Compared with the
DI/DQ outputs, these outputs represent the earlier time
sample. These outputs should always be terminated with a
100Ω differential resistor.
ADC08D1000
79
80
82
81
2, 5, 8,
13, 16,
17, 20,
25, 28,
33, 128
OR+
OR-
DCLK+
DCLK-
V
A
Out Of Range output. A differential high at these pins
indicates that the differential input is out of range (outside the
±
range
Differential Clock outputs used to latch the output data.
Delayed and non-delayed data outputs are supplied
synchronous to this signal. This signal is at 1/2 the input clock
rate in SDR mode and at 1/4 the input clock rate in the DDR
mode.
Analog power supply pins. Bypass these pins to ground.
300 mV or±400 mV as defined by the FSR pin).
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Pin Descriptions and Equivalent Circuits (Continued)
Pin Functions
Pin No. Symbol Equivalent Circuit Description
ADC08D1000
40, 51
,62, 73,
88, 99,
110, 121
1, 6, 9,
12, 21,
24, 27,
41
42, 53,
64, 74,
87, 97,
108, 119
52, 63,
98, 109,
120
V
DR
GND Ground return for V
DR GND Ground return for V
NC No Connection. Make no connection to these pins.
Output Driver power supply pins. Bypass these pins to DR
GND.
.
A
.
DR
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ADC08D1000
Absolute Maximum Ratings
(Notes 1, 2)
If Military/Aerospace specified devices are required,
please contact the National Semiconductor Sales Office/
Distributors for availability and specifications.
Supply Voltage (V
Voltage on Any Input Pin −0.15V to (V
Ground Difference
|GND - DR GND| 0V to 100 mV
Input Current at Any Pin (Note 3)
Package Input Current (Note 3)
Power Dissipation at T
ESD Susceptibility (Note 4)
Human Body Model
Machine Model
Soldering Temperature, Infrared,
10 seconds (Note 5) 235˚C
Storage Temperature −65˚C to +150˚C
) 2.2V
A,VDR
= 25˚C 2.0 W
A
+0.15V)
±
25 mA
±
50 mA
2500V
250V
A
Operating Ratings (Notes 1, 2)
Ambient Temperature Range −40˚C ≤ T
Supply Voltage (V
Driver Supply Voltage (V
) +1.8V to +2.0V
A
) +1.8V to V
DR
Analog Input Common Mode
Voltage 1.2V to 1.3V
V
Differential Voltage Range −VFS/2 to +VFS/2
IN
Ground Difference
(|GND - DR GND|) 0V
CLK Pins Voltage Range 0V to V
Differential CLK Amplitude 0.6V
P-P
≤ +85˚C
A
to 2.0V
Package Thermal Resistance
θ
J-PAD
(Thermal
Pad)
Package
128-Lead Exposed
Pad LQFP
θ
(Top of
JC
Package)
10˚C / W 2.8˚C / W
Converter Electrical Characteristics
[Note: This product is currently in development. As such, the parameters specified in this section are DESIGN TARGETS. The specifications in this section cannot be guaranteed until device characterization has taken place.]
The following specifications apply after calibration for V
860mV
Extended Control Mode, R
to T
T
MIN
= 10 pF, Differential, a.c. coupled Sinewave Input Clock, f
P-P,CL
. All other limits TA= 25˚C, unless otherwise noted. (Notes 6, 7)
MAX
= 3300Ω±0.1%, Analog Signal Source Impedance = 100Ω. Boldface limits apply for TA=
EXT
A=VDR
Symbol Parameter Conditions
STATIC CONVERTER CHARACTERISTICS
INL Integral Non-Linearity
DNL Differential Non-Linearity
Resolution with No Missing Codes 8 Bits
V
OFF
V
OFF
TC V
Offset Error -0.45
_ADJ Input Offset Adjustment Range Extended Control Mode
Offset Error Tempco −40˚C to +85˚C −3 ppm/˚C
OFF
PFSE Positive Full-Scale Error (Note 9) −2.2
NFSE Negative Full-Scale Error (Note 9) −1.1
FS_ADJ Full-Scale Adjustment Range Extended Control Mode
TC PFSE Positive Full-Scale Error Tempco −40˚C to +85˚C 20 ppm/˚C
TC NFSE Negative Full-Scale Error Tempco −40˚C to +85˚C 13 ppm/˚C
Dynamic Converter Characteristics
FPBW Full Power Bandwidth Normal (non DES) Mode 1.7 GHz
FPBW
(DES)
Full Power Bandwidth Dual Edge Sampling Mode 900 MHz
B.E.R. Bit Error Rate 10
Gain Flatness
ENOB Effective Number of Bits
d.c. to 500 MHz
d.c. to 1 GHz
= 100 MHz, VIN= FSR − 0.5 dB 7.5 Bits
f
IN
f
= 248 MHz, VIN= FSR − 0.5 dB 7.5 TBD Bits (min)
IN
f
= 498 MHz, VIN= FSR − 0.5 dB 7.5 TBD Bits (min)
IN
= +1.9VDC, OutV = 1.9V, VINFSR (a.c. coupled) = differential
= 1 GHz at 0.5V
CLK
Typical
(Note 8)
with 50% duty cycle, Non-
P-P
Limits
(Note 8)
±
±
0.35
0.25
±
TBD LSB (max)
±
TBD LSB (max)
−TBD
TBD
±
45 mV
±
TBD mV (max)
±
TBD mV (max)
±
20
-18
±
0.5 dBFS
±
1.0 dBFS
±
15 %FS
(Limits)
LSB (min)
LSB (max)
Error/Bit
Units
A
A
P-P
www.national.com7
Converter Electrical Characteristics (Continued)
[Note: This product is currently in development. As such, the parameters specified in this section are DESIGN TARGETS. The specifications in this section cannot be guaranteed until device characterization has taken place.]
The following specifications apply after calibration for V
ADC08D1000
860mV
Extended Control Mode, R
to T
T
MIN
= 10 pF, Differential, a.c. coupled Sinewave Input Clock, f
P-P,CL
. All other limits TA= 25˚C, unless otherwise noted. (Notes 6, 7)
MAX
= 3300Ω±0.1%, Analog Signal Source Impedance = 100Ω. Boldface limits apply for TA=
EXT
A=VDR
Symbol Parameter Conditions
STATIC CONVERTER CHARACTERISTICS
= 100 MHz, VIN= FSR − 0.5 dB 47 dB
f
SINAD
Signal-to-Noise Plus Distortion
Ratio
SNR Signal-to-Noise Ratio
THD Total Harmonic Distortion
2nd Harm Second Harmonic Distortion
3rd Harm Third Harmonic Distortion
SFDR Spurious-Free dynamic Range
IMD Intermodulation Distortion
Out of Range Output Code
(In addition to OR Output high)
IN
f
= 248 MHz, VIN= FSR − 0.5 dB 47 TBD dB (min)
IN
f
= 498 MHz, VIN= FSR − 0.5 dB 47 TBD dB (min)
IN
= 100 MHz, VIN= FSR − 0.5 dB 48 dB
f
IN
f
= 248 MHz, VIN= FSR − 0.5 dB 48 TBD dB (min)
IN
f
= 498 MHz, VIN= FSR − 0.5 dB 48 TBD dB (min)
IN
= 100 MHz, VIN= FSR − 0.5 dB -57 dB
f
IN
f
= 248 MHz, VIN= FSR − 0.5 dB -57 dB (max)
IN
f
= 498 MHz, VIN= FSR − 0.5 dB -57 dB (max)
IN
= 100 MHz, VIN= FSR − 0.5 dB −64 dB
f
IN
f
= 248 MHz, VIN= FSR − 0.5 dB −64 dB
IN
f
= 498 MHz, VIN= FSR − 0.5 dB −64 dB
IN
= 100 MHz, VIN= FSR − 0.5 dB −64 dB
f
IN
f
= 248 MHz, VIN= FSR − 0.5 dB −64 dB
IN
f
= 498 MHz, VIN= FSR − 0.5 dB −64 dB
IN
= 100 MHz, VIN= FSR − 0.5 dB 58.5 dB
f
IN
f
= 248 MHz, VIN= FSR − 0.5 dB 58.5 TBD dB (min)
IN
f
= 498 MHz, VIN= FSR − 0.5 dB 58.5 TBD dB (min)
IN
f
= 121 MHz, VIN=FSR−7dB
IN1
= 126 MHz, VIN=FSR−7dB
f
IN2
(V
+)−(VIN−)>+ Full Scale 255
IN
(V
+)−(VIN−)<− Full Scale 0
IN
ANALOG INPUT AND REFERENCE CHARACTERISTICS
V
IN
V
CMI
Full Scale Analog Differential Input
Range
Analog Input Common Mode
Voltage
Analog Input Capacitance, normal
C
IN
operation (Note 10)
Analog Input Capacitance, DES
Mode (Note 10)
R
IN
Differential Input Resistance 100
FSR pin 14 Low 650
FSR pin 14 High 860
Differential 0.02 pF
Each input pin to ground 1.6 pF
Differential 0.8 pF
Each input pin to ground 2.2 pF
ANALOG OUTPUT CHARACTERISTICS
V
CMO
TC V
C
LOAD
V
CMO
Common Mode Output Voltage 1.25
Common Mode Output Voltage
CMO
Temperature Coefficient
= −40˚C to +85˚C 118 ppm/˚C
T
A
Maximum VCMO load Capacitance 80 pF
= +1.9VDC, OutV = 1.9V, VINFSR (a.c. coupled) = differential
= 1 GHz at 0.5V
CLK
Typical
(Note 8)
with 50% duty cycle, Non-
P-P
Limits
(Note 8)
-51 dB
600 mV
700 mV
810 mV
910 mV
V
−50
V
CMO
CMO
+50
V
CMO
94 Ω (min)
106 Ω (max)
0.95
1.45
Units
(Limits)
(min)
P-P
(max)
P-P
(min)
P-P
(max)
P-P
mV (min)
mV (max)
V (min)
V (max)
www.national.com 8
Converter Electrical Characteristics (Continued)
[Note: This product is currently in development. As such, the parameters specified in this section are DESIGN TARGETS. The specifications in this section cannot be guaranteed until device characterization has taken place.]
The following specifications apply after calibration for V
860mV
Extended Control Mode, R
to T
T
MIN
= 10 pF, Differential, a.c. coupled Sinewave Input Clock, f
P-P,CL
. All other limits TA= 25˚C, unless otherwise noted. (Notes 6, 7)
MAX
= 3300Ω±0.1%, Analog Signal Source Impedance = 100Ω. Boldface limits apply for TA=
EXT
A=VDR
Symbol Parameter Conditions
ANALOG OUTPUT CHARACTERISTICS
V
BG
TC V
C
LOAD
V
BG
Bandgap Reference Output
Voltage
Bandgap Reference Voltage
BG
Temperature Coefficient
Maximum Bandgap Reference load
Capacitance
=±100 µA 1.26
I
BG
TA= −40˚C to +85˚C,
=±100 µA
I
BG
TEMPERATURE DIODE CHARACTERISTICS
∆I
, 100 µA vs. 10 µA,
DIODE
= 25˚C
T
Temperature Diode Voltage
J
∆I
, 100 µA vs. 10 µA,
DIODE
= 85˚C
T
J
CHANNEL-TO-CHANNEL CHARACTERISTICS
Offset Match 2 TBD LSB (max)
Positive Full-Scale Match
Negative Full-Scale Match
X-TALK Crosstalk from I to Q Channel
X-TALK Crosstalk from Q to I Channel
Zero offset selected in Control
Register
Zero offset selected in Control
Register
Aggressor =867 MHz F.S.
Victim = 100 MHz F.S.
Aggressor =867 MHz F.S.
Victim = 100 MHz F.S.
CLOCK INPUT CHARACTERISTICS
Sine Wave Clock 0.6
V
ID
Differential Clock Input Level
Square Wave Clock 0.6
I
I
C
IN
Input Current VIN=0orVIN=V
Input Capacitance (Note 11)
Differential 0.02 pF
Each input to ground 1.5 pF
DIGITAL CONTROL PIN CHARACTERISTICS
V
IH
V
IL
I
I
C
IN
Logic High Input Voltage (Note 12) 1.4 V (min)
Logic Low Input Voltage (Note 12) 0.5 V (max)
=0orVIN=VA, Pins 4, 14, 127
V
Input Current
IN
V
=0orVIN=VA, All Other Pins
IN
Input Capacitance (Note 11) Each input to ground 1.2 pF
DIGITAL OUTPUT CHARACTERISTICS
OutV = V
V
OD
LVDS Differential Output Voltage
OutV = GND, measured
differentially
∆ V
V
O DIFF
OS
Change in LVDS Output Swing
Between Logic Levels
Output Offset Voltage 800 mV
= +1.9VDC, OutV = 1.9V, VINFSR (a.c. coupled) = differential
= 1 GHz at 0.5V
CLK
Typical
(Note 8)
with 50% duty cycle, Non-
P-P
Limits
(Note 8)
1.22
1.33
28 ppm/˚C
80 pF
TBD mV
TBD mV
6 TBD mV (max)
6 TBD mV (max)
-77 dB
-77 dB
0.4
2.0
0.4
2.0
±
A
, measured differentially 600
A
1µA
±
80 µA
±
1µA
400 mV
900 mV
450
±
1mV
280 mV
680 mV
Units
(Limits)
V (min)
V (max)
V
P-P
V
P-P
V
P-P
V
P-P
P-P
P-P
P-P
P-P
ADC08D1000
(min)
(max)
(min)
(max)
(min)
(max)
(min)
(max)
www.national.com9
Converter Electrical Characteristics (Continued)
[Note: This product is currently in development. As such, the parameters specified in this section are DESIGN TARGETS. The specifications in this section cannot be guaranteed until device characterization has taken place.]
The following specifications apply after calibration for V
ADC08D1000
860mV
Extended Control Mode, R
to T
T
MIN
= 10 pF, Differential, a.c. coupled Sinewave Input Clock, f
P-P,CL
. All other limits TA= 25˚C, unless otherwise noted. (Notes 6, 7)
MAX
= 3300Ω±0.1%, Analog Signal Source Impedance = 100Ω. Boldface limits apply for TA=
EXT
A=VDR
Symbol Parameter Conditions
DIGITAL OUTPUT CHARACTERISTICS
∆ V
I
OS
Z
OS
O
Output Offset Voltage Change
Between Logic Levels
Output Short Circuit Current
Output+ & Output- connected to
0.8V
Differential Output Impedance 100 Ohms
POWER SUPPLY CHARACTERISTICS
PD = PDQ = Low
I
A
Analog Supply Current
PD = Low, PDQ = High
PD = High
PD = PDQ = Low
I
DR
Output Driver Supply Current
PD = Low, PDQ = High
PD = PDQ = High
PD = PDQ = Low
P
D
Power Consumption
PD = Low, PDQ = High
PD = PDQ = High
PSRR1 D.C. Power Supply Rejection Ratio
Change in Full Scale Error with
change in V
PSRR2 A.C. Power Supply Rejection Ratio 248 MHz, 50mV
AC ELECTRICAL CHARACTERISTICS
≤ 85˚C 1.1 1.0 GHz (min)
T
f
CLK1
f
CLK2
t
CL
t
CH
Maximum Conversion Rate
Minimum Conversion Rate 200 MHz
Input Clock Duty Cycle
Input Clock Duty Cycle
Input Clock Low Time (Note 12) 500 200 ps (min)
Input Clock High Time (Note 12) 500 200 ps (min)
A
T
≤ 75˚C 1.3 GHz
A
200 MHz ≤ Input clock frequency ≤
1 GHz (Normal Mode)
500MHz ≤ Input clock frequency ≤ 1
GHz (DES Mode)
DCLK Duty Cycle (Note 12) 50
t
RS
t
RH
t
SD
t
RPW
t
LHT
t
HLT
Reset Setup Time (Note 12) 150 TBD ps (min)
Reset Hold Time (Note 12) 250 TBD ps (min)
Syncronizing Edge to DCLK Output
Delay
f
CLKIN
f
CLKIN
= 1.0 GHz
= 200 MHz
Reset Pulse Width 4
Differential Low to High Transition
Time
Differential High to Low Transition
Time
10% to 90%, C
10% to 90%, C
50% of DCLK transition to 50% of
t
OSK
DCLK to Data Output Skew
Data transition, SDR Mode
and DDR Mode, 0˚ DCLK (Note 12)
t
SU
Data to DCLK Set-Up Time DDR Mode, 180˚ DCLK (Note 12) 750 TBD ps (min)
= +1.9VDC, OutV = 1.9V, VINFSR (a.c. coupled) = differential
= 1 GHz at 0.5V
CLK
Typical
(Note 8)
with 50% duty cycle, Non-
P-P
Limits
(Note 8)
±
1mV
±
4mA
627
325
690
360
4.3
202
116
257
135
1
1.6
0.84
1.8
0.94
20
from 1.8V to 2.0V
A
riding on V
P-P
A
73 dB
TBD dB
50
50
20
80
20
80
45
55
3.53
3.85
= 2.5 pF 250 ps
L
= 2.5 pF 250 ps
L
±
50
±
200 ps (max)
Units
(Limits)
mA (max)
mA
mA
mA (max)
mA (max)
mA
W (max)
W
mW
% (min)
% (max)
% (min)
% (max)
% (min)
% (max)
ns
Clock Cycles
(min)
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