Rainbow Electronics ADC0838 User Manual

January 1995

ADC0831/ADC0832/ADC0834 and ADC0838 8-Bit Serial I/O A/D Converters with Multiplexer Options

ADC0831/ADC0832/ADC0834 and ADC0838

8-Bit Serial I/O A/D Converters with Multiplexer Options

General Description

The ADC0831 series are 8-bit successive approximation A/D converters with a serial I/O and configurable input multiplexers with up to 8 channels. The serial I/O is configured to comply with the NSC MICROWIRE change standard for easy interface to the COPS

serial data ex-

family of processors, and can interface with standard shift registers or mPs.

The 2-, 4- or 8-channel multiplexers are software configured for single-ended or differential inputs as well as channel assignment.

The differential analog voltage input allows increasing the common-mode rejection and offsetting the analog zero input voltage value. In addition, the voltage reference input can be adjusted to allow encoding any smaller analog voltage span to the full 8 bits of resolution.

Features

NSC MICROWIRE compatibleÐdirect interface to COPS family processors

Easy interface to all microprocessors, or operates ‘‘stand-alone’’

Typical Application

Operates ratiometrically or with 5 VDCvoltage reference

No zero or full-scale adjust required

2-, 4- or 8-channel multiplexer options with address logic

Shunt regulator allows operation with high voltage supplies

0V to 5V input range with single 5V power supply

Remote operation with serial digital data link

TTL/MOS input/output compatible

0.3×standard width, 8-, 14- or 20-pin DIP package

20 Pin Molded Chip Carrier Package (ADC0838 only)

Surface-Mount Package

Key Specifications

Resolution 8 Bits

Total Unadjusted Error

Single Supply 5 V

Low Power 15 mW

Conversion Time 32 ms

(/2 LSB andg1 LSB

TL/H/5583– 1

TRI-STATEÉis a registered trademark of National Semiconductor Corporation.

COPS

and MICROWIRETMare trademarks of National Semiconductor Corporation.

1995 National Semiconductor Corporation RRD-B30M115/Printed in U. S. A.

TL/H/5583

Absolute Maximum Ratings (Notes1&2)

If Military/Aerospace specified devices are required, please contact the National Semiconductor Sales Office/Distributors for availability and specifications.

Current into V

Supply Voltage, VCC(Note 3) 6.5V

Voltage

Logic Inputs Analog Inputs

Input Current per Pin (Note 4)

Storage Temperature

Package Dissipation

at T

(Note 3) 15 mA

0.3V to V

CC CC

Package

65§Ctoa150§C

25§C (Board Mount) 0.8W

a a

20 mA

0.3V

5mA

Lead Temperature (Soldering 10 sec.)

Dual-In-Line Package (Plastic) 260 Dual-In-Line Package (Ceramic) 300 Molded Chip Carrier Package

Vapor Phase (60 sec.) 215 Infrared (15 sec.) 220

ESD Susceptibility (Note 5) 2000V

Operating Ratings (Notes1&2)

Supply Voltage, V

Temperature Range T

ADC0831/8BCJ, ADC0831/4/8CCJ, ADC0832BIWM, ADC0831/2/4/8CIWM ADC0831/2//4/8BCN, ADC0838BCV, ADC0831/2/4/8CCN, ADC0838CCV, ADC0831/2/4/8CCWM 0

4.5 VDCto 6.3 V

MIN

40§Ctoa85§C

Ctoa70§C

MAX

Converter and Multiplexer Electrical Characteristics

The following specifications apply for V unless otherwise specified. Boldface limits apply from T

eVae

5V, V

REF

MIN

BCJ, BIWM, BCV, CCV, CCWM, BCN

CIWM and CCJ Devices and CCN Devices

Parameter Conditions

Typ

(Note 12)

Tested Design

Limit Limit

(Note 13) (Note 14) (Note 13) (Note 14)

CONVERTER AND MULTIPLEXER CHARACTERISTICS

Total Unadjusted Error V

ADC0838BCV (Note 6)

REF

5.00 V

ADC0831/2/4/8BCN ADC0831/8BCJ ADC0832BIWM

g g

ADC0838CCV ADC0831/2/4/8CCN ADC0831/2/4/8CCWM ADC0831/4/8CCJ ADC0831/2/4/8CIWM

g g

Minimum Reference 3.5 1.3 3.5 1.3 1.3 kX Input Resistance (Note 7)

Maximum Reference 3.5 5.9 3.5 5.4 5.9 kX Input Resistance (Note 7)

Maximum Common-Mode Input V Range (Note 8)

Minimum Common-Mode Input GNDb0.05 GNDb0.05 GNDb0.05 V Range (Note 8)

DC Common-Mode Error

(/16

to T

REF

MAX

0.1V, T

Typ

(Note 12)

(/2 (/2

1 1

0.05 V

(/4

(/16

25§C, and f

Tested Design

Limit Limit

(/2

0.05 V

(/4

CLK

(/2

(/2 LSB

0.05 V

(/4 LSB

250 kHz

Units

Converter and Multiplexer Electrical Characteristics (Continued)

The following specifications apply for V

Boldface limits apply from T

MIN

to T

eVae

MAX

Parameter Conditions

(Note 12)

CONVERTER AND MULTIPLEXER CHARACTERISTICS (Continued)

Change in zero 15 mA into V error from V to internal zener V operation (Note 3) 1 1 1 LSB

5V V

REF

VZ, internal MIN 15 mA into V

N.C.

diode breakdown MAX 8.5 8.5 8.5 V (at V

) (Note 3)

Power Supply Sensitivity V

, Off Channel Leakage On Channele5V,

OFF

Current (Note 9) Off Channel

5Vg5%

On Channele0V, Off Channel

ION, On Channel Leakage On Channele0V, Current (Note 9) Off Channele5V

On Channele5V, Off Channel

DIGITAL AND DC CHARACTERISTICS

, Logical ‘‘1’’ Input V

IN(1)

Voltage (Min)

, Logical ‘‘0’’ Input V

IN(0)

Voltage (Max)

, Logical ‘‘1’’ Input V

IN(1)

Current (Max)

, Logical ‘‘0’’ Input V

IN(0)

Current (Max)

, Logical ‘‘1’’ Output V

OUT(1)

Voltage (Min) I

, Logical ‘‘0’’ Output V

OUT(0)

Voltage (Max) I

, TRI-STATE Output V

OUT

Current (Max) V

, Output Source V

SOURCE

Current (Min)

, Output Sink Current (Min) V

SINK

5.25V 2.0 2.0 2.0 V

4.75V 0.8 0.8 0.8 V

5.0V 0.005 1 0.005 1 1 mA

4.75V

360 mA 2.4 2.4 2.4 V

OUT

10 mA 4.5 4.5 4.5 V

OUT

4.75V 0.4 0.4 0.4 V

1.6 mA

OUT

5V 0.1 3 0.1

OUT

ICC, Supply Current (Max)

ADC0831, ADC0834, 0.9 2.5 0.9 2.5 2.5 mA ADC0838

ADC0832 Includes Ladder 2.3 6.5 2.3 6.5 6.5 mA

Current

5V, T

25§C, and f

250 kHz unless otherwise specified.

CLK

BCJ, BIWM, BCV, CCV, CCWM, BCN

CIWM and CCJ Devices and CCN Devices

Typ

Tested Design

Limit Limit

(Note 13) (Note 14) (Note 13) (Note 14)

Typ

(Note 12)

Tested Design

Limit Limit

6.3 6.3 6.3

(/16

0.005

0.1

(/4

0.2

6.5

(/4

(/16

(/4

0.2

(/4 LSB

1 mA

0.2

1 mA

0.2

1 mA

0.2

1 mA

0.005

0.1

b a

7.5

3 3

1 mA

3 mA

6.5 mA

16 8.0 16 9.0 8.0 mA

Units

AC Characteristics

The following specifications apply for V

Parameter Conditions

, Clock Frequency

CLK

Min 10 kHz Max 400 kHz

5V, t

20 ns and 25§C unless otherwise specified.

(Note 12)

Typ

Tested Design

Limit Limit

(Note 13) (Note 14)

Limit Units

tC, Conversion Time Not including MUX Addressing Time 8 1/f

Clock Duty Cycle Min 40 % (Note 10) Max 60 %

,CSFalling Edge or 250 ns

SET-UP

Data Input Valid to CLK Rising Edge

, Data Input Valid 90 ns

HOLD

after CLK Rising Edge

ÐCLK Falling C

pd1,tpd0

Edge to Output Data Valid Data MSB First 650 1500 ns

100 pF

(Note 11) Data LSB First 250 600 ns

t1H,t0H,ÐRising Edge of C CS to Data Output and (see TRI-STATE SARS Hi–Z

10 pF, R

100 pf, R

10k 125 250 ns

Test Circuits)

2k 500 ns

CIN, Capacitance of Logic 5 pF Input

, Capacitance of Logic 5 pF

OUT

Outputs

Note 1: Absolute Maximum Ratings indicate limits beyond which damage to the device may occur. DC and AC electrical specifications do not apply when operating the device beyond its specified operating conditions.

Note 2: All voltages are measured with respect to the ground plugs.

Note 3: Internal zener diodes (6.3 to 8.5V) are connected from V

via a conventional diode. Since the zener voltage equals the A/D’s breakdown voltage, the diode insures that VCCwill be below breakdown when the device

to V

is powered from V

6.5V. It is recommended that a resistor be used to limit the max current into V

Note 4: When the input voltage (V to 5 mA or less. The 20 mA package input current limits the number of pins that can exceed the power supply boundaries witha5mAcurrent limit to four.

Note 5: Human body model, 100 pF discharged through a 1.5 kX resistor.

Note 6: Total unadjusted error includes offset, full-scale, linearity, and multiplexer errors.

Note 7: Cannot be tested for ADC0832.

Note 8: For V

conduct for analog input voltages one diode drop below ground or one diode drop greater then the V as high level analog inputs (5V) can cause this input diode to conductÐespecially at elevated temperatures, and cause errors for analog inputs near full-scale. The spec allows 50 mV forward bias of either diode. This means that as long as the analog V output code will be correct. To achieve an absolute 0 V temperature variations, initial tolerance and loading.

Note 9: Leakage current is measured with the clock not switching.

Note 10: A 40% to 60% clock duty cycle range insures proper operation at all clock frequencies. In the case that an available clock has a duty cycle outside of

these limits, the minimum, time the clock is high or the minimum time the clock is low must be at least 1 ms. The maximum time the clock can be high is 60 ms. The clock can be stopped when low so long as the analog input voltage remains stable.

Note 11: Since data, MSB first, is the output of the comparator used in the successive approximation loop, an additional delay is built in (see Block Diagram) to allow for comparator response time.

Note 12: Typicals are at 25

Note 13: Tested limits are guaranteed to National’s AOQL (Average Outgoing Quality Level).

Note 14: Guaranteed but not 100% production tested. These limits are not used to calculate outgoing quality levels.

. Functionality is therefore guaranteed for Vaoperation even though the resultant voltage at VCCmay exceed the specified Absolute Max of

) at any pin exceeds the power supply rails (V

(b)tVIN(a) the digital output code will be 0000 0000. Two on-chip diodes are tied to each analog input (see Block Diagram) which will forward

C and represent most likely parametric norm.

to GND and V

to5VDCinput voltage range will therefore require a minimum supply voltage of 4.950 VDCover

to GND. The zener at Vacan operate as a shunt regulator and is connected

. (See

Figure 3

in Functional Description Section 6.0)

Vbor V

Va) the absolute value of current at that pin should be limited

supply. Be careful, during testing at low VCClevels (4.5V),

or V

does not exceed the supply voltage by more than 50 mV, the

REF

CLK

Typical Performance Characteristics

Unadjusted Offset Error vs V

Voltage

REF

Linearity Error vs f

CLK

Power Supply Current vs f

CLK

Linearity Error vs V Voltage

REF

Power Supply Current vs Temperature (ADC0838, ADC0831, ADC0834)

Note: For ADC0832 add I

REF

Leakage Current Test Circuit

Linearity Error vs Temperature

TL/H/5583– 2

Output Current vs Temperature

. TL/H/5583 –40

TL/H/5583– 29

TL/H/5583– 3

TRI-STATE Test Circuits and Waveforms

Timing Diagrams

Data Input Timing

TL/H/5583– 4

TL/H/5583– 23

Data Output Timing

TL/H/5583– 24

ADC0831 Start Conversion Timing

TL/H/5583– 25

TL/H/5583– 26

Timing Diagrams (Continued)

ADC0831 Timing

*LSB first output not available on ADC0831.

ADC0832 Timing

ADC0834 Timing

TL/H/5583– 27

TL/H/5583– 28

TL/H/5583– 5

Timing Diagrams (Continued)

TL/H/5583– 6

ADC0838 Timing

18 clocks in the LSB before SE is taken low

* Make sure clock edge

ADC0838 Functional Block Diagram

TL/H/5583– 7

*Some of these functions/pins are not available with other options.

Note 1: For the ADC0834, D1 is input directly to the D input of SELECT 1. SELECT 0 is forced to a ‘‘1’’. For the ADC0832, DI is input directly to the DI input of ODD/SIGN. SELECT 0 is forced to a ‘‘0’’ and SELECT 1 is forced to a ‘‘1’’.

Connection Diagrams

ADC0838 8-Channel MUX

Small Outline/Dual-In-Line Package (J, M and N)

Top View

ADC0832 2-Channel MUX

Dual-In-Line Package (J and N)

Top View

TL/H/5583– 31

COM internally connected to GND.

internally connected to VCC.

REF

Small Outline/Dual-In-Line Package (J, M, and N)

TL/H/5583– 8

ADC0832 2-Channel MUX

Small Outline Package (M)

TL/H/5583– 41

Top View

ADC0834 4-Channel MUX

TL/H/5583– 30

Top View

COM internally connected to A GND

ADC0831 Single

Differential Input

Dual-In-Line Package (J and N)

TL/H/5583– 32

Top View

ADC0831 Single Differential Input

Small Outline Package (M)

Top View

ADC0838 8-Channel MUX

Molded Chip Carrier (PCC) Package (V)

TL/H/5583– 42

TL/H/5583– 33

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