January 1995
ADC0831/ADC0832/ADC0834 and ADC0838
8-Bit Serial I/O A/D Converters with Multiplexer Options
ADC0831/ADC0832/ADC0834 and ADC0838
8-Bit Serial I/O A/D Converters with Multiplexer Options
General Description
The ADC0831 series are 8-bit successive approximation
A/D converters with a serial I/O and configurable input multiplexers with up to 8 channels. The serial I/O is configured
to comply with the NSC MICROWIRE
change standard for easy interface to the COPS
TM
serial data ex-
TM
family of
processors, and can interface with standard shift registers
or mPs.
The 2-, 4- or 8-channel multiplexers are software configured
for single-ended or differential inputs as well as channel assignment.
The differential analog voltage input allows increasing the
common-mode rejection and offsetting the analog zero input voltage value. In addition, the voltage reference input
can be adjusted to allow encoding any smaller analog voltage span to the full 8 bits of resolution.
Features
Y
NSC MICROWIRE compatibleÐdirect interface to
COPS family processors
Y
Easy interface to all microprocessors, or operates
‘‘stand-alone’’
Typical Application
Y
Operates ratiometrically or with 5 VDCvoltage
reference
Y
No zero or full-scale adjust required
Y
2-, 4- or 8-channel multiplexer options with address
logic
Y
Shunt regulator allows operation with high voltage
supplies
Y
0V to 5V input range with single 5V power supply
Y
Remote operation with serial digital data link
Y
TTL/MOS input/output compatible
Y
0.3×standard width, 8-, 14- or 20-pin DIP package
Y
20 Pin Molded Chip Carrier Package (ADC0838 only)
Y
Surface-Mount Package
Key Specifications
Y
Resolution 8 Bits
Y
Total Unadjusted Error
Y
Single Supply 5 V
Y
Low Power 15 mW
Y
Conversion Time 32 ms
g
(/2 LSB andg1 LSB
DC
TL/H/5583– 1
TRI-STATEÉis a registered trademark of National Semiconductor Corporation.
TM
COPS
and MICROWIRETMare trademarks of National Semiconductor Corporation.
C
1995 National Semiconductor Corporation RRD-B30M115/Printed in U. S. A.
TL/H/5583
Absolute Maximum Ratings (Notes1&2)
If Military/Aerospace specified devices are required,
please contact the National Semiconductor Sales
Office/Distributors for availability and specifications.
Current into V
Supply Voltage, VCC(Note 3) 6.5V
Voltage
Logic Inputs
Analog Inputs
Input Current per Pin (Note 4)
Storage Temperature
Package Dissipation
at T
a
(Note 3) 15 mA
b
0.3V to V
0.3V to V
CC
CC
b
Package
b
65§Ctoa150§C
e
25§C (Board Mount) 0.8W
A
a
a
g
g
20 mA
0.3V
0.3V
5mA
Lead Temperature (Soldering 10 sec.)
Dual-In-Line Package (Plastic) 260
Dual-In-Line Package (Ceramic) 300
Molded Chip Carrier Package
Vapor Phase (60 sec.) 215
Infrared (15 sec.) 220
ESD Susceptibility (Note 5) 2000V
Operating Ratings (Notes1&2)
Supply Voltage, V
CC
Temperature Range T
ADC0831/8BCJ,
ADC0831/4/8CCJ,
ADC0832BIWM,
ADC0831/2/4/8CIWM
ADC0831/2//4/8BCN,
ADC0838BCV,
ADC0831/2/4/8CCN,
ADC0838CCV,
ADC0831/2/4/8CCWM 0
4.5 VDCto 6.3 V
s
s
T
MIN
b
T
A
40§Ctoa85§C
Ctoa70§C
§
DC
MAX
C
§
C
§
C
§
C
§
Converter and Multiplexer Electrical Characteristics
The following specifications apply for V
unless otherwise specified. Boldface limits apply from T
eVae
CC
e
V
5V, V
REF
MIN
BCJ, BIWM, BCV, CCV, CCWM, BCN
CIWM and CCJ Devices and CCN Devices
Parameter Conditions
Typ
(Note 12)
Tested Design
Limit Limit
(Note 13) (Note 14) (Note 13) (Note 14)
CONVERTER AND MULTIPLEXER CHARACTERISTICS
Total Unadjusted Error V
ADC0838BCV (Note 6)
REF
e
5.00 V
ADC0831/2/4/8BCN
ADC0831/8BCJ
ADC0832BIWM
g
g
ADC0838CCV
ADC0831/2/4/8CCN
ADC0831/2/4/8CCWM
ADC0831/4/8CCJ
ADC0831/2/4/8CIWM
g
g
Minimum Reference 3.5 1.3 3.5 1.3 1.3 kX
Input Resistance (Note 7)
Maximum Reference 3.5 5.9 3.5 5.4 5.9 kX
Input Resistance (Note 7)
Maximum Common-Mode Input V
Range (Note 8)
CC
Minimum Common-Mode Input GNDb0.05 GNDb0.05 GNDb0.05 V
Range (Note 8)
DC Common-Mode Error
g
(/16
g
s
a
V
to T
REF
MAX
.
CC
0.1V, T
A
Typ
(Note 12)
(/2
(/2
1
1
a
0.05 V
(/4
g
(/16
e
e
T
25§C, and f
j
Tested Design
Limit Limit
g
(/2
g
(/2
g
1
g
1
g
1
a
0.05 V
CC
g
(/4
e
CLK
g
(/2
g
(/2 LSB
g
1
g
1
g
1
a
0.05 V
CC
g
(/4 LSB
250 kHz
Units
2
Converter and Multiplexer Electrical Characteristics (Continued)
The following specifications apply for V
Boldface limits apply from T
MIN
to T
eVae
CC
.
MAX
Parameter Conditions
(Note 12)
CONVERTER AND MULTIPLEXER CHARACTERISTICS (Continued)
Change in zero 15 mA into V
error from V
to internal zener V
operation (Note 3) 1 1 1 LSB
e
5V V
CC
CC
REF
VZ, internal MIN 15 mA into V
a
e
N.C.
e
5V
a
diode breakdown MAX 8.5 8.5 8.5 V
(at V
) (Note 3)
a
Power Supply Sensitivity V
I
, Off Channel Leakage On Channele5V,
OFF
Current (Note 9) Off Channel
CC
e
5Vg5%
e
0V
On Channele0V,
Off Channel
e
5V
ION, On Channel Leakage On Channele0V,
Current (Note 9) Off Channele5V
On Channele5V,
Off Channel
e
0V
DIGITAL AND DC CHARACTERISTICS
V
, Logical ‘‘1’’ Input V
IN(1)
Voltage (Min)
V
, Logical ‘‘0’’ Input V
IN(0)
Voltage (Max)
I
, Logical ‘‘1’’ Input V
IN(1)
Current (Max)
I
, Logical ‘‘0’’ Input V
IN(0)
Current (Max)
V
, Logical ‘‘1’’ Output V
OUT(1)
Voltage (Min) I
V
, Logical ‘‘0’’ Output V
OUT(0)
Voltage (Max) I
I
, TRI-STATE Output V
OUT
Current (Max) V
I
, Output Source V
SOURCE
Current (Min)
I
, Output Sink Current (Min) V
SINK
e
5.25V 2.0 2.0 2.0 V
CC
e
4.75V 0.8 0.8 0.8 V
CC
e
5.0V 0.005 1 0.005 1 1 mA
IN
e
0V
IN
e
4.75V
CC
eb
360 mA 2.4 2.4 2.4 V
OUT
eb
I
10 mA 4.5 4.5 4.5 V
OUT
e
4.75V 0.4 0.4 0.4 V
CC
e
1.6 mA
OUT
e
0V
OUT
e
5V 0.1 3 0.1
OUT
e
0V
OUT
e
V
OUT
CC
ICC, Supply Current (Max)
ADC0831, ADC0834, 0.9 2.5 0.9 2.5 2.5 mA
ADC0838
ADC0832 Includes Ladder 2.3 6.5 2.3 6.5 6.5 mA
Current
e
5V, T
e
T
A
25§C, and f
j
e
250 kHz unless otherwise specified.
CLK
BCJ, BIWM, BCV, CCV, CCWM, BCN
CIWM and CCJ Devices and CCN Devices
Typ
Tested Design
Limit Limit
(Note 13) (Note 14) (Note 13) (Note 14)
Typ
(Note 12)
Tested Design
Limit Limit
6.3 6.3 6.3
b
g
(/16
0.005
b
0.1
b
14
g
(/4
b
0.2
b
a
0.2
a
b
0.2
b
a
0.2
a
b
b
b
6.5
g
g
(/4
(/16
g
(/4
b
0.2
g
(/4 LSB
b
1 mA
1
a
0.2
a
1 mA
1
b
0.2
b
1 mA
1
a
0.2
a
1 mA
1
1
3
b
0.005
b
b
0.1
14
b
b
a
b
7.5
b
1
3
3
1 mA
b
3 mA
a
3 mA
b
6.5 mA
16 8.0 16 9.0 8.0 mA
Units
3
AC Characteristics
The following specifications apply for V
Parameter Conditions
f
, Clock Frequency
CLK
Min 10 kHz
Max 400 kHz
CC
e
e
5V, t
e
t
20 ns and 25§C unless otherwise specified.
r
f
(Note 12)
Typ
Tested Design
Limit Limit
(Note 13) (Note 14)
Limit
Units
tC, Conversion Time Not including MUX Addressing Time 8 1/f
Clock Duty Cycle Min 40 %
(Note 10) Max 60 %
t
,CSFalling Edge or 250 ns
SET-UP
Data Input Valid to CLK
Rising Edge
t
, Data Input Valid 90 ns
HOLD
after CLK Rising Edge
t
ÐCLK Falling C
pd1,tpd0
Edge to Output Data Valid Data MSB First 650 1500 ns
L
e
100 pF
(Note 11) Data LSB First 250 600 ns
t1H,t0H,ÐRising Edge of C
CS to Data Output and (see TRI-STATE
SARS Hi–Z
L
C
L
e
10 pF, R
e
100 pf, R
e
10k 125 250 ns
L
Test Circuits)
É
e
2k 500 ns
L
CIN, Capacitance of Logic 5 pF
Input
C
, Capacitance of Logic 5 pF
OUT
Outputs
Note 1: Absolute Maximum Ratings indicate limits beyond which damage to the device may occur. DC and AC electrical specifications do not apply when operating
the device beyond its specified operating conditions.
Note 2: All voltages are measured with respect to the ground plugs.
Note 3: Internal zener diodes (6.3 to 8.5V) are connected from V
via a conventional diode. Since the zener voltage equals the A/D’s breakdown voltage, the diode insures that VCCwill be below breakdown when the device
to V
CC
is powered from V
6.5V. It is recommended that a resistor be used to limit the max current into V
Note 4: When the input voltage (V
to 5 mA or less. The 20 mA package input current limits the number of pins that can exceed the power supply boundaries witha5mAcurrent limit to four.
Note 5: Human body model, 100 pF discharged through a 1.5 kX resistor.
Note 6: Total unadjusted error includes offset, full-scale, linearity, and multiplexer errors.
Note 7: Cannot be tested for ADC0832.
Note 8: For V
conduct for analog input voltages one diode drop below ground or one diode drop greater then the V
as high level analog inputs (5V) can cause this input diode to conductÐespecially at elevated temperatures, and cause errors for analog inputs near full-scale. The
spec allows 50 mV forward bias of either diode. This means that as long as the analog V
output code will be correct. To achieve an absolute 0 V
temperature variations, initial tolerance and loading.
Note 9: Leakage current is measured with the clock not switching.
Note 10: A 40% to 60% clock duty cycle range insures proper operation at all clock frequencies. In the case that an available clock has a duty cycle outside of
these limits, the minimum, time the clock is high or the minimum time the clock is low must be at least 1 ms. The maximum time the clock can be high is 60 ms. The
clock can be stopped when low so long as the analog input voltage remains stable.
Note 11: Since data, MSB first, is the output of the comparator used in the successive approximation loop, an additional delay is built in (see Block Diagram) to
allow for comparator response time.
Note 12: Typicals are at 25
Note 13: Tested limits are guaranteed to National’s AOQL (Average Outgoing Quality Level).
Note 14: Guaranteed but not 100% production tested. These limits are not used to calculate outgoing quality levels.
a
. Functionality is therefore guaranteed for Vaoperation even though the resultant voltage at VCCmay exceed the specified Absolute Max of
) at any pin exceeds the power supply rails (V
IN
(b)tVIN(a) the digital output code will be 0000 0000. Two on-chip diodes are tied to each analog input (see Block Diagram) which will forward
IN
C and represent most likely parametric norm.
§
a
to GND and V
to5VDCinput voltage range will therefore require a minimum supply voltage of 4.950 VDCover
DC
to GND. The zener at Vacan operate as a shunt regulator and is connected
CC
a
. (See
Figure 3
k
IN
in Functional Description Section 6.0)
l
Vbor V
Va) the absolute value of current at that pin should be limited
IN
supply. Be careful, during testing at low VCClevels (4.5V),
CC
or V
does not exceed the supply voltage by more than 50 mV, the
IN
REF
CLK
4
Typical Performance Characteristics
Unadjusted Offset Error
vs V
Voltage
REF
Linearity Error vs f
CLK
Power Supply Current
vs f
CLK
Linearity Error vs V
Voltage
REF
Power Supply Current vs
Temperature (ADC0838,
ADC0831, ADC0834)
Note: For ADC0832 add I
REF
Leakage Current Test Circuit
Linearity Error vs
Temperature
TL/H/5583– 2
Output Current vs
Temperature
. TL/H/5583 –40
TL/H/5583– 29
TL/H/5583– 3
5
TRI-STATE Test Circuits and Waveforms
Timing Diagrams
Data Input Timing
t
1H
t
0H
TL/H/5583– 4
t
1H
t
0H
TL/H/5583– 23
Data Output Timing
TL/H/5583– 24
ADC0831 Start Conversion Timing
6
TL/H/5583– 25
TL/H/5583– 26
Timing Diagrams (Continued)
ADC0831 Timing
*LSB first output not available on ADC0831.
ADC0832 Timing
ADC0834 Timing
TL/H/5583– 27
TL/H/5583– 28
TL/H/5583– 5
7
Timing Diagrams (Continued)
TL/H/5583– 6
ADC0838 Timing
18 clocks in the LSB before SE is taken low
Ý
* Make sure clock edge
8
ADC0838 Functional Block Diagram
TL/H/5583– 7
*Some of these functions/pins are not available with other options.
Note 1: For the ADC0834, D1 is input directly to the D input of SELECT 1. SELECT 0 is forced to a ‘‘1’’. For the ADC0832, DI is input directly to the DI input of
ODD/SIGN. SELECT 0 is forced to a ‘‘0’’ and SELECT 1 is forced to a ‘‘1’’.
9
Connection Diagrams
ADC0838 8-Channel MUX
Small Outline/Dual-In-Line Package (J, M and N)
Top View
ADC0832 2-Channel MUX
Dual-In-Line Package (J and N)
Top View
TL/H/5583– 31
COM internally connected to GND.
V
internally connected to VCC.
REF
Small Outline/Dual-In-Line Package (J, M, and N)
TL/H/5583– 8
ADC0832 2-Channel MUX
Small Outline Package (M)
TL/H/5583– 41
Top View
ADC0834 4-Channel MUX
TL/H/5583– 30
Top View
COM internally connected to A GND
ADC0831 Single
Differential Input
Dual-In-Line Package (J and N)
TL/H/5583– 32
Top View
ADC0831 Single Differential Input
Small Outline Package (M)
Top View
ADC0838 8-Channel MUX
Molded Chip Carrier (PCC) Package (V)
TL/H/5583– 42
TL/H/5583– 33
10
Functional Description
1.0 MULTIPLEXER ADDRESSING
The design of these converters utilizes a sample-data comparator structure which provides for a differential analog input to be converted by a successive approximation routine.
The actual voltage converted is always the difference between an assigned ‘‘
minal. The polarity of each input terminal of the pair being
converted indicates which line the converter expects to be
the most positive. If the assigned ‘‘
b
‘‘
’’ input the converter responds with an all zeros output
code.
A unique input multiplexing scheme has been utilized to provide multiple analog channels with software-configurable
single-ended, differential, or a new pseudo-differential option which will convert the difference between the voltage at
any analog input and a common terminal. The analog signal
conditioning required in transducer-based data acquisition
systems is significantly simplified with this type of input flexibility. One converter package can now handle ground referenced inputs and true differential inputs as well as signals
with some arbitrary reference voltage.
A particular input configuration is assigned during the MUX
addressing sequence, prior to the start of a conversion. The
MUX address selects which of the analog inputs are to be
enabled and whether this input is single-ended or differen-
a
’’ input terminal and a ‘‘b’’ input ter-
a
’’ input is less than the
TABLE I. Multiplexer/Package Options
Part Number of Analog Channels Number of
Number
ADC0831 1 1 8
ADC0832 2 1 8
ADC0834 4 2 14
ADC0838 8 4 20
Single-Ended Differential
tial. In the differential case, it also assigns the polarity of the
channels. Differential inputs are restricted to adjacent channel pairs. For example channel 0 and channel 1 may be
selected as a different pair but channel 0 or 1 cannot act
differentially with any other channel. In addition to selecting
differential mode the sign may also be selected. Channel 0
may be selected as the positive input and channel 1 as the
negative input or vice versa. This programmability is best
illustrated by the MUX addressing codes shown in the following tables for the various product options.
The MUX address is shifted into the converter via the DI
line. Because the ADC0831 contains only one differential
input channel with a fixed polarity assignment, it does not
require addressing.
The common input line on the ADC0838 can be used as a
pseudo-differential input. In this mode, the voltage on this
pin is treated as the ‘‘
channels. This voltage does not have to be analog ground;
it can be any reference potential which is common to all of
the inputs. This feature is most useful in single-supply application where the analog circuitry may be biased up to a
potential other than ground and the output signals are all
referred to this potential.
b
’’ input for any of the other input
Package Pins
11
Functional Description (Continued)
Single-Ended MUX Mode
MUX Address Analog Single-Ended Channel
SGL/ ODD/ SELECT
DIF
SIGN 1 0
1000
1001
1010
1011
1100
1101
1110
1111
Differential MUX Mode
MUX Address Analog Differential Channel-Pair
SGL/ ODD/ SELECT 0123
DIF SIGN
0000
0001
0010
0011
0100
0101
0110
0111
TABLE II. MUX Addressing: ADC0838
1 0 01234567
Ý
01234567COM
ab
ab
ab
ab
ab
ab
ab
ab
Ý
ab
ab
ab
ab
ba
ba
ba
ba
Single-Ended MUX Mode
TABLE III. MUX Addressing: ADC0834
MUX Address Channel
SGL/ ODD/ SELECT
DIF SIGN
10 0
10 1
11 0
11 1
Differential MUX Mode
MUX Address Channel
SGL/ ODD/ SELECT
DIF SIGN
00 0
00 1
01 0
01 1
TABLE IV. MUX Addressing:
ADC0832
Ý
1
0123
a
a
a
a
COM is internally tied to A GND
Single-Ended MUX Mode
MUX Address Channel
SGL/ ODD/
DIF
SIGN
10
01
a
11
COM is internally tied to A GND
Ý
a
Differential MUX Mode
Ý
1
0123
ab
ab
ba
ba
MUX Address Channel
SGL/ ODD/
DIF
SIGN
00
01
ab
ba
Ý
01
12
Functional Description (Continued)
Since the input configuration is under software control, it
can be modified, as required, at each conversion. A channel
can be treated as a single-ended, ground referenced input
for one conversion; then it can be reconfigured as part of a
differential channel for another conversion.
trates the input flexibility which can be achieved.
The analog input voltages for each channel can range from
50 mV below ground to 50 mV above V
without degrading conversion accuracy.
2.0 THE DIGITAL INTERFACE
A most important characteristic of these converters is their
serial data link with the controlling processor. Using a serial
communication format offers two very significant system improvements; it allows more function to be included in the
converter package with no increase in package size and it
can eliminate the transmission of low level analog signals by
locating the converter right at the analog sensor; transmitting highly noise immune digital data back to the host processor.
Figure 1
(typically 5V)
CC
illus-
To understand the operation of these converters it is best to
refer to the Timing Diagrams and Functional Block Diagram
and to follow a complete conversion sequence. For clarity a
separate diagram is shown of each device.
1. A conversion is initiated by first pulling the CS
lect) line low. This line must be held low for the entire conversion. The converter is now waiting for a start bit and its
MUX assignment word.
2. A clock is then generated by the processor (if not provided continuously) and output to the A/D clock input.
3. On each rising edge of the clock the status of the data in
(DI) line is clocked into the MUX address shift register. The
start bit is the first logic ‘‘1’’ that appears on this line (all
leading zeros are ignored). Following the start bit the converter expects the next 2 to 4 bits to be the MUX assignment word.
(chip se-
8 Single-Ended
4 Differential
8 Pseudo-Differential
Mixed Mode
FIGURE 1. Analog Input Multiplexer Options for the ADC0838
13
TL/H/5583– 9
Functional Description (Continued)
4. When the start bit has been shifted into the start location
of the MUX register, the input channel has been assigned
and a conversion is about to begin. An interval of (/2 clock
period (where nothing happens) is automatically inserted to
allow the selected MUX channel to settle. The SAR status
line goes high at this time to signal that a conversion is now
in progress and the DI line is disabled (it no longer accepts
data).
5. The data out (DO) line now comes out of TRI-STATE and
provides a leading zero for this one clock period of MUX
settling time.
6. When the conversion begins, the output of the SAR comparator, which indicates whether the analog input is greater
than (high) or less than (low) each successive voltage from
the internal resistor ladder, appears at the DO line on each
falling edge of the clock. This data is the result of the conversion being shifted out (with the MSB coming first) and
can be read by the processor immediately.
7. After 8 clock periods the conversion is completed. The
SAR status line returns low to indicate this (/2 clock cycle
later.
8. If the programmer prefers, the data can be provided in an
LSB first format[this makes use of the shift enable (SE
control line]. All 8 bits of the result are stored in an output
shift register. On devices which do not include the SE
trol line, the data, LSB first, is automatically shifted out the
DO line, after the MSB first data stream. The DO line then
goes low and stays low until CS
ADC0838 the SE
line is brought out and if held high, the
is returned high. On the
value of the LSB remains valid on the DO line. When SE
forced low, the data is then clocked out LSB first. The
ADC0831 is an exception in that its data is only output in
MSB first format.
9. All internal registers are cleared when the CS
If another conversion is desired, CS
must make a high to
low transition followed by address information.
con-
line is high.
The DI and DO lines can be tied together and controlled
through a bidirectional processor I/O bit with one wire. This
is possible because the DI input is only ‘‘looked-at’’ during
the MUX addressing interval while the DO line is still in a
high impedance state.
3.0 REFERENCE CONSIDERATIONS
The voltage applied to the reference input to these converters defines the voltage span of the analog input (the difference between V
possible output codes apply. The devices can be used in
IN(MAX)
and V
) over which the 256
IN(MIN)
either ratiometric applications or in systems requiring absolute accuracy. The reference pin must be connected to a
voltage source capable of driving the reference input resistance of typically 3.5 kX. This pin is the top of a resistor
divider string used for the successive approximation conversion.
In a ratiometric system, the analog input voltage is proportional to the voltage used for the A/D reference. This voltage is typically the system power supply, so the V
can be tied to V
technique relaxes the stability requirements of the system
reference as the analog input and A/D reference move to-
)
gether maintaining the same output code for a given input
(done internally on the ADC0832). This
CC
condition.
For absolute accuracy, where the analog input varies between very specific voltage limits, the reference pin can be
biased with a time and temperature stable voltage source.
The LM385 and LM336 reference diodes are good low current devices to use with these converters.
is
The maximum value of the reference is limited to the V
supply voltage. The minimum value, however, can be quite
small (see Typical Performance Characteristics) to allow direct conversions of transducer outputs providing less than a
5V output span. Particular care must be taken with regard to
noise pickup, circuit layout and system error voltage sources when operating with a reduced span due to the increased sensitivity of the converter (1 LSB equals V
256).
REF
REF
pin
CC
/
a) Ratiometric b) Absolute with a Reduced Span
FIGURE 2. Reference Examples
14
TL/H/5583– 10
Functional Description (Continued)
4.0 THE ANALOG INPUTS
The most important feature of these converters is that they
can be located right at the analog signal source and through
just a few wires can communicate with a controlling processor with a highly noise immune serial bit stream. This in itself
greatly minimizes circuitry to maintain analog signal accuracy which otherwise is most susceptible to noise pickup.
However, a few words are in order with regard to the analog
inputs should the input be noisy to begin with or possibly
riding on a large common-mode voltage.
The differential input of these converters actually reduces
the effects of common-mode input noise, a signal common
to both selected ‘‘
Hz is most typical). The time interval between sampling the
a
‘‘
’’ input and then the ‘‘b’’ input is (/2 of a clock period.
The change in the common-mode voltage during this short
time interval can cause conversion errors. For a sinusoidal
common-mode signal this error is:
V
(max)eV
error
where fCMis the frequency of the common-mode signal,
V
PEAK
and f
CLK
For a 60 Hz common-mode signal to generate a (/4 LSB
error (&5 mV) with the converter running at 250 kHz, its
peak value would have to be 6.63V which would be larger
than allowed as it exceeds the maximum analog input limits.
Due to the sampling nature of the analog inputs short spikes
of current enter the ‘‘
clock edges during the actual conversion. These currents
decay rapidly and do not cause errors as the internal comparator is strobed at the end of a clock period. Bypass capacitors at the inputs will average these currents and cause
an effective DC current to flow through the output resistance of the analog signal source. Bypass capacitors should
not be used if the source resistance is greater than 1 kX.
This source resistance limitation is important with regard to
the DC leakage currents of input multiplexer as well. The
worst-case leakage current of
createa1mVinput error witha1kXsource resistance. An
op amp RC active low pass filter can provide both impedance buffering and noise filtering should a high impedance
signal source be required.
5.0 OPTIONAL ADJUSTMENTS
5.1 Zero Error
The zero of the A/D does not require adjustment. If the
minimum analog input voltage value, V
a zero offset can be done. The converter can be made to
output 0000 0000 digital code for this minimum input voltage
by biasing any V
utilizes the differential mode operation of the A/D.
The zero error of the A/D converter relates to the location
of the first riser of the transfer function and can be measured by grounding the V
magnitude positive voltage to the V
the difference between the actual DC input voltage which is
necessary to just cause an output digital code transition
from 0000 0000 to 0000 0001 and the ideal (/2 LSB value
e
((/2 LSB
a
’’ and ‘‘b’’ inputs for a conversion (60
(2qfCM)
PEAK
is its peak voltage value
, is the A/D clock frequency.
a
’’ input and exit the ‘‘b’’ input at the
(b) input at this V
IN
9.8 mV for V
REF
0.5
f
#
CLK
g
1 mA over temperature will
(b) input and applying a small
IN
IN
e
5.000 VDC).
J
, is not ground
IN(MIN)
value. This
IN(MIN)
(a) input. Zero error is
5.2 Full-Scale
The full-scale adjustment can be made by applying a differential input voltage which is 1 (/2 LSB down from the desired
analog full-scale voltage range and then adjusting the magnitude of the V
digital output code which is just changing from 1111 1110 to
1111 1111.
5.3 Adjusting for an Arbitrary Analog Input Voltage
Range
If the analog zero voltage of the A/D is shifted away from
ground (for example, to accommodate an analog input signal which does not go to ground), this new zero reference
should be properly adjusted first. A V
equals this desired zero reference plus (/2 LSB (where the
LSB is calculated for the desired analog span, using
e
1 LSB
analog span/256) is applied to selected ‘‘a’’ input
and the zero reference voltage at the corresponding ‘‘
input should then be adjusted to just obtain the 00
01
code transition.
HEX
The full-scale adjustment should be made[with the proper
V
(b) voltage applied]by forcing a voltage to the VIN(a)
IN
input which is given by:
(a)fsadjeV
V
IN
where:
and
The V
code change from FE
justment procedure.
6.0 POWER SUPPLY
A unique feature of the ADC0838 and ADC0834 is the inclusion of a zener diode connected from the V
ground which also connects to the V
the actual converter supply) through a silicon diode, as
shown in
e
V
MAX
e
V
MIN
REF
Figure 3
FIGURE 3. An On-Chip Shunt Regulator Diode
input (or VCCfor the ADC0832) for a
REF
(a) voltage which
IN
b
HEX
b
(V
V
b
MAX
the high end of the analog input range
the low end (the offset zero) of the analog
range.
(Both are ground referenced.)
(or VCC) voltage is then adjusted to provide a
to FF
HEX
. (See Note 3)
MAX
1.5
Ð
. This completes the ad-
HEX
CC
)
MIN
256
(
a
terminal to
terminal (which is
TL/H/5583– 11
’’
to
15
Functional Description (Continued)
This zener is intended for use as a shunt voltage regulator
to eliminate the need for any additional regulating components. This is most desirable if the converter is to be remotely located from the system power source.
and 5
illustrate two useful applications of this on-board ze-
Figures 4
ner when an external transistor can be afforded.
An important use of the interconnecting diode between V
and VCCis shown in
used as a rectifier to allow the V
Figures 6 and 7
supply for the converter
CC
. Here, this diode is
Applications
to be derived from the clock. The low current requirements
of the A/D and the relatively high clock frequencies used
(typically in the range of 10k –400 kHz) allows using the
small value filter capacitor shown to keep the ripple on the
V
line to well under (/4 of an LSB. The shunt zener regula-
CC
tor can also be used in this mode. This requires a clock
a
voltage swing which is in excess of V
zener is needed, either built into the clock generator or a
. A current limit for the
Z
resistor can be used from the CLK pin to the V
a
pin.
FIGURE 4. Operating with a Temperature
TL/H/5583– 12
Compensated Reference
*Note: 4.5VsV
TL/H/5583– 35
FIGURE 6. Generating VCCfrom the Converter Clock
FIGURE 5. Using the A/D as
TL/H/5583– 34
the System Supply Regulator
s
6.3V
CC
TL/H/5583– 36
FIGURE 7. Remote SensingÐ
Clock and Power on 1 Wire
16
Applications (Continued)
Digital Link and Sample Controlling Software for the
Serially Oriented COP420 and the Bit Programmable I/O INS8048
COP CODING EXAMPLE
Mnemonic Instruction
LEI ENABLES SIO’s INPUT AND OUTPUT
SC C
OGI G0
CLR A CLEARS ACCUMULATOR
AISC 1 LOADS ACCUMULATOR WITH 1
XAS EXCHANGES SIO WITH ACCUMULATOR
LDD LOADS MUX ADDRESS FROM RAM
NOP Ð
XAS LOADS MUX ADDRESS FROM
e
1
e
0 (CSe0)
AND STARTS SK CLOCK
INTO ACCUMULATOR
ACCUMULATOR TO SIO REGISTER
u
8 INSTRUCTIONS
v
XAS READS HIGH ORDER NIBBLE (4 BITS)
XIS PUTS HIGH ORDER NIBBLE INTO RAM
CLR A CLEARS ACCUMULATOR
RC C
XAS READS LOW ORDER NIBBLE INTO
XIS PUTS LOW ORDER NIBBLE INTO RAM
OGI G0
LEI DISABLES SIO’s INPUT AND OUTPUT
INTO ACCUMULATOR
e
0
ACCUMULATOR AND STOPS SK
e
1 (CSe1)
8048 CODING EXAMPLE
Mnemonic Instruction
START: ANL P1,
MOV B,
MOV A,
LOOP 1: RRC A ;CY
JC ONE ;TEST BIT
ZERO: ANL P1,
JMP CONT ;CONTINUE
ONE: ORL P1,
CONT: CALL PULSE ;PULSE SK 0
DJNZ B, LOOP 1 ;CONTINUE UNTIL DONE
CALL PULSE ;EXTRA CLOCK FOR SYNC
MOV B,
LOOP 2: CALL PULSE ;PULSE SK 0
IN A, P1 ;CY
RRC A
RRC A
MOV A, C ;A
RLC A ;A(0)
MOV C, A ;C
DJNZ B, LOOP 2 ;CONTINUE UNTIL DONE
RETR
PULSE: ORL P1,
NOP ;DELAY
ANL P1,
RET
Ý
0F7H ;SELECT A/D (CSe0)
Ý
5 ;BIT COUNTERw5
Ý
ADDR ;AwMUX ADDRESS
Ý
0FEH ;DIw0
Ý
1 ;DIw1
Ý
8 ;BIT COUNTERw8
Ý
04 ;SKw1
Ý
0FBH ;SKw0
w
ADDRESS BIT
e
;BIT
0
e
;BIT
1
w
DO
w
RESULT
w
BIT AND SHIFT
w
RESULT
;PULSE SUBROUTINE
TL/H/5583– 13
x1x
x1x
0
0
17
Applications (Continued)
A ‘‘Stand-Alone’’ Hook-Up for ADC0838 Evaluation
*Pinouts shown for ADC0838.
For all other products tie to
pin functions as shown.
Low-Cost Remote Temperature Sensor
TL/H/5583– 14
18
Applications (Continued)
Digitizing a Current Flow
TL/H/5583– 15
Operating with Ratiometric Transducers
*VIN(b)e0.15 V
15% of V
s
CC
CC
s
V
85% of V
XDR
CC
TL/H/5583– 37
19
Applications (Continued)
s
Span Adjust: OV
V
IN
Zero-Shift and Span Adjust: 2V
s
3V
s
s
V
5V
IN
TL/H/5583– 16
20
Applications (Continued)
Obtaining Higher Resolution
Controller performs a routine to determine which input polarity (9-bit example) or which channel pair (10-bit example) provides a non-zero output code.
This information provides the extra bits.
TL/H/5583– 17
a) 9-Bit A/D b)10-Bit A/D
Protecting the Input
Diodes are 1N914
TL/H/5583– 18
21
Applications (Continued)
DOeall 1s ifaV
DOeall 0s ifaV
High Accuracy Comparators
l
b
V
IN
IN
k
b
V
IN
IN
Digital Load Cell
TL/H/5583– 38
Uses one more wire than load cell itself
#
Two mini-DIPs could be mounted inside load cell for digital output transducer
#
Electronic offset and gain trims relax mechanical specs for gauge factor and offset
#
Low level cell output is converted immediately for high noise immunity
#
22
TL/H/5583– 19
Applications (Continued)
4 mA–20 mA Current Loop Converter
All power supplied by loop
#
1500V isolation at output TL/H/5583– 20
#
Isolated Data Converter
No power required remotely
#
1500V isolation
#
TL/H/5583– 39
23
Applications (Continued)
Two Wire Interface for 8 Channels
TL/H/5583– 21
24
Applications (Continued)
Two Wire 1-Channel Interface
Ordering Information
Part Number
ADC0831BCJ
ADC0831BCN Molded (N) 0
ADC0831CCJ
ADC0831CCN Molded (N) 0
ADC0831CIWM SO(M)
ADC0831CCWM SO(M) 0§Ctoa70§C
ADC0832BIWM
ADC0832BCN Molded (N) 0
ADC0832CIWM
ADC0832CCN Molded (N) 0
ADC0832CCWM SO(M) 0
Analog Input Total
Channels Unadjusted Error Range
g
(/2
1
2
g
1
g
(/2
g
1
Package
Hermetic (J)
Hermetic (J)
SO(M)
SO(M)
Temperature
b
40§Ctoa85§C
Ctoa70§C
§
b
40§Ctoa85§C
Ctoa70§C
§
b
40§Ctoa85§C
b
40§Ctoa85§C
Ctoa70§C
§
b
40§Ctoa85§C
Ctoa70§C
§
Ctoa70§C
§
TL/H/5583– 22
25
Ordering Information (Continued)
Part Number
ADC0834BCN
ADC0834CCJ
ADC0834CCN Molded (N) 0
ADC0834CCWM SO(M) 0
ADC0834CIWM SO(M)
ADC0838BCJ
ADC0838BCV PCC (V) 0
ADC0838BCN Molded (N) 0
ADC0838CCJ
ADC0838CCV PCC (V) 0
ADC0838CCN Molded (N) 0
ADC0838CIWM SO(M)
ADC0838CCWM SO(M) 0§Ctoa70§C
See NS Package Number J08A, J14A, J20A, M14B, M20B, N08E, N14A, N20A or V20A
Analog Input Total
Channels Unadjusted Error Range
g
(/2 Molded (N) 0§Ctoa70§C
4
8
g
1
g
(/2
g
1
Package
Hermetic (J)
Hermetic (J)
Hermetic (J)
Temperature
b
40§Ctoa85§C
Ctoa70§C
§
Ctoa70§C
§
b
40§Ctoa85§C
b
40§Ctoa85§C
Ctoa70§C
§
Ctoa70§C
§
b
40§Ctoa85§C
Ctoa70§C
§
Ctoa70§C
§
b
40§Ctoa85§C
26
27
Physical Dimensions inches (millimeters)
Ceramic Dual-In-Line Package (J)
NS Package Number J08A
Ceramic Dual-In-Line Package (J)
NS Package Number J14A
28
Physical Dimensions inches (millimeters) (Continued)
Ceramic Dual-In-Line Package (J)
NS Package Number J20A
Hermetic Dual-In-Line Package (M)
NS Package Number M14B
29
Physical Dimensions inches (millimeters) (Continued)
Hermetic Dual-In-Line Package (M)
NS Package Number M20B
Molded Dual-In-Line Package (N)
NS Package Number N08E
30
Physical Dimensions inches (millimeters) (Continued)
Molded Dual-In-Line Package (N)
NS Package Number N14A
Molded-Dual-In-Line Package (N)
NS Package Number N20A
31
Physical Dimensions inches (millimeters) (Continued)
Molded Chip Carrier Package (V)
Order Number ADC0838BCV or ADC0838CCV
NS Package Number V20A
ADC0831/ADC0832/ADC0834 and ADC0838
8-Bit Serial I/O A/D Converters with Multiplexer Options
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DEVICES OR SYSTEMS WITHOUT THE EXPRESS WRITTEN APPROVAL OF THE PRESIDENT OF NATIONAL
SEMICONDUCTOR CORPORATION. As used herein:
1. Life support devices or systems are devices or 2. A critical component is any component of a life
systems which, (a) are intended for surgical implant support device or system whose failure to perform can
into the body, or (b) support or sustain life, and whose be reasonably expected to cause the failure of the life
failure to perform, when properly used in accordance support device or system, or to affect its safety or
with instructions for use provided in the labeling, can effectiveness.
be reasonably expected to result in a significant injury
to the user.
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Corporation Europe Hong Kong Ltd. Japan Ltd.
1111 West Bardin Road Fax: (
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Tel: 1(800) 272-9959 Deutsch Tel: (
Fax: 1(800) 737-7018 English Tel: (
National does not assume any responsibility for use of any circuitry described, no circuit patent licenses are implied and National reserves the right at any time without notice to change said circuitry and specifications.
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a
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