Rainbow Electronics ADC08351 User Manual

ADC08351
8-Bit, 42 MSPS, 40 mW A/D Converter

General Description

The ADC08351 is an easy to use low power, low cost, small
size, 42 MSPS analog-to-digital converter that digitizes sig­nals to 8 bits. The ADC08351 uses an unique architecture
that achieves 7.2 Effective Bits with a 4.4 MHz input and
42 MHz clock frequency and 6.8 Effective Bits with a 21 MHz
input and 42 MHz clock frequency. Output formatting is
straight binary coding.

To minimize system cost and power consumption, the
ADC08351 requires minimal external components and in­cludes input biasing to allow optional a.c. input signal cou­pling. The user need only provide a +3V supply and a clock.
Many applications require no separate reference or driver
components.

The excellent dc and ac characteristics of this device, to­gether with its low power consumption and +3V single supply
operation, make it ideally suited for many video and imaging
applications, including use in portable equipment. Total
power consumption is reduced to less than 7 mW in the
power-down mode. Furthermore, the ADC08351 is resistant
to latch-up and the outputs are short-circuit proof.

Fabricated on a 0.35 micron CMOS process, the ADC08351
is offered in TSSOP and LLP (a molded lead frame-based
chip-scale package), and is designed to operate over the
industrial temperature range of −40˚C to +85˚C.

Features

n Low Input Capacitance
n Internal Sample-and-Hold Function

n Single +3V Operation
n Power Down Feature
n TRI-STATE Outputs

Key Specifications

j

Resolution 8 Bits

j

Maximum Sampling Frequency 42 MSPS (min)

j

ENOB@f

j

Guaranteed No Missing Codes

j

Power Consumption 40 mW (typ); 48 mW (max)

CLK

Applications

n Video Digitization
n Digital Still Cameras
n Set Top Boxes
n Digital Camcorders
n Communications
n Medical Imaging
n Personal Computer Video
n CCD Imaging
n Electro-Optics

ADC08351 8-Bit, 42 MSPS, 40 mW A/D Converter

November 2003

= 42 MHz, fIN= 4.4 MHz 7.2 Bits (typ)

(Excluding Reference Current)

Pin Configuration

20-Pin TSSOP 24-Pin LLP (CSP)

Top View

© 2003 National Semiconductor Corporation DS100895 www.national.com

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Bottom View

Ordering Information

ADC08351

ADC08351 Block Diagram

ADC08351CIMTC TSSOP

ADC08351CIMTCX TSSOP (tape & reel)

ADC08351CILQ LLP (tape & reel - 1, 000 units)

ADC08351CILQX LLP (tape & reel - 4, 500 units)

Pin Descriptions and Equivalent Circuits (LLP pins in parentheses)

Pin
No.

17

(17)

14

(14)

1

(22)

12

(11)

15

(15)

Symbol Equivalent Circuit Description

V

IN

Analog signal input. Conversion range is 0.5 V

.

0.68 V

A

Positive reference voltage input. Operating range of
this voltage is 0.75V to V

V

REF

bypassed with a 10 µF tantalum or aluminum
electrolytic capacitor and a 0.1 µF ceramic chip
capacitor.

CMOS/TTL compatible digital input that, when low,

OE

enables the digital outputs of the ADC08351. When
high, the outputs are in a high impedance state.

CLK

CMOS/TTL compatible digital clock input. V
sampled on the falling edge of CLK input.

CMOS/TTL compatible digital input that, when high,

PD

puts the ADC08351 into the power down mode,
where it consumes minimal power. When this pin is
low, the ADC08351 is in the normal operating mode.

. This pin should be

A

10089502

IN

to

P-P

is

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Pin Descriptions and Equivalent Circuits (LLP pins in parentheses) (Continued)

ADC08351

Pin
No.

3 thru

10

(1 thru

8)

11, 13

(10,

12)

2, 20

(21,

23)

16

(16)

18, 19

(18,

19)

Symbol Equivalent Circuit Description

Conversion data digital output pins. D0 is the LSB,

D0–D7

D7 is the MSB. Valid data is output just after the
rising edge of the CLK input. These pins are enabled
by bringing the OE pin low.

Positive digital supply pin. Connect to a clean, quiet
voltage source of +3V. V

V

D

common supply and be separately bypassed with a
10 µF tantalum or aluminum electrolytic capacitor and

and VDshould have a

A

a 0.1 µF ceramic chip capacitor. See Section 3.0 for
more information.

The ground return for the digital supply. AGND and

DGND

DGND should be connected together close to the
ADC08351.

Positive analog supply pin. Connected to a clean,
quiet voltage source of +3V. V

V

A

a common supply and be separately bypassed with a
10 µF tantalum or aluminum electrolytic capacitor and

A

a 0.1 µF ceramic chip capacitor. See Section 3.0 for
more information.

The ground return for the analog supply. AGND and

AGND

DGND should be connected together close to the
ADC08351 package.

and VDshould have

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Absolute Maximum Ratings (Notes 1,

2)

If Military/Aerospace specified devices are required,

ADC08351

please contact the National Semiconductor Sales Office/
Distributors for availability and specifications.

Supply Voltage (V

) 4.2V

A,VD

Package Dissipation at T

= 25˚C (Note 4)

A

ESD Susceptibility (Note 5)

Human Body Model 4000V

Machine Model 200V

Soldering Temp., Infrared, 10 sec. (Note 6) 235˚C

Storage Temperature −65˚C to +150˚C
Voltage on Any Input or Output
Pin −0.3V to 4.2V

Operating Ratings (Notes 1, 2)

Ground Difference
(AGND–DGND)

CLK, OE Voltage Range

Digital Output Voltage (V

OH,VOL

Input Current at Any Pin (Note 3)

Package Input Current (Note 3)

±

100 mV

−0.5 to (VA+ 0.5V)

)V

to DGND

D

±

25 mA

±

50 mA

Operating Temperature Range −40˚C T

Supply Voltage (V

) +2.7V to +3.6V

A,VD

Ground Difference
|DGND–AGND| 0V to 100 mV

V

Voltage Range (V

IN

) 0.5V to 0.68 V

P-P

Converter Electrical Characteristics

The following specifications apply for VA=VD= +3.0 VDC,V
f

= 42 MHz, 50% duty cycle, unless otherwise specified. Boldface limits apply for TA=T

CLK

25˚C (Notes 7, 8)

Symbol Parameter Conditions

DC Accuracy

INL Integral Non Linearity Error

DNL Differential Non Linearity

Missing Codes 0 (max)

E

Z

E

FS

Zero Scale Offset Error −17 mV

Full Scale Offset Error −7 mV

Video Accuracy

DP Differential Phase Error f

DG Differential Gain Error f

= 20 MHz, Video Ramp Input 1.0 Degree

CLK

= 20 MHz, Video Ramp Input 1.5 %

CLK

Analog Input and Reference Characteristics

C

IN

R

IN

VINInput Capacitance VIN= 1.5V + 0.7 Vrms

RINInput Resistance 7.2 kΩ

FPBW Full-Power Bandwidth 120 MHz

V

I

REF

REF

Reference Input Voltage At pin 14

Reference Input Current 7.7 mA

Power Supply Characteristics

I

A

I

D

Analog Supply Current

Digital Supply Current

PD = Low 10.5 mA

PD = High 1 mA

PD = Low, No Digital Output Load 2.9 mA

PD = High 0.5 mA

Total Operating Current Excluding Reference Current, V

Power Consumption (active) PD = Low (excluding reference current) 40.2 48 mW (max)

Power Consumption (power
down)

PD = High (excluding reference current)

CLK, OE Digital Input Characteristics

V

IH

V

IL

I

IH

I

IL

Logical High Input Voltage VD=VA=3V 2.0 V (min)

Logical Low Input Voltage VD=VA=3V 1.0 V (max)

Logical High Input Current VIH=VD=VA= 3.3V 10 µA

Logic Low Input Current VIL= 0V, VD=VA= 3.3V −10 µA

= 2.4V, VIN= 1.63 V

REF

, OE = 0V, CL= 20 pF,

P-P

to T

MIN

Typical

(Note 9)

±

0.7

±

0.6

: all other limits TA=

MAX

Limits

(Note 9)

±

1.4 LSB (max)

+1.3 LSB (max)

−1.0 LSB (min)

(CLK LOW) 4 pF

(CLK HIGH) 11 pF

0.735 V

V

A

IN

=0V

DC

13.4 16 mA (max)

<

7mW

≤ +85˚C

A

Units

(Limits)

A

V

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Converter Electrical Characteristics (Continued)

The following specifications apply for VA=VD= +3.0 VDC,V
f

= 42 MHz, 50% duty cycle, unless otherwise specified. Boldface limits apply for TA=T

CLK

25˚C (Notes 7, 8)

Symbol Parameter Conditions

C

IN

Logic Input Capacitance 10 pF

Digital Output Characteristics

I

I

V

V

I
I

OH

OL

OH

OL

OZH

OZL

High Level Output Current VD= 2.7V, VOH=VD−0.5V −1.1 mA (min)

Low Level Output Current VD= 2.7V, OE = DGND, VOL= 0.4V 1.8 mA (min)

High Level Output Voltage VD= 2.7V, IOH= −360 µA 2.65 V

Low Level Output Voltage VD= 2.7V, IOL= 1.6 mA 0.2 V

,

TRI-STATE®Output Current OE = VD= 3.3V, VOH= 3.3V or VOL=0V

AC Electrical Characteristics

f

C1

f

C2

t

OD

Maximum Conversion Rate 42 MHz (min)

Minimum Conversion Rate 2 MHz

Output Delay CLK High to Data Valid 14 19 ns (max)

Pipline Delay (Latency) 2.5

t

DS

t

OH

t

EN

t

DIS

ENOB Effective Number of Bits

SINAD Signal-to-Noise & Distortion

SNR Signal-to-Noise Ratio

THD Total Harmonic Distortion

SFDR Spurious Free Dynamic Range

Note 1: Absolute Maximum Ratings indicate limits beyond which damage to the device may occur. Operating Ratings indicate conditions for which the device is
functional, but do not guarantee specific performance limits. For guaranteed specifications and test conditions, see the Electrical Characteristics. The guaranteed
specifications apply only for the test conditions listed. Some performance characteristics may degrade when the device is not operated under the listed test
conditions.

Note 2: All voltages are measured with respect to GND = AGND = DGND = 0V, unless otherwise specified.

Note 3: When the input voltage at any pin exceeds the power supplies (that is, less than AGND or DGND, or greater than V

be limited to 25 mA. The 50 mA maximum package input current rating limits the number of pins that can safely exceed the power supplies with an input current of
25 mA to two.

Note 4: The absolute maximum junction temperature (T
junction-to-ambient thermal resistance (θ
TSSOP, θ
device under normal operation will typically be about 68 mW (40 mW quiescent power + 23 mW reference ladder power+5mWdueto1TTLloan on each digital
output). The values for maximum power dissipation listed above will be reached only when the ADC08351 is operated in a severe fault condition (e.g., when input
or output pins are driven beyond the power supply voltages, or the power supply polarity is reversed). Obviously, such conditions should always be avoided.

Note 5: Human body model is 100 pF capacitor discharged through a 1.5 kΩ resistor. Machine model is 220 pF discharged through ZERO Ohms.

Note 6: See AN-450, “Surface Mounting Methods and Their Effect on Product Reliability”, or the section entitled “Surface Mount” found in any post 1986 National

Semiconductor Linear Data Book, for other methods of soldering surface mount devices.

Sampling (Aperture) Delay CLK Low to Acquisition of Data 2 ns

Output Hold Time CLK High to Data Invalid 9 ns

OE Low to Data Valid Loaded as in Figure 2 14 ns

OE High to High Z State Loaded as in Figure 2 10 ns

= 30 MHz, fIN= 1 MHz 7.2 Bits

f

CLK

f

= 42 MHz, fIN= 4.4 MHz 7.2 Bits

CLK

f

= 42 MHz, fIN= 21 MHz 6.8 6.1 Bits (min)

CLK

= 30 MHz, fIN= 1 MHz 45 dB

f

CLK

f

= 42 MHz, fIN= 4.4 MHz 45 dB

CLK

f

= 42 MHz, fIN= 21 MHz 43 38.5 dB (min)

CLK

= 30 MHz, fIN= 1 MHz 44 dB

f

CLK

f

= 42 MHz, fIN= 4.4 MHz 45 dB

CLK

f

= 42 MHz, fIN= 21 MHz 44 41 dB (min)

CLK

= 30 MHz, fIN= 1 MHz −57 dB

f

CLK

f

= 42 MHz, fIN= 4.4 MHz −51 dB

CLK

f

= 42 MHz, fIN= 21 MHz −46 −41 dB (min)

CLK

= 30 MHz, fIN= 1 MHz 57 dB

f

CLK

f

= 42 MHz, fIN= 4.4 MHz 54 dB

CLK

f

= 42 MHz, fIN= 21 MHz 49 41 dB (min)

CLK

max) for this device is 150˚C. The maximum allowable power dissipation is dictated by TJmax, the

), and the ambient temperature (TA), and can be calculated using the formula PDMAX=(TJmax - TA)/θJA. For the 20-pin

is 135˚C/W, so PDMAX = 926 mW at 25˚C and 481 mW at the maximum operating ambient temperature of 85˚C. Note that the power dissipation of this

JA

JA

J

= 2.4V, VIN= 1.63 V

REF

, OE = 0V, CL= 20 pF,

P-P

MIN

to T

MAX

Typical

(Note 9)

±

10 µA

or VD), the current at that pin should

A

: all other limits TA=

Limits

(Note 9)

Units

(Limits)

Clock

Cycles

ADC08351

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Note 7: All inputs are protected as shown below. Input voltage magnitudes up to 500 mV above the supply voltage or 500 mV below GND will not damage this
device. However, errors in the A/D conversion can occur if the input goes above V
full-scale input voltage must be ≤3.3 V

to ensure accurate conversions.

DC

or below AGND by more than 300 mV. As an example, if VAis 3.0 VDC, the

A

ADC08351

10089506

Note 8: To guarantee accuracy, it is required that VAand VDbe well bypassed. Each VAand VDpin must be decoupled with separate bypass capacitors.

Note 9: Typical figures are at T

Level).

= 25˚C, and represent most likely parametric norms. Test limits are guaranteed to National’s AOQL (Average Outgoing Quality

J

Typical Performance Characteristics

VA=VD=VDI/O = 3V, f

specified

@

42 MSPS DNL vs Sample Rate DNL vs V

DNL

= 42 MHz, unless otherwise

CLK

A

10089507

10089508

DNL vs Temperature INL@42 MSPS INL vs Sample Rate

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