ADC08200
8-Bit, 20 MSPS to 200 MSPS, 1.05 mW/MSPS A/D
Converter
ADC08200 8-Bit, 20 MSPS to 200 MSPS, 1.05 mW/MSPS A/D Converter
July 2004
General Description
The ADC08200 is a low-power, 8-bit, monolithic analog-todigital converter with an on-chip track-and-hold circuit. Optimized for low cost, low power, small size and ease of use,
this product operates at conversion rates up to 230 MSPS
while consuming just 1.05 mW per MHz of clock frequency,
or 210 mW at 200 MSPS. Raising the PD pin puts the
ADC08200 into a Power Down mode where it consumes
about 1 mW.
The unique architecture achieves 7.3 Effective Bits with
50 MHz input frequency. The ADC08200 is resistant to
latch-up and the outputs are short-circuit proof. The top and
bottom of the ADC08200’s reference ladder are available for
connections, enabling a wide range of input possibilities. The
digital outputs are TTL/CMOS compatible with a separate
output power supply pin to support interfacing with 3V or
2.5V logic. The digital inputs (CLK and PD) are TTL/CMOS
compatible.
The ADC08200 is offered in a 24-lead plastic package
(TSSOP) and is specified over the industrial temperature
range of −40˚C to +85˚C. An evaluation board is available to
assist in the easy evaluation of the ADC08200.
Features
n Single-ended input
n Internal sample-and-hold function
n Low voltage (single +3V) operation
n Small package
n Power-down feature
Key Specifications
n Resolution 8 Bits
n Maximum sampling frequency 200 MSPS (min)
n DNL
n ENOB (f
n THD (f
n Power Consumption
— Operating 1.05 mW/MSPS (typ)
— Power Down 1 mW (typ)
= 50 MHz) 7.3 bits (typ)
IN
= 50 MHz) 61 dB (typ)
IN
±
0.4 LSB (typ)
Applications
n Flat panel displays
n Projection systems
n Set-top boxes
n Battery-powered instruments
n Communications
n Medical imaging
n Astronomy
Pin Configuration
20017901
© 2004 National Semiconductor Corporation DS200179 www.national.com
Ordering Information
ADC08200
Block Diagram
Order Number (−40˚C ≤ TA≤ +85˚C) Package
ADC08200CIMT TSSOP
ADC08200CIMTX TSSOP (tape and reel)
ADC08200EVAL Evaluation Board
Pin Descriptions and Equivalent Circuits
Pin No. Symbol Equivalent Circuit Description
6V
3V
9V
10 V
IN
RT
RM
RB
Analog signal input. Conversion range is VRBto VRT.
Analog Input that is the high (top) side of the reference
ladder of the ADC. Nominal range is 0.5V to V
and VRBinputs define the VINconversion range.
on V
RT
Bypass well. See Section 2.0 for more information.
Mid-point of the reference ladder. This pin should be
bypassed to a quiet point in the analog ground plane with
a 0.1 µF capacitor.
Analog Input that is the low side (bottom) of the
reference ladder of the ADC. Nominal range is 0.0V to
– 0.5V). Voltage on VRTand VRBinputs define the
(V
RT
conversion range. Bypass well. See Section 2.0 for
V
IN
more information.
20017902
. Voltage
A
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Pin Descriptions and Equivalent Circuits (Continued)
Pin No. Symbol Equivalent Circuit Description
Power Down input. When this pin is high, the converter is
23 PD
in the Power Down mode and the data output pins hold
the last conversion result.
ADC08200
24 CLK
13 thru 16
and
D0–D7
19 thru 22
7V
IN
GND Reference ground for the single-ended analog input, VIN.
CMOS/TTL compatible digital clock Input. V
on the rising edge of CLK input.
Conversion data digital Output pins. D0 is the LSB, D7 is
the MSB. Valid data is output just after the rising edge of
the CLK input.
Positive analog supply pin. Connect to a quiet voltage
1, 4, 12 V
A
source of +3V. V
ceramic chip capacitor for each pin, plus one
should be bypassed with a 0.1 µF
A
10 µF capacitor. See Section 3.0 for more information.
18 V
DR
Power supply for the output drivers. If connected to VA,
decouple well from V
.
A
17 DR GND The ground return for the output driver supply.
2, 5, 8, 11 AGND The ground return for the analog supply.
is sampled
IN
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Absolute Maximum Ratings
(Notes 1, 2)
If Military/Aerospace specified devices are required,
ADC08200
please contact the National Semiconductor Sales Office/
Distributors for availability and specifications.
Supply Voltage (V
Driver Supply Voltage (V
Voltage on Any Input or Output
Pin −0.3V to V
Reference Voltage (VRT,VRB)V
CLK, PD Voltage Range −0.05V to
Input Current at Any Pin (Note 3)
Package Input Current (Note 3)
Power Dissipation at T
) 3.8V
A
)V
DR
(V
= 25˚C See (Note 4)
A
A
to AGND
A
+ 0.05V)
A
±
25 mA
±
50 mA
+0.3V
A
Operating Ratings (Notes 1, 2)
Operating Temperature Range −40˚C ≤ T
Supply Voltage (V
Driver Supply Voltage (V
) +2.7V to +3.6V
A
) +2.4V to V
DR
Ground Difference |GND - DR GND| 0V to 300 mV
Upper Reference Voltage (V
Lower Reference Voltage (V
V
Voltage Range VRBto V
IN
) 0.5V to (VA−0.3V)
RT
) 0Vto(VRT−0.5V)
RB
Package Thermal Resistance
Package θ
24-Lead TSSOP 92˚C/W
JA
ESD Susceptibility (Note 5)
Human Body Model
Machine Model
2500V
200V
Soldering Temperature, Infrared,
10 seconds (Note 6) 235˚C
Storage Temperature −65˚C to +150˚C
Converter Electrical Characteristics
The following specifications apply for VA=VDR= +3.0VDC,VRT= +1.9V, VRB= 0.3V, CL= 5 pF, f
cycle. Boldface limits apply for T
J=TMIN
to T
Symbol Parameter Conditions
: all other limits TJ= 25˚C (Notes 7, 8)
MAX
Typical
(Note 9)
DC ACCURACY
INL Integral Non-Linearity
DNL Differential Non-Linearity
+1.0
−0.3
±
0.4
Missing Codes 0 (max)
FSE Full Scale Error 36 50 mV (max)
V
OFF
Zero Scale Offset Error 46 60 mV (max)
ANALOG INPUT AND REFERENCE CHARACTERISTICS
V
IN
C
IN
R
IN
Input Voltage 1.6
VINInput Capacitance VIN= 0.75V +0.5 Vrms
RINInput Resistance
(CLK
LOW)
(CLK
HIGH)
3pF
4pF
>
1MΩ
BW Full Power Bandwidth 500 MHz
V
RT
V
RB
R
REF
Top Reference Voltage 1.9
Bottom Reference Voltage 0.3
Reference Ladder Resistance VRTto V
RB
160
CLK, PD DIGITAL INPUT CHARACTERISTICS
V
IH
V
IL
I
IH
Logical High Input Voltage VDR=VA= 3.6V 2.0 V (min)
Logical Low Input Voltage VDR=VA= 2.7V 0.8 V (max)
Logical High Input Current VIH=VDR=VA= 3.6V 10 nA
= 200 MHz at 50% duty
CLK
Limits
(Note 9)
+1.9
−1.2
±
0.95 LSB (max)
V
RB
V
RT
V
A
0.5 V (min)
− 0.5 V (max)
V
RT
0 V (min)
120 Ω (min)
200 Ω (max)
≤ +85˚C
A
RT
Units
(Limits)
LSB (max)
LSB (min)
V (min)
V (max)
V (max)
A
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Converter Electrical Characteristics (Continued)
The following specifications apply for VA=VDR= +3.0VDC,VRT= +1.9V, VRB= 0.3V, CL= 5 pF, f
cycle. Boldface limits apply for T
J=TMIN
to T
Symbol Parameter Conditions
CLK, PD DIGITAL INPUT CHARACTERISTICS
I
IL
C
IN
Logical Low Input Current VIL= 0V, VDR=VA= 2.7V −50 nA
Logic Input Capacitance 3 pF
DIGITAL OUTPUT CHARACTERISTICS
V
OH
V
OL
High Level Output Voltage VA=VDR= 2.7V, IOH= −400 µA 2.6 2.4 V (min)
Low Level Output Voltage VA=VDR= 2.7V, IOL= 1.0 mA 0.4 0.5 V (max)
DYNAMIC PERFORMANCE
ENOB Effective Number of Bits
SINAD Signal-to-Noise & Distortion
SNR Signal-to-Noise Ratio
SFDR Spurious Free Dynamic Range
THD Total Harmonic Distortion
HD2 2nd Harmonic Distortion
HD3 3rd Harmonic Distortion
IMD Intermodulation Distortion
POWER SUPPLY CHARACTERISTICS
I
A
Analog Supply Current
: all other limits TJ= 25˚C (Notes 7, 8)
MAX
Typical
(Note 9)
f
= 4 MHz, VIN= FS − 0.25 dB 7.5 Bits
IN
f
= 20 MHz, VIN= FS − 0.25 dB 7.4 Bits
IN
f
= 50 MHz, VIN= FS − 0.25 dB 7.3 6.9 Bits (min)
IN
f
= 70 MHz, VIN= FS − 0.25 dB 7.2 Bits
IN
f
= 100 MHz, VIN= FS − 0.25 dB 7.0 Bits
IN
f
= 4 MHz, VIN= FS − 0.25 dB 47 dB
IN
f
= 20 MHz, VIN= FS − 0.25 dB 46 dB
IN
f
= 50 MHz, VIN= FS − 0.25 dB 46 43.3 dB (min)
IN
f
= 70 MHz, VIN= FS − 0.25 dB 45 dB
IN
f
= 100 MHz, VIN= FS − 0.25 dB 44 dB
IN
f
= 4 MHz, VIN= FS − 0.25 dB 47 dB
IN
f
= 20 MHz, VIN= FS − 0.25 dB 46 dB
IN
f
= 50 MHz, VIN= FS − 0.25 dB 46 43.4 dB (min)
IN
f
= 70 MHz, VIN= FS − 0.25 dB 45 dB
IN
f
= 100 MHz, VIN= FS − 0.25 dB 44 dB
IN
f
= 4 MHz, VIN= FS − 0.25 dB 60 dBc
IN
f
= 20 MHz, VIN= FS − 0.25 dB 58 dBc
IN
f
= 50 MHz, VIN= FS − 0.25 dB 60 dBc
IN
f
= 70 MHz, VIN= FS − 0.25 dB 57 dBc
IN
f
= 100 MHz, VIN= FS − 0.25 dB 54 dBc
IN
f
= 4 MHz, VIN= FS − 0.25 dB −60 dBc
IN
f
= 20 MHz, VIN= FS − 0.25 dB −58 dBc
IN
f
= 50 MHz, VIN= FS − 0.25 dB −60 dBc
IN
f
= 70 MHz, VIN= FS − 0.25 dB -56 dBc
IN
f
= 100 MHz, VIN= FS − 0.25 dB −53 dBc
IN
f
= 4 MHz, VIN= FS − 0.25 dB −66 dBc
IN
f
= 20 MHz, VIN= FS − 0.25 dB -68 dBc
IN
f
= 50 MHz, VIN= FS − 0.25 dB −66 dBc
IN
f
= 70 MHz, VIN= FS − 0.25 dB -60 dBc
IN
f
= 100 MHz, VIN= FS − 0.25 dB −55 dBc
IN
f
= 4 MHz, VIN= FS − 0.25 dB −72 dBc
IN
f
= 20 MHz, VIN= FS − 0.25 dB −58 dBc
IN
f
= 50 MHz, VIN= FS − 0.25 dB −72 dBc
IN
f
= 70 MHz, VIN= FS − 0.25 dB -58 dBc
IN
f
= 100 MHz, VIN= FS − 0.25 dB −60 dBc
IN
f
= 11 MHz, VIN= FS − 6.25 dB
1
= 12 MHz, VIN= FS − 6.25 dB
f
2
-55 dBc
DC Input 69.75 86 mA (max)
= 10 MHz, VIN=FS−3dB 69.75 mA
f
IN
= 200 MHz at 50% duty
CLK
Limits
(Note 9)
ADC08200
Units
(Limits)
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Converter Electrical Characteristics (Continued)
The following specifications apply for VA=VDR= +3.0VDC,VRT= +1.9V, VRB= 0.3V, CL= 5 pF, f
cycle. Boldface limits apply for T
ADC08200
J=TMIN
to T
Symbol Parameter Conditions
: all other limits TJ= 25˚C (Notes 7, 8)
MAX
Typical
(Note 9)
POWER SUPPLY CHARACTERISTICS
I
DR
I
A+IDR
PC Power Consumption
PSRR
PSRR
Output Driver Supply Current DC Input, PD = Low 0.25 0.6 mA (max)
Total Operating Current
DC Input, PD = Low 70 86.6 mA (max)
CLK Low, PD = Hi 0.3 mA
DC Input, Excluding Reference 210 260 mW (max)
CLK Low, PD = Hi 1 mW
Power Supply Rejection Ratio
1
Power Supply Rejection Ratio
2
FSE change with 2.7V to 3.3V change
in V
A
SNR reduction with 200 mV at 1MHz
on supply
54 dB
45 dB
AC ELECTRICAL CHARACTERISTICS
f
C1
f
C2
t
CL
t
CH
t
OH
t
OD
Maximum Conversion Rate 230 200 MHz (min)
Minimum Conversion Rate 10 MHz
Minimum Clock Low Time 0.87 1.0 ns (min)
Minimum Clock High Time 0.65 0.75 ns (min)
Output Hold Time CLK to Data Invalid 2.1 ns
Output Delay CLK to Data Transition 3.5
Pipeline Delay (Latency) 6 Clock Cycles
t
AD
t
AJ
Note 1: Absolute Maximum Ratings indicate limits beyond which damage to the device may occur. Operating Ratings indicate conditions for which the device is
functional, but do not guarantee specific performance limits. For guaranteed specifications and test conditions, see the Electrical Characteristics. The guaranteed
specifications apply only for the test conditions listed. Some performance characteristics may degrade when the device is not operated under the listed test
conditions.
Note 2: All voltages are measured with respect to GND = AGND = DR GND = 0V, unless otherwise specified.
Note 3: When the input voltage at any pin exceeds the power supplies (that is, less thanAGND or DR GND, or greater than V
be limited to 25 mA. The 50 mA maximum package input current rating limits the number of pins that can safely exceed the power supplies with an input current of
25 mA to two.
Note 4: The absolute maximum junction temperature (T
junction-to-ambient thermal resistance (θ
for maximum power dissipation listed above will be reached only when this device is operated in a severe fault condition (e.g., when input or output pins are driven
beyond the power supply voltages, or the power supply polarity is reversed). Obviously, such conditions should always be avoided.
Note 5: Human body model is 100 pF capacitor discharged through a 1.5 kΩ resistor. Machine model is 220 pF discharged through ZERO Ohms.
Note 6: See AN-450, “Surface Mounting Methods and Their Effect on Product Reliability”.
Note 7: The analog inputs are protected as shown below. Input voltage magnitudes up to V
However, errors in the A/D conversion can occur if the input goes above V
voltage must be ≤2.8V
Sampling (Aperture) Delay CLK Rise to Acquisition of Data 2.6 ns
Aperture Jitter 2 ps rms
max) for this device is 150˚C. The maximum allowable power dissipation is dictated by TJmax, the
), and the ambient temperature (TA), and can be calculated using the formula PDMAX = (TJmax − TA)/θJA. The values
JA
to ensure accurate conversions.
DC
J
+ 300 mV or to 300 mV below GND will not damage this device.
or below GND by more than 100 mV. For example, if VAis 2.7VDCthe full-scale input
DR
A
= 200 MHz at 50% duty
CLK
Limits
(Note 9)
2.5 ns (min)
5 ns (max)
or VDR), the current at that pin should
A
Units
(Limits)
20017907
Note 8: To guarantee accuracy, it is required that VAand VDRbe well bypassed. Each supply pin must be decoupled with separate bypass capacitors.
Note 9: Typical figures are at T
Level).
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= 25˚C, and represent most likely parametric norms. Test limits are guaranteed to National’s AOQL (Average Outgoing Quality
J
Specification Definitions
APERTURE (SAMPLING) DELAY is that time required after
the rise of the clock input for the sampling switch to open.
The Sample/Hold circuit effectively stops capturing the input
signal and goes into the “hold” mode t
high.
APERTURE JITTER is the variation in aperture delay from
sample to sample. Aperture jitter shows up as input noise.
CLOCK DUTY CYCLE is the ratio of the time that the clock
wave form is at a logic high to the total time of one clock
period.
DIFFERENTIAL NON-LINEARITY (DNL) is the measure of
the maximum deviation from the ideal step size of 1 LSB.
Measured at 200 MSPS with a ramp input.
EFFECTIVE NUMBER OF BITS (ENOB, or EFFECTIVE
BITS) is another method of specifying Signal-to-Noise and
Distortion Ratio, or SINAD. ENOB is defined as (SINAD –
1.76) / 6.02 and says that the converter is equivalent to a
perfect ADC of this (ENOB) number of bits.
FULL POWER BANDWIDTH is a measure of the frequency
at which the reconstructed output fundamental drops 3 dB
below its low frequency value for a full scale input.
FULL-SCALE ERROR is a measure of how far the last code
transition is from the ideal 1
1
⁄2LSB below VRTand is defined
as:
+ 1.5 LSB – V
V
max
where V
is the voltage at which the transition to the
max
maximum (full scale) code occurs.
INTEGRAL NON-LINEARITY (INL) is a measure of the
deviation of each individual code from a line drawn from zero
1
⁄2LSB below the first code transition) through positive
scale (
full scale (
1
⁄2LSB above the last code transition). The deviation of any given code from this straight line is measured
from the center of that code value. The end point test method
is used. Measured at 200 MSPS with a ramp input.
INTERMODULATION DISTORTION (IMD) is the creation of
additional spectral components as a result of two sinusoidal
frequencies being applied to the ADC input at the same time.
it is defined as the ratio of the power in the second and third
order intermodulation products to the power in one of the
original frequencies. IMD is usually expressed in dBFS.
MISSING CODES are those output codes that are skipped
and will never appear at the ADC outputs. These codes
cannot be reached with any input value.
OUTPUT DELAY is the time delay after the rising edge of
the input clock before the data update is present at the
output pins.
OUTPUT HOLD TIME is the length of time that the output
data is valid after the rise of the input clock.
PIPELINE DELAY (LATENCY) is the number of clock cycles
between initiation of conversion and when that data is pre-
after the clock goes
AD
RT
sented to the output driver stage. New data is available at
every clock cycle, but the data lags the conversion by the
Pipeline Delay plus the Output Delay.
POWER SUPPLY REJECTION RATIO (PSRR) is a measure of how well the ADC rejects a change in the power
supply voltage. For the ADC08200, PSRR1 is the ratio of the
change in Full-Scale Error that results from a change in the
d.c. power supply voltage, expressed in dB. PSRR2 is a
measure of how well an a.c. signal riding upon the power
supply is rejected from the output and is here defined as
where SNR0 is the SNR measured with no noise or signal on
the supply line and SNR1 is the SNR measured with a
1 MHz, 200 mV
signal riding upon the supply lines.
P-P
SIGNAL TO NOISE RATIO (SNR) is the ratio, expressed in
dB, of the rms value of the input signal at the output to the
rms value of the sum of all other spectral components below
one-half the sampling frequency, not including harmonics or
d.c.
SIGNAL TO NOISE PLUS DISTORTION (S/(N+D) or
SINAD) is the ratio, expressed in dB, of the rms value of the
input signal at the output to the rms value of all of the other
spectral components below half the clock frequency, including harmonics but excluding d.c.
SPURIOUS FREE DYNAMIC RANGE (SFDR) is the difference, expressed in dB, between the rms values of the input
signal at the output and the peak spurious signal, where a
spurious signal is any signal present in the output spectrum
that is not present at the input.
TOTAL HARMONIC DISTORTION (THD) is the ratio expressed in dB, of the rms total of the first nine harmonic
levels at the output to the level of the fundamental at the
output. THD is calculated as
where Af1is the RMS power of the fundamental (output)
frequency and A
through A
f2
are the RMS power of the
f10
first 9 harmonic frequencies in the output spectrum
ZERO SCALE OFFSET ERROR is the error in the input
voltage required to cause the first code transition. It is defined as
V
OFF=VZT−VRB
where VZTis the first code transition input voltage.
ADC08200
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Timing Diagram
ADC08200
20017931
FIGURE 1. ADC08200 Timing Diagram
Typical Performance Characteristics
wise stated
INL INL vs. Temperature
20017908
INL vs. Supply Voltage INL vs. Sample Rate
VA=VDR= 3V, f
= 200 MHz, fIN= 50 MHz, unless other-
CLK
20017914
20017915 20017910
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ADC08200
Typical Performance Characteristics V
otherwise stated (Continued)
DNL DNL vs. Temperature
20017909
DNL vs. Supply Voltage DNL vs. Sample Rate
A=VDR
= 3V, f
= 200 MHz, fIN= 50 MHz, unless
CLK
20017917
20017918
SNR vs. Temperature SNR vs. Supply Voltage
20017920 20017921
20017911
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Typical Performance Characteristics V
otherwise stated (Continued)
A=VDR
= 3V, f
= 200 MHz, fIN= 50 MHz, unless
CLK
ADC08200
SNR vs. Sample Rate SNR vs. Input Frequency
20017912
SNR vs. Clock Duty Cycle Distortion vs. Temperature
20017923
20017924 20017925
Distortion vs. Supply Voltage Distortion vs. Sample Rate
20017926
20017913
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ADC08200
Typical Performance Characteristics V
otherwise stated (Continued)
Distortion vs. Input Frequency Distortion vs. Clock Duty Cycle
20017928 20017929
SINAD/ENOB vs. Temperature SINAD/ENOB vs. Supply Voltage
A=VDR
= 3V, f
= 200 MHz, fIN= 50 MHz, unless
CLK
20017930
SINAD/ENOB vs. Sample Rate SINAD/ENOB vs. Input Frequency
20017916
20017938
20017939
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Typical Performance Characteristics V
otherwise stated (Continued)
A=VDR
= 3V, f
= 200 MHz, fIN= 50 MHz, unless
CLK
ADC08200
SINAD/ENOB vs. Clock Duty Cycle Power Consumption vs. Sample Rate
20017940
20017919
Spectral Response@fIN= 50 MHz Spectral Response@fIN=76MHz
20017946 20017947
Spectral Response@fIN= 99 MHz Intermodulation Distortion
20017948
20017943
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Functional Description
The ADC08200 uses a new, unique architecture that
achieves over 7 effective bits at input frequencies up to and
beyond 100 MHz.
The analog input signal that is within the voltage range set by
and VRBis digitized to eight bits. Input voltages below
V
RT
will cause the output word to consist of all zeroes. Input
V
RB
voltages above V
all ones.
Incorporating a switched capacitor bandgap, the ADC08200
exhibits a power consumption that is proportional to frequency, limiting power consumption to what is needed at the
clock rate that is used. This and its excellent performance
over a wide range of clock frequencies makes it an ideal
choice as a single ADC for many 8-bit needs.
Data is acquired at the rising edge of the clock and the digital
equivalent of that data is available at the digital outputs 6
clock cycles plus t
long as the clock signal is present.
The device is in the active state when the Power Down pin
(PD) is low. When the PD pin is high, the device is in the
will cause the output word to consist of
RT
later. The ADC08200 will convert as
OD
power down mode, where the output pins hold the last
conversion before the PD pin went high and the device
consumes just 1.4 mW . Holding the clock input low will
further reduce the power consumption in the power down
mode to about 1 mW.
Applications Information
1.0 REFERENCE INPUTS
The reference inputs V
the reference ladder, respectively. Input signals between
these two voltages will be digitized to 8 bits. External voltages applied to the reference input pins should be within the
range specified in the Operating Ratings table (0.5V to (V
0.3V) for V
and −100 mV to (VRT− 0.5V) for VRB). Any
RT
device used to drive the reference pins should be able to
source sufficient current into the V
current from the V
and VRBare the top and bottom of
RT
pin and sink sufficient
pin.
RB
RT
A
ADC08200
−
20017932
FIGURE 2. Simple, low component count reference biasing. Because of the ladder and external resistor tolerances,
the reference voltage of this circuit can vary too much for some applications.
The reference bias circuit of Figure 2 is very simple and the
performance is adequate for many applications. However,
circuit tolerances will lead to a wide reference voltage range.
Better reference stability can be achieved by driving the
reference pins with low impedance sources.
The circuit of Figure 3 will allow a more accurate setting of
the reference voltages. The lower amplifier must have bipolar supplies as its output voltage must go negative to force
to any voltage below the VBEof the PNP transistor. Of
V
RB
course, the divider resistors at the amplifier input could be
changed to suit your reference voltage needs, or the divider
can be replaced with potentiometers for precise settings.
The bottom of the ladder (V
ground if the minimum input signal excursion is 0V. Be sure
that the driving source can source sufficient current into the
pin and sink enough current from the VRBpin to keep
V
RT
these pins stable.
The LMC662 amplifier shown was chosen for its low offset
voltage and low cost. V
more positive than V
The V
pin is the center of the reference ladder and should
RM
RB
be bypassed to a quiet point in the analog ground plane with
a 0.1 µF capacitor. DO NOT leave this pin open.
) may simply be returned to
RB
should always be at least 0.5V
RT
to minimize noise.
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Applications Information (Continued)
ADC08200
FIGURE 3. Driving the reference to force desired values requires driving with a low impedance source.
2.0 THE ANALOG INPUT
The analog input of the ADC08200 is a switch followed by an
integrator. The input capacitance changes with the clock
level, appearing as 3 pF when the clock is low, and 4 pF
when the clock is high. Since a dynamic capacitance is more
difficult to drive than is a fixed capacitance, choose an
amplifier that can drive this type of load.
Figure 4 shows an example of an input circuit using the
LMH6702. Any input amplifier should incorporate some gain
as operational amplifiers exhibit better phase margin and
transient response with gains above 2 or 3 than with unity
gain. If an overall gain of less than 3 is required, attenuate
the input and operate the amplifier at a higher gain, as
shown in Figure 4.
The RC at the amplifier output filters the clock rate energy
that comes out of the analog input due to the input sampling
circuit. The optimum time constant for this circuit depends
not only upon the amplifier and ADC, but also on the circuit
layout and board material. A resistor value should be chosen
between 18Ω and 47Ω and the capacitor value chose according to the formula
20017933
This will provide optimum SNR performance. Best THD performance is realized when the capacitor and resistor values
are both zero. To optimize SINAD, reduce the capacitor
value until SINAD performance is optimized. That is, until
SNR = −THD. This value will usually be in the range of 20%
to 65% of the value calculated with the above formula. An
accurate calculation is not possible because of the board
material and layout dependence.
The circuit of Figure 4 has both gain and offset adjustments.
If you eliminate these adjustments normal circuit tolerances
may result in signal clipping unless care is exercised in the
worst case analysis of component tolerances and the input
signal excursion is appropriately limited to account for the
worst case conditions.
www.national.com 14
Applications Information (Continued)
ADC08200
FIGURE 4. The input amplifier should incorporate some gain for best performance (see text).
3.0 POWER SUPPLY CONSIDERATIONS
A/D converters draw sufficient transient current to corrupt
their own power supplies if not adequately bypassed. A
10 µF tantalum or aluminum electrolytic capacitor should be
placed within an inch (2.5 cm) of the A/D power pins, with a
0.1 µF ceramic chip capacitor placed within one centimeter
of the converter’s power supply pins. Leadless chip capacitors are preferred because they have low lead inductance.
While a single voltage source is recommended for the V
and VDRsupplies of the ADC08200, these supply pins
should be well isolated from each other to prevent any digital
noise from being coupled into the analog portions of the
ADC. A choke or 27Ω resistor is recommended between
these supply lines with adequate bypass capacitors close to
the supply pins.
As is the case with all high speed converters, the ADC08200
should be assumed to have little power supply rejection.
None of the supplies for the converter should be the supply
that is used for other digital circuitry in any system with a lot
of digital power being consumed. The ADC supplies should
be the same supply used for other analog circuitry.
No pin should ever have a voltage on it that is in excess of
the supply voltage or below ground by more than 300 mV,
not even on a transient basis. This can be a problem upon
application of power and power shut-down. Be sure that the
supplies to circuits driving any of the input pins, analog or
digital, do not come up any faster than does the voltage at
the ADC08200 power pins.
20017934
4.0 THE DIGITAL INPUT PINS
The ADC08200 has two digital input pins: The PD pin and
the Clock pin.
4.1 The PD Pin
The Power Down (PD) pin, when high, puts the ADC08200
into a low power mode where power consumption is reduced
to about 1.4 mW with the clock running, or to about 1 mW
A
with the clock held low. Output data is valid and accurate
about 1 microsecond after the PD pin is brought low.
The digital output pins retain the last conversion output code
when either the clock is stopped or the PD pin is high.
4.2 The ADC08200 Clock
Although the ADC08200 is tested and its performance is
guaranteed with a 200 MHz clock, it typically will function
well with clock frequencies from 10 MHz to 230 MHz.
The low and high times of the clock signal can affect the
performance of any A/D Converter. Because achieving a
precise duty cycle is difficult, the ADC08200 is designed to
maintain performance over a range of duty cycles. While it is
specified and performance is guaranteed with a 50% clock
duty cycle and 200 Msps, ADC08200 performance is typically maintained with clock high and low times of 0.65 ns and
0.87 ns, respectively, corresponding to a clock duty cycle
range of 13% to 82.5% with a 200 MHz clock. Note that
minimum low and high times may not be simultaneously
asserted.
www.national.com15
Applications Information (Continued)
The CLOCK line should be series terminated at the clock
source in the characteristic impedance of that line if the clock
ADC08200
line is longer than
The analog input should be isolated from noisy signal traces
to avoid coupling of spurious signals into the input. Any
external component (e.g., a filter capacitor) connected between the converter’s input and ground should be connected
to a very clean point in the analog ground plane.
where tris the clock rise time and t
of the signal along the trace. Typical t
is the propagation rate
prop
is about 150
prop
ps/inch (59 ps/cm) on FR-4 board material.
If the clock source is used to drive more than just the
ADD08200, the CLOCK pin should be a.c. terminated with a
series RC to ground such that the resistor value is equal to
the characteristic impedance of the clock line and the capacitor value is
where tPDis the signal propagation rate down the clock line,
"L" is the line length and Z
is the characteristic impedance
O
of the clock line. This termination should be located as close
as possible to, but within one centimeter of, the ADC08200
clock pin. Further, this termination should be close to but
beyond the ADC08200 clock pin as seen from the clock
source. Typical t
is about 150 ps/inch on FR-4 board
prop
material. For FR-4 board material, the value of C becomes
Where L is the length of the clock line in inches.
This termination should be located as close as possible to,
but within one centimeter of, the ADC08200 clock pin.
5.0 LAYOUT AND GROUNDING
Proper grounding and proper routing of all signals are essential to ensure accurate conversion. A combined analog
and digital ground plane should be used.
Since digital switching transients are composed largely of
high frequency components, total ground plane copper
weight will have little effect upon the logic-generated noise
because of the skin effect. Total surface area is more important than is total ground plane volume. Capacitive coupling
between the typically noisy digital circuitry and the sensitive
analog circuitry can lead to poor performance that may seem
impossible to isolate and remedy. The solution is to keep the
analog circuitry well separated from the digital circuitry.
High power digital components should not be located on or
near a straight line between the ADC or any linear component and the power supply area as the resulting common
return current path could cause fluctuation in the analog
input “ground” return of the ADC.
Generally, analog and digital lines should cross each other at
90˚ to avoid getting digital noise into the analog path. In high
frequency systems, however, avoid crossing analog and
digital lines altogether. Clock lines should be isolated from
ALL other lines, analog AND digital. Even the generally
accepted 90˚ crossing should be avoided as even a little
coupling can cause problems at high frequencies. Best performance at high frequencies is obtained with a straight
signal path.
20017936
FIGURE 5. Layout Example
Figure 5 gives an example of a suitable layout. All analog
circuitry (input amplifiers, filters, reference components, etc.)
should be placed together away from any digital components.
6.0 DYNAMIC PERFORMANCE
The ADC08200 is a.c. tested and its dynamic performance is
guaranteed. To meet the published specifications, the clock
source driving the CLK input must exhibit less than 2 ps
(rms) of jitter. For best a.c. performance, isolating the ADC
clock from any digital circuitry should be done with adequate
buffers, as with a clock tree. See Figure 6.
It is good practice to keep the ADC clock line as short as
possible and to keep it well away from any other signals.
Other signals can introduce jitter into the clock signal. The
clock signal can also introduce noise into the analog path.
20017937
FIGURE 6. Isolating the ADC Clock from Digital
Circuitry
7.0 COMMON APPLICATION PITFALLS Driving the inputs (analog or digital) beyond the power
supply rails. For proper operation, all inputs should not go
more than 300 mV below the ground pins or 300 mV above
www.national.com 16
Applications Information (Continued)
the supply pins. Exceeding these limits on even a transient
basis may cause faulty or erratic operation. It is not uncommon for high speed digital circuits (e.g., 74F and 74AC
devices) to exhibit undershoot that goes more than a volt
below ground. A 51Ω resistor in series with the offending
digital input will usually eliminate the problem.
Care should be taken not to overdrive the inputs of the
ADC08200. Such practice may lead to conversion inaccuracies and even to device damage.
Attempting to drive a high capacitance digital data bus.
The more capacitance the output drivers must charge for
each conversion, the more instantaneous digital current is
required from V
rent spikes can couple into the analog section, degrading
dynamic performance. Buffering the digital data outputs (with
a 74AF541, for example) may be necessary if the data bus
capacitance exceeds 5 pF. Dynamic performance can also
be improved by adding 100Ω series resistors at each digital
output, reducing the energy coupled back into the converter
input pins.
and DR GND. These large charging cur-
DR
Using an inadequate amplifier to drive the analog input.
As explained in Section 2.0, the capacitance seen at the
input alternates between 3 pF and 4 pF with the clock. This
dynamic capacitance is more difficult to drive than is a fixed
capacitance, and should be considered when choosing a
driving device.
Driving the V
pin or the VRBpin with devices that can
RT
not source or sink the current required by the ladder. As
mentioned in Section 1.0, care should be taken to see that
any driving devices can source sufficient current into the V
RT
pin and sink sufficient current from the VRBpin. If these pins
are not driven with devices than can handle the required
current, these reference pins will not be stable, resulting in a
reduction of dynamic performance.
Using a clock source with excessive jitter, using an
excessively long clock signal trace, or having other
signals coupled to the clock signal trace. This will cause
the sampling interval to vary, causing excessive output noise
and a reduction in SNR performance. The use of simple
gates with RC timing is generally inadequate as a clock
source.
ADC08200
www.national.com17
Physical Dimensions inches (millimeters)
unless otherwise noted
NOTES: UNLESS OTHERWISE SPECIFIED
REFERENCE JEDEC REGISTRATION mo-153, VARIATION AD, DATED 7/93.
24-Lead Package TC
Order Number ADC08200CIMT
NS Package Number MTC24
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ADC08200 8-Bit, 20 MSPS to 200 MSPS, 1.05 mW/MSPS A/D Converter
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www.national.com
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