Rainbow Electronics ADC0820 User Manual

ADC0820 8-Bit High Speed mP Compatible A/D Converter with Track/Hold Function

February 1995

General Description

By using a half-flash conversion technique, the 8-bit ADC0820 CMOS A/D offers a 1.5 ms conversion time and dissipates only 75 mW of power. The half-flash technique consists of 32 comparators, a most significant 4-bit ADC and a least significant 4-bit ADC.

The input to the ADC0820 is tracked and held by the input sampling circuitry eliminating the need for an external sample-and-hold for signals moving at less than 100 mV/ms.

For ease of interface to microprocessors, the ADC0820 has been designed to appear as a memory location or I/O port without the need for external interfacing logic.

Key Specifications

Y

Resolution 8 Bits

Y

Conversion Time 2.5 ms Max (RD Mode)

1.5 ms Max (WR-RD Mode)

Y

Input signals with slew rate of 100 mV/ms converted without external sample-and-hold to 8 bits

Y

Low Power 75 mW Max

Y

Total Unadjusted Error

g

(/2 LSB andg1 LSB

Connection and Functional Diagrams

Dual-In-Line, Small Outline and

SSOP Packages

Features

Y

Built-in track-and-hold function

Y

No missing codes

Y

No external clocking

Y

Single supplyÐ5 V

Y

Easy interface to all microprocessors, or operates stand-alone

Y

Latched TRI-STATEÉoutput

Y

Logic inputs and outputs meet both MOS and T2L voltage level specifications

Y

Operates ratiometrically or with any reference value equal to or less than V

Y

0V to 5V analog input voltage range with single 5V supply

Y

No zero or full-scale adjust required

Y

Overflow output available for cascading

Y

0.3×standard width 20-pin DIP

Y

20-pin molded chip carrier package

Y

20-pin small outline package

Y

20-pin shrink small outline package (SSOP)

DC

CC

Top View

TL/H/5501– 1

Molded Chip Carrier

Package

FIGURE 1

TL/H/5501– 2

TRI-STATEÉis a registered trademark of National Semiconductor Corporation.

C

1995 National Semiconductor Corporation RRD-B30M115/Printed in U. S. A.

TL/H/5501– 33

TL/H/5501

See Ordering Information

Absolute Maximum Ratings (Notes1&2)

If Military/Aerospace specified devices are required, please contact the National Semiconductor Sales Office/Distributors for availability and specifications.

Supply Voltage (V

Logic Control Inputs

Voltage at Other Inputs and Output

Storage Temperature Range

Package Dissipation at T

) 10V

CC

e

A

b

0.2V to V

b

CC

0.2V to V

CC

b

65§Ctoa150§C

25§C 875 mW

a

0.2V

a

0.2V

Input Current at Any Pin (Note 5) 1 mA

Package Input Current (Note 5) 4 mA

ESD Susceptability (Note 9) 1200V

Converter Characteristics The following specifications apply for RD mode (pin 7

and V

Resolution 8 8 8 Bits

Total Unadjusted ADC0820BCN, BCWM Error ADC0820CCJ (Note 3) ADC0820CCN, CCWM, CIWM,

Minimum Reference 2.3 1.00 2.3 1.2 kX Resistance

Maximum Reference 2.3 6 2.3 5.3 6 kX Resistance

Maximum V Input Voltage

Minimum V Input Voltage

Maximum V Input Voltage

Maximum VINInput V Voltage

Minimum VINInput GNDb0.1 GNDb0.1 GNDb0.1 V Voltage

Maximum Analog CSeV Input Leakage V Current V

Power Supply V Sensitivity

(b)eGND unless otherwise specified. Boldface limits apply from T

REF

Parameter Conditions

Typ

(Note 6)

ADC0820CCMSA

(a) V

REF

(b) GND GND GND V

REF

(a) V

REF

(b) V

REF

CC

e

V

IN

CC

e

GND

IN

CC

e

5Vg5%

g

(/16

Lead Temp. (Soldering, 10 sec.)

Dual-In-Line Package (plastic) 260 Dual-In-Line Package (ceramic) 300 Surface Mount Package

Vapor Phase (60 sec.) 215 Infrared (15 sec.) 220

Operating Ratings (Notes1&2)

Temperature Range T

ADC0820CCJ ADC0820CIWM ADC0820BCN, ADC0820CCN 0 ADC0820BCV, ADC0820CCV 0 ADC0820BCWM, ADC0820CCWM 0 ADC0820CCMSA 0

VCCRange 4.5V to 8V

e

MIN

to T

0), V

; all other limits T

MAX

ADC0820BCN, ADC0820CCN

ADC0820CCJ

ADC0820BCV, ADC0820CCV ADC0820BCWM, ADC0820CCWM ADC0820CCMSA, ADC0820CIWM

Tested Design

Limit Limit

(Note 7) (Note 8) (Note 7) (Note 8)

g

1 LSB

CC

(b) V

REF

(a) V

REF

a

0.1 V

CC

Typ (Note 6)

Tested Design

Limit Limit

g

V

REF

CC

3 0.3 3 mA

b

3

g

(/4

g

(/16

b

g

b b

e

CC

(/2

1 1

CC

(b) V

(a) V

a

0.1 V

0.3

(/4

MIN

40§CsT 40§CsT

5V, V

s

T

A

s

A

s

A

CsT

§

A

CsT

§

A

CsT

§

A

CsT

§

A

(a)e5V,

REF

e

T

A

j

g

(/2 LSB

g

1 LSB

g

1 LSB

V

CC

(b) V

REF

(a) V

REF

a

0.1 V

CC

b

3 mA

g

(/4 LSB

s

a a

s s s s

e

T

MAX

85§C 85§C 70§C 70§C 70§C 70§C

25§C.

Limit Units

C

§

C

§

C

§

C

§

V

2

DC Electrical Characteristics The following specifications apply for V

Boldface limits apply from T

MIN

to T

MAX

; all other limits T

e

T

25§C.

A

J

ADC0820CCJ

Parameter Conditions

Tested Design

V

, Logical ‘‘1’’ V

IN(1)

Input Voltage

V

, Logical ‘‘0’’ V

IN(0)

Input Voltage

I

, Logical ‘‘1’’ V

IN(1)

Input Current V

I

, Logical ‘‘0’’ V

IN(0)

Input Current Mode

V

, Logical ‘‘1’’ V

OUT(1)

Output Voltage DB0– DB7, OFL, INT

V

, Logical ‘‘0’’ V

OUT(0)

Output Voltage DB0– DB7, OFL

I

, TRI-STATE V

OUT

Output Current V

I

, Output V

SOURCE

Source Current INT

I

, Output Sink V

SINK

Current INT, RDY

ICC, Supply Current CS

e

5.25V CS,WR,RD 2.0 2.0 2.0 V

CC

e

4.75V CS,WR,RD 0.8 0.8 0.8 V

CC

e

5V; CS,RD 0.005 1 0.005 1 mA

IN(1)

e

5V; WR 0.1 3 0.1 0.3 3 mA

IN(1)

e

V

5V; Mode 50 200 50 170 200 mA

IN(1)

e

0V; CS,RD,WR,

IN(0)

e

4.75V, I

CC

e

V

CC

DB0–DB7, OFL

e

CC

OUT

eWReRDe

OUT

4.75V, I

OUT

, INT

4.75V, I

OUT

, INT, RDY

e

5V; DB0–DB7, RDY 0.1 3 0.1 0.3 3 mA

e

0V; DB0–DB7, RDY

e

0V; DB0–DB7, OFL

e

5V; DB0–DB7, OFL,147 14 8.4 7 mA

0 7.5 15 7.5 13 15 mA

Typ

(Note 6)

Mode 3.5 3.5 3.5 V

Mode 1.5 1.5 1.5 V

b

eb

360 mA; 2.4 2.8 2.4 V

eb

10 mA; 4.5 4.6 4.5 V

e

1.6 mA; 0.4 0.34 0.4 V

b

Limit Limit

(Note 7) (Note 8) (Note 7) (Note 8)

0.1

12

b

1

b

3

b

6

b

9

4.0

0.005

b

e

5V, unless otherwise specified.

CC

ADC0820BCN, ADC0820CCN

ADC0820BCV, ADC0820CCV ADC0820BCWM, ADC0820CCWM ADC0820CCMSA, ADC0820CIWM

Typ

(Note 6)

b

0.005

b

Tested Design

Limit Limit

0.1

12

b

b b

9

0.3

7.2

5.3

b

1 mA

b

3 mA

b

6 mA

b

4.0 mA

Limit Units

AC Electrical Characteristics The following specifications apply for V

V

(b)e0V and T

REF

t

, Conversion Time for RD Mode Pin 7e0,

CRD

t

, Access Time (Delay from Pin 7e0,

ACC0

Falling Edge of RD

t

, Conversion Time for Pin 7eVCC;t

CWR-RD

WR-RD Mode t

tWR, Write Time Min Pin 7eVCC;

e

25§C unless otherwise specified.

A

Parameter Conditions

(Figure 2)

to Output Valid)

600 ns;

WR

(Figures 3a

RD

e

(Figures 3a

(Note 6)

t

CRD

600 ns, 1.52 ms

and

3b)

and

3b)

Max (Note 4) See Graph 50 ms

tRD, Read Time Min Pin 7eVCC;

(Figures 3a

and

3b)

(Note 4) See Graph

e

1k and C

RD

k

tI;

(Figure 3a)

l

tI;

(Figure 3b)

e

15 pF 30 ns

L

t

, Access Time (Delay from Pin 7eVCC,t

ACC1

Falling Edge of RD to Output Valid) C

C

t

, Access Time (Delay from Pin 7eVCC,t

ACC2

Falling Edge of RD to Output Valid) C

C

t

, Access Time (Delay from Rising R

ACC3

Edge of RDY to Output Valid)

e

15 pF 190 280 ns

L

e

100 pF 210 320 ns

L

e

15 pF 70 120 ns

L

e

100 pF 90 150 ns

L

PULLUP

3

e

5V, t

t

Typ

CC

20 ns, V

r

f

Tested Design

Limit Limit Units

REF

(a)e5V,

(Note 7) (Note 8)

1.6 2.5 ms

a

20 t

CRD

a

50 ns

600 ns

e

AC Electrical Characteristics (Continued) The following specifications apply for V

V

(a)e5V, V

REF

tI, Internal Comparison Time Pin 7eVCC;

t1H,t0H, TRI-STATE Control R (Delay from Rising Edge of RD

(b)e0V and T

REF

Parameter Conditions

e

25§C unless otherwise specified.

A

e

C

50 pF

L

e

1k, C

L

to

L

Typ

(Note 6)

(Figures 3b

e

10 pF 100 200 ns

and

4)

800 1300 ns

Tested Design

Limit Limit Units

(Note 7) (Note 8)

CC

5V, t

e

t

20 ns,

r

f

Hi-Z State)

t

, Delay from Rising Edge of Pin 7eVCC,C

INTL

WR

to Falling Edge of INT t

t

, Delay from Rising Edge of

INTH

RD

to Rising Edge of INT C

t

, Delay from Rising Edge of

INTHWR

WR

to Rising Edge of INT

t

, Delay from CS to RDY

RDY

tID, Delay from INT to Output Valid

l

tI;

RD

k

t

tI;

RD

(Figures 2, 3a

e

50 pF

L

(Figure 4)

(Figure 2)

(Figure 4)

tRI, Delay from RD to INT Pin 7eVCC,t

(Figure 3a)

tP, Delay from End of Conversion

(Figures 2, 3a, 3b

e

50 pF

L

(Figure 3b) (Figure 3a)

and

3b)

e

,C

50 pF 175 270 ns

L

e

,C

50 pF, Pin 7e0 50 100 ns

L

a

t

200 t

RD

125 225 ns

20 50 ns

k

RD

t

I

and

4)

200 290 ns

t

I

a

290 ns

RD

500 ns

ns

to Next Conversion (Note 4) See Graph

Slew Rate, Tracking 0.1 V/ms

C

, Analog Input Capacitance 45 pF

VIN

C

, Logic Output Capacitance 5 pF

OUT

CIN, Logic Input Capacitance 5 pF

Note 1: Absolute Maximum Ratings indicate limits beyond which damage to the device may occur. DC and AC electrical specifications do not apply when operating the device beyond its specified operating conditions.

Note 2: All voltages are measured with respect to the GND pin, unless otherwise specified.

Note 3: Total unadjusted error includes offset, full-scale, and linearity errors.

Note 4: Accuracy may degrade if t

Note 5: When the input voltage (V

to 1 mA or less. The 4 mA package input current limits the number of pins that can exceed the power supply boundaries witha1mAcurrent limit to four.

Note 6: Typicals are at 25

Note 7: Tested limits are guaranteed to National’s AOQL (Average Outgoing Quality Level).

Note 8: Design limits are guaranteed but not 100% tested. These limits are not used to calculate outgoing quality levels.

Note 9: Human body model, 100 pF discharaged through a 1.5 kX resistor.

§

or tRDis shorter than the minimum value specified. See Accuracy vs tWRand Accuracy vs tRDgraphs.

WR

) at any pin exceeds the power supply rails (V

IN

C and represent most likely parametric norm.

k

IN

Vbor V

l

Va) the absolute value of current at that pin should be limited

IN

TRI-STATE Test Circuits and Waveforms

t

1H

TL/H/5501– 3

t

0H

TL/H/5501– 5

4

TL/H/5501– 4

e

t

20 ns TL/H/5501 – 6

r

Timing Diagrams

Note: On power-up the state of INT can be high or low.

FIGURE 3a. WR-RD Mode (Pin 7 is High and t

FIGURE 2. RD Mode (Pin 7 is Low)

RD

TL/H/5501– 7

TL/H/5501– 8

k

tI)

FIGURE 3b. WR-RD Mode (Pin 7 is High and t

RD

l

TL/H/5501– 10

FIGURE 4. WR-RD Mode (Pin 7 is High)

Stand-Alone Operation

TL/H/5501– 9

tI)

5

Typical Performance Characteristics

Logic Input Threshold Voltage vs Supply Voltage

Conversion Time (RD Mode) vs Temperature

Power Supply Current vs Temperature (not including reference ladder)

*1 LSB

e

Accuracy vs t

Accuracy vs V

e

[

V

REF

V

REF

256

WR

REF

(a)bV

REF

(b)

Accuracy vs t

RD

tI, Internal Time Delay vs

]

Temperature

Accuracy vs t

p

Output Current vs Temperature

TL/H/5501– 11

6