ADC08131/ADC08134/ADC08138 8-Bit High-Speed
Serial I/O A/D Converters with Multiplexer Options,
Voltage Reference, and Track/Hold Function
December 1994
ADC08131/ADC08134/ADC08138 8-Bit High-Speed Serial I/O A/D Converters
with Multiplexer Options, Voltage Reference, and Track/Hold Function
General Description
The ADC08131/ADC08134/ADC08138 are 8-bit successive approximation A/D converters with serial I/O and configurable input multiplexers with up to 8 channels. The serial
I/O is configured to comply with the NSC MICROWIRE
serial data exchange standard for easy interface to the
TM
COPS
family of controllers, and can easily interface with
standard shift registers or microprocessors.
All three devices provide a 2.5V band-gap derived reference
with guaranteed performance over temperature.
A track/hold function allows the analog voltage at the positive input to vary during the actual A/D conversion.
The analog inputs can be configured to operate in various
combinations of single-ended, differential, or pseudo-differential modes. In addition, input voltage spans as small as 1V
can be accommodated.
Applications
Y
Digitizing automotive sensors
Y
Process control/monitoring
Y
Remote sensing in noisy environments
Y
Embedded diagnostics
Ordering Information
Industrial
b
(
40§CsT
s
a
85§C)
A
ADC08131BIN, ADC08131CIN N08E
ADC08134BIN, ADC08134CIN N14A
ADC08138BIN, ADC08138CIN N20A
ADC08134BIWM, ADC08134CIWM M14B
ADC08138BIWM, ADC08138CIWM M20B
Package
Features
Y
Serial digital data link requires few I/O pins
Y
Analog input track/hold function
Y
4- or 8-channel input multiplexer options with address
TM
logic
Y
On-chip 2.5V band-gap reference (g2% over temperature guaranteed)
Y
No zero or full scale adjustment required
Y
TTL/CMOS input/output compatible
Y
0V to 5V analog input range with single 5V power
supply
Key Specifications
Y
Resolution 8 Bits
Y
Conversion time (f
Y
Power dissipation 20 mW (Max)
Y
Single supply 5 VDC(
Y
Total unadjusted error
Y
Linearity Error (V
Y
No missing codes (over temperature)
Y
On-board Reference
e
1 MHz) 8 ms (Max)
C
g
(/2 LSB andg1 LSB
a
REF
e
2.5V)
Connection Diagrams
ADC08138
Dual-In-Line and
Small Outline
Packages
Dual-In-Line and
Small Outline
g
5%)
g
(/2 LSB
2.5Vg1.5% (Max)
ADC08134
Packages
TL/H/10749– 3
TL/H/10749– 2
ADC08131
Dual-In-Line Package
TRI-STATEÉis a registered trademark of National Semiconductor Corporation.
TM
COPS
microcontrollers and MICROWIRETMare trademarks of National Semiconductor Corporation.
C
1995 National Semiconductor Corporation RRD-B30M75/Printed in U. S. A.
TL/H/10749
TL/H/10749– 4
Absolute Maximum Ratings (Notes1&3)
If Military/Aerospace specified devices are required,
please contact the National Semiconductor Sales
Office/Distributors for availability and specifications.
Supply Voltage (V
Voltage at Inputs and Outputs
Input Current at Any Pin (Note 4)
Package Input Current (Note 4)
Power Dissipation at T
ESD Susceptibility (Note 6) 1500V
Soldering Information
N Package (10 sec.) 260
SO Package:
Vapor Phase (60 sec.) 215
Infrared (15 sec.) (Note 7) 220
Storage Temperature
) 6.5V
CC
e
25§C (Note 5) 800 mW
A
b
0.3V to V
b
65§Ctoa150§C
CC
g
a
0.3V
g
5mA
20 mA
§
§
§
Operating Ratings (Notes2&3)
Temperature Range T
ADC08131BIN, ADC08131CIN,
ADC08134BIN, ADC08134CIN,
ADC08138BIN, ADC08138CIN,
ADC08134BIWM, ADC08138BIWM,
ADC08134CIWM, ADC08138CIWM
Supply Voltage (V
C
C
C
) 4.5 VDCto 6.3 V
CC
b
40§CsT
MIN
s
s
T
T
A
MAX
s
a
85§C
A
DC
Electrical Characteristics
The following specifications apply for V
Boldface limits apply for T
e
T
A
ea
5VDC,V
CC
e
T
MIN
to T
MAX
J
ea
REF
; all other limits T
2.5 VDCand f
e
CLK
e
e
T
A
25§C.
J
ADC08131,
ADC08134 and
ADC08138 with BIN,
Symbol Parameter Conditions CIN, BIWM or
CIWM Suffixes
Typical Limits
(Note 8) (Note 9)
CONVERTER AND MULTIPLEXER CHARACTERISTICS
Linearity Error V
BIN, BIWM
REF
ea
2.5 V
DC
CIN, CIWM
Full Scale Error V
BIN, BIWM
REF
ea
2.5 V
DC
CIN, CIWM
Zero Error V
BIN, BIWM
REF
ea
2.5 V
DC
CIN, CIWM
Total Unadjusted Error V
BIN, BIWM (Note 10)
REF
ea
5V
DC
CIN, CIWM
Differential Linearity V
R
REF
V
IN
Reference Input Resistance (Note 11) 3.5 kX
Analog Input Voltage (Note 12) (V
REF
ea
2.5 V
DC
1 MHz unless otherwise specified.
Units
(Limits)
g
(/2 LSB (max)
g
1 LSB (max)
g
(/2 LSB (max)
g
1 LSB (max)
g
1 LSB (max)
g
1 LSB (max)
g
(/2 LSB (max)
g
1 LSB (max)
8 Bits (min)
1.3 kX (min)
6.0 kX (max)
a
0.05) V (max)
CC
b
(GND
0.05) V (min)
2
Electrical Characteristics (Continued)
The following specifications apply for V
Boldface limits apply for T
e
T
A
ea
5VDC,V
CC
e
T
MIN
to T
MAX
J
ea
REF
; all other limits T
2.5 VDCand f
e
CLK
e
e
T
A
25§C.
J
ADC08131,
ADC08134 and
ADC08138 with BIN,
Symbol Parameter Conditions CIN, BIWM or
CIWM Suffixes
Typical Limits
(Note 8) (Note 9)
CONVERTER AND MULTIPLEXER CHARACTERISTICS (Continued)
DC Common-Mode Error V
Power Supply Sensitivity V
e
2.5 V
REF
CC
V
REF
ea
ea
DC
5Vg5%,
2.5 V
DC
On Channel Leakage On Channele5V, 0.2
Current (Note 13) Off Channel
e
0V 1
On Channele0V,
Off Channele5V
Off Channel Leakage On Channele5V,
Current (Note 13) Off Channel
e
0V
On Channele0V, 0.2
Off Channel
e
5V 1
DIGITAL AND DC CHARACTERISTICS
V
IN(1)
V
IN(0)
I
IN(1)
I
IN(0)
V
OUT(1)
V
OUT(0)
I
OUT
I
SOURCE
I
SINK
I
CC
Logical ‘‘1’’ Input Voltage V
Logical ‘‘0’’ Input Voltage V
Logical ‘‘1’’ Input Current V
Logical ‘‘0’’ Input Current V
Logical ‘‘1’’ Output Voltage V
Logical ‘‘0’’ Output Voltage V
TRI-STATEÉOutput Current V
Output Source Current V
Output Sink Current V
Supply Current CSeHIGH
ADC08134, ADC08138 3.0 mA (max)
e
5.25V 2.0 V (min)
CC
e
4.75V 0.8 V (max)
CC
e
5.0V 1 mA (max)
IN
e
0V
IN
e
4.75V:
CC
eb
I
I
I
V
360 mA 2.4 V (min)
OUT
eb
10 mA 4.5 V (min)
OUT
e
4.75V 0.4 V (max)
CC
e
1.6 mA
OUT
e
0V
OUT
e
5V 3.0 mA (max)
OUT
e
0V
OUT
e
V
OUT
CC
ADC08131 (Note 16) 6.0 mA (max)
1 MHz unless otherwise specified.
Units
(Limits)
g
(/2 LSB (max)
g
(/4 LSB (max)
mA (max)
b
0.2
b
1
b
0.2
b
1
mA (max)
mA (max)
mA (max)
b
1 mA (max)
b
3.0 mA (max)
b
6.5 mA (min)
8.0 mA (min)
3
Electrical Characteristics (Continued)
The following specifications apply for V
e
T
e
T
T
to T
A
J
MIN
; all other limits T
MAX
CC
ea
A
5VDCand f
e
e
T
J
25§C.
e
1 MHz unless otherwise specified. Boldface limits apply for
CLK
ADC08131,
ADC08134 and
ADC08138 with BIN,
Symbol Parameter Conditions CIN, BIWM or
CIWM Suffixes
Typical Limits
(Note 8) (Note 9)
REFERENCE CHARACTERISTICS
V
OUT Output Voltage ADC08134, 2.5
REF
ADC08138
g
2%
ADC08131 2.5
g
2%
DV
/DT Temperature Coefficient 40 ppm/§C
REF
DV
REF
/DI
Load Regulation Sourcing
L
(Note 17) (0sI
s
L
ADC08134,
ADC08138
a
4 mA)
0.003 0.1
Sourcing
s
s
(0
ADC08131 0.003 0.1
a
I
2 mA)
L
Sinking
s
(b1sI
ADC08134,
ADC08138
0 mA)
L
0.2 0.5
Sinking
s
b
(
1sI
0 mA)
L
ADC08131 0.2 0.5
Line Regulation 4.75VsV
I
SC
Short Circuit Current V
REF
ADC08134,
ADC08138
V
REF
ADC08131 8 25
T
SU
DV
/Dt Long Term Stability 200 ppm/1 kHr
REF
Start-Up Time VCC:0Vx5V
e
C
L
CC
e
0V
e
0V
100 mF
s
5.25V
0.5 6
8 25
20 ms
2.5
2.5
g
g
Units
(Limits)
1.5%
V
1.5%
%/mA
(max)
mV
(max)
mA
(max)
4
Electrical Characteristics (Continued)
The following specifications apply for V
Boldface limits apply for T
Symbol Parameter Conditions
f
CLK
Clock Frequency 10 kHz (min)
e
T
A
ea
5VDC,V
CC
e
T
MIN
to T
MAX
J
ea
REF
; all other limits T
2.5 VDCand t
e
e
t
r
e
e
T
A
J
20 ns unless otherwise specified.
f
25§C.
Typical Limits Units
(Note 8) (Note 9) (Limits)
1 MHz (max)
Clock Duty Cycle 40 % (min)
(Note 14) 60 % (max)
T
C
t
CA
t
SELECT
t
SET-UP
t
HOLD
t
pd1,tpd0
Conversion Time (Not Including f
MUX Addressing Time) 8 ms (max)
Acquisition Time (/2 1/f
CLK High while CS is High 50 ns
CS Falling Edge or Data Input
Valid to CLK Rising Edge
Data Input Valid after CLK
Rising Edge
CLK Falling Edge to Output C
Data Valid (Note 15) Data MSB First 250 ns (max)
e
1 MHz 8 1/f
CLK
e
100 pF:
L
(max)
CLK
(max)
CLK
25 ns (min)
20 ns (min)
Data LSB First 200 ns (max)
t1H,t
C
IN
C
OUT
Note 1: Absolute Maximum Ratings indicate limits beyond which damage to the device may occur.
Note 2: Operating Ratings indicate conditions for which the device is functional. These ratings do not guarantee specific performance limits. For guaranteed
specifications and test conditions, see the Electrical Characteristics. The guaranteed specifications apply only for the test conditions listed. Some performance
characteristics may degrade when the device is not operated under the listed test conditions.
Note 3: All voltages are measured with respect to AGND
Note 4: When the input voltage (V
5 mA. The 20 mA maximum package input current rating limits the number of pins that can safely exceed the power supplies with an input current of 5 mA to four
pins.
Note 5: The maximum power dissipation must be derated at elevated temperatures and is dictated by T
allowable power dissipation at any temperature is P
with suffixes BIN, CIN, BIJ, CIJ, BIWM, and CIWM T
parts when board mounted follow: ADC08131 with BIN and CIN suffixes 120
suffixes 80
Note 6: Human body model, 100 pF capacitor discharged through a 1.5 kX resistor.
Note 7: See AN450 ‘‘Surface Mounting Methods and Their Effect on Product Reliability’’ or
soldering surface mount devices.
Note 8: Typicals are at T
Note 9: Guaranteed to National’s AOQL (Average Outgoing Quality Level).
Note 10: Total unadjusted error includes zero, full-scale, linearity, and multiplexer error. Total unadjusted error with V
and ADC08138. See Note 16.
Note 11: Cannot be tested for the ADC08131.
Note 12: For V
for analog input voltages one diode drop below ground or one diode drop greater than V
inputs (e.g., 5V) can cause an input diode to conduct, especially at elevated temperatures. This will cause errors for analog inputs near full-scale. The specification
allows 50 mV forward bias of either diode; this means that as long as the analog V
be correct. Exceeding this range on an unselected channel will corrupt the reading of a selected channel. Achievement of an absolute 0 V
range will therefore require a minimum supply voltage of 4.950 V
Note 13: Channel leakage current is measured after a single-ended channel is selected and the clock is turned off. For off channel leakage current the following
two cases are considered: one, with the selected channel tied high (5 V
channels is measured; two, with the selected channel tied low and the off channels tied high, total current flow through the off channels is again measured. The two
cases considered for determining on channel leakage current are the same except total current flow through the selected channel is measured.
Note 14: A 40% to 60% duty cycle range insures proper operation at all clock frequencies. In the case that an available clock has a duty cycle outside of these
limits the minimum time the clock is high or low must be at least 450 ns. The maximum time the clock can be high or low is 100 m s.
Note 15: Since data, MSB first, is the output of the comparator used in the successive approximation loop, an additional delay is built in (see Block Diagram) to
allow for comparator response time.
Note 16: For the ADC08131 V
reference current (700 mA typical, 2 mA maximum).
Note 17: Load regulation test conditions and specifications for the ADC08131 differ from those of the ADC08134 and ADC08138 because the ADC08131 has the
on-board reference as a permanent load.
TRI-STATE Delay from Rising Edge C
0H
of CS
to Data Output and SARS Hi-Z (see TRI-STATE Test Circuits)
Capacitance of Logic Inputs 5 pF
Capacitance of Logic Outputs 5 pF
) at any pin exceeds the power supplies (V
IN
C/W. ADC08134 with BIWM and CIWM suffixes 140§C/W, ADC08138 with BIWM and CIWM suffixes 91§C/W,
§
e
25§C and represent the most likely parametric norm.
J
t
V
IN(b)
the digital code will be 0000 0000. Two on-chip diodes are tied to each analog input (see Block Diagram) which will forward-conduct
IN(a)
IN is internally tied to the on chip 2.5V band-gap reference output; therefore, the supply current is larger because it includes the
REF
e
e
(T
D
J
MAX
e
J
MAX
e
10 pF, R
L
e
C
100 pF, R
L
DGNDe0VDC, unless otherwise specified.
b
TA)/iJAor the number given in the Absolute Maximum Ratings, whichever is lower. For devices
125§C. For devices with suffix CMJ, T
over temperature variations, initial tolerance and loading.
DC
) and the remaining seven off channels tied low (0 VDC), total current flow through the off
DC
e
10 kX
L
e
2kX 180 ns (max)
L
k
(AGND or DGND) or V
IN
J
MAX
J
C/W, ADC08134 with BIN and CIN suffixes 95§C/W, ADC08138 with BIN and CIN
§
does not exceed the supply voltage by more than 50 mV, the output code will
IN
MAX
Linear Data Book
supply. During testing at low VCClevels (e.g., 4.5V), high level analog
CC
50 ns
l
AVCC,) the current at that pin should be limited to
IN
, iJAand the ambient temperature, TA. The maximum
e
150§C. The typical thermal resistances (iJA) of these
section ‘‘Surface Mount’’ for other methods of
ea
5V only applies to the ADC08134
REF
to5VDCinput voltage
DC
5
ADC08138 Simplified Block Diagram
TL/H/10749– 1
6
Typical Converter Performance Characteristics
Linearity Error vs
Reference Voltage
Power Supply Current vs
Temperature (ADC08138,
ADC08134)
Note: For ADC08131 add I
(Note 16) TL/H/10749– 5
REF
Linearity Error vs
Temperature
Output Current vs
Temperature
Typical Reference Performance Characteristics
Load Regulation (3 Typical Parts)
Line Regulation
Linearity Error vs
Clock Frequency
Power Supply Current
vs Clock Frequency
Output Drift
vs Temperature
(3 Typical Parts)
Available
Output Current
vs Supply Voltage
7
TL/H/10749– 6
TRI-STATE Test Circuits and Waveforms
t
1H
t
0H
t
1H
t
0H
TL/H/10749– 7
Timing Diagrams
Data Input Timing
*To reset these devices, CLK and CS must be simultaneously high for a period of t
standards ADC0831/4/8.
Data Output Timing
ADC08131 Start Conversion Timing
or greater. Otherwise these devices are compatible with industry
SELECT
TL/H/10749– 10
TL/H/10749– 9
TL/H/10749– 8
TL/H/10749– 11
8
Timing Diagrams (Continued)
ADC08131 Timing
*LSB first output not available on ADC08131.
LSB information is maintained for remainder of clock periods until CS
ADC08134 Timing
TL/H/10749– 12
goes high.
TL/H/10749– 13
9
Timing Diagrams (Continued)
TL/H/10749– 14
ADC08138 Timing
18 clocks in the LSB before SE is taken low
Ý
*Make sure clock edge
10
ADC08138 Functional Block Diagram
TL/H/10749– 15
are internally tied together.
REFIN
and V
REFOUT
*Some of these functions/pins are not available with other options.
Note 1: For the ADC08134, the ‘‘SEL 1’’ Flip-Flop is bypassed. For the ADC08131, V
11
Functional Description
1.0 MULTIPLEXER ADDRESSING
The design of these converters utilizes a comparator structure with built-in sample-and-hold which provides for a differential analog input to be converted by a successiveapproximation routine.
The actual voltage converted is always the difference between an assigned ‘‘
minal. The polarity of each input terminal of the pair indicates which line the converter expects to be the most positive. If the assigned ‘‘
input voltage the converter responds with an all zeros output code.
A unique input multiplexing scheme has been utilized to provide multiple analog channels with software-configurable
single-ended, differential, or pseudo-differential (which will
convert the difference between the voltage at any analog
input and a common terminal) operation. The analog signal
conditioning required in transducer-based data acquisition
systems is significantly simplified with this type of input flexibility. One converter package can now handle ground referenced inputs and true differential inputs as well as signals
with some arbitrary reference voltage.
A particular input configuration is assigned during the MUX
addressing sequence, prior to the start of a conversion. The
MUX address selects which of the analog inputs are to be
enabled and whether this input is single-ended or differential. Differential inputs are restricted to adjacent channel
pairs. For example, channel 0 and channel 1 may be selected as a differential pair but channel 0 or 1 cannot act
Single-Ended MUX Mode
START
11000
11001
11010
11011
11100
11101
11110
11111
a
’’ input terminal and a ‘‘b’’ input ter-
a
’’ input voltage is less than the ‘‘b’’
TABLE II. MUX Addressing: ADC08138
MUX Address Analog Single-Ended Channel
SGL/ ODD/ SELECT
DIF SIGN
10
01234567COM
a b
differentially with any other channel. In addition to selecting
differential mode the polarity may also be selected. Channel
0 may be selected as the positive input and channel 1 as
the negative input or vice versa. This programmability is
best illustrated by the MUX addressing codes shown in the
following tables for the various product options.
The MUX address is shifted into the converter via the DI
line. Because the ADC08131 contains only one differential
input channel with a fixed polarity assignment, it does not
require addressing.
The common input line (COM) on the ADC08138 can be
used as a pseudo-differential input. In this mode the voltage
on this pin is treated as the ‘‘
b
’’ input for any of the other
input channels. This voltage does not have to be analog
ground; it can be any reference potential which is common
to all of the inputs. This feature is most useful in single-supply applications where the analog circuity may be biased up
to a potential other than ground and the output signals are
all referred to this potential.
TABLE I. Multiplexer/Package Options
Part Number of Analog Channels Number of
Number
Single-Ended Differential
Package Pins
ADC08131 1 1 8
ADC08134 4 2 14
ADC08138 8 4 20
Ý
ab
ab
ab
ab
ab
ab
ab
12
Functional Description (Continued)
TABLE II. MUX Addressing: ADC08138 (Continued)
Differential MUX Mode
MUX Address Analog Differential Channel-Pair
START
10000
10001
10010
10011
10100
10101
10110
10111
SGL/ ODD/ SELECT 0 1 2 3
DIF SIGN
1001234567
TABLE III. MUX Addressing: ADC08134
Single-Ended MUX Mode
MUX Address Channel
START
SGL/ ODD/ SELECT
DIF SIGN
110 0
110 1
111 0
111 1
Ý
ab
ab
ab
ab
ba
ba
ba
ba
Ý
0123
1
a
a
a
a
COM is internally tied to AGND
Differential MUX Mode
MUX Address Channel
START
SGL/ ODD/ SELECT
DIF SIGN
100 0
100 1
101 0
101 1
13
Ý
0123
1
ab
ab
ba
ba
Functional Description (Continued)
Since the input configuration is under software control, it
can be modified as required before each conversion. A
channel can be treated as a single-ended, ground referenced input for one conversion; then it can be reconfigured
as part of a differential channel for another conversion.
ure 1
illustrates the input flexibility which can be achieved.
The analog input voltages for each channel can range from
50mV below ground to 50mV above V
out degrading conversion accuracy.
2.0 THE DIGITAL INTERFACE
A most important characteristic of these converters is their
serial data link with the controlling processor. Using a serial
communication format offers two very significant system improvements; it allows many functions to be included in a
small package and it can eliminate the transmission of low
level analog signals by locating the converter right at the
analog sensor; transmitting highly noise immune digital data
back to the host processor.
(typically 5V) with-
CC
8 Single-Ended 8 Pseudo-Differential
Fig-
To understand the operation of these converters it is best to
refer to the Timing Diagrams and Functional Block Diagram
and to follow a complete conversion sequence. For clarity a
separate timing diagram is shown for each device.
1. A conversion is initiated by pulling the CS
line low. This line must be held low for the entire conversion. The converter is now waiting for a start bit and its
MUX assignment word.
2. On each rising edge of the clock the status of the data in
(DI) line is clocked into the MUX address shift register.
The start bit is the first logic ‘‘1’’ that appears on this line
(all leading zeros are ignored). Following the start bit the
converter expects the next 2 to 4 bits to be the MUX
assignment word.
(chip select)
4 Differential Mixed Mode
FIGURE 1. Analog Input Multiplexer Options for the ADC08138
14
TL/H/10749– 16
Functional Description (Continued)
3. When the start bit has been shifted into the start location
of the MUX register, the input channel has been assigned
and a conversion is about to begin. An interval of (/2 clock
period is automatically inserted to allow for sampling the
analog input. The SARS line goes high at the end of this
time to signal that a conversion is now in progress and
the DI line is disabled (it no longer accepts data).
4. The data out (DO) line now comes out of TRI-STATE and
provides a leading zero.
5. During the conversion the output of the SAR comparator
indicates whether the analog input is greater than (high)
or less than (low) a series of successive voltages generated internally from a ratioed capacitor array (first 5 bits)
and a resistor ladder (last 3 bits). After each comparison
the comparator’s output is shipped to the DO line on the
falling edge of CLK. This data is the result of the conversion being shifted out (with the MSB first) and can be
read by the processor immediately.
6. After 8 clock periods the conversion is completed. The
SARS line returns low to indicate this (/2 clock cycle later.
7. The stored data in the successive approximation register
is loaded into an internal shift register. If the programmer
prefers the data can be provided in an LSB first format
[
this makes use of the shift enable (SE
the ADC08138 the SE
line is brought out and if held high
the value of the LSB remains valid on the DO line. When
SE
is forced low the data is clocked out LSB first. On
devices which do not include the SE
data, LSB first, is automatically shifted out the DO line
after the MSB first data stream. The DO line then goes
low and stays low until CS
ADC08131 is an exception in that its data is only output in
MSB first format.
8. All internal registers are cleared when the CS
and the t
ing under Timing Diagrams. If another conversion is desired CS
requirement is met. See Data Input Tim-
SELECT
must make a high to low transition followed by
address information.
) control line].On
control line, the
is returned high. The
line is high
The DI and DO lines can be tied together and controlled
through a bidirectional processor I/O bit with one wire.
This is possible because the DI input is only ‘‘looked-at’’
during the MUX addressing interval while the DO line is
still in a high impedance state.
3.0 REFERENCE CONSIDERATIONS
The V
divider string and capacitor array used for the successive
IN pin on these converters is the top of a resistor
REF
approximation conversion. The voltage applied to this reference input defines the voltage span of the analog input (the
difference between V
256 possible output codes apply). The reference source
IN(MAX)
and V
IN(MIN)
over which the
must be capable of driving the reference input resistance,
which can be as low as 1.3 kX.
For absolute accuracy, where the analog input varies between specific voltage limits, the reference input must be
biased with a stable voltage source. The ADC08134 and the
ADC08138 provide the output of a 2.5V band-gap reference
at V
OUT. This voltage does not vary appreciably with
REF
temperature, supply voltage, or load current (see Reference
Characteristics in the Electrical Characteristics tables) and
can be tied directly to V
to 2.5V. This output can also be used to bias external cir-
IN for an analog input span of 0V
REF
cuits and can therefore be used as the reference in ratiometric applications. Bypassing V
pacitor is recommended.
OUT with a 100 mF ca-
REF
For the ADC08131, the output of the on-board reference is
internally tied to the reference input. Consequently, the analog input span for this device is set at 0V to 2.5V. The pin
V
C is provided for bypassing purposes and biasing ex-
REF
ternal circuits as suggested above.
The maximum value of the reference is limited to the V
supply voltage. The minimum value, however, can be quite
CC
small (see Typical Performance Characteristics) to allow direct conversions of transducer outputs providing less than a
5V output span. Particular care must be taken with regard to
noise pickup, circuit layout and system error voltage sources when operating with a reduced span due to the increased sensitivity of the converter (1 LSB equals V
256).
REF/
a) Ratiometric
TL/H/10749– 17
FIGURE 2. Reference Examples
15
b) Absolute
TL/H/10749– 18
Functional Description (Continued)
4.0 THE ANALOG INPUTS
The most important feature of these converters is that they
can be located right at the analog signal source and through
just a few wires can communicate with a controlling processor with a highly noise immune serial bit stream. This in itself
greatly minimizes circuitry to maintain analog signal accuracy which otherwise is most susceptible to noise pickup.
However, a few words are in order with regard to the analog
inputs should the input be noisy to begin with or possibly
riding on a large common-mode voltage.
The differential input of these converters actually reduces
the effects of common-mode input noise, a signal common
to both selected ‘‘
(60 Hz is most typical). The time interval between sampling
a
the ‘‘
’’ input and then the ‘‘b’’ input is (/2 of a clock period. The change in the common-mode voltage during this
short time interval can cause conversion errors. For a sinusoidal common-mode signal this error is:
where fCMis the frequency of the common-mode signal,
V
PEAK
and f
CLK
For a 60Hz common-mode signal to generate a (/4 LSB error (&5mV) with the converter running at 250kHz, its peak
value would have to be 6.63V which would be larger than
allowed as it exceeds the maximum analog input limits.
Source resistance limitation is important with regard to the
DC leakage currents of the input multiplexer. While operating near or at maximum speed bypass capacitors should not
be used if the source resistance is greater than 1kX. The
worst-case leakage current of
create a 1mV input error with a 1kX source resistance. An
op amp RC active low pass filter can provide both impedance buffering and noise filtering should a high impedance
signal source be required.
5.0 OPTIONAL ADJUSTMENTS
5.1 Zero Error
The zero of the A/D does not require adjustment. If the
minimum analog input voltage value, V
a zero offset can be done. The converter can be made to
output 0000 0000 digital code for this minimum input voltage
by biasing any V
utilizes the differential mode operation of the A/D.
a
’’ and ‘‘b’’ inputs for a conversion
V
(max)eV
error
is its peak voltage value
is the A/D clock frequency.
(b) input at this V
IN
(2qfCM)
PEAK
g
1mA over temperature will
f
#
IN(MIN)
IN(MIN)
0.5
CLK
J
, is not ground
value. This
The zero error of the A/D converter relates to the location
of the first riser of the transfer function and can be measured by grounding the V
magnitude positive voltage to the V
is the difference between the actual DC input voltage which
is necessary to just cause an output digital code transition
from 0000 0000 to 0000 0001 and the ideal (/2 LSB value
e
((/2 LSB
5.2 Full Scale
A full-scale adjustment can be made by applying a differential input voltage which is 1(/2 LSB down from the desired
analog full-scale voltage range and then adjusting the magnitude of the V
just changing from 1111 1110 to 1111 1111 (See figure entitled ‘‘Span Adjust; 0V
with the ADC08134 and ADC08138. (The reference is internally connected to V
5.3 Adjusting for an Arbitrary Analog Input
Voltage Range
If the analog zero voltage of the A/D is shifted away from
ground (for example, to accommodate an analog input signal which does not go to ground), this new zero reference
should be properly adjusted first. A V
equals this desired zero reference plus (/2 LSB (where the
LSB is calculated for the desired analog span, using 1 LSB
e
the zero reference voltage at the corresponding ‘‘
should then be adjusted to just obtain the 00
code transition.
The full-scale adjustment should be made[with the proper
V
IN
input which is given by:
where:
and
The V
code change from FE
justment procedure.
9.8mV for V
IN input for a digital output code which is
REF
analog span/256) is applied to selected ‘‘a’’ input and
(b) voltage applied]by forcing a voltage to the VIN(a)
V
(a)fsadjeV
IN
e
V
the high end of the analog input range
MAX
e
V
the low end (the offset zero) of the analog range.
MIN
(Both are ground referenced.)
IN (or VCC) voltage is then adjusted to provide a
REF
(b) input and applying a small
IN
e
REF
s
V
IN
IN of the ADC08131).
REF
b
1.5
MAX
to FF
HEX
(a) input. Zero error
IN
5.000VDC).
s
3V’’). This is possible only
(a) voltage which
IN
b
(V
MAX
256
Ð
. This completes the ad-
HEX
b
’’ input
to 01
HEX
V
MIN
HEX
)
(
16
Applications
A ‘‘Stand-Alone’’ Hook-Up for ADC08138 Evaluation
*Pinouts shown for ADC08138.
For all other products tie to pin functions as shown.
Low-Cost Remote Temperature Sensor
TL/H/10749– 21
17
Applications (Continued)
Protecting the Input
Diodes are 1N914
Operating with Ratiometric Transducers
*VIN(b)e0.15 V
15% of V
REF
s
REF
s
V
85% of V
XDR
REF
Span Adjust; 0VsV
TL/H/10749– 22
TL/H/10749– 23
s
3V
IN
TL/H/10749– 24
18
Applications (Continued)
Zero-Shift and Span Adjust: 2V
Physical Dimensions inches (millimeters)
s
s
V
5V
IN
TL/H/10749– 25
Order Number ADC08134BIWM or ADC08134CIWM
NS Package Number M14B
19
Physical Dimensions inches (millimeters) (Continued)
Order Number ADC08138BIWM or ADC08138CIWM
Order Number ADC08131BIN or ADC08131CIN
NS Package Number M20B
NS Package Number N08E
20
Physical Dimensions inches (millimeters) (Continued)
Order Number ADC08134BIN or ADC08134CIN
NS Package Number N14A
21
Physical Dimensions inches (millimeters) (Continued)
Order Number ADC08138CIN or ADC08138BIN
NS Package Number N20A
LIFE SUPPORT POLICY
with Multiplexer Options, Voltage Reference, and Track/Hold Function
NATIONAL’S PRODUCTS ARE NOT AUTHORIZED FOR USE AS CRITICAL COMPONENTS IN LIFE SUPPORT
DEVICES OR SYSTEMS WITHOUT THE EXPRESS WRITTEN APPROVAL OF THE PRESIDENT OF NATIONAL
SEMICONDUCTOR CORPORATION. As used herein:
1. Life support devices or systems are devices or 2. A critical component is any component of a life
ADC08131/ADC08134/ADC08138 8-Bit High-Speed Serial I/O A/D Converters
systems which, (a) are intended for surgical implant support device or system whose failure to perform can
into the body, or (b) support or sustain life, and whose be reasonably expected to cause the failure of the life
failure to perform, when properly used in accordance support device or system, or to affect its safety or
with instructions for use provided in the labeling, can effectiveness.
be reasonably expected to result in a significant injury
to the user.
National Semiconductor National Semiconductor National Semiconductor National Semiconductor National Semiconductores National Semiconductor
Corporation GmbH Japan Ltd. Hong Kong Ltd. Do Brazil Ltda. (Australia) Pty, Ltd.
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