Rainbow Electronics ADC081000 User Manual

ADC081000
High Performance, Low Power 8-Bit, 1 GSPS A/D
Converter

ADC081000 High Performance, Low Power 8-Bit, 1 GSPS A/D Converter

July 2004

General Description

The ADC081000 is a low power, high performance CMOS
analog-to-digital converter that digitizes signals to 8 bits
resolution at sampling rates up to 1.6 GSPS. Consuming a
typical 1.4 Watts at 1 GSPS from a single 1.9 Volt supply,
this device is guaranteed to have no missing codes over the
full operating temperature range. The unique folding and
interpolating architecture, the fully differential comparator
design, the innovative design of the internal sample-and­hold amplifier and the self-calibration scheme enable a very
flat response of all dynamic parameters beyond Nyquist,
producing a high 7.5 ENOB with a 500 MHz input signal and
a 1 GHz sample rate. Output formatting is offset binary and
the LVDS digital outputs are compliant with IEEE 1596.3­1996, with the exception of a reduced common mode volt­age of 0.8V.

The converter has a 1:2 demultiplexer that feeds two LVDS
buses, reducing the output data rate on each bus to half the
sampling rate. The data on these buses are interleaved in
time to provide a 500 MHz output rate per bus and a com­bined output rate of 1 GSPS.

The converter typically consumes less than 10 mW in the
Power Down Mode and is available in a 128-lead, thermally
enhanced exposed pad LQFP and operates over the indus­trial (-40˚C ≤ T

≤ +85˚C) temperature range.

A

Block Diagram

Features

n Internal Sample-and-Hold
n Single +1.9V
n Adjustable Output Levels
n Guaranteed No Missing Codes
n Low Power Standby Mode

±

0.1V Operation

Key Specifications

n Resolution 8 Bits
n Max Conversion Rate 1 GSPS (min)
n ENOB
n DNL
n Conversion Latency 7 and 8 Clock Cycles
n Power Consumption

@

500 MHz Input 7.5 Bits (typ)

±

0.25 LSB (typ)

— Operating 1.45 W (typ)
— Power Down Mode 9 mW (typ)

Applications

n Direct RF Down Conversion
n Digital Oscilloscopes
n Satellite Set-top boxes
n Communications Systems
n Test Instrumentation

20068153

© 2004 National Semiconductor Corporation DS200681 www.national.com

Ordering Information

ADC081000

Pin Configuration

Extended Commercial Temperature

<

<

T

Range (-40˚C

ADC081000CIYB 128-Pin Exposed Pad LQFP

ADC081000LEVAL Evaluation Board

A

+85˚C)

NS Package

* Exposed pad on back of package must be soldered to ground plane to ensure rated performance.

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20068101

Pin Descriptions and Equivalent Circuits

Pin Functions

Pin No. Symbol Equivalent Circuit Description

Output Voltage Amplitude set. Tie this pin high for

3 OutV

4 OutEdge

14 DC_Coup

26 PD

30 CAL

35 FSR

127 CalDly

normal differential output amplitude. Ground this pin for
a reduced differential output amplitude and reduced
power consumption. See Section 1.5.

Output Edge Select. Sets the edge of the DCLK+ (pin

82) at which the output data transitions. The output
transitions with the DCLK+ rising edge when this pin is
high or on the falling edge when this pin is low. See
Section 5.3.

DC Coupling select. When this pin is high, the V

- analog inputs are d.c. coupled and the input

V

IN

common mode voltage should equal the V
output voltage. When this pin is low, the analog input
pins are internally biased and the input signal should be
a.c. coupled to the analog input pins. See Section 3.0.

Power Down Pin. A logic high on this pin puts the ADC
into the Power Down mode. A logic low on this pin
allows normal operation.

Calibration. A minimum 10 clock cycles low followed by
a minimum of 10 clock cycles high on this pin will
initiate the self calibration sequence. See Section 1.1.

Full scale Range Select. With a logic low on this pin,
the full-scale differential input is 600 mV
high on this pin, the full-scale differential input is 800

. See Section 1.3.

mV

P-P

Calibration Delay. This sets the number of clock cycles
after power up before calibration begins. See Section

1.1.

(pin 7)

CMO

. With a logic

P-P

+ and

IN

ADC081000

18
19

11
10

CLK+

CLK-

V

IN

V

IN

Clock input pins for the ADC. The differential clock
signal must be a.c. coupled to these pins. The input
signal is sampled on the falling edge of CLK+.

+

-

Analog Signal Differential Inputs to the ADC.

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Pin Descriptions and Equivalent Circuits (Continued)

Pin Functions

ADC081000

Pin No. Symbol Equivalent Circuit Description

7V

31 V

CMO

BG

126 CalRun

32 R

83
84
85
86
89
90
91
92
93
94
95

96
100
101
102
103

EXT

D7-

D7+

D6-

D6+

D5-

D5+

D4-

D4+

D3-

D3+

D2-

D2+

D1-

D1+

D0-

D0+

Common Mode Output voltage for VIN+ and VIN- when
d.c. input coupling is used. See Section 3.0.

Bandgap output voltage. This pin is capable of sourcing
or sinking up to 100 µA.

Calibration Running indication. This pin is at a logic
high when calibration is running.

External Bias Resistor connection. The required value

±

is 3.3k-Ohms (

0.1%) to ground. See Section 1.1.

LVDS data output bits sampled second in time
sequence. These outputs should always be terminated
with a differential 100Ω resistance.

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Pin Descriptions and Equivalent Circuits (Continued)

Pin Functions

Pin No. Symbol Equivalent Circuit Description

104
105
106
107
111
112
113
114
115
116
117
118
122
123
124
125

79
80

Dd7­Dd7+
Dd6­Dd6+
Dd5­Dd5+
Dd4­Dd4+
Dd3­Dd3+
Dd2­Dd2+
Dd1­Dd1+
Dd0­Dd0+

OR+

OR-

LVDS data output bits sampled first in time sequence.
These outputs should always be terminated with a
differential 100Ω resistance.

Out of Range output. A differential high at these pins
indicates that the differential input is out of range

±

(outside the range of

300 mV or±400 mV as defined

by the FSR pin). See Section 1.6.

ADC081000

82
81

2, 5, 8, 13, 16,
17, 20, 25, 28,

33, 128

40, 51, 62, 73,

88, 99, 110,

121

1, 6, 9, 12, 15,

21, 24, 27

42, 53, 64, 74,

87, 97, 108,

119

22, 23, 29, 34,

36 - 39,
41, 43 - 50,
52, 54 - 61,
63, 65 - 72,
75 - 78, 98,

109, 120

DCLK+

DCLK-

V

A

V

DR

GND Ground return for V

DR GND Ground return for V

Differential Clock Outputs used to latch the output data.
Delayed and non-delayed data outputs are supplied
synchronous to this signal.

Analog power supply pins. Bypass these pins to GND.

Output Driver power supply pins. Bypass these pins to
DR GND.

A

DR

NC No Connection. Make no connection to these pins.

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Absolute Maximum Ratings

(Notes 1, 2)

If Military/Aerospace specified devices are required,

ADC081000

please contact the National Semiconductor Sales Office/
Distributors for availability and specifications.

Supply Voltage (V

Voltage on Any Input Pin −0.15V to

Ground Difference

|GND - DR GND| 0V to 100 mV

Input Current at Any Pin (Note 3)

Package Input Current (Note 3)

Power Dissipation at T

ESD Susceptibility (Note 4)

Human Body Model
Machine Model

Soldering Temperature, Infrared,

10 seconds (Note 5) 235˚C

Storage Temperature −65˚C to +150˚C

) 2.2V

A,VDR

= 25˚C 2.0 W

A

(V

+0.15V)

A

±

25 mA

±

50 mA

2500V

250V

Operating Ratings (Notes 1, 2)

Ambient Temperature Range −40˚C ≤ T

Supply Voltage (V

Driver Supply Voltage (V

) +1.8V to +2.0V

A

) +1.8V to V

DR

Analog Input Common Mode
Voltage 1.2V to 1.3V

V

Differential Voltage Range −VFS/2 to +VFS/2

IN

Ground Difference
(|GND - DR GND|) 0V

CLK Pins Voltage Range 0V to V

Differential CLK Amplitude 0.6V

P-P

Package Thermal Resistances

θ

J-C

Package

128-Lead Exposed Pad

LQFP

(Top of

Package)

10˚C / W 2.8˚C / W

Converter Electrical Characteristics

The following specifications apply after calibration for VA=VDR= +1.9VDC, OutV = 1.9V, VINFSR (a.c. coupled) = differential
800mV

±

0.1%, Analog Signal Source Impedance = 100Ω. Boldface limits apply for TA=T

= 10 pF, Differential, a.c. coupled Sinewave Clock, f

P-P,CL

unless otherwise stated. (Notes 6, 7)

Symbol Parameter Conditions

STATIC CONVERTER CHARACTERISTICS

INL Integral Non-Linearity

DNL Differential Non-Linearity

Resolution with No Missing Codes 8 Bits

V

OFF

TC V

Offset Error −0.45

Offset Error Tempco −40˚C to +85˚C −3 ppm/˚C

OFF

PFSE Positive Full-Scale Error (Note 9) −2.2

NFSE Negative Full-Scale Error (Note 9) −1.1

TC PFSE Positive Full Scale Error Tempco −40˚C to +85˚C 20 ppm/˚C

TC NFSE Negative Full Scale Error Tempco −40˚C to +85˚C 13 ppm/˚C

Dynamic Converter Characteristics

FPBW Full Power Bandwidth 1.7 GHz

Gain Flatness

ENOB Effective Number of Bits

SINAD

Signal-to-Noise Plus Distortion
Ratio

SNR Signal-to-Noise Ratio

d.c. to 500 MHz

d.c. to 1 GHz

= 100 MHz, VIN= FSR − 0.5 dB 7.5 Bits

f

IN

f

= 248 MHz, VIN= FSR − 0.5 dB 7.5 7.1 Bits (min)

IN

f

= 498 MHz, VIN= FSR − 0.5 dB 7.5 7.1 Bits (min)

IN

= 100 MHz, VIN= FSR − 0.5 dB 47 dB

f

IN

f

= 248 MHz, VIN= FSR − 0.5 dB 47 44.8 dB (min)

IN

f

= 498 MHz, VIN= FSR − 0.5 dB 47 44.8 dB (min)

IN

= 100 MHz, VIN= FSR − 0.5 dB 48 dB

f

IN

f

= 248 MHz, VIN= FSR − 0.5 dB 48 45.5 dB (min)

IN

f

= 498 MHz, VIN= FSR − 0.5 dB 48 45.5 dB (min)

IN

= 1 GHz at 0.5V

CLK

with 50% duty cycle, R

P-P

MIN

Typical

(Note 8)

to T

±
±

. All other limits TA= 25˚C,

MAX

Limits

(Note 8)

0.35

0.25

±

0.9 LSB (max)

±

0.7 LSB (max)

−1.5

0.5

±

25 mV (max)

±

25 mV (max)

±

0.5 dBFS

±

1.0 dBFS

≤ +85˚C

A

to 2.0V

θ

J-PAD

(Thermal

Pad)

= 3300Ω

EXT

Units

(Limits)

LSB (min)

LSB (max)

A

A

P-P

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Converter Electrical Characteristics (Continued)

The following specifications apply after calibration for VA=VDR= +1.9VDC, OutV = 1.9V, VINFSR (a.c. coupled) = differential
800mV

±

0.1%, Analog Signal Source Impedance = 100Ω. Boldface limits apply for TA=T

= 10 pF, Differential, a.c. coupled Sinewave Clock, f

P-P,CL

unless otherwise stated. (Notes 6, 7)

Symbol Parameter Conditions

STATIC CONVERTER CHARACTERISTICS

= 100 MHz, VIN= FSR − 0.5 dB -57 dB

f

IN

f

THD Total Harmonic Distortion

2nd Harm Second Harmonic Distortion

3rd Harm Third Harmonic Distortion

SFDR Spurious-Free dynamic Range

IMD Intermodulation Distortion

Out of Range Output Code
(In addition to OR Output high)

= 248 MHz, VIN= FSR − 0.5 dB -57 −50 dB (max)

IN

f

= 498 MHz, VIN= FSR − 0.5 dB -57 −50 dB (max)

IN

= 100 MHz, VIN= FSR − 0.5 dB −64 dB

f

IN

f

= 248 MHz, VIN= FSR − 0.5 dB −64 dB

IN

f

= 498 MHz, VIN= FSR − 0.5 dB −64 dB

IN

= 100 MHz, VIN= FSR − 0.5 dB −64 dB

f

IN

f

= 248 MHz, VIN= FSR − 0.5 dB −64 dB

IN

f

= 498 MHz, VIN= FSR − 0.5 dB −64 dB

IN

= 100 MHz, VIN= FSR − 0.5 dB 58.5 dB

f

IN

f

= 248 MHz, VIN= FSR − 0.5 dB 58.5 50 dB (min)

IN

f

= 498 MHz, VIN= FSR − 0.5 dB 58.5 50 dB (min)

IN

f

= 121 MHz, VIN=FSR−7dB

IN1

= 126 MHz, VIN=FSR−7dB

f

IN2

(V

+)−(VIN−)>+ Full Scale 255

IN

(V

+)−(VIN−)<− Full Scale 0

IN

ANALOG INPUT AND REFERENCE CHARACTERISTICS

V

IN

V

CMI

C

IN

R

IN

Full Scale Analog Differential Input
Range

Common Mode Analog Input
Voltage

Analog Input Capacitance
(Note 10)

Differential Input Resistance 100

FSR pin Low 600

FSR pin High 800

Differential 0.02 pF

Each input to ground 1.6 pF

ANALOG OUTPUT CHARACTERISTICS

V

CMO

TC V

V

BG

TC V

Common Mode Output Voltage I

Common Mode Output Voltage

CMO

Temperature Coefficient

Bandgap Reference Output
Voltage

Bandgap Reference Voltage

BG

Temperature Coefficient

=±1 µA 1.21

CMO

= −40˚C to +85˚C 118 ppm/˚C

T

A

=±100 µA 1.26

I

BG

TA= −40˚C to +85˚C,

=±100 µA

I

BG

CLOCK INPUT CHARACTERISTICS

Square Wave Clock 0.6

V

ID

Differential Clock Input Level

Sine Wave Clock 0.6

I

I

C

IN

Input Current VIN=0VorVIN=V

Input Capacitance (Note 10)

Differential 0.02 pF

Each Input to Ground 1.5 pF

= 1 GHz at 0.5V

CLK

A

with 50% duty cycle, R

P-P

MIN

to T

. All other limits TA= 25˚C,

MAX

Typical

(Note 8)

Limits

(Note 8)

EXT

(Limits)

= 3300Ω

Units

-51 dB

550 mV

650 mV

750 mV

850 mV

V

−50

V

CMO

V

CMO

CMO

+50

P-P

P-P

P-P

P-P

mV (min)

mV (max)

94 Ω (min)

106 Ω (max)

0.95

1.45

1.22

1.33

V (min)

V (max)

V (min)

V (max)

-28 ppm/˚C

0.4

2.0

0.4

2.0

±

1µA

V

P-P

V

P-P

V

P-P

V

P-P

ADC081000

(min)

(max)

(min)

(max)

(min)

(max)

(min)

(max)

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Converter Electrical Characteristics (Continued)

The following specifications apply after calibration for VA=VDR= +1.9VDC, OutV = 1.9V, VINFSR (a.c. coupled) = differential
800mV

ADC081000

±

0.1%, Analog Signal Source Impedance = 100Ω. Boldface limits apply for TA=T

= 10 pF, Differential, a.c. coupled Sinewave Clock, f

P-P,CL

unless otherwise stated. (Notes 6, 7)

Symbol Parameter Conditions

DIGITAL CONTROL PIN CHARACTERISTICS

V

IH

V

IL

I

I

C

IN

Logic High Input Voltage (Note 12) 1.4 V (min)

Logic Low Input Voltage (Note 12) 0.5 V (max)

Input Current VIN=0orVIN=V

Logic Input Capacitance (Note 13) Each input to ground 1.2 pF

DIGITAL OUTPUT CHARACTERISTICS

OutV = V

V

OD

LVDS Differential Output Voltage

OutV = GND, measured

, measured single-ended 300

A

single-ended

∆ V

DIFF

V

∆ V

I

OS

Z

OD

OS

OS

O

Change in LVDS Output Swing
Between Logic Levels

Output Offset Voltage 800 mV

Output Offset Voltage Change
Between Logic Levels

Output Short Circuit Current

Output+ & Output- connected to

0.8V

Differential Output Impedance 100 Ohms

POWER SUPPLY CHARACTERISTICS

I

A

I

DR

P

D

Analog Supply Current

Output Driver Supply Current

Power Consumption

PSRR1 D.C. Power Supply Rejection Ratio

PD = Low
PD = High

PD = Low 108 160 mA (max)

PD = High 0.1 mA

PD = Low 1.43 1.8 W (max)

PD = High 8.7 mW

Change in Offset Error with change
in V

from 1.8V to 2.0V

A

AC ELECTRICAL CHARACTERISTICS

= 85˚C 1.1 1.0 GHz (min)

T

A

f

CLK1

f

CLK2

t

CL

t

CH

Maximum Conversion Rate

Minimum Conversion Rate 200 MHz

Input Clock Duty Cycle

Input Clock Low Time (Note 12) 500 200 ps (min)

Input Clock High Time (Note 12) 500 200 ps (min)

T

≤ 75˚C 1.3 GHz

A

T

≤ 70˚C 1.6 GHz

A

200 MHz ≤ Input clock frequency
1 GHz

DCLK Duty Cycle (Note 12) 50

t

t

t

t

LHT

HLT

OSK

AD

Differential Low to High Transition
Time

Differential High to Low Transition
Time

DCLK to Data Output Skew
(Note 11)

Sampling (Aperture) Delay

10% to 90%, C

10% to 90%, C

50% of DCLK transition to 50% of
Data transition

Input CLK+ Fall to Acquisition of
Data

= 1 GHz at 0.5V

CLK

A

with 50% duty cycle, R

P-P

MIN

Typical

(Note 8)

to T

. All other limits TA= 25˚C,

MAX

Limits

(Note 8)

±

1µA

200 mV

450 mV

225

±

1mV

±

1mV

140 mV

340 mV

−4 mA

646

792 mA (max)

4.5

73 dB

<

50

20
80

45
55

= 2.5 pF 250 ps

L

= 2.5 pF 250 ps

L

±

0

200 ps (max)

930 ps

EXT

(Limits)

% (min)
% (max)

% (min)
% (max)

= 3300Ω

Units

(min)

P-P

(max)

P-P

(min)

P-P

(max)

P-P

mA

www.national.com 8

Converter Electrical Characteristics (Continued)

The following specifications apply after calibration for VA=VDR= +1.9VDC, OutV = 1.9V, VINFSR (a.c. coupled) = differential
800mV

±

0.1%, Analog Signal Source Impedance = 100Ω. Boldface limits apply for TA=T

= 10 pF, Differential, a.c. coupled Sinewave Clock, f

P-P,CL

unless otherwise stated. (Notes 6, 7)

Symbol Parameter Conditions

AC ELECTRICAL CHARACTERISTICS

t

AJ

t

OD

t

WU

t

CAL

Note 1: Absolute Maximum Ratings indicate limits beyond which damage to the device may occur. There is no guarantee of operation at the Absolute Maximum
Ratings. Operating Ratings indicate conditions for which the device is functional, but do not guarantee specific performance limits. For guaranteed specifications and
test conditions, see the Electrical Characteristics. The guaranteed specifications apply only for the test conditions listed. Some performance characteristics may
degrade when the device is not operated under the listed test conditions.

Note 2: All voltages are measured with respect to GND = DR GND = 0V, unless otherwise specified.

Note 3: When the input voltage at any pin exceeds the power supply limits (that is, less than GND or greater than V

25 mA. The 50 mA maximum package input current rating limits the number of pins that can safely exceed the power supplies with an input current of 25 mA to two.
This limit is not placed upon the power, ground and digital output pins.

Note 4: Human body model is 100 pF capacitor discharged through a 1.5 kΩ resistor. Machine model is 220 pF discharged through ZERO Ohms.

Note 5: See AN-450, “Surface Mounting Methods and Their Effect on Product Reliability”.

Note 6: The analog inputs are protected as shown below. Input voltage magnitudes beyond the Absolute Maximum Ratings may damage this device.

Aperture Jitter 0.4 ps rms

Input Clock to Data Output Delay

Pipeline Delay (Latency) (Note 11)

50% of Input Clock transition to
50% of Data transition

"D" Outputs 7

"Dd" Outputs 8

PD low to Rated Accuracy
Conversion (Wake-Up Time)

Calibration Cycle Time 46,000 Clock Cycles

= 1 GHz at 0.5V

CLK

with 50% duty cycle, R

P-P

MIN

(Note 8)

to T

Typical

. All other limits TA= 25˚C,

MAX

Limits

(Note 8)

2.7 ns

500 ns

), the current at that pin should be limited to

A

= 3300Ω

EXT

Units

(Limits)

Clock Cycles

ADC081000

20068104

Note 7: To guarantee accuracy, it is required that VAand VDRbe well bypassed. Each supply pin must be decoupled with separate bypass capacitors. Additionally,
achieving rated performance requires that the backside exposed pad be well grounded.

Note 8: Typical figures are at T
Level).

Note 9: Calculation of Full-Scale Error for this device assumes that the actual reference voltage is exactly its nominal value. Full-Scale Error for this device,
therefore, is a combination of Full-Scale Error and Reference Voltage Error. See Transfer Characteristic Figure 2. For relationship between Gain Error and Full-Scale
Error, see Specification Definitions for Gain Error.

Note 10: The analog and clock input capacitances are die capacitances only.Additional package capacitances of 0.65 pF differential and 0.95 pF each pin to ground
are isolated from the die capacitances by lead and bond wire inductances.

Note 11: This parameter is guaranteed by design and is not tested in production.

Note 12: This parameter is guaranteed by design and characterization and is not tested in production.

Note 13: The digital control pin capacitances are die capacitances only. Additional package capacitance of 1.6 pF each pin to ground are isolated from the die

capacitances by lead and bond wire inductances.

Note 14: The ADC081000 has two interleaved LVDS output buses, which each clock data out at one half the sample rate. The data at each bus is clocked out at
one half the sample rate. The second bus (D0 through D7) has a pipeline latency that is one clock cycle less than the latency of the first bus (Dd0 through Dd7).

= 25˚C, and represent most likely parametric norms. Test limits are guaranteed to National’s AOQL (Average Outgoing Quality

J

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