Rainbow Electronics ADC0809 User Manual
November 1995
ADC0808/ADC0809
8-Bit µP Compatible A/D Converters with 8-Channel
Multiplexer
ADC0808/ADC0809 8-Bit µP Compatible A/D Converters with 8-Channel Multiplexer
General Description
The ADC0808, ADC0809 data acquisition component is a
monolithic CMOS device with an 8-bit analog-to-digital converter,8-channelmultiplexerand microprocessor compatible
control logic. The 8-bit A/D converter uses successive approximation as the conversion technique. The converter features a high impedance chopper stabilized comparator, a
256R voltage divider with analog switch tree and a successive approximation register. The 8-channel multiplexer can
directly access any of 8-single-ended analog signals.
The device eliminates the need for external zero and
full-scale adjustments. Easy interfacing to microprocessors
is provided by the latched and decoded multiplexer address
inputs and latched TTL TRI-STATE
The design of the ADC0808, ADC0809 has been optimized
by incorporating the most desirable aspects of several A/D
conversion techniques. The ADC0808, ADC0809 offers high
speed, high accuracy, minimal temperature dependence, excellent long-term accuracy and repeatability, and consumes
minimal power. These features make this device ideally
suited to applications from process and machine control to
consumer and automotive applications. For 16-channel multiplexer with common output (sample/hold port) see
ADC0816 data sheet. (See AN-247 for more information.)
®
outputs.
Features
n Easy interface to all microprocessors
n Operates ratiometrically or with 5 V
adjusted voltage reference
n No zero or full-scale adjust required
n 8-channel multiplexer with address logic
n 0V to 5V input range with single 5V power supply
n Outputs meet TTL voltage level specifications
n Standard hermetic or molded 28-pin DIP package
n 28-pin molded chip carrier package
n ADC0808 equivalent to MM74C949
n ADC0809 equivalent to MM74C949-1
or analog span
DC
Key Specifications
n Resolution: 8 Bits
n Total Unadjusted Error:
n Single Supply: 5 V
n Low Power: 15 mW
n Conversion Time: 100 µs
1
±
⁄2LSB and±1 LSB
DC
TRI-STATE®is a registered trademark of National Semiconductor Corp.
© 1997 National Semiconductor Corporation DS005672 www.national.com
Block Diagram
DS005672-1
See Ordering
Information
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Absolute Maximum Ratings (Notes 1,
2)
If Military/Aerospace specified devices are required,
please contact the National Semiconductor Sales Office/
Distributors for availability and specifications.
Supply Voltage (V
Voltage at Any Pin −0.3V to (V
Except Control Inputs
Voltage at Control Inputs −0.3V to +15V
(START, OE, CLOCK, ALE, ADD A, ADD B, ADD C)
Storage Temperature Range −65˚C to +150˚C
Package Dissipation at T
Lead Temp. (Soldering, 10 seconds)
Dual-In-Line Package (plastic) 260˚C
) (Note 3) 6.5V
CC
=
25˚C 875 mW
A
CC
+0.3V)
Dual-In-Line Package (ceramic) 300˚C
Molded Chip Carrier Package
Vapor Phase (60 seconds) 215˚C
Infrared (15 seconds) 220˚C
ESD Susceptibility (Note 8) 400V
Operating Conditions (Notes 1, 2)
Temperature Range (Note 1) T
ADC0808CJ −55˚C≤TA≤+125˚C
ADC0808CCJ, ADC0808CCN,
ADC0809CCN −40˚C≤T
ADC0808CCV, ADC0809CCV −40˚C ≤ T
Range of V
(Note 1) 4.5 VDCto 6.0 V
CC
MIN≤TA≤TMAX
≤+85˚C
A
≤ +85˚C
A
DC
Electrical Characteristics
Converter Specifications: V
=
5V
CC
V
DC
REF+,VREF(−)
=
GND, T
MIN≤TA≤TMAX
and f
=
640 kHz unless otherwise stated.
CLK
=
Symbol Parameter Conditions Min Typ Max Units
ADC0808
1
Total Unadjusted Error 25˚C
(Note 5) T
MIN
to T
MAX
±
⁄
2
3
±
⁄
4
ADC0809
Total Unadjusted Error 0˚C to 70˚C
(Note 5) T
MIN
to T
MAX
±
1 LSB
±
11⁄
4
Input Resistance From Ref(+) to Ref(−) 1.0 2.5 kΩ
V
REF(+)
Analog Input Voltage Range (Note 4) V(+) or V(−) GND−0.10 V
Voltage, Top of Ladder Measured at Ref(+) V
CC
+0.10 V
CC
VCC+0.1 V
Voltage, Center of Ladder VCC/2-0.1 VCC/2 VCC/2+0.1 V
V
I
REF(−)
IN
Voltage, Bottom of Ladder Measured at Ref(−) −0.1 0 V
Comparator Input Current f
=
640 kHz, (Note 6) −2
c
±
0.5 2 µA
Electrical Characteristics
Digital Levels and DC Specifications: ADC0808CJ 4.5V≤VCC≤5.5V, −55˚C≤TA≤+125˚C unless otherwise noted
ADC0808CCJ, ADC0808CCN, ADC0808CCV, ADC0809CCN and ADC0809CCV, 4.75≤VCC≤5.25V, −40˚C≤TA≤+85˚C unless
otherwise noted
Symbol Parameter Conditions Min Typ Max Units
ANALOG MULTIPLEXER
=
I
OFF(+)
I
OFF(−)
OFF Channel Leakage Current V
OFF Channel Leakage Current V
CONTROL INPUTS
V
V
I
IN(1)
IN(0)
IN(1)
Logical “1” Input Voltage VCC−1.5 V
Logical “0” Input Voltage 1.5 V
Logical “1” Input Current V
(The Control Inputs)
I
IN(0)
Logical “0” Input Current V
(The Control Inputs)
I
CC
Supply Current f
CC
=
T
A
T
MIN
CC
=
T
A
T
MIN
IN
IN
CLK
=
5V, V
5V,
IN
25˚C 10 200 nA
to T
=
5V, V
MAX
=
0,
IN
1.0 µA
25˚C −200 −10 nA
to T
MAX
=
15V 1.0 µA
=
0 −1.0 µA
=
640 kHz 0.3 3.0 mA
−1.0 µA
LSB
LSB
LSB
DC
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Electrical Characteristics (Continued)
Digital Levels and DC Specifications: ADC0808CJ 4.5V≤VCC≤5.5V, −55˚C≤TA≤+125˚C unless otherwise noted
ADC0808CCJ, ADC0808CCN, ADC0808CCV, ADC0809CCN and ADC0809CCV, 4.75≤VCC≤5.25V, −40˚C≤TA≤+85˚C unless
otherwise noted
Symbol Parameter Conditions Min Typ Max Units
DATA OUTPUTS AND EOC (INTERRUPT)
V
V
V
I
OUT
OUT(1)
OUT(0)
OUT(0)
Logical “1” Output Voltage I
Logical “0” Output Voltage I
Logical “0” Output Voltage EOC I
TRI-STATE Output Current V
=
−360 µA V
O
=
1.6 mA 0.45 V
O
=
1.2 mA 0.45 V
O
=
5V 3 µA
O
=
V
0−3 µA
O
−0.4 V
CC
Electrical Characteristics
=
Timing Specifications V
CC
V
REF(+)
=
5V, V
Symbol Parameter Conditions MIn Typ Max Units
t
WS
t
WALE
t
s
t
H
t
D
Minimum Start Pulse Width (
Minimum ALE Pulse Width (
Minimum Address Set-Up Time (
Minimum Address Hold Time (
Analog MUX Delay Time R
From ALE
t
H1,tH0
t
1H,t0H
t
c
f
c
t
EOC
C
IN
C
OUT
OE Control to Q Logic State C
OE Control to Hi-Z C
Conversion Time f
Clock Frequency 10 640 1280 kHz
EOC Delay Time (
Input Capacitance At Control Inputs 10 15 pF
TRI-STATE Output At TRI-STATE Outputs 10 15 pF
Capacitance
Note 1: AbsoluteMaximum Ratings indicate limits beyond which damage to the device may occur. DC and AC electrical specifications do not apply when operating
the device beyond its specified operating conditions.
Note 2: All voltages are measured with respect to GND, unless othewise specified.
Note 3: A zener diode exists, internally, from V
Note 4: Two on-chip diodes are tied to each analog input which will forward conduct for analog input voltages one diode drop below ground or one diode drop greater
than the V
than 100 mV,the output code will be correct. To achieve an absolute 0V
over temperature variations, initial tolerance and loading.
Note 5: Total unadjusted error includes offset, full-scale, linearity, and multiplexer errors. See
ever,if an all zero code is desired for an analog input other than 0.0V, or if a narrow full-scale span exists (for example: 0.5V to 4.5V full-scale) the reference voltages
can be adjusted to achieve this. See
Note 6: Comparator input current is a bias current into or out of the chopper stabilized comparator. The bias current varies directly with clock frequency and has little
temperature dependence (
Note 7: The outputs of the data register are updated one clock cycle before the rising edge of EOC.
Note 8: Human body model, 100 pF discharged through a 1.5 kΩ resistor.
n supply. The spec allows 100 mV forward bias of either diode. This means that as long as the analog VINdoes not exceed the supply voltage by more
CC
Figure *NO TGT: fig NS0592*
Figure 13
CC
.
=
=
GND, t
REF(−)
Figure 5
Figure 5
Figure 5
Figure 5
S
=
L
=
L
=
c
Figure 5
to GND and has a typical breakdown voltage of 7 VDC.
). See paragraph 4.0.
=
t
20 ns and T
r
f
) 100 200 ns
) 100 200 ns
)2550ns
)2550ns
=
Figure 5
0Ω (
50 pF, R
10 pF, R
640 kHz, (
) 1 2.5 µS
=
10k (
L
=
10k (
L
Figure 5
) 0 8+2 µS Clock
to 5VDCinput voltage range will therefore require a minimum supply voltage of 4.900 V
DC
=
25˚C unless otherwise noted.
A
Figure 8
) 125 250 ns
Figure 8
) 125 250 ns
) (Note 7) 90 100 116 µS
Figure 2
. None of these A/Ds requires a zero or full-scale adjust. How-
Periods
DC
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Functional Description
Multiplexer.The device contains an 8-channel single-ended
analog signal multiplexer. A particular input channel is selected by using the address decoder.
states for the address lines to select any channel. The address is latched into the decoder on the low-to-high transition
of the address latch enable signal.
TABLE 1.
SELECTED ADDRESS LINE
ANALOG
CHANNEL
IN0 L L L
IN1 L L H
IN2 L H L
IN3 L H H
IN4 H L L
IN5 H L H
IN6 H H L
IN7 H H H
CONVERTER CHARACTERISTICS
The Converter
The heart of this single chip data acquisition system is its
8-bit analog-to-digital converter.The converter is designed to
give fast, accurate, and repeatable conversions over a wide
range of temperatures. The converter is partitioned into 3
major sections: the 256R ladder network, the successive approximation register, and the comparator. The converter’s
digital outputs are positive true.
The 256R ladder network approach (
over the conventional R/2R ladder because of its inherent
monotonicity, which guarantees no missing digital codes.
Monotonicity is particularly important in closed loop feedback
control systems. Anon-monotonic relationship can cause oscillations that will be catastrophic for the system. Additionally,
the 256R network does not cause load variations on the reference voltage.
Table1
shows the input
CBA
Figure 1
) was chosen
The bottom resistor and the top resistor of the ladder network in
Figure 1
the network. The difference in these resistors causes the
output characteristic to be symmetrical with the zero and
full-scale points of the transfer curve. The first output transition occurs when the analog signal has reached +
and succeeding output transitions occur every 1 LSB later up
to full-scale.
The successive approximation register (SAR) performs 8 iterations to approximate the input voltage. For any SAR type
converter, n-iterations are required for an n-bit converter.
Figure 2
ADC0808, ADC0809, the approximation technique is extended to 8 bits using the 256R network.
The A/D converter’s successive approximation register
(SAR) is reset on the positive edge of the start conversion
(SC) pulse. The conversion is begun on the falling edge of
the start conversion pulse. A conversion in process will be interrupted by receipt of a new start conversion pulse. Continuous conversion may be accomplished by tying the
end-of-conversion (EOC) output to the SC input. If used in
this mode, an external start conversion pulse should be applied after power up. End-of-conversion will go low between
0 and 8 clock pulses after the rising edge of start conversion.
The most important section of the A/D converter is the comparator. It is this section which is responsible for the ultimate
accuracy of the entire converter. It is also the comparator
drift which has the greatest influence on the repeatability of
the device. A chopper-stabilized comparator provides the
most effective method of satisfying all the converter requirements.
The chopper-stabilized comparator converts the DC input
signal into an AC signal. This signal is then fed throught a
high gain AC amplifier and has the DC level restored. This
technique limits the drift component of the amplifier since the
drift is a DC component which is not passed by the AC amplifier. This makes the entire A/D converter extremely insensitive to temperature, long term drift and input offset errors.
Figure 4
measured using the procedures outlined in AN-179.
are not the same value as the remainder of
1
⁄2LSB
shows a typical example of a 3-bit converter. In the
shows a typical error curve for the ADC0808 as
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