Rainbow Electronics ADC08062 User Manual

ADC08061/ADC08062
500 ns A/D Converter with S/H Function
and Input Multiplexer

November 1995

ADC08061/ADC08062

500 ns A/D Converter with S/H Function and Input Multiplexer

General Description

Using a patented multi-step A/D conversion technique, the
8-bit ADC08061 and ADC08062 CMOS ADCs offer 500 ns
(typ) conversion time, internal sample-and-hold (S/H), and
dissipate only 125 mW of power. The ADC08062 has a two­channel multiplexer. The ADC08061/2 family performs an
8-bit conversion using a 2-bit voltage estimator that gener­ates the 2 MSBs and two low-resolution (3-bit) flashes that
generate the 6 LSBs.

Input track-and-hold circuitry eliminates the need for an ex­ternal sample-and-hold. The ADC08061/2 family performs
accurate conversions of full-scale input signals that have a
frequency range of DC to 300 kHz (full-power bandwidth)
without need of an external S/H.

The digital interface has been designed to ease connection
to microprocessors and allows the parts to be I/O or memo­ry mapped.

Block Diagram

Key Specifications

Y

Resolution 8 bits

Y

Conversion Time 560 ns max (WR-RD Mode)

Y

Full Power Bandwidth 300 kHz

Y

Throughput rate 1.5 MHz

Y

Power Dissipation 100 mW max

Y

Total Unadjusted Error

g

(/2 LSB andg1 LSB

Features

Y

1 or 2 input channels

Y

No external clock required

Y

Analog input voltage range from GND to V

Y

Overflow output available for cascading (ADC08061)

Y

ADC08061 pin-compatible with the industry standard

a

ADC0820

Applications

Y

Mobile telecommunications

Y

Hard disk drives

Y

Instrumentation

Y

High-speed data acquisition systems

*ADC08061 TL/H/11086– 1

**ADC08062

TRI-STATEÉis a registered trademark of National Semiconductor Corporation.

C

1996 National Semiconductor Corporation RRD-B30M36/Printed in U. S. A.

TL/H/11086

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Absolute Maximum Ratings (Notes1&2)

If Military/Aerospace specified devices are required,
please contact the National Semiconductor Sales
Office/Distributors for availability and specifications.

Supply Voltage (V

Logic Control Inputs

Voltage at Other Inputs and Outputs

Input Current at Any Pin (Note 3) 5 mA

Package Input Current (Note 3) 20 mA

Power Dissipation (Note 4)

J Package 875 mW
N Package 875 mW
WM Package 875 mW

Storage Temperature

a

)6V

b

b

a

0.3V to V

a

0.3V to V

b

65§Ctoa150§C

a

0.3V

a

0.3V

Lead Temperature (Note 5)

J Package (Soldering, 10 sec.)
N Package (Soldering, 10 sec.)
WM Package (Vapor Phase, 60 sec.)
WM Package (Infrared, 15 sec.)

a
a
a
a

300§C
260§C
215§C
220§C

ESD Susceptibility (Note 6) 2 kV

Operating Ratings (Notes1&2)

s

Temperature Range T

ADC08061/2BIN,

MIN

ADC08061/2CIN,
ADC08061/2BIWM,
ADC08061/2CIWM
ADC08061CMJ/883

b

40§CsT

b

55§CsT

Supply Voltage, (Va) 4.5V to 5.5V

s

T

T

A

MAX

s

85§C

A

s

125§C

A

Converter Characteristics

The following specifications apply for RD Mode, V

Boldface limits apply for T

Symbol Parameter Conditions

e

e

T

A

J

a

e

to T

MAX

5V, V

; all other limits T

T

MIN

REF

a

e

5V, and V

e

b

REF

e

e

T

A

25§C.

J

Typical Limits

(Note 7) (Note 8)

GND unless otherwise specified.

Units

(Limit)

INL Integral Non Linearity ADC08061/2

g

BIN, BIWM

ADC08061/2
CIN, CIWM, CMJ

TUE Total Unadjusted Error ADC08061/2

BIN, BIWM

ADC08061/2
CIN, CIWM, CMJ

(/2 LSB (max)

g

1 LSB (max)

g

(/2 LSB (max)

g

1 LSB (max)

Missing Codes 0 Bits (max)

Reference Input Resistance 700 500 X(min)

700 1250 X (max)

V

REF

V

REF

V

IN

PSS Power Supply Sensitivity V

Positive Reference V

a

Input Voltage V

Negative Reference GND V (min)

b

Input Voltage V

Analog (Note 10) GNDb0.1 V (min)
Input Voltage V

On Channel Input On Channel Inpute5V,

e

Current Off Channel Input

0V (Note 11)

On Channel Inpute0V,

e

Off Channel Input

a

e

5Vg5%, V

All Codes Tested

5V (Note 11)

REF

e

4.75V

b

0.4

b

0.4

g

(/16

b

REF

a

a

REF

a

a

0.1 V (max)

b

20 mA (max)

b

20 mA (max)

g

(/2 LSB (max)

V (min)

V (max)

V (max)

Effective Bits 7.8 Bits

Full-Power Bandwidth 300 kHz

THD Total Harmonic Distortion 0.5 %

S/N Signal-to-Noise Ratio 50 dB

IMD Intermodulation Distortion 50 dB

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AC Electrical Characteristics

The following specifications apply for V

Boldface limits apply for T

a

e

e

e

T

A

J

T

5V, t

MIN

r

to T

e

MAX

e

t

10 ns, V

f

; all other limits T

REF

e

5V, V

a

e

T

A

e

0V unless otherwise specified.

b

REF

e

25§C.

J

AD08061 and

Symbol Parameter Condition

ADC08062 with BIN,

Typical

(Note 7)

BIWM, CIN and
CIWM suffixes

ADC08061CMJ

Limits (Limit)

(Note 8) (Note 8)

t

Write Time Mode Pin to Va;

WR

t

Read Time (Time from Falling Edge Mode Pin to Va;

RD

t

RDW

t

CONV

t

CRD

t

ACCO

t

ACC1

t

ACC2

t

0H

t

1H

t

INTL

t

INTH

t

INTH

t

RDY

t

ID

t

RI

t

N

t

AH

t

AS

t

CSS

t

CSH

C

VIN

C

OUT

C

IN

to Falling Edge of RD)

of WR

Width Mode Pin to GND;

RD

WR-RD Mode Conversion Time Mode Pin to Va;

a

(t

WR

a

t

t

ACC1

)

RD

RD Mode Conversion Time Mode Pin to GND;

Access Time (Delay from Falling C
Edge of RD

to Output Valid) Mode Pin to GND;

Access Time (Delay from C
Falling Edge C

to Output Valid) Mode Pin to Va,t

of RD

Access Time (Delay from C
Falling Edge C

to Output Valid) t

of RD

TRI-STATEÉControl (Delay from R
Rising Edge of RD

to HI-Z State)

TRI-STATE Control (Delay from R
Rising Edge of RD to HI-Z State)

Delay from Rising Edge of (

to Falling Edge of INT Mode PineVa,C

WR

Delay from Rising Edge of C

to Rising Edge of INT

RD

Delay from Rising Edge of C

to Rising Edge of INT

WR

Delay from CS to RDY Mode Pine0V, C

Delay from INT to Output Valid R

Delay from RD to INT Mode PineVa,t

Time between End of RD (
and Start of New Conversion

Channel Address Hold Time (

Channel Address Setup Time (

CS Setup Time (

CS Hold Time (

Analog Input Capacitance 25 pF

Logic Output Capacitance 5 pF

Logic Input Capacitance 5 pF

(

Figures 2a, 2b,

and3)

(Figure 2a)

(Figure 4)

(Figure 2a)

(Figure 1)

s

100 pF

L

s

10 pF 45

L

e

100 pF 50

L

(Figure 2a)

s

10 pF 25

L

e

100 pF 30

L

l

t

RD

INTL

e

3kX,C

L

e

3kX,C

L

Figures 2b,

e

50 pF; (

L

2b, and 4

e

50 pF;

L

e

3kX

R

L

e

3kX,C

L

(Figure 3)

(Figure 2a)

Figures 1, 2a, 2b, 3

Figures 1, 2a, 2b, 3

Figures 1, 2a, 2b, 3

Figures 1, 2a, 2b, 3

Figures 1, 2a, 2b, 3

;(

Figures 2b

e

L

e

L

and3)

Figures 1, 2a,

)

(Figure 3)

(Figure 1)

e

L

(Figure 1)

s

RD

10 pF

10 pF

e

L

e

50 pF,

L

100 pF; 0

s

RD

and4)

and4)10 60 60 ns (min)

and4)0 00ns (max)

and4)0 00ns (max)

and4)0 00ns (min)

t

INTL

and4)

50 pF

t

100 100 100 ns (min)

350 350 515 ns (min)

200 250 250 ns (min)
400 400 400 ns (max)

500 560 790 ns (max)

655 900 940 ns (max)

640 900 940 ns (max)

110 175 ns (max)

55 60 ns (max)

30 60 60 ns (max)

30 60 60 ns (max)

520 690 690 ns (max)

50 95 100 ns (max)

45 95 100 ns (max)

25 45 50 ns (max)

15 15 ns (max)

;

INTL

60 115 175 ns (max)

50 50 50 ns (min)

Units

(Limit)

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DC Electrical Characteristics The following specifications apply for V

Boldface limits apply for T

Symbol Parameter Conditions

V

IH

Logic ‘‘1’’ Input Voltage V

e

e

T

T

to T

A

J

MIN

; all other limits T

MAX

e

e

T

A

J

(Note 7) (Note 8)

a

e

5.5V

Mode Pin 3.5 V (min)

ADC08062
CS

,WR,RD, A0 Pins 2.2 V (min)

ADC08061
CS

,WR,RDPins 2.0 V (min)

a

V

IL

Logic ‘‘0’’ Input Voltage V

e

4.5V

Mode Pin 1.5 V (max)

ADC08062
CS

,WR,RD, A0 Pins 0.7 V (max)

ADC08061
CS

,WR,RDPins 0.8 V (max)

I

IH

Logic ‘‘1’’ Input Current V

e

5V

IH

CS

,RD, A0 Pins 0.005 1 mA (max)

WR

Pin 0.1 3 mA (max)

Mode Pin 50 200 mA (max)

I

IL

Logic ‘‘0’’ Input Current V

e

0V

IL

CS,RD,WR, A0 Pins
Mode Pin

a

V

OH

V

OL

I

O

I

SOURCE

I

SINK

I

C

Logic ‘‘1’’ Output Voltage V

Logic ‘‘0’’ Output Voltage V

TRI-STATE Output Current V

Output Source Current V

Output Sink Current V

Supply Current CSeWReRDe0 11.5 20 mA (max)

e

4.75V

eb

I
DB0–DB7, OFL
I
DB0–DB7, OFL

I
DB0–DB7, OFL

DB0–DB7, RDY

V
DB0–DB7, RDY

DB0–DB7, OFL

DB0–DB7, OFL

360 mA

OUT

OUT

a

OUT

OUT

OUT

OUT

OUT

eb

e

e

, INT 2.4 V (min)

10 mA

, INT 4.5 V (min)

4.75V

1.6 mA 0.4 V (max)

, INT, RDY

e

5.0V

e

0V

e

0V

, INT

e

5V

, INT, RDY

a

e

5V unless otherwise specified.

25§C.

Typical Limits

Units

(Limit)

b

0.005 mA (max)

b

2

0.1 3 mA (max)

b

0.1

b

26

b

3 mA (max)

b

6 mA (min)

24 7 mA (min)

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Electrical Characteristics (Continued)

Note 1: Absolute Maximum Ratings indicate limits beyond which damage to the device may occur. DC and AC electrical specifications do not apply when operating

the device beyond its specified operating ratings. Operating Ratings indicate conditions for which the device is functional, but do not guarantee performance limits.
For guaranteed specifications and test conditions, see the Electrical Characteristics. The guaranteed specifications apply only for the test conditions listed. Some
performance characteristics may degrade when the device is not operated under the listed test conditions.

Note 2: All voltages are measured with respect to the GND pin, unless otherwise specified.

Note 3: When the input voltage (V

limited to 5 mA or less. The 20 mA package input current specification limits the number of pins that can exceed the power supply boundaries witha5mAcurrent
limit to four.

Note 4: The power dissipation of this device under normal operation should never exceed 875 mW (Quiescent Power Dissipation
outputs). Caution should be taken not to exceed absolute maximum power rating when the device is operating in a severe fault condition (e.g., when any input or
output exceeds the power supply). The maximum power dissipation must be derated at elevated temperatures and is dictated by T
temperature), i
is PD

max

packages and versions of the ADC08061/2.

(package junction to ambient thermal resistance), and TA(ambient temperature). The maximum allowable power dissipation at any temperature

JA

e

b

(T

TA)/iJAor the number given in the Absolute Maximum Ratings, whichever is lower. The table below details T

JMAX

) at any pin exceeds the power supply voltage (V

IN

Part Number T

ADC08061/2BIN 105 51
ADC08061/2CIN 105 51
ADC08061/2BIWM 105 85
ADC08061/2CIWM 105 85
ADC08061/2CMJ 125 76

Note 5: See AN-450 ‘‘Surface Mounting Methods and Their Effect on Product Reliability’’ for other methods of soldering surface mount devices.

Note 6: Human body model, 100 pF discharged through a 1.5 kX resistor.

Note 7: Typicals are at 25

C and represent most likely parametric norm.

§

Note 8: Limits are guaranteed to National’s AOQL (Average Output Quality Level).

Note 9: Total unadjusted error includes offset, full-scale, and linearity errors.

Note 10: Two on-chip diodes are tied to each analog input and are reversed biased during normal operation. One is connected to V

GND. They will become forward biased and conduct when an analog input voltage is equal to or greater than one diode drop above V
caution should be exercised when testing with V
temperatures. This can create conversion errors for analog signals near full-scale. The specification allows 50 mV forward bias on either diode; e.g., the output
code will be correct as long as the analog input signal does not exceed the supply voltage by more than 50 mV. Exceeding this range on an unselected channel will
corrupt the reading of a selected channel. An absolute analog input signal voltage range of 0V
voltage applied to V

a

is 4.950V over temperature variations, initial tolerance, and loading.

a

e

4.5V. Analog inputs with magnitudes equal to 5V can cause an input diode to conduct, especially at elevated

Note 11: Off-channel leakage current is measured after the on-channel selection.

IN

k

GND or V

JMAX

l

Va), the absolute value of the current at that pin should be

IN

a

the loads on the digital

JMAX

and iJAfor the various

JMAX

i

JA

a

and the other is connected to

a

or below GND. Therefore,

s

s

V

5V can be achieved by ensuring that the minimum supply

IN

(maximum junction

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