ADC08061/ADC08062
500 ns A/D Converter with S/H Function
and Input Multiplexer
November 1995
ADC08061/ADC08062
500 ns A/D Converter with S/H Function and Input Multiplexer
General Description
Using a patented multi-step A/D conversion technique, the
8-bit ADC08061 and ADC08062 CMOS ADCs offer 500 ns
(typ) conversion time, internal sample-and-hold (S/H), and
dissipate only 125 mW of power. The ADC08062 has a twochannel multiplexer. The ADC08061/2 family performs an
8-bit conversion using a 2-bit voltage estimator that generates the 2 MSBs and two low-resolution (3-bit) flashes that
generate the 6 LSBs.
Input track-and-hold circuitry eliminates the need for an external sample-and-hold. The ADC08061/2 family performs
accurate conversions of full-scale input signals that have a
frequency range of DC to 300 kHz (full-power bandwidth)
without need of an external S/H.
The digital interface has been designed to ease connection
to microprocessors and allows the parts to be I/O or memory mapped.
Block Diagram
Key Specifications
Y
Resolution 8 bits
Y
Conversion Time 560 ns max (WR-RD Mode)
Y
Full Power Bandwidth 300 kHz
Y
Throughput rate 1.5 MHz
Y
Power Dissipation 100 mW max
Y
Total Unadjusted Error
g
(/2 LSB andg1 LSB
Features
Y
1 or 2 input channels
Y
No external clock required
Y
Analog input voltage range from GND to V
Y
Overflow output available for cascading (ADC08061)
Y
ADC08061 pin-compatible with the industry standard
a
ADC0820
Applications
Y
Mobile telecommunications
Y
Hard disk drives
Y
Instrumentation
Y
High-speed data acquisition systems
*ADC08061 TL/H/11086– 1
**ADC08062
TRI-STATEÉis a registered trademark of National Semiconductor Corporation.
C
1996 National Semiconductor Corporation RRD-B30M36/Printed in U. S. A.
TL/H/11086
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Absolute Maximum Ratings (Notes1&2)
If Military/Aerospace specified devices are required,
please contact the National Semiconductor Sales
Office/Distributors for availability and specifications.
Supply Voltage (V
Logic Control Inputs
Voltage at Other Inputs and Outputs
Input Current at Any Pin (Note 3) 5 mA
Package Input Current (Note 3) 20 mA
Power Dissipation (Note 4)
J Package 875 mW
N Package 875 mW
WM Package 875 mW
Storage Temperature
a
)6V
b
b
a
0.3V to V
a
0.3V to V
b
65§Ctoa150§C
a
0.3V
a
0.3V
Lead Temperature (Note 5)
J Package (Soldering, 10 sec.)
N Package (Soldering, 10 sec.)
WM Package (Vapor Phase, 60 sec.)
WM Package (Infrared, 15 sec.)
a
a
a
a
300§C
260§C
215§C
220§C
ESD Susceptibility (Note 6) 2 kV
Operating Ratings (Notes1&2)
s
Temperature Range T
ADC08061/2BIN,
MIN
ADC08061/2CIN,
ADC08061/2BIWM,
ADC08061/2CIWM
ADC08061CMJ/883
b
40§CsT
b
55§CsT
Supply Voltage, (Va) 4.5V to 5.5V
s
T
T
A
MAX
s
85§C
A
s
125§C
A
Converter Characteristics
The following specifications apply for RD Mode, V
Boldface limits apply for T
Symbol Parameter Conditions
e
e
T
A
J
a
e
to T
MAX
5V, V
; all other limits T
T
MIN
REF
a
e
5V, and V
e
b
REF
e
e
T
A
25§C.
J
Typical Limits
(Note 7) (Note 8)
GND unless otherwise specified.
Units
(Limit)
INL Integral Non Linearity ADC08061/2
g
BIN, BIWM
ADC08061/2
CIN, CIWM, CMJ
TUE Total Unadjusted Error ADC08061/2
BIN, BIWM
ADC08061/2
CIN, CIWM, CMJ
(/2 LSB (max)
g
1 LSB (max)
g
(/2 LSB (max)
g
1 LSB (max)
Missing Codes 0 Bits (max)
Reference Input Resistance 700 500 X(min)
700 1250 X (max)
V
REF
V
REF
V
IN
PSS Power Supply Sensitivity V
Positive Reference V
a
Input Voltage V
Negative Reference GND V (min)
b
Input Voltage V
Analog (Note 10) GNDb0.1 V (min)
Input Voltage V
On Channel Input On Channel Inpute5V,
e
Current Off Channel Input
0V (Note 11)
On Channel Inpute0V,
e
Off Channel Input
a
e
5Vg5%, V
All Codes Tested
5V (Note 11)
REF
e
4.75V
b
0.4
b
0.4
g
(/16
b
REF
a
a
REF
a
a
0.1 V (max)
b
20 mA (max)
b
20 mA (max)
g
(/2 LSB (max)
V (min)
V (max)
V (max)
Effective Bits 7.8 Bits
Full-Power Bandwidth 300 kHz
THD Total Harmonic Distortion 0.5 %
S/N Signal-to-Noise Ratio 50 dB
IMD Intermodulation Distortion 50 dB
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AC Electrical Characteristics
The following specifications apply for V
Boldface limits apply for T
a
e
e
e
T
A
J
T
5V, t
MIN
r
to T
e
MAX
e
t
10 ns, V
f
; all other limits T
REF
e
5V, V
a
e
T
A
e
0V unless otherwise specified.
b
REF
e
25§C.
J
AD08061 and
Symbol Parameter Condition
ADC08062 with BIN,
Typical
(Note 7)
BIWM, CIN and
CIWM suffixes
ADC08061CMJ
Limits (Limit)
(Note 8) (Note 8)
t
Write Time Mode Pin to Va;
WR
t
Read Time (Time from Falling Edge Mode Pin to Va;
RD
t
RDW
t
CONV
t
CRD
t
ACCO
t
ACC1
t
ACC2
t
0H
t
1H
t
INTL
t
INTH
t
INTH
t
RDY
t
ID
t
RI
t
N
t
AH
t
AS
t
CSS
t
CSH
C
VIN
C
OUT
C
IN
to Falling Edge of RD)
of WR
Width Mode Pin to GND;
RD
WR-RD Mode Conversion Time Mode Pin to Va;
a
(t
WR
a
t
t
ACC1
)
RD
RD Mode Conversion Time Mode Pin to GND;
Access Time (Delay from Falling C
Edge of RD
to Output Valid) Mode Pin to GND;
Access Time (Delay from C
Falling Edge C
to Output Valid) Mode Pin to Va,t
of RD
Access Time (Delay from C
Falling Edge C
to Output Valid) t
of RD
TRI-STATEÉControl (Delay from R
Rising Edge of RD
to HI-Z State)
TRI-STATE Control (Delay from R
Rising Edge of RD to HI-Z State)
Delay from Rising Edge of (
to Falling Edge of INT Mode PineVa,C
WR
Delay from Rising Edge of C
to Rising Edge of INT
RD
Delay from Rising Edge of C
to Rising Edge of INT
WR
Delay from CS to RDY Mode Pine0V, C
Delay from INT to Output Valid R
Delay from RD to INT Mode PineVa,t
Time between End of RD (
and Start of New Conversion
Channel Address Hold Time (
Channel Address Setup Time (
CS Setup Time (
CS Hold Time (
Analog Input Capacitance 25 pF
Logic Output Capacitance 5 pF
Logic Input Capacitance 5 pF
(
Figures 2a, 2b,
and3)
(Figure 2a)
(Figure 4)
(Figure 2a)
(Figure 1)
s
100 pF
L
s
10 pF 45
L
e
100 pF 50
L
(Figure 2a)
s
10 pF 25
L
e
100 pF 30
L
l
t
RD
INTL
e
3kX,C
L
e
3kX,C
L
Figures 2b,
e
50 pF; (
L
2b, and 4
e
50 pF;
L
e
3kX
R
L
e
3kX,C
L
(Figure 3)
(Figure 2a)
Figures 1, 2a, 2b, 3
Figures 1, 2a, 2b, 3
Figures 1, 2a, 2b, 3
Figures 1, 2a, 2b, 3
Figures 1, 2a, 2b, 3
;(
Figures 2b
e
L
e
L
and3)
Figures 1, 2a,
)
(Figure 3)
(Figure 1)
e
L
(Figure 1)
s
RD
10 pF
10 pF
e
L
e
50 pF,
L
100 pF; 0
s
RD
and4)
and4)10 60 60 ns (min)
and4)0 00ns (max)
and4)0 00ns (max)
and4)0 00ns (min)
t
INTL
and4)
50 pF
t
100 100 100 ns (min)
350 350 515 ns (min)
200 250 250 ns (min)
400 400 400 ns (max)
500 560 790 ns (max)
655 900 940 ns (max)
640 900 940 ns (max)
110 175 ns (max)
55 60 ns (max)
30 60 60 ns (max)
30 60 60 ns (max)
520 690 690 ns (max)
50 95 100 ns (max)
45 95 100 ns (max)
25 45 50 ns (max)
15 15 ns (max)
;
INTL
60 115 175 ns (max)
50 50 50 ns (min)
Units
(Limit)
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DC Electrical Characteristics The following specifications apply for V
Boldface limits apply for T
Symbol Parameter Conditions
V
IH
Logic ‘‘1’’ Input Voltage V
e
e
T
T
to T
A
J
MIN
; all other limits T
MAX
e
e
T
A
J
(Note 7) (Note 8)
a
e
5.5V
Mode Pin 3.5 V (min)
ADC08062
CS
,WR,RD, A0 Pins 2.2 V (min)
ADC08061
CS
,WR,RDPins 2.0 V (min)
a
V
IL
Logic ‘‘0’’ Input Voltage V
e
4.5V
Mode Pin 1.5 V (max)
ADC08062
CS
,WR,RD, A0 Pins 0.7 V (max)
ADC08061
CS
,WR,RDPins 0.8 V (max)
I
IH
Logic ‘‘1’’ Input Current V
e
5V
IH
CS
,RD, A0 Pins 0.005 1 mA (max)
WR
Pin 0.1 3 mA (max)
Mode Pin 50 200 mA (max)
I
IL
Logic ‘‘0’’ Input Current V
e
0V
IL
CS,RD,WR, A0 Pins
Mode Pin
a
V
OH
V
OL
I
O
I
SOURCE
I
SINK
I
C
Logic ‘‘1’’ Output Voltage V
Logic ‘‘0’’ Output Voltage V
TRI-STATE Output Current V
Output Source Current V
Output Sink Current V
Supply Current CSeWReRDe0 11.5 20 mA (max)
e
4.75V
eb
I
DB0–DB7, OFL
I
DB0–DB7, OFL
I
DB0–DB7, OFL
DB0–DB7, RDY
V
DB0–DB7, RDY
DB0–DB7, OFL
DB0–DB7, OFL
360 mA
OUT
OUT
a
OUT
OUT
OUT
OUT
OUT
eb
e
e
, INT 2.4 V (min)
10 mA
, INT 4.5 V (min)
4.75V
1.6 mA 0.4 V (max)
, INT, RDY
e
5.0V
e
0V
e
0V
, INT
e
5V
, INT, RDY
a
e
5V unless otherwise specified.
25§C.
Typical Limits
Units
(Limit)
b
0.005 mA (max)
b
2
0.1 3 mA (max)
b
0.1
b
26
b
3 mA (max)
b
6 mA (min)
24 7 mA (min)
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Electrical Characteristics (Continued)
Note 1: Absolute Maximum Ratings indicate limits beyond which damage to the device may occur. DC and AC electrical specifications do not apply when operating
the device beyond its specified operating ratings. Operating Ratings indicate conditions for which the device is functional, but do not guarantee performance limits.
For guaranteed specifications and test conditions, see the Electrical Characteristics. The guaranteed specifications apply only for the test conditions listed. Some
performance characteristics may degrade when the device is not operated under the listed test conditions.
Note 2: All voltages are measured with respect to the GND pin, unless otherwise specified.
Note 3: When the input voltage (V
limited to 5 mA or less. The 20 mA package input current specification limits the number of pins that can exceed the power supply boundaries witha5mAcurrent
limit to four.
Note 4: The power dissipation of this device under normal operation should never exceed 875 mW (Quiescent Power Dissipation
outputs). Caution should be taken not to exceed absolute maximum power rating when the device is operating in a severe fault condition (e.g., when any input or
output exceeds the power supply). The maximum power dissipation must be derated at elevated temperatures and is dictated by T
temperature), i
is PD
max
packages and versions of the ADC08061/2.
(package junction to ambient thermal resistance), and TA(ambient temperature). The maximum allowable power dissipation at any temperature
JA
e
b
(T
TA)/iJAor the number given in the Absolute Maximum Ratings, whichever is lower. The table below details T
JMAX
) at any pin exceeds the power supply voltage (V
IN
Part Number T
ADC08061/2BIN 105 51
ADC08061/2CIN 105 51
ADC08061/2BIWM 105 85
ADC08061/2CIWM 105 85
ADC08061/2CMJ 125 76
Note 5: See AN-450 ‘‘Surface Mounting Methods and Their Effect on Product Reliability’’ for other methods of soldering surface mount devices.
Note 6: Human body model, 100 pF discharged through a 1.5 kX resistor.
Note 7: Typicals are at 25
C and represent most likely parametric norm.
§
Note 8: Limits are guaranteed to National’s AOQL (Average Output Quality Level).
Note 9: Total unadjusted error includes offset, full-scale, and linearity errors.
Note 10: Two on-chip diodes are tied to each analog input and are reversed biased during normal operation. One is connected to V
GND. They will become forward biased and conduct when an analog input voltage is equal to or greater than one diode drop above V
caution should be exercised when testing with V
temperatures. This can create conversion errors for analog signals near full-scale. The specification allows 50 mV forward bias on either diode; e.g., the output
code will be correct as long as the analog input signal does not exceed the supply voltage by more than 50 mV. Exceeding this range on an unselected channel will
corrupt the reading of a selected channel. An absolute analog input signal voltage range of 0V
voltage applied to V
a
is 4.950V over temperature variations, initial tolerance, and loading.
a
e
4.5V. Analog inputs with magnitudes equal to 5V can cause an input diode to conduct, especially at elevated
Note 11: Off-channel leakage current is measured after the on-channel selection.
IN
k
GND or V
JMAX
l
Va), the absolute value of the current at that pin should be
IN
a
the loads on the digital
JMAX
and iJAfor the various
JMAX
i
JA
a
and the other is connected to
a
or below GND. Therefore,
s
s
V
5V can be achieved by ensuring that the minimum supply
IN
(maximum junction
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TRI-STATE Test Circuits and Waveforms
Timing Diagrams
t
1H
TL/H/11086– 2
t
0H
TL/H/11086– 3
t1H,C
e
t
r
t0H,C
e
t
r
10 ns
10 ns
e
10 pF
L
TL/H/11086– 4
e
10 pF
L
TL/H/11086– 5
FIGURE 1. RD Mode (Mode Pin is Low)
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TL/H/11086– 6
Timing Diagrams (Continued)
FIGURE 2a. WR-RD Mode (Mode Pin is High and t
FIGURE 2b. WR-RD Mode (Mode Pin is High and t
RD
RD
s
t
)
INTL
l
t
)
INTL
TL/H/11086– 7
TL/H/11086– 8
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Timing Diagrams (Continued)
FIGURE 3. WR-RD Mode (Mode Pin is High) Reduced Interface System Connection (CSeRDe0)
FIGURE 4. RD Mode (Pipeline Operation) (Mode Pin is Low and t
must be between 200 ns and 400 ns)
RDW
TL/H/11086– 9
TL/H/11086– 10
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Typical Performance Characteristics
t
vs Temperature Reference Voltage
CRD
Supply Current
vs Temperature
Connection Diagrams
Linearity Error vs
Logic Threshold
vs Temperature
Offset Error vs
Reference Voltage
Output Current
vs Temperature
TL/H/11086– 24
Dual-In-Line and Wide-Body
Small-Outline
Packages J20A, N20A or M20B
Ordering Information
TL/H/11086– 14
Industrial (b40§CsT
ADC08061BIN, ADC08061CIN,
ADC08062BIN, ADC08062CIN
ADC08061BIWM, ADC08061CIWM,
ADC08062BIWM, ADC08062CIWM
ADC08061CMJ/883, 5962 J20A
s
85§C) Package
A
Dual-In-Line and Wide-Body
Packages N20A or M20B
N20A
M20B
TL/H/11086– 15
Small-Outline
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Pin Description
VIN,V
DB0–DB7 TRI-STATE data outputsÐbit 0 (LSB) through
WR
MODE This pin is pulled to a logic low through an inter-
RD
INT This is an active low output that indicates that a
GND This is the power supply ground pin. The
These are analog inputs. The input range is
IN1–8
GND–50 mV
ADC08061 has a single input (V
s
V
INPUT
ADC08062 has a two-channel multiplexer
(V
).
IN1–2
a
s
a
V
50 mV. The
) and the
IN
bit 7 (MSB).
/RDY WR-RD Mode (Logic high applied to MODE
pin)
WR
: With CS low, the conversion is started on
the falling edge of WR
. The digital result will be
strobed into the output latch at the end of conversion (see
RD
Figures 2a, 2b,
and3).
Mode (Logic low applied to MODE pin)
RDY: This is an open drain output (no internal
pull-up device). RDY will go low after the falling
edge of CS
and return high at the end of con-
version.
Mode: Mode (RD
or WR-RD) selection inputÐ
nal 50 mA current sink when left unconnected.
RD
Mode is selected if the MODE pin is left
unconnected or externally forced low. A complete conversion is accomplished by pulling RD
low until output data appears.
WR
-RD Mode is selected when a high is ap-
plied to the MODE pin. A conversion starts with
the WR
signal’s rising edge and then using RD
to access the data.
WR-RD Mode (logic high on the MODE pin)
This is the active low Read input. With a logic
low applied to the CS
pin, the TRI-STATE data
outputs (DB0 – DB7) will be activated when RD
goes low (see
RD
Mode (logic low on the MODE pin)
With CS
edge of RD
at the end of conversion (see
Figures 2a, 2b
and3).
low, a conversion starts on the falling
. Output data appears on DB0 – DB7
Figures 1
and4).
conversion is complete and the data is in the
output latch. INT
RD
.
is reset by the rising edge of
ground pin should be connected to a ‘‘clean’’
ground reference point.
V
b
REF
V
REF
These are the reference voltage inputs. They
may be placed at any voltage between GND
a
50 mV and V
greater than V
equal to V
and an input voltage greater than V
a
a
50 mV, but V
. Ideally, an input voltage
b
REF
produces an output code of 0,
b
REF
1.5 LSB produces an output code of 255.
For the ADC08062, an input voltage on any unselected input that exceeds V
must be
a
REF
REF
a
by more than
a
100 mV or is below GND by more than 100 mV
will create errors in a selected channel that is
operating within proper operating conditions.
CS
This is the active low Chip Select input. A logic
low signal applied to this input pin enables the
RD
and WR inputs. Internally, the CS signal is
ORed with RD
OFL Overflow Output. If the analog input is higher
than V
end of conversion. It can be used when cas-
and WR signals.
b
(/2 LSB, OFL will be low at the
a
REF
cading two ADC08061s to achieve higher resolution (9 bits). This output is always active and
does not go into TRI-STATE as DB0 –DB7 do.
When OFL
is set, all data outputs remain high
when the ADC08061’s output data is read.
NC No connection.
A0 This logic input is used to select one of the
ADC08062’s input multiplexer channels. A
channel is selected as shown in the table below.
ADC08062
A0
0V
1V
a
V
Positive power supply voltage input. Nominal
operating supply voltage is
Channel
IN1
IN2
a
5V. The supply
pin should be bypassed with a 10 mF bead tantalum in parallel with a 0.1 ceramic capacitor.
Lead length should be as short as possible.
b
b
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Application Information
1.0 FUNCTIONAL DESCRIPTION
The ADC08061 and ADC08062 perform an 8-bit analog-todigital conversion using a multi-step flash technique. The
first flash generates the five most significant bits (MSBs)
and the second flash generates the three least significant
bits (LSBs).
the ADC08061/2’s multi-step flash converter. It consists of
an over-encoded 2(/2-bit Voltage Estimator, an internal DAC
with two different voltage spans, a 3-bit half-flash converter
and a comparator multiplexer.
The resistor string near the center of the block diagram in
Figure 5
resistors at the bottom of the string is equal to 1/256 of the
total string resistance. These resistors form the LSB Lad-
der and have a voltage drop of 1/256 of the total reference
voltage (V
sistors make up the MSB Ladder. They are made up of
eight groups of four resistors connected in series. Each
MSB Ladder section has (/8 of the total reference voltage
across it. Within a given MSB Ladder section, each of the
MSB resistors has 8/256, or (/32 of the total reference
Figure 5
shows the major functional blocks of
forms the internal main DAC. Each of the eight
b
V
REF
a
) across them. The remaining re-
b
REF
voltage across it. Tap points are found between all of the
resistors in both the MSB and LSB Ladders. Through the
Comparator Multiplexer these tap points can be connected,
in groups of eight, to the eight comparators shown at the
right of
Figure 5
. This function provides the necessary reference voltages to the comparators during each flash conversion.
The six comparators, seven-resistor string (estimator DAC),
and Estimator Decoder at the left of
Figure 5
form the Voltage Estimator. The estimator DAC connected between
V
and V
a
REF
the six Voltage Estimator comparators. These comparators
generates the reference voltages for
b
REF
perform a very low resolution A/D conversion to obtain an
‘‘estimate’’ of the input voltage. This estimate is then used
to control the Comparator Multiplexer, connecting the appropriate MSB Ladder section to the eight flash comparators. Only 14 comparators, six in the Voltage Estimator and
eight in the flash converter, are needed to achieve the full
eight-bit resolution, instead of 32 comparators that would be
needed by traditional half-flash methods.
FIGURE 5. Block Diagram of the ADC08061/2 Multi-Step Flash Architecture
TL/H/11086– 18
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Application Information (Continued)
A conversion begins with the Voltage Estimator comparing
the analog input signal against the six tap voltages on the
estimator DAC. The estimator decoder then selects one of
the groups of tap points along the MSB Ladder. These eight
tap points are then connected to the eight flash comparators. For example, if the analog input signal applied to V
between 0 and */16 of V
estimator decoder instructs the comparator multiplexer to
REF(VREF
e
b
V
a
REF
select the eight tap points between 8/256 and 2/8 of V
and connects them to the eight flash comparators. The first
flash conversion is now performed, producing the five MSBs
of data.
The remaining three LSBs are generated next using the
same eight comparators that were used for the first flash
conversion. As determined by the results of the MSB flash,
a voltage from the MSB Ladder equivalent to the magnitude
of the five MSBs is subtracted from the analog input voltage
as the upper switch is moved from position one to position
two. The resulting remainder voltage is applied to the eight
flash comparators and, with the lower switch in position two,
compared with the eight tap points from the LSB Ladder.
By using the same eight comparators for both flash conversions, the number of comparators needed by the multi-step
converter is significantly reduced when compared to standard half-flash techniques.
Voltage Estimator errors as large as (/16 of V
will be corrected since the flash comparators are connected
REF
to ladder voltages that extend beyond the range specified
by the Voltage Estimator. For example, if -/16 V
'/16 V
tap points below '/16 V
decoded by the estimator decoder to ‘‘10’’. The eight flash
the Voltage Estimator’s comparators tied to the
REF
will output ‘‘1’’s (000111). This is
REF
comparators will be placed at the MSB Ladder tap points
between */8 V
each side of the Voltage Estimator’s span will automatically
correct an error of up to 16 LSBs (16 LSBs
e
V
REF
input voltage is between */8 V
the Voltage Estimator’s output code will be corrected by
REF
and ±/8 V
. The overlap of (/16 V
REF
e
5V). If the first flash conversion determines that the
and 4/8 V
REF
REF
subtracting ‘‘1’’. This results in a corrected value of ‘‘01’’. If
the first flash conversion determines that the input voltage is
between 8/16 V
Estimator’s output code remains unchanged.
REF
b
LSB/2 and ±/8 V
REF
After correction, the 2-bit data from both the Voltage Estimator and the first flash conversion are decoded to produce
the five MSBs. Decoding is similar to that of a 5-bit flash
converter since there are 32 tap points on the MSB Ladder.
However, 31 comparators are not needed since the Voltage
Estimator places the eight comparators along the MSB Ladder where reference tap voltages are present that fall above
and below the magnitude of V
ed outside this selected range. If a comparator’s output is a
. Comparators are not need-
IN
‘‘0’’, all comparators above it will also have outputs of ‘‘0’’
and if a comparator’s output is a ‘‘1’’, all comparators below
it will also have outputs of ‘‘1’’.
2.0 DIGITAL INTERFACE
The ADC08061/2 has two basic interface modes which are
selected by connecting the MODE pin to a logic high or low.
IN
V
), the
b
REF
REF
(16 LSBs)
k
V
REF
IN
on
REF
312.5 mV for
b
LSB/2,
, the Voltage
2.1 RD
Mode
With a logic low applied to the MODE pin, the converter is
set to Read mode. In this configuration (see
complete version is done by pulling RD
low, until the conversion is complete and output data ap-
is
pears. This typically takes 655 ns. The INT
Figure 1
), a
low, and holding
(interrupt) line
goes low at the end of conversion. A typical delay of 50 ns is
needed between the rising edge of RD
(after the end of a
conversion) and the start of the next conversion (by pulling
RD
low). The RDY output goes low after the falling edge of
CS
and goes high at the end-of-conversion. It can be used
to signal a processor that the converter is busy or serve as a
system Transfer Acknowledge signal. For the ADC08062
the data generated by the first conversion cycle after powerup is from an unknown channel.
2.2 RD
Mode Pipelined Operation
Applications that require shorter RD pulse widths than those
used in the Read mode as described above can be
achieved by setting RD
(Figure 4)
.RDpulse widths outside this range will create
’s width between 200 ns –400 ns
conversion linearity errors. These errors are caused by exercising internal interface logic circuitry using CS
and/or RD
during a conversion.
When RD goes low, a conversion is initiated and the data
from the previous conversion is available on the DB0–DB7
outputs. Reading D0– D7 for the first two times after powerup produces random data. The data will be valid during the
third RD
k
pulse that occurs after the first conversion.
2.3 WR
-RD (WR then RD) Mode
The ADC08061/2 is in the WR-RD mode with the MODE
pin tied high. A conversion starts on the falling edge of the
WR
signal. There are two options for reading the output
data which relate to interface timing. If an interrupt-driven
scheme is desired, the user can wait for the INT
low before reading the conversion result (see
Typically, INT
will go low 520 ns, maximum, after WR’s ris-
output to go
Figure 2b
).
ing edge. However, if a shorter conversion time is desired,
the processor need not wait for INT
after only 350 ns (see
INT
goes low, INT will immediately go low and data will ap-
pear at the outputs. This is the fastest operating mode (t
s
t
) with a conversion time, including data access time,
INTL
of 560 ns. Allowing 100 ns for reading the conversion data
Figure 2a
and can exercise a read
). If RD is pulled low before
RD
and the delay between conversions gives a total throughput
time of 660 ns (throughput rate of 1.5 MHz).
2.4 WR
-RD Mode with Reduced Interface
System Connection
CS
and RD can be tied low, using only WR to control the
start of conversion for applications that require reduced digital interface while operating in the WR
Data will be valid approximately 705 ns following WR
-RD mode
(Figure 3)
’s ris-
.
ing edge.
2.5 Multiplexer Addressing
The ADC08062 has 2 multiplexer inputs. These are selected
using the A0 multiplexer channel selection input. Table I
http://www.national.com 12
Application Information (Continued)
shows the input code needed to select a given channel. The
multiplexer address is latched when received but the multiplexer channel is updated after the completion of the current conversion.
TABLE I. Multiplexer Addressing
ADC08062
A0
0V
1V
The multiplexer address data must be valid at the time of
RD
’s falling edge, remain valid during the conversion, and
can go high after RD
goes high when operating in the Read
Mode.
The multiplexer address data should be valid at or before
the time of WR
and go invalid after WR
WR
-RD Mode.
’s falling edge, remain valid while WR is low,
goes high when operating in the
3.0 REFERENCE INPUTS
The two V
tial and define the zero to full-scale input range of the A to D
inputs of the ADC08061/2 are fully differen-
REF
converter. This allows the designer to vary the span of the
analog input since this range will be equivalent to the voltage difference between V
with minimum output voltages above GND can also be compensated by connecting V
this minimum voltage. By reducing V
b
V
) to less than 5V, the sensitivity of the converter
b
REF
can be increased (i.e., if V
9.8 mV). The ADC08061/2’s reference arrangement also
REF
REF
a
b
REF
facilitates ratiometric operation and in many cases the
ADC08061/2’s power supply can be used for transducer
power as well as the V
achieved by connecting V
V
and a transducer’s power supply input to Va. The
a
REF
ADC08061/2’s linearity degrades when V
source. Ratiometric operation is
REF
REF
is less than 2.0V.
The voltage at V
digital output of all zeros. Though V
sets the input level that produces a
b
REF
the referencedesignaffordsnearly differential-input capability
for some measurement applications.
possible differential configuration.
It should be noted that, while the two V
differential, the digital output will be zero for any analog input voltage if V
REF
t
V
b
REF
a
Channel
IN1
IN2
and V
to a voltage that is equal to
e
to GND and connecting
b
IN
. Transducers
b
REF
e
REF(VREF
V
REF
2.5V, then 1 LSB
b
V
a
REF
l
REF
is not itself differential,
Figure 6
inputs are fully
REF
shows one
.
4.0 ANALOG INPUT AND SOURCE IMPEDANCE
The ADC08061/2’s analog input circuitry includes an analog switch with an ‘‘on’’ resistance of 70X and capacitance
of 1.4 pF and 12 pF (see
during the A/D’s input signal acquisition time (while WR
low when using the WR
Figure 6
). The switch is closed
-RD Mode). A small transient current
is
flows into the input pin each time the switch closes. A transient voltage, whose magnitude can increase as the source
impedance increases, may be present at the input. So long
as the source impedance is less than 500X, the input voltage transient will not cause errors and need not be filtered.
Large source impedances can slow the charging of the
sampling capacitors and degrade conversion accuracy.
Therefore, only signal sources with output impedances less
than 500X should be used if rated accuracy is to be
achieved at the minimum sample time (100 ns maximum). A
signal source with a high output impedance should have its
output buffered with an operational amplifier. Any ringing or
voltage shifts at the op amp’s output during the sampling
period can result in conversion errors.
Correct conversion results will be obtained for input voltages greater than GND
100 mV. Do not allow the signal source to drive the analog
input pin more than 300 mV higher than V
b
100 mV and less than V
a
a
, or more than
a
300 mV lower than GND. The current flowing through any
analog input pin should be limited to 5 mA or less to avoid
permanent damage to the IC if an analog input pin is forced
beyond these voltages. The sum of all the overdrive cur-
a
rents into all pins must be less than 20 mA. Some sort of
e
protection scheme should be used when the input signal is
expected to extend more than 300 mV beyond the power
supply limits. A simple protection network using resistors
and diodes is shown in
Figure 8
.
6.0 INHERENT SAMPLE-AND-HOLD
An important benefit of the ADC08061/2’s input architecture is the inherent sample-and-hold (S/H) and its ability to
b
measure relatively high speed signals without the help of an
l
external S/H. In a non-sampling converter, regardless of its
speed, the input must remain stable to at least (/2 LSB
throughout the conversion process if full accuracy is to be
maintained. Consequently, for many high speed signals, this
signal must be externally sampled and held stationary during the conversion.
The ADC08061 and ADC08062 are suitable for DSP-based
systems because of the direct control of the S/H through
*Represents a multiplexer channel in the ADC08062.
FIGURE 6. ADC08061 and ADC08062 Equivalent Input Circuit Model
TL/H/11086– 19
http://www.national.com13
Application Information (Continued)
External Reference 2.5V Full-Scale
Power Supply as Reference
(Standard Application)
TL/H/11086– 20
Note: Bypass capacitors consist of a 0.1 m F ceramic in parallel with a 10 mF bead tantalum.
TL/H/11086– 21
FIGURE 7. Analog Input Options
Input Not Referred to GND
*Signal source driving VIN(b) must be capable of
sinking 5 mA.
TL/H/11086– 22
Note the multiple bypass capacitors on the reference and power supply pins. V
grounded (see Section 7.0 ‘‘Layout, Grounds, and Bypassing’’). V
is shown with an optional input protection network.
IN1
FIGURE 8. Typical Connection
the WR
signal. The WR input signal allows the A/D to be
synchronized to a DSP system’s sampling rate or to other
ADC08061 and ADC08062s.
The ADC08061 can perform accurate conversions of fullscale input signals at frequencies from dc to more than
300 kHz (full power bandwidth) without the need of an external sample-and-hold (S/H).
7.0 LAYOUT, GROUNDS, AND BYPASSING
In order to ensure fast, accurate conversions from the
ADC08061/2, it is necessary to use appropriate circuit
board layout techniques. Ideally, the analog-to-digital converter’s ground reference should be low impedance and
free of noise from other parts of the system. Digital circuits
can produce a great deal of noise on their ground returns
http://www.national.com 14
should be bypass to analog ground using multiple capacitors if it is not
b
REF
TL/H/11086– 23
and, therefore, should have their own separate ground lines.
Best performance is obtained using separate ground planes
for the digital and analog parts of the system.
The analog inputs should be isolated from noisy signal
traces to avoid having spurious signals couple to the input.
Any external component (e.g., an input filter capacitor) connected across the inputs should be returned to a very clean
ground point. Incorrectly grounding the ADC08061/2 will result in reduced conversion accuracy.
a
The V
supply pin, V
should be bypassed with a parallel combination of a 0.1 mF
REF
, and V
a
(if not grounded)
b
REF
ceramic capacitor and a 10 mF tantalum capacitor placed as
close as possible to the supply pin using short circuit board
traces. See
Figures 7
and8.
Physical Dimensions inches (millimeters)
Order Number ADC08061CMJ or ADC08061CMJ/883,5962
Order Number ADC08061BIWM, ADC08061CIWM, ADC08062BIWM or ADC08062CIWM
Ceramic Dual-In-Line Package (J)
NS Package Number J20A
Wide-Body Small-Outline Package (M)
NS Package Number M20B
http://www.national.com15
Physical Dimensions inches (millimeters) (Continued)
ADC08061/ADC08062
Order Number ADC08061BIN, ADC08061CIN, ADC08062BIN or ADC08062CIN
Dual-In-Line Package (N)
NS Package Number N20A
500 ns A/D Converter with S/H Function and Input Multiplexer
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with instructions for use provided in the labeling, can effectiveness.
be reasonably expected to result in a significant injury
to the user.
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