Rainbow Electronics 71M6542G User Manual

71M6541D/71M6541F/71M6542F

Energy Meter ICs

A Maxim Integrated Product s Brand

MPU

RTC

TIMERS

IAP

VA IBP

XIN

XOUT

RX TX

TX RX

COM0...5

V3P3A V3P3SYS

VBAT

VBAT_RTC

SEG

GNDA GNDD

SEG/DIO

DIO

ICE

LINE

NEUTRAL

LOAD

8888.8888

PULSES,

DIO

AMR

POWER FAULT COMPARATOR

MODUL-

ATOR

SERIAL PORTS

OSCILLATOR/

PLL

MUX and ADC

LCD DRIVER

DIO, PULSES

COMPUTE

ENGINE

FLASH

MEMORY

RAM

32 kHz

REGULATOR

Shunt

POWER SUPPLY

TERIDIAN

71M6541D/F

TEMPERATURE

SENSOR

VREF

BATTERY

PWR MODE

CONTROL

WAKE-UP

NEUTRAL

I2C or µWire

EEPROM

IAN

IBN

RTC BATTERY

V3P3D

BATTERY MONITOR

SPI INTERFACE

HOST

LCD DISPLAY

Resistor Divider

Pulse Transformer

TERIDIAN

71M6xx1

Shunt

LINE

Note:

This system is referenced to LINE

11/5/2010

19-5376; Rev 1.1; 4/11

Single Conv ert er Technology is a regis t er ed trade ma rk of Maxim Integrated

April 2011

GENERAL DESCRIPTION

The 71M6541D/71M6541F/71M6542F are Teridian’s 4t h-generation single-phase m etering SoC s with a 5 MHz 8051 -compatible MPU core, low-power RTC wi th digital temperat ure compensation, fl ash memory, and LCD driver. Our Single Converter Technology® with a 22-bit deltasigma ADC, three or four analog inputs, digital temperature compensation, precision voltage reference, and a 32-bit computation engine (CE) supports a wide range of metering applications with very few external components.

The 71M6541D/71M6541F/71M6542F support optional interfaces to the Teridian 71M6x01 series of isolated sensors, w hich offer BOM cost reduction, immunity to magnetic tamper, and enhanced reliability. Other features include an SPI™ interface, advanced power management, ultra-low-power operat ion in active and battery modes, 3/5KB shared RAM and 32/64K B of flash mem ory that can be programmed in the field with code and/or data during meter operation and the ability to drive up to six LCD segments per SEG driver pin. High processing and sampling rates combined with differential inputs offer a powerful metering platform for residential meters.

A complete array of code development tools, demonstration code, and reference designs enable rapid development and certification of meters t hat meet all ANSI and IEC electric ity metering standards worldwide.

Products, Inc. SPI is a trademark of Mot orol a, Inc. MICROWIRE i s a trademark of N at ional Semiconduct or Corp.

D ATA SHEET

FEATURES

• 0.1% Accuracy Over 2000:1 Current Range

• Exceeds IEC 62053/ANSI C12.20 Standards

• Two Current Sensor Inputs with Selectable

Differential Mode

• Selectable Gain of 1 or 8 for One Current Input to Support Shunts

• High-Speed Wh/VARh Pulse Outputs with Programmable Width

• 32KB Flash, 3KB RAM (71M6541D)

• 64KB Flash, 5KB RAM (71M6541F/42F)

• Up to Four Pulse Outputs with Pulse Count

• Four-Quadrant Metering

• Digital Temperature Compensation:

- Metrology Compensation

- Accurate RTC for TOU Functions with

Automatic Temperature Compensation for Crystal in All Power Modes

• Independent 32-Bit Compute Engine

• 46-64Hz Line Frequency Range with the Same

Calibration

• Phase Compensation (±10°)

• Three Battery-Backup Modes:

- Brownout Mode (BRN)

- LCD Mode (LCD)

- Sleep Mode (SLP)

• Wake-Up on Pin Events and Wake-On Timer

• 1µA in Sleep Mode

• Flash Security

• In-System Program Update

• 8-Bit MPU (80515), Up to 5 MIPS

• Full-Speed MPU Clock in Brownout Mode

• LCD Drive r:

- Up to 6 Commons/Up to 56 Pins

• 5V LCD Driver with DAC

• Up to 51 Multifunction DIO Pins

• Hardware Watchdog Timer (WDT)

• I2C/MICROWIRE™ EEPROM Interface

• SPI In terface with Flash Program Capability

• Two UARTs for IR and AMR

• IR LED Driver with Modulation

• Industrial Temperature Range

• 64-Pin (71M6541D/71M6541F) and 100-pin

(71M6542F) Lead(Pb)-Free LQFP Package

Table of Contents

1 Introduction ................................................................................................................................. 10

2 Hardware Descript io n .................................................................................................................. 11

2.1 Hardware Overview............................................................................................................... 11

2.2 Analog Front End (AFE) ........................................................................................................ 12

2.2.1 Signal Input Pins ....................................................................................................... 14

2.2.2 Input Multiplexer ........................................................................................................ 15

2.2.3 Delay Compensation ................................................................................................. 19

2.2.4 ADC Pre-Amplifier ..................................................................................................... 20

2.2.5 A/D Converter (ADC) ................................................................................................. 20

2.2.6 FIR Filter ................................................................................................................... 20

2.2.7 Voltage Refer enc es ................................................................................................... 20

2.2.8 71M6x01 Isolated Sensor Interface (Remote Sensor I nterface) .................................. 22

2.3 Digital Computation Engine (CE) ........................................................................................... 24

2.3.1 CE Program Memory ................................................................................................. 24

2.3.2 CE Data Memory ....................................................................................................... 24

2.3.3 CE Communicati on with t he MPU .............................................................................. 25

2.3.4 Meter Equations ........................................................................................................ 25

2.3.5 Real-Time Monitor (RTM) .......................................................................................... 25

2.3.6 Pulse Generators ...................................................................................................... 27

2.3.7 CE Functional Ov erview ............................................................................................ 28

2.4 80515 MPU Core .................................................................................................................. 31

2.4.1 Memory Organization and Addressing ....................................................................... 31

2.4.2 Special Function Registers (SFRs) ............................................................................ 33

2.4.3 Generic 80515 Speci al Function Registers ................................................................ 34

2.4.4 Instructi on S et ........................................................................................................... 36

2.4.5 UARTs ...................................................................................................................... 36

2.4.6 Timers and Counters ................................................................................................. 39

2.4.7 WD Timer (Software Watchdog Timer) ...................................................................... 40

2.4.8 Interrupts ................................................................................................................... 40

2.5 On-Chip Resources............................................................................................................... 48

2.5.1 Physical Memory ....................................................................................................... 48

2.5.2 Oscillator ................................................................................................................... 50

2.5.3 PLL and Internal Cl ocks............................................................................................. 50

2.5.4 Real-Time Clock (RTC) ............................................................................................. 51

2.5.5 71M654x Temperature Sensor .................................................................................. 56

2.5.6 71M654x Battery Monitor ........................................................................................... 57

2.5.7 UART and Optical Int erfac e ....................................................................................... 58

2.5.8 Digital I/O and LCD Segment Drivers ......................................................................... 59

2.5.9 EEPROM Interface .................................................................................................... 70

2.5.10 SPI Slave Port ........................................................................................................... 73

2.5.11 Hardware Watchdog Timer ........................................................................................ 78

2.5.12 Test Ports (TMUXOUT and TMUX2OUT Pins)........................................................... 78

3 Functional Description ................................................................................................................ 80

3.1 Theory of Operation .............................................................................................................. 80

3.2 Battery Modes ....................................................................................................................... 81

3.2.1 BRN Mode ................................................................................................................ 83

3.2.2 LCD Mode ................................................................................................................. 83

3.2.3 SLP Mode ................................................................................................................. 84

3.3 Fault and Reset Behavi or ...................................................................................................... 85

3.3.1 Events at Power-Down .............................................................................................. 85

3.3.2 IC Behavior at Low Batt er y Volt age ........................................................................... 86

3.3.3 Reset Sequence ........................................................................................................ 86

3.3.4 Watchdog Timer Reset .............................................................................................. 86

3.4 Wake Up Behavior ................................................................................................................ 87

3.4.1 Wake on Hardware Event s ........................................................................................ 87

3.4.2 Wake on Timer .......................................................................................................... 90

3.5 Data Flow and MPU/CE Communic ation ............................................................................... 91

4 Application Information ............................................................................................................... 92

4.1 Connecting 5 V Devic es ........................................................................................................ 92

4.2 Direct Connection of Sensors ................................................................................................ 92

4.3 71M6541D/F Using Local Sensors ........................................................................................ 93

4.4 71M6541D/F Using 71M6x01and Current Shunts .................................................................. 94

4.5 71M6542F Using Local S ensors ............................................................................................ 95

4.6 71M6542F Using 71M6x 01 and Cur r ent Shunts .................................................................... 96

4.7 Metrology Tem per ature Compensation .................................................................................. 97

4.7.1 Voltage Reference Precision ..................................................................................... 97

4.7.2 Temperature Coefficients for the 71M654x ................................................................ 97

4.7.3 Temperature Compensation for VREF with Local Sensors ......................................... 98

4.7.4 Temperature Compensation for VREF with Remote Sensor ....................................... 99

4.8 Connecting I2C EEPROMs .................................................................................................. 100

4.9 Connecting Thr ee-Wire EEPROMs ..................................................................................... 101

4.10 UART0 (TX/RX) .................................................................................................................. 101

4.11 Optical Int erfac e ( UA RT1) ................................................................................................... 101

4.12 Connecting the Reset Pi n .................................................................................................... 102

4.13 Connecting the Emulator Port Pins ...................................................................................... 102

4.14 Flash Programming ............................................................................................................. 104

4.14.1 Flash Programming via the ICE Port ........................................................................ 104

4.14.2 Flash Programming via the SPI Port ........................................................................ 104

4.15 MPU Firmware Librar y ........................................................................................................ 104

4.16 Crystal Oscill ator ................................................................................................................. 104

4.17 Meter Calibration ................................................................................................................. 104

5 Firmware Interface ..................................................................................................................... 105

5.1 I/O RAM Map –Functional Order ......................................................................................... 105

5.2 I/O RAM Map – Alphabetical Order ..................................................................................... 111

5.3 CE Interface Descri ption ..................................................................................................... 125

5.3.1 CE Program ............................................................................................................ 125

5.3.2 CE Data Format ...................................................................................................... 125

5.3.3 Constants ................................................................................................................ 125

5.3.4 Environment ............................................................................................................ 126

5.3.5 CE Calculations ....................................................................................................... 126

5.3.6 CE Front End Data (Raw Data)................................................................................ 127

5.3.7 FCE Status and Control ........................................................................................... 127

5.3.8 CE Transfer Variables ............................................................................................. 129

5.3.9 Pulse Generation..................................................................................................... 132

5.3.10 Other CE Parameters .............................................................................................. 134

5.3.11 CE Calibration Paramet er s ...................................................................................... 135

5.3.12 CE Flow Diagrams .................................................................................................. 136

6 Electrical Specifications ............................................................................................................ 138

6.1 Absolute Maximum Ratings ................................................................................................. 138

6.2 Recommended External Com ponents ................................................................................. 139

6.3 Recommended Operating Conditions .................................................................................. 139

6.4 Performance Specifications ................................................................................................. 140

6.4.1 Input Logic Lev els ................................................................................................... 140

6.4.2 Output Logic Levels ................................................................................................. 140

6.4.3 Battery Monitor ........................................................................................................ 141

6.4.4 Temperature Monitor ............................................................................................... 141

6.4.5 Supply Current ........................................................................................................ 142

6.4.6 V3P3D Switch ......................................................................................................... 143

6.4.7 Internal Power Faul t Compar ators ........................................................................... 143

6.4.8 2.5 V Voltage Regul ator – System Power ................................................................ 143

6.4.9 2.5 V Voltage Regul ator – Batt er y Power ................................................................. 144

6.4.10 Crystal Oscillator ..................................................................................................... 144

6.4.11 Phase-Locked Loop (PLL) ....................................................................................... 144

6.4.12 LCD Drivers ............................................................................................................ 145

6.4.13 VLCD Generator...................................................................................................... 146

6.4.14 VREF ...................................................................................................................... 148

6.4.15 ADC Converter ........................................................................................................ 149

6.4.16 Pre-Amplifier for IAP-IAN ......................................................................................... 150

6.5 Timing Specifications .......................................................................................................... 151

6.5.1 Flash Memory ......................................................................................................... 151

6.5.2 SPI Slave ................................................................................................................ 151

6.5.3 EEPROM Interface .................................................................................................. 151

6.5.4 RESET Pin .............................................................................................................. 151

6.5.5 RTC ........................................................................................................................ 152

6.6 Package Outline Drawings .................................................................................................. 153

6.6.1 64-Pin LQFP Outline Pac k age Dr awing ................................................................... 153

6.6.2 100-Pin LQFP Package Outline Drawing ................................................................. 154

6.7 Pinout Diagrams ................................................................................................................. 155

6.7.1 71M6541D/F LQFP-64 Package Pinout ................................................................... 155

6.7.2 71M6542F LQFP-100 Package Pi nout..................................................................... 156

6.8 Pin Descripti ons .................................................................................................................. 157

6.8.1 Power and Ground Pins........................................................................................... 157

6.8.2 Analog Pins ............................................................................................................. 158

6.8.3 Digital Pins .............................................................................................................. 159

6.8.4 I/O Equivalent Circ uits ............................................................................................. 161

7 Ordering Information ................................................................................................................. 162

7.1 71M6541D/F and 71M6542F ............................................................................................... 162

8 Related Informati on ................................................................................................................... 162

9 Contact Information ................................................................................................................... 162

Appendix A: Acronyms ..................................................................................................................... 163

Appendix B: Revision Hi story ........................................................................................................... 164

Figures

Figure 1: IC Functi onal Bl oc k Di agr am ..................................................................................................... 9

Figure 2. 71M6541D/F AFE Bl oc k Di agr am (Local S ensors) .................................................................. 12

Figure 3. 71M6541D/F AFE Bl oc k Di agr am with 71M 6x01 ..................................................................... 13

Figure 4. 71M6542F AFE Block Diagr am ( Loc al S ensors) ...................................................................... 13

Figure 5. 71M6542F AFE Block Diagr am with 71M6x01 ......................................................................... 14

Figure 6: States in a Multiplexer Frame (MUX_DIV[3:0] = 3) .................................................................. 17

Figure 7: States in a Multiplexer Fram e (MUX_DIV[3:0] = 4) .................................................................. 17

Figure 8: General Topology of a Chopped Amplifier ............................................................................... 21

Figure 9: CROSS Signal wit h CHOP_E = 00 ........................................................................................... 21

Figure 10: RTM Timing .......................................................................................................................... 26

Figure 11: Timing r elationship between ADC MUX, CE, and RTM Serial Transfer .................................. 26

Figure 12. Pulse Generat or FI FO Timing ............................................................................................... 28

Figure 13: Accum ulation Interval ............................................................................................................ 29

Figure 14: Samples from Multiplexer Cycle (MUX_DIV[3:0] = 3) ............................................................. 30

Figure 15: Samples from Multiplexer Cycle (MUX_DIV[3:0] = 4) ............................................................. 30

Figure 16: Interrupt Structure ................................................................................................................. 47

Figure 17: Autom atic Temper ature Compensation ................................................................................. 54

Figure 18: Optical I nterface .................................................................................................................... 58

Figure 19: Optical I nterface (UART1) ..................................................................................................... 59

Figure 20: Connecting an External Load to DIO Pins ............................................................................. 60

Figure 21: LCD Waveform s ................................................................................................................... 68

Figure 22: 3-wire Interface. Write Command, HiZ=0. ............................................................................. 72

Figure 23: 3-wire Interface. Write Command, HiZ=1 .............................................................................. 72

Figure 24: 3-wire Interface. Read Command. ........................................................................................ 72

Figure 25: 3-Wire Int erfac e. Write Command when CNT=0 ................................................................... 73

Figure 26: 3-wire Interface. Write Command when HiZ=1 and WFR=1. ................................................. 73

Figure 27: SPI Slave Port - Typical Multi-Byte Read and Write operations .............................................. 75

Figure 28: Voltage, Current, Momentary and Accumulated Ener gy ......................................................... 80

Figure 29: Operation Modes State Diagram ........................................................................................... 81

Figure 30: MPU/CE Data Flow ............................................................................................................... 91

Figure 31: Resistive Voltage Divider (Voltage Sensi ng) .......................................................................... 92

Figure 32. CT with Single-Ended Input Connection (Current S ensing) .................................................... 92

Figure 33: CT with Differential Input Connection ( Cur r ent Sensi ng) ........................................................ 92

Figure 34: Diff er ential Resistive Shunt Connecti ons (Curr ent Sensing) ................................................... 92

Figure 35. 71M6541D/F with Local Sensors ........................................................................................... 93

Figure 36: 71M6541D/F with 71M6x01 isolated Sensor .......................................................................... 94

Figure 37: 71M6542F with Local Sensors .............................................................................................. 95

Figure 38: 71M6542F with 71M6x01 Isolated Sensor ............................................................................. 96

Figure 39: I2C EEPROM Connection .................................................................................................... 100

Figure 40: Connections for UART0 ...................................................................................................... 101

Figure 41: Connection for Optical Components .................................................................................... 102

Figure 42: External Components for the RE SE T P in: Pu s h-Button (Left), Production Circuit (Right) ......... 102

Figure 43: External Components for the Emulator Int erface ................................................................. 103

Figure 44: CE Data Flow: Multi plexer and ADC .................................................................................... 136

Figure 45: CE Data Flow: Scaling, Gain Control, Intermediate Variables .............................................. 136

Figure 46: CE Data Flow: Squaring and Summation Stages ................................................................. 137

Figure 51: 64-pin LQFP Pac k age Outli ne ............................................................................................. 153

Figure 52: 100-pin LQF P Pack age Outli ne ........................................................................................... 154

Figure 53: Pinout for the 71M6541D/F (LQFP-64 Package) ................................................................. 155

Figure 54: Pinout for the 71M6542F (LQFP-100 Package) ................................................................... 156

Figure 55: I/O Equivalent Circuits ......................................................................................................... 161

Tables

Table 1. Required CE Code and Set tings for Local Sensors ................................................................... 15

Table 2. Required CE Code and Set tings for 71M6x01 isolated Sensor ................................................. 15

Table 3: ADC Input Configur ation ......................................................................................................... 17

Table 4: Multiplexer and A DC Configuration Bits ................................................................................... 19

Table 5. RCMD[4:0] Bits ........................................................................................................................ 22

Table 6: Remote Interfac e Read Commands ........................................................................................ 23

Table 7: I/O RAM Control Bits for I sol ated Sensor ................................................................................. 23

Table 8: Inputs Selected in Multiplexer Cycles ....................................................................................... 25

Table 9: CKMPU Clock Frequencies ...................................................................................................... 31

Table 10: Memory Map .......................................................................................................................... 32

Table 11: Inter nal Data Memory Map ..................................................................................................... 33

Table 12: Special Func tion Register Map ............................................................................................... 33

Table 13: Generic 80515 SFRs - Locati on and Reset V alues ................................................................. 34

Table 14: PSW Bit Functions (SFR 0xD0) ................................................................................................. 35

Table 15: Port Register s (SE GDIO0-15) ................................................................................................ 36

Table 16: Stretch M em ory Cycl e Widt h .................................................................................................. 36

Table 18: Baud Rate Generat ion............................................................................................................ 37

Table 19: UART Modes ......................................................................................................................... 37

Table 20: The S0CON (UART0) Register (SFR 0x98) ............................................................................. 38

Table 21: The S1CON (UART1) Register (SFR 0x9B ) ............................................................................. 38

Table 22: PCON Register Bi t Description (SFR 0x87) ............................................................................ 39

Table 23: Timers/Counters Mode Descripti on ........................................................................................ 39

Table 24: Allowed Timer /Counter Mode Combinations ........................................................................... 39

Table 25: TMOD Regi ster Bit Description (SFR 0x89) ............................................................................ 40

Table 26: The TCON Register Bit Functions (SF R 0x 88) ........................................................................ 40

Table 27: The IEN0 Bit Functions (SFR 0xA8) ........................................................................................ 41

Table 28: The IEN1 Bit Functions (SFR 0xB8) ........................................................................................ 41

Table 29: The IEN2 Bit Func tions (SFR 0x9A) ........................................................................................ 42

Table 30: TCON Bit Functi ons (SFR 0x88) ............................................................................................. 42

Table 31: The T2CON Bit F unctions (SFR 0xC8) ................................................................................... 42

Table 32: The IRCON Bit F unc tions (SFR 0xC0) .................................................................................... 42

Table 33: External MPU Interrupts ......................................................................................................... 44

Table 34: Interrupt Enable and Flag Bits ............................................................................................... 44

Table 35: Inter r upt Pri ori ty Level Groups ................................................................................................ 45

Table 36: Inter r upt Pri ori ty Levels .......................................................................................................... 45

Table 37: Inter r upt Pri ori ty Registers (IP0 and IP1) ................................................................................. 45

Table 38: Inter r upt Polling Sequence ..................................................................................................... 46

Table 39: Inter r upt Vector s .................................................................................................................... 46

Table 40: Flash Memory Access ............................................................................................................ 48

Table 41: Flash Securit y ........................................................................................................................ 49

Table 42: Clock System Summ ar y ......................................................................................................... 51

Table 43: RTC Control Regi ster s ........................................................................................................... 52

Table 44: I/O RAM Registers for RTC Temperature Compensati on ........................................................ 53

Table 45: NV RAM Temperature Table Structure ................................................................................... 54

Table 46: I/O RAM Registers for RTC Interrupts .................................................................................... 55

Table 47: I/O RAM Registers for Temperature and Battery Measurement .............................................. 56

Table 48: Selectable Resources using the DIO_Rn[2:0] Bits................................................................... 59

Table 49: Data/Dir ec tion Registers for SEGDIO0 to SEGDIO14 (71M6541D/F)...................................... 61

Table 50: Data/Dir ec tion Registers for SEGDIO19 to SEGDIO 27 ( 71M 6541D/F).................................... 62

Table 51: Data/Dir ec tion Registers for SEGDIO36-39 to SEGDIO44 -45 (71M6541D/F) .......................... 62

Table 52: Data/Dir ec tion Registers for SEGDIO51 and SEG DIO 55 ( 71M 6541D/F) ................................. 62

Table 53: Data/Dir ec tion Registers for SEGDIO0 to SEGDIO15 (71M6542F) ......................................... 63

Table 54: Data/Dir ec tion Registers for SEGDIO16 to SEGDIO 31 ( 71M 6542F) ....................................... 64

Table 55: Data/Dir ec tion Registers for SEGDIO32 to SEGDIO45 ( 71M 6542F) ....................................... 64

Table 56: Data/Dir ec tion Registers for SEGDIO51 to SEGDIO 55 ( 71M 6542F) ....................................... 64

Table 57: LCD_VMODE[1:0] Configurations .......................................................................................... 65

Table 58: LCD Configurations ............................................................................................................... 67

Table 59: 71M6541D/F LCD Data Registers for SEG46 to SEG50 ......................................................... 69

Table 60: 71M6542F LCD Dat a Register s for SEG46 to SEG50 ............................................................ 70

Table 61: EECTRL Bits for 2-pin Interface ............................................................................................... 71

Table 62: EECTRL B its for the 3-wir e Interface ....................................................................................... 71

Table 63: SPI Transacti on Fields ........................................................................................................... 74

Table 64: SPI Command Sequenc es ..................................................................................................... 75

Table 65: SPI Register s ......................................................................................................................... 76

Table 66: TMUX[5:0] Selections ............................................................................................................ 79

Table 67: TMUX2[4:0] Selections ........................................................................................................... 79

Table 68: Avail able Cir c uit Functions ..................................................................................................... 82

Table 69: VSTAT[2:0] (SFR 0xF9[2:0]) .................................................................................................... 85

Table 70: Wake Enables and Flag Bi ts .................................................................................................. 87

Table 71: Wake Bits .............................................................................................................................. 89

Table 72: Clear Event s for WAKE fl ags .................................................................................................. 90

Table 73: GAIN_ADJn Com pensation Channels .................................................................................... 98

Table 74: GAIN_ADJn Com pensation Channels .................................................................................. 100

Table 75: I/O RAM Map – Functional Order , Basi c Configuration ......................................................... 105

Table 76: I/O RAM Map – Functional Order ......................................................................................... 107

Table 77: I/O RAM Map – Functional Order ......................................................................................... 111

Table 78. Standard CE Codes ............................................................................................................. 125

Table 79: CE EQU Equations and Element Input Mapping ................................................................... 126

Table 80: CE Raw Data Access Locati ons ........................................................................................... 127

Table 81: CESTATUS Register .............................................................................................................. 127

Table 82: CESTATUS (CE RAM 0x80) Bit Definitions .............................................................................. 128

Table 83: CECONFIG Register ............................................................................................................. 128

Table 84: CECONFIG (CE RAM 0x20) Bit Definit ions ............................................................................. 128

Table 85: Sag Threshold and Gain Adjust Control ................................................................................ 129

Table 86: CE Transfer Variables (with Local Sensors).......................................................................... 130

Table 87: CE Transfer Variables (with Remote Sensor) ....................................................................... 130

Table 88: CE Energy Measurem ent Variables (with Local S ensors) ..................................................... 131

Table 89: CE Energy Measurem ent Variables (with Remote Sensor) ................................................... 131

Table 90: Other Transf er V ari ables ...................................................................................................... 132

Table 91: CE Pulse Generati on P ar am eters......................................................................................... 132

Table 92: CE Parameters for Noise Suppres si on and Code V er si on..................................................... 134

Table 93: CE Calibration Parameters ................................................................................................... 135

Table 94: Absolute M aximum Ratings .................................................................................................. 138

Table 95: Recommended Ex ternal Components .................................................................................. 139

Table 96: Recommended O per ating Conditions ................................................................................... 139

Table 97: Input Logic Lev els ................................................................................................................ 140

Table 98: Output Logic Levels ............................................................................................................. 140

Table 99 : Battery Monit or Performance Specifications (TEMP_BAT= 1) ................................................ 141

Table 100. Temperature Monitor .......................................................................................................... 141

Table 101: Supply Current Performance Specifications ........................................................................ 142

Table 102: V3P3D Swit c h Perf ormance Specifications ......................................................................... 143

Table 103. Inter nal P ower Fault Comparator Specifications ................................................................. 143

Table 104: 2.5 V Voltage Regulator Performance Specif ications .......................................................... 143

Table 105: Low-Power Voltage Regulator Performanc e Specif ic ations ................................................. 144

Table 106: Crystal Oscill ator Performance Specifications ..................................................................... 144

Table 107: PLL Perf ormance S pecifications ......................................................................................... 144

Table 108: LCD Driv er Performance Specifications .............................................................................. 145

Table 109: LCD Driv er Performance Specifications .............................................................................. 146

Table 110: VREF Perf ormance S pecifications ...................................................................................... 148

Table 111. ADC Convert er Performance Specifications ....................................................................... 149

Table 112: Pre-Amplifier Performance Specifications ........................................................................... 150

Table 113: Flash Memory Timing Specifications .................................................................................. 151

Table 114. SPI Slave Timing Specifications ......................................................................................... 151

Table 115: EEPROM Interface Timing ................................................................................................. 151

Table 116: RESET Pin Timing ............................................................................................................. 151

Table 117: RTC Range for Date........................................................................................................... 152

Table 118: Power and Ground Pins ..................................................................................................... 157

Table 119: Analog Pins ........................................................................................................................ 158

Table 120: Digit al Pi ns ......................................................................................................................... 159

IAP

MUX

and

PREAMP

XIN

XOUT

VREF

CKADC

32-bit Compute

Engine

MPU

(80515)

CE CONTROL

OPT_RX/

SEGDIO55

OPT_TX/

SEGDIO51/

WPULSE/

VARPULSE

RESET

VBIAS

EMULATOR

PORT

CE_BUSY

OPTICAL

INTERFACE

UART0

XFER BUSY

COM0..5

VLC2

LCD DRIVER

CEDATA

0x000...0x2FF

PROG

0x000...0x3FF

DATA

0x0000...0xFFFF

PROGRAM

0x0000...0xFFFF

0x0000…

0xFFFF

DIGITAL I/O

CONFIGURATION

RAM

(I/O RAM)

0x2000...0x20FF

I/O RAM

MEMORY SHARE

0x0000...0x13FF

RTCLK

RTCLK (32KHz)

MUX_SYNC CKCE

CKMPU

CK32

POWER FAULT

DETECTION

4.9 MHZ

< 4.9MHz

4.9 MHz

GNDD

V3P3A

V3P3D

VBAT

Voltage

Regulator

2.5V to logic

VDD

32KHz

MPU_RSTZ

FAULTZ

WAKE

CONFIGURATION PARAMETERS

GNDA

VBIAS

2/15/2011

CROSS

CLOCK GEN

Oscillator

32 KHz

CK32

MCK

PLL

VREF

DIV

ADC

MUX CTRL

STRT

MUX

CKFIR

RTM

SEGDIO Pins

WPULSE VARPULSE

WPULSE

VARPULSE

TEST

MODE

VLC1 VLC0

< 4.9MHz

CKMPU_2x

SDCK

SDOUT

SDIN

E_RXTX/SEG48

E_TCLK/SEG49

E_RST/SEG50

FLASH

64/32 KB

V3P3A

FIR

EEPROM

INTERFACE

CK_4X

LCD_GEN

RTC

VBIAS

MEMORY

E_RXTX E_TCLK E_RST(Open Drain)

ICE_E

∆ Σ

AD CONVERTER

VREF

V3P3SYS

TEST MUX

VLCD

Voltage

Boost

MPU RAM

3/5 KB

SPI

VSTAT

VBAT_RTC

IAN IBP IBN

VB*

SEG Pins

TEST MUX

Non-Volatile

CONFIGURATION

RAM

BAT

TEST

TEMP

SENSOR

RTM

* 71M6542 only

Figure 1: IC Functional Block Diagram

1 Introduction

This data sheet covers the 71M6541D (32KB) , 71M6541F (64KB) and 71M6542F (64KB) fourth generation Teri dian energy measurement S oCs. The t erm “71M 654x ” is used when discus si ng a dev ice feature or behavior that is applicable to all three part numbers. The appropriate part num ber is i ndic ated when a device feature or behav ior is being discussed that appl ies only to a specific part number. This data sheet also cover s basic details about the companion 71M6x01 isolated c ur r ent sensor device. For more complete information on the 71M6x01 sensors, r efer to the 71M6xxx Data Sheet.

This document covers the use of the 71M654x with local ly connected sensors as well when it is used in conjunction wit h the 71M6x01 isolated current sensor. T he 71M 654x and 71M6x01 chipset make it possible to use one non-isol ated and one isolated shunt cur r ent sensor t o c r eate single-phase and twophase energy meters using i nexpensive shunt resistors , while achieving unprecedented performance with this type of sensor technology . The 71M654x SoCs also support confi gur ations involving one loc ally connected shunt and one locally connected Curr ent Transformer ( CT), or two CTs.

To facilitat e doc um ent navigation, hyperlink s are often used to reference figures, tables and section headings that are l oc at ed in other par ts of the document. All hyperlinks i n this document are highlight ed in

blue. Hyperlinks are used extensively to inc r ease the level of detail and clarity pr ov ided within each

section by refer enci ng other relevant parts of the document. To further facilitate document navigation, t his document is published as a PDF docum ent with bookmarks enabled.

The reader is also encouraged to obt ain and review the documents listed in 8 Related Information on page 162 of this document.

2 Hardware Description

2.1 Hardware Overview

The Teridian 71M6541D/F and 71M6542F single-chip energy meter ICs integrate all primary functional blocks required to implement a solid-state residential electricity meter. Included on the chip are:

• An analog front end (AFE) feat uri ng a 22-bit second-order sigma-delta ADC

• An independent 32-bi t digital computation engi ne ( CE) to implement DSP functions

• An 8051-compatible microprocessor (MPU) whic h ex ecutes one i nstr uc tion per clock cycle (80515)

• A precision voltage reference (VREF)

• A temperature sensor for digital temperature c om pensation:

- Metrology digital temperature compensation (MPU)

- Automatic RTC digital temper ature compensation operational in all power states

• LCD drivers

• RAM and Flash memory

• A real time clock (RTC)

• A variety of I/O pins

• A power failure interr upt

• A zero-crossing interrupt

• Selectable cur r ent sensor interfaces for loc ally -c onnec ted sensors as well as isolated sensors (i .e.,

using the 71M6x01 companion IC with a shunt resistor sensor)

• Resistive Shunt and Cur r ent Transformers are supported Resistive Shunts and Current Transformers (CT) current sensors are supported. Resistive shunt curr ent

sensors may be connected directly to the 71M654x device or i sol ated using a companion 71M6x01 isolator IC in order to implement a variety of single-phase / split-phase (71M6541D/F) or two-phase (71M6542F) metering configurations. An inexpensive, small size pulse transformer is used to isolate the 71M6x01 isolated sensor from the 71M654x. The 71M654x performs digital communications bidirectionally with the 71M6x01 and also provi des power t o the 71M6x01 through the isolating pulse transformer. Isolated (remote) shunt current sensors ar e c onnec ted to the differenti al input of the 71M6x01. Included on t he 71M6x01 companion isolat or chip are:

• Digital isol ation communications interface

• An analog front end (AFE)

• A precision voltage reference (VREF)

• A temperature sensor (for digital temperature compensation)

• A fully diff er ential shunt resistor sensor input

• A pre-amplifier to optimize shunt current sensor perform anc e

• Isolated power circ uitry obtains dc power fr om pul ses sent by the 71M654x

In a typical application, the 32-bit compute engine (CE) of the 71M654x sequentially processes the samples from the voltage inputs on analog input pins and from the external 71M6x01 isolated sensors and pe r forms calculations to measure ac tive energy (Wh) and reactive energy (VA Rh) , as well as A

quadrant metering. These measurements are then ac cessed by the M P U, processed further and output using the peripheral dev ices available to the MPU.

In addition to ad vanced measurement func t ions , the c loc k func tion allows the 71M6541D/F and 71M6542F to record time-of-use (TOU) metering information for multi-rate applications and to time-stamp tamper or other events. Measurements can be displayed on 3.3 V LCDs commonly used in low-temperature environments. An on-chip charge pum p is available to drive 5 V LCDs. Flexible mapping of LCD display segments facilitate integration of existing custom LCDs. Design trade-off bet ween the number of LCD segments and DIO pins can be im plem ented in software to accommodat e various requi r ements.

h, and V2h for four-

In addition to the temperature-trimmed ultra-precisi on vol tage reference, the on-chip digital temperatur e compensation mechanism includes a temperature sensor and associated controls for correction of unwanted temperature effects on measurement and RTC accuracy, e.g., to meet the requirements of ANSI and IEC standards. Temperature-dependent ext ernal components such as crystal oscillator, resistive sh unts, current

∆Σ ADC

CONVERTER

VREF

MUX

VREF

VADC

FIR

IBP

IAP

VADC10 (VA)

IAN

IBN

71M6541D/F

CE RAM

*IN = Optional Neutral Current

Local

Shunt

IN*

LINE

11/5/2010

LINE

transformer s (CT s) and their corresponding signal conditioning ci rcuit s can be char ac terized and their correcti on factors can be programmed to produce electricity meters with exc eptional accuracy over the industrial t e mper ature ran ge.

One of the two internal UARTs is adapted to support an Infrared L ED with internal drive and s ens e con figuration and can als o function as a stan dard UART. The optical output can be modulated at 38 kHz. This flexibility makes it possible t o im plem ent AM R meter s with an IR int erface. A block diagram of the IC is shown in

Figure 1.

2.2 Analog Front End (AFE)

The AFE functions as a data acquisition system, controlled by the MPU. When used with locally connected sensors, as seen i n Figure 2, the analog input signal s (IAP-IAN, VA and IBP-IBN) are multiplexed to the ADC input and sampled by the ADC. The ADC output is decimated by the FIR filter and stored in CE RAM where it can be accessed and proces sed by t he CE .

See Figure 6 for the m ultiplexer sequence correspondi ng to Figure 2. See Figure 35 for the meter configurati on c or r espondi ng to Figure 2.

Figure 2. 71M6541D/F AFE Block Diagram (Local Sensors)

∆Σ ADC

CONVERTER

VREF

MUX

VREF

VADC

FIR

IBP

IAP

VADC10 (VA)

IAN

IBN

71M6541D/F

CE RAM

71M6x01

INP

INN

Remote

Shunt

IN*

Digital

Isolation

Interface

Local

Shunt

LINE

11/5/2010

* IN = Optional Neutral Current

∆Σ ADC

CONVERTER

VREF

MUX

VREF

VADC

FIR

IBP

IAP

VADC10 (VA)

IAN

IBN

71M6542F

CE RAM

Local

Shunt

11/5/2010

VADC9 (VB)

Figure 3 shows the 71M6541D/F multiplexer interface with one local and one remote resistive shunt

sensor. As seen in Figure 3, when a remote isolated shunt sensor is connected via the 71M6x01, the samples associated with this current channel are not routed to the multipl ex er, and ar e instead transferred digitally to the 71M6541D/F via the digital isol ation interface and are dir ectly stored in CE RAM.

See Figure 6 for the m ultiplexer timing sequence correspondi ng to Figure 3. See Figure 36 for the meter configurati ons corr espondi ng to Figure 3.

Figure 3. 71M6541D/F AFE Block Diagram with 71M6x01

Figure 4 shows the 71M6542F AFE with locally connected sensors. The anal og input signals (IAP-IAN,

VA, IBP-IBN and VB) are multiplexed t o the ADC input and sampl ed by the ADC. The ADC out put is decimated by the FIR filt er and stor ed in CE RAM where it can be accessed and processed by the CE.

See Figure 7 for the multiplexer timing sequence corresponding to Figure 4. See Figure 37 for the meter configurati on c or r espondi ng to Figure 4.

Figure 4. 71M6542F AFE Block Diagram (Local Sensors)

∆Σ ADC

CONVERTER

VREF

MUX

VREF

VADC

FIR

IBP

VADC9 (VB)

IAP

VADC10 (VA)

IAN

IBN

71M6542F

CE RAM

71M6x01

INP

INN

Remote

Shunt

Digital Isolation Interface

Local

Shunt

11/5/2010

Figure 5 shows t he 71M6542F multiplexer interface with one l oc al and one r em ote resistive shunt sensor.

As seen in Figure 5, when a remote isolat ed shunt sen sor is connected via the 71M6x01, the samples associated with t his curr ent channel are not routed to the multi plex er , and are instead transferred digitally to the 71M6542F via the digit al isolation interface and are di r ectly stored in CE RAM.

See Figure 6 for the multiplexer timing sequence corresponding to Figure 5. See Figure 38 for the meter configurati ons corr espondi ng to Figure 5.

Figure 5. 71M6542F AFE Block Diagram with 71M6x01

2.2.1 Signal Input Pins

The 71M6541D/F f eatures five ADC inputs. The 71M6542F feat ur es six A DC input s. IAP-IAN and IBP-IBN are intended for use as current sensor inputs. These four current sensor inputs can be

configured as four s ingle-ended inputs, or can be paired to form two differential inputs. For best performance , it is reco m men ded to con figure the cu rrent sensor inputs as diffe ren tial inputs (i.e., IAP-IAN and IBP-IBN). The first differential input (IAP-IAN) features a pre-amplif ier with a selectable gain of 1 or 8, and is intended for dire c t conne ction to a shunt res istor sensor , and can also be us ed with a Cur ren t Transformer (CT). The remaining differential pair (i.e., IBP-IBN) may be used with CTs, or may be enabled to interface to a r emote 71M6x01 isolated current senso r providing isol ation for a sh unt resist or sensor using a low cost pulse transformer.

The remaining input in the 71M6541D/F (VA) is single-ended, and is intended for sensing the line voltage in a single-phase meter application using Equation 0 or 1 (see 2.3.4 Meter Equati ons on page 25). The 71M6542F features an additional single-ended voltage s ens ing input (VB) to su pport bi-phase applicat ions using Equation 2. These s ingle-ended inputs are referenced to the V3 P3A pin.

All analog si gnal input pins measure voltage. In th e c ase of sh unt cur rent sensors, currents are sensed as a voltage drop in the shunt resistor sens or . Referring to Figure 3, shunt sensors can be conne c ted dire c t ly to the 71M654x (re ferre d to as a ‘loc al’ shunt sensor) or connec te d via an isolated 71M6x01 (referred to as a ‘remote’ shunt sensor). In the case of Cur ren t Transformers (CT), the current is measur ed as a voltage across a bur den resistor that is connected to the secondary winding of the CT. Meanwhile, line voltages are sensed through resistive voltage dividers. The VA and VB pins (VB is available in the 71M6542F only) are single-ended and their c ommon return is the V3P3A pin.

Pins IAP-IAN can be programmed individually to be differential or single-ended as determined by the DIFFA_E (I/O RAM 0x210C[4]) control bit. However, for most appli c ations, IAP-IAN are c onfigured as a differential input to work wit h a shunt or CT directly interfaced to the IAP-IAN differential input with the appropriate external signal conditioning components (see 4.2 Direct Connec tion of Sensors on page 92).

The performance of t he IAP-IAN pins can be enhanced by enabling a pr e-amplifier with a fixed gain of 8, using the I/O RAM contr ol bit PRE_E (I/O RAM 0x2704[5]). When PRE_E = 1, IAP-IAN become the inputs to the 8x pre-amplifi er, and the output of this amplifier is supplied to the multiplexer. The 8x amplification

71M6542F

(hex)

Eq. 0 or 1

Eq. 2

FIR_LEN[1:0]

210C[2:1] 1 1

ADC_DIV

2200[5] 1 1

PLL_FAST

2200[4] 1 1

MUX_DIV[3:0]

2100[7:4] 3 3

MUX0_SEL[3:0]

2105[3:0] 0 0

MUX1_SEL[3:0]

2105[7:4] A A

MUX2_SEL[3:0]

2104[3:0] 2 2

MUX3_SEL[3:0]

2104[7:4] 1 1

RMT_E

2709[3] 0 0

DIFFA_E

210C[4] 1 1 1 DIFFB_E

210C[5] 1 1

EQU[2:0]

2106[7:5]

0 or 1

CE Code

CE41A01

CE41A04

Equations

0 or 1

1 Shunt and 1 CT

2 CTs

1 Shunt and 1 CT

2 CTs

1 Shunt and 1 CT

2 CTs

Applicable Figure

Figure 2

Figure 4

during initialization.

is useful when current sensor s with low sensitivit y, such as shunt r esi stor s, ar e used. With PRE_E set, the IAP-IAN input signal am plitude is restricted t o 31.25 mV peak.

For the 71M 654x application utilizing two shunt resistor s ens o rs (Figure 3), the IAP-IAN pins are configured for differential mode to interface to a local shunt by setting the DIFFA_E control bit. Meanwhile , the IBP-IBN pins are re-configured as digital balanced pair to communicate with a Teridian 71M6x01 Isolated Sensor interface by setting t he RMT_E control bit (I/O RAM 0x2709[3]). The 71M6x01 communicates with the 71M654x using a bi-directional digital data stream through an isolating low -cost pulse transformer. The 71M654x also supplies power to the 71 M6 x01 through the isola ting transformer. This type of interface is further described at the end of this chapter (see 2.2.8 71M6x01 Isolated Sensor Interface (Remote Sensor

Interface)).

For use with Current Transformers (CTs), as shown in Figure 2, the RMT_E control bit is reset, so that the IBP-IBN pins are c onfigured as local analog inputs. The IAP-IAN pins cannot be configured as a remote sensor interf ac e.

2.2.2 Input Mu lt ip le x e r

When operating with local sensors, the input multiplexer sequentially applies the input signals from the analog input pins to the input of the ADC (see Figure 2 and Figure 4). One complete sampling sequence is called a multiplexer frame. The multiplexer of the 71M6541D/F can selec t up to three input signals (IAP-IAN, VA, and IBP-IBN) per multiplexer frame as controlled by the I/O RAM control field MUX_DIV[3:0] (I/O RAM 0x2100[7:4]) (see Figure 6). T he multiplex er of t he 71M65 42F add s the VB signal to achiev e a total of four inputs (see Figure 7). T he mult iplex er al way s sta rts at state 1 an d pro ceed s unt i l as many s tat e s as determined by MUX_DIV[3:0] have been conv er ted.

The 71M65 41D/ F an d 71M 65 42F ea ch re qui r e a uni que CE c ode that is written f or the spec ific appli c ation. M oreover, each CE code r equire s specific AFE and MUX settings in or der to function properly. Table 1 prov ides the CE code and settings corresponding to the local sensor c onfigurations shown in Figure 2 and Figure 4. Table 2 pr ov ides the CE code and sett ings corresponding to the local/remote sensor configuration utilizing the 71M6x01 as shown in Figure 3 and Figure 5.

Table 1. Required CE Code and Settings for Lo cal Senso rs

I/O RAM

Mnemonic

Current Sensor Types

Notes:

TERIDIAN updates the CE code periodically. Please contact your local TERIDIAN representative to obtain the latest CE code and the associated settings. The configuration presented in this table is set by the MPU demonstration code

I/O RAM

Location

71M6541D/E

(hex)

Table 2. Required CE Code and Settings for 71M6x01 isol at ed Sensor

I/O RAM

Mnemonic

I/O RAM

Location

71M6541D/E

(hex)

71M6542F

(hex)

FIR_LEN[1:0]

210C[2:1] 1 1

ADC_DIV

2200[5] 1 1

PLL_FAST

2200[4] 1 1

MUX_DIV[3:0]

2100[7:4] 3 3

MUX0_SEL[3:0]

2105[3:0] 0 0

MUX1_SEL[3:0]

2105[7:4] A A

MUX2_SEL[3:0]1

2104[3:0] 1 9

MUX3_SEL[3:0]1

2104[7:4] 1 1

RMT_E

2709[3] 1 1

DIFFA_E

210C[4] 1 1

DIFFB_E

210C[5] 0 0

EQU[2:0]

2106[7:5]

0 or 1

0, 1 or 2

CE41B0162012 CE41B0166013

Equations

0, 1

0, 1 and 2

1 Local Shunt

1 Remote Shunt

1 Local Shunt

1 Remote Shunt

Applicable Figure

Figure 3

Figure 5

is set by th e MPU d em ons trati on c od e dur i ng in it i al iz ation.

CE Code --

Current Sensor Type --

Notes:

1. Although not used, set to 1 (the sample data is ignored by the CE)

2. 71M654x with 71M6201 remote sensor (200 Amps)

3. 71M654x with 71M6601 remote sensor (60 Amps) TERIDIAN updates the CE code periodically. Please contact your local TERIDIAN representative to obtain the latest CE code and the associated settings. The configuration presented in this table

and

Using settings for the I/ O RAM Mnemoni cs listed in Table 1 and Table 2 that do not match those required by the corresponding CE co de being u sed results in unde sira bl e si de ef f ect s and must not b e selected by the MPU. Consult your lo c al TERIDIAN repre se ntati ve to obtain the correct CE co de and AFE / MU X s et t i ng s correspo nding to the application.

For a basic single-phase application, the IAP-IAN current input is configured for differential mode, whereas the VA pin is single-ended and is typically connected to the phase voltage via a resistor divider. The IBP-IBN differential input may be optionally used to s ens e the Neutral current. This configuration implies that t he m ultiplexer applies a total of three inputs to the ADC. For this confi gur ation, the multiplexer sequence is as shown in Figure 6. In this configuration IAP-IAN, IBP-IBN and VA are sampled, the ext r a conversi on time slot (i.e., slot 2) is the optional Neutral curr ent, and the physical current sensor for the Neutral current measurement m ay be omit ted if not required.

For a standard single-phase appl ication with tamper sensor in the neutral path, two current inputs can be configured for differential mode, using the pin pair s IAP-IAN and IBP-IBN. This means that the multiplexer applies a total of three inputs to the ADC. In this application, the system design may use two locally connected current sensors via IAP-IAN and IBP-IBN, as show n in Figure 2, and configured as differential inputs. Alternately, the IAP-IAN pin pair is con fig ure d as a diffe ren tial input and connected to a local current shunt, and IBP-IBN is configured to connect to an isolated 71M6x01 isolated sensor (i.e., RMT_E = 1), as shown in Figure 3. The VA pin is typically connected to the phase voltage via resistor div iders. For this configuration, the multiplexer frame is also as sho wn in Figure 6 and time slot 2 is unused and ignored by the CE, as the samples correspondi ng to the remote sensor (IBP-IBN) do not pass through the multiplexer and are stored directly in CE RAM. The remote current sensor channel is sampled during t he second half of the multiplexer frame and its timing rel ationship to the VA voltage is precisel y k nown so that delay compensation can be properly applied.

The 71M6542F adds the ability to sample a second phase voltage (applied at the VB pin), which makes it suitable for met er s with two voltage and two current sensors, such as m eters implementing Equation 2 for dual-phase operation (P = VA*IA+VB*IB). Figure 7 shows the multiplexer sequence when four input s are processed with l oc ally c onnec ted sensors, as shown in Figure 3. When using one loc al and one r em ote senso r (Figure 5), the multiplexer sequence is also as shown in Figure 7.

CK32

MUX STATE

00 1 2

MUX_DIV[3:0] = 3 Conversions

Settle

Multiplexer Frame

CROSS

MUX_SYNC

11/5/2010

Fig. 2: IA VA IB Fig. 3: IA VA Not Used Fig. 5: IA VA VB

CK32

MUX STATE

0 1 2 3

MUX_DIV = 4 Conversions

Settle

Multiplexer Frame

CROSS

MUX_SYNC

11/5/2010

Fig. 4: IA VA IB VB

disturbed.

For both multiplex er sequences sho wn in Figure 6 and Figure 7, the frame dur ation is 13 CK32 cycles (where CK32 = 32768 Hz), t her ef or e, the resulting sample rate is 32768 Hz / 13 = 2520.6 Hz.

Table 3 summarizes the various AFE input configurations.

Figure 6: States in a Multipl exer Frame (MUX_DIV[3:0] = 3)

Figure 7: States in a Multipl exer Frame (MUX_DIV[3:0] = 4)

Table 3: ADC Input Configuration

ADC

Channel

IAP ADC0 IAN ADC1

Required

Setting

DIFFA_E = 1

Comment

Differential mode must be selected with DIFFA_E = 1 (I/O RAM 0x21 0C[4]). The ADC results are stored i n CE RAM

location ADC0 (CE RAM 0x0), and ADC1 (CE RAM 0x1) is not

For locally connected sensors (Figure 2 and Figure 4), the

IBP ADC2

differential input must be enabled by setting DIFFB_E (I/O RAM 0x21 0C[5].

IBN ADC3

DIFFB_E = 1

RMT_E = 1

For the r emote connected sensor (Figure 3 and Figure 5) with a remote shunt sensor, RMT_E (I/O RAM 0x2709[3]) must be set. In both cases , the ADC results are stored in RA M loca tion ADC2 (CE R AM 0x2 ), and ADC3 (CE RAM 0x3 ) is not disturbed.

VA ADC10 --

VB ADC9 --

Multiplexer adv anc e, FIR initiation and chopping of the ADC reference voltage (using the internal CROSS signal, see 2.2.7 Voltage References) are cont r olled by the internal MUX_CTRL circuit. Additionally,

Single-ended mode only . The ADC resul t is stored in RAM location ADC10 (CE RAM 0xA).

Single-ended mode only ( 71M 6542F only). The ADC result is stored in RAM location ADC9 (CE RAM 0x9).

MUX_CTRL launches each pass of the CE through its code. Conceptually, MUX_CTRL is clocked by CK32, the 32768 Hz clock from the PLL block. The behavior of the MUX_CTRL circuit is governed by:

• CHOP_E[1:0] (I/O RAM 0x2106[3:2])

• MUX_DIV[3:0] (I/O RAM 0x2100[7:4])

• FIR_LEN[1:0] (I/O RAM 0x210C[2:1])

• ADC_DIV (I/O RAM 0x2200[5])

The duration of each multiplexer state depends on the number of ADC sampl es processed by the FI R as determined by the FIR_LEN[1:0] (I/O RAM 0x210C[2:1] control field. Each multiplexer state starts on the rising edge of CK32, t he 32-kHz clock.

It is recomm ended that MUX_DIV[3:0] (I/O RAM 0x220 0[ 2:0]) be s et to zero whi le cha nging the ADC confi guration. Although not required, it minimizes system transients that might be caused by momentary shorts between the AD C inpu ts, especially when changing the DIFFn_E control bits (I/O RAM 0x210C[5:4]). After the configuration bits are set, MUX_DIV[3:0] should be set to the required value.

Additionall y , t he ADC can be configured to operate at ½ rate (32768*75=2.46MHz). In this mode, the bias current to the ADC am plifiers is reduced and overall system power i s reduced. The ADC_DIV (I/O RAM 0x2200[5]) bit selects full speed or half speed. At half speed, if FIR_LEN[1:0] is set to 01 (288), each conversion requir es 4 XTAL cy cl es, r esul ting in a 2520Hz sample rate when MUX_DIV[3:0] = 3. Note that in order to work with these power-reduci ng se ttings, a corresponding CE c ode is required.

The duration of each time sl ot in CK32 cycles depends on FIR_LEN[1:0], ADC_DIV and PLL_FAST:

Time_Slot _Dur ation (PLL_FAST = 1) = (FIR_LEN[1:0]+1) * (ADC_DIV+1) Time_Slot _Dur ation (PLL_FAST = 0) = 3*(FIR_LEN[1:0]+1) * (ADC_DIV+1)

The duration of a multiplexer frame in CK32 cycles is:

MUX_Frame_Durati on = 3-2*PLL_FAST + Time_Slot_Duration * MUX_DIV[3:0]

The duration of a multiplexer frame in CK_FIR c ycle s is: MUX frame duration (CK_FI R c ycles) =

[3-2*PLL_FAST + Time_Slot_Dur ation * MUX_DIV] * (48+PLL_FAST*102)

The ADC conversion sequence is progr ammable through the MUXx_SEL control fields (I/O RAM 0x2100 to 0x2105). As stated above, there are three ADC time slots in the 71M6541D/F and four ADC time slots in the 71M6542F, as set by MUX_DIV[3:0] (I/O RAM 0x2100[7:4]). In the expression MUXx_SEL[3:0] = n, ‘x’ refers to the multiplexer frame time slot number and n refers to the desired ADC input number or ADC handle (i.e., ADC0 to ADC10, or simply 0 to 10 decimal). Thus, there are a total of 11 valid ADC handles in the 71M654x devices. For example, if MUX0_SEL[3:0] = 0, then ADC0, corresponding to the sample from the IAP-IAN input (configured as a differential input), is positioned in the multiplexer frame during time slot 0. See

Table 1 and Table 2 f or the appropriate MUXx_SEL[3:0] settings and other settings applic able to a

particular CE code. Note that whe n the remote s ensor interface is enabled, and even though th e samples corresponding to

the remote sensor current (IBP-IBN) do not pass t hrough the mul tiplexer, the MUX2_SEL[3:0] and MUX3_SEL[3:0] control fields must be written wit h a v alid ADC handle that is not being used. Typically, ADC1 is used for this purp ose (see Table 2). I n this manne r , the ADC1 handle, whic h is not used i n the 71M6541D/F or 71M65 42F, i s used a s a place holder in the multiplex er fram e, in order to gener ate th e correct multiplexer frame sequence and the correct s ampl e r ate. The re sul ti n g sampl e dat a st or ed in CE RAM 0x1 is undefined and is ignored by the CE code. Meanwhile, the digital isol ation interface t akes care of automatically storin g the sample s for the remote interfac e current (IBP-IBN) in CE RAM 0x2.

Delay compensati on and other functions in the CE code require the settings for MUX_DIV[3:0], MUXx_SEL[3:0], RMT_E, FIR_LEN[1:0], ADC_DIV and PLL_FAST to be fixed for a given CE code. Refer to Table 1 and Table 2 for the settings that are applicable to the 71M6541D/F and 71M6542F.

MUX5_SEL[3:0]

MUX6_SEL[3:0]

2102[3:0]

Selects the ADC input conver ted during time slot 6.

2102[7:0]

Selects the ADC input conver ted during time slot 7.

MUX9_SEL[3:0]

Controls the rat e of the ADC and FIR cl oc k s.

MUX_DIV[3:0]

PLL_FAST

Determines the num ber of ADC cycles i n the ADC decimation FIR filter.

DIFFA_E

210C[5]

Enables the diff er ential configuration for analog input pins IBP-IBN.

PRE_E

delay

360360 ⋅⋅=⋅=

Table 4 summarizes t he I/ O RAM registers used for configuring the multiplexer, signals pins, and ADC.

All listed registe rs are 0 after reset a nd wake from battery m odes, and are readable and wri table.

Table 4: Multiplexer and ADC Configuratio n Bi t s

Name Location Description

MUX0_SEL[3:0] MUX1_SEL[3:0] MUX2_SEL[3:0] MUX3_SEL[3:0] MUX4_SEL[3:0]

2105[3:0] Selects the ADC input converted during time slot 0. 2105[7:4] Selects the ADC input converted during time slot 1. 2104[3:0] Selects the ADC input converted during time slot 2. 2104[7:4] Selects the ADC input converted during time slot 3. 2103[3:0] Selects the ADC input converted during time slot 4. 2103[7:4] Selects the ADC input converted during time slot 5.

MUX7_SEL[3:0] MUX8_SEL[3:0]

2101[3:0] Selects the ADC input converted during time slot 8. 2101[7:0] Selects the ADC input converted during time slot 9.

MUX10_SEL[3:0]

ADC_DIV

2100[3:0] Selects the ADC input converted during time slot 10.

2200[5]

2100[7:4] The number of ADC time slots in each multiplexer frame (maximum = 11).

2200[4] Contr ols the speed of the PLL and MCK.

FIR_LEN[1:0]

210C[1] 210C[4] Enables the differential confi gur ation for analog input pins IAP-IAN.

DIFFB_E

Enables the remote sensor interface transforming pins IBP-IBN into a

RMT_E

2709[3]

digital bal anc ed differential pair f or communications with the 71M6x01 sensor.

2704[5] Enables the 8x pre-amplifier.

Refer to Table 76 start ing on page 111 for more complete details about these I/O RAM locations.

2.2.3 Delay Compensation

When measuring the energy of a phase (i .e., Wh and VARh) in a service, the volt age and current for that phase must be sampled at the same instant . Otherwise, the phase difference, Ф, introduces errors.

Where f is the frequency of t he input signal, T = 1/f and t voltage.

Traditionally, sampling is accomplished by using two A/D converters per phase (one for voltage and the other one for curr ent) c ontrolled to sample simultaneously . Teridian’s Single-Converter Technology however, exploits the 32-bit signal processing capabi lity of its CE to implement “constant delay” all-pass

filters. The all-pass filter corrects for the conver si on time diff er enc e between the voltage and the corresponding current samples that are obtai ned with a single multiplexed A/D converter.

The “constant del ay ” all -pass fi lter provides a broad-band delay 360 the difference in sample time between the voltage and the current of a given phase. This digital filter does not affect the amplit ude of the signal, but provides a preci sel y cont r olled phase response.

The recommended ADC multiplexer sequence samples the cur r ent fi r st, immediately foll owed by sampling of the corr espondi ng phase voltage, thus the voltage is delayed by a phase angle Ф relative to the current. The delay compensation implemented in the CE aligns the voltage sam ples with their corresponding current samples by first delaying the current samples by one full sample interval (i.e.,

), then routing the voltage samples through t he all-pass filter, thus delaying the voltage samples by

is the sampling delay between current and

delay

– θ, which is precisely matched t o

360o - θ, resulting in the residual phase error between the cur r ent and its corresponding v oltage of θ – Ф. The residual phase error is negligible, and is typi c ally less than ±1. 5 mil li-degrees at 100Hz, thus it does not contribute to errors in the energy measurements.

When using remote sensors, t he CE performs the same delay compensati on described above to align each voltage sam ple with its corresponding current sam ple. Ev en though the remote current sam ples do not pass through the 71M654x multiplexer, their timing relationship to their corresponding voltages is fixed and precisel y known, provided that the MUXn_SEL[3:0] slot assignment fields are programmed as shown in Table 1 and Table 2.

2.2.4 ADC Pre-Amplifier

The ADC pre-amplifier is a low-noise differential amplifier with a fix ed gain of 8 available only on the IAPIAN sensor input pins. A gain of 8 is enabled by setting PRE_E = 1 (I/O RAM 0x2704[5]). When disabled, the supply current of t he pr e-am plifier is <10 nA and the gain is unity. With proper settings of the PRE_E and DIFFA_E (I/O RAM 0x210C[4]) bits, the pre-ampl if ier can be u sed wh et he r dif ferential mode is selected or not. F or best performance, the differ ential mode is recommended. In order to save power, the bias current of the pre -amplifier and AD C is adjusted acco rdi ng to the ADC_DIV control bit (I/O RAM 0x2200[5]).

2.2.5 A/D Converter (ADC)

A single 2nd order delta-sigma A/D converter digitizes the voltage and current inputs to the device. The resolution of the ADC, including the sign bit, is 21 bits (FIR_LEN[1:0] = 1, I/O RAM 0x210C[2:1]) , or 22 bits (FIR_LEN[1:0] = 2). The ADC is clocked by CKA DC.

Initiation of each ADC conversion is contro lled by MUX_CTRL internal circuit as described above. At the end of each ADC conversion, the FIR filter output data is stored into the CE RAM location determined by the multiplexer selection. FIR data is stored LSB justified, but shifted left 9 bits.

2.2.6 FIR Fi lter

The finite impulse response filter is an integral part of the ADC and it is optimized for use with the multiplexer. The purpose of the FIR filter is to decimate the ADC output to the desired resol ution. At the end of each ADC conversion, t he output data is stored into the fixed CE RAM location det ermined by the multiplexer selection as shown in Table 1 and Table 2.

2.2.7 Voltage References

A bandgap circuit provides the reference voltage to the ADC. The amplifier within the reference is chopper stabilized, i.e., the chopper ci r c uit can be enabled or disabled by the MPU using the I/O RAM control field CHOP_E[1:0] (I/O RAM 0x2106[3:2]). The two bits in the CHOP_E[1:0] field enable the MPU to operate the chopper circuit in regular or inverted oper ation, or in toggling m odes (recommended). When the chopper circuit is toggled in betwe en multiplexer cycl es, dc off sets on VREF are automatically be averaged out, ther efore the chopper circuit shoul d always be conf igured for one of the toggli ng m odes.

Since the VREF band-ga p a mp lifie r is chopper-stabilized, the dc offset volt age, which is the most significant long-term drift mechanism in the voltage references (VREF ) , is automatically remov ed by the chopper circ uit. B oth the 71M654x and the 71M6x01 feature chopper circuit s for their respective VREF voltage ref er enc e.

The general topology of a chopped am plifier is shown in Figure 8. The CROSS signal is an int er nal onchip signal and is not accessibl e on any pin or register.

inp

outp

outn

inn

CROSS

A B

Figure 8: General Topology of a Chopped Amplifier

It is as s umed that an offset v oltage Voff appears at the positive amplifi er input. With all switches, as controlled by CROSS (an internal si gnal) , in the A position, the output voltage is:

Voutp – Voutn = G (Vinp + Voff – Vinn) = G (Vinp – Vinn) + G Voff

With all switches set to the B position by applying the inverted CROSS signal, the output volt age is:

Voutn – Voutp = G (Vinn – Vinp + V off ) = G (Vinn – Vinp) + G Voff, or Voutp – Voutn = G (Vinp – Vinn) - G Voff

Thus, when CROSS is toggl ed, e.g., after each multiplex er cycl e, the offset alternatel y appears on the output as positiv e and negative, which results in the offset effectively bei ng elimi nated, regardless of its polarity or magnitude.

When CROSS is high, the connection o f the a mp lifie r input devices is reversed. This preserves the overall polarity of that amplifier gain; it inverts its inpu t o ffse t. By alternately reversing the connection, the amplifier’s offset is averaged t o z er o. This rem ov es the most signif icant long-term drift m echani sm in the voltage reference. The CHOP_E[1:0] (I/O RAM 0x2106[3:2]) control field controls the beh avio r of CROSS. The CROSS signal reverses the amplifier connection in the voltage reference in orde r to negate the effects o f its offset. On the first CK32 rising edge after the last multiplexer state of its sequence, the multi plex er wait s one additional CK 32 cycle before beginning a new frame. At the beginning of this cycle, the value of CROSS is updated according to the CHOP_E[1:0] field. The extra CK32 cycle allows time for the chopped VRE F to settle. During this cycle, MUXSYNC is held high. The leading edge of MUXSYNC initiates a pass through the CE program sequence. The beginning of the sequence is the serial readout of the four RTM words.

CHOP_E[1:0] has four states: positive, reverse, and two toggle stat es. In t he posi tive state, CHOP_E[1:0] = 01, CROSS is held low. In the reverse state, CHOP_E[1:0] = 10, CROSS is held high.

Figure 9: CROSS Signal with CHOP_E = 00

Figure 9 shows CROSS over two accumulation intervals when CHOP_E[1:0] = 00: At the end of the

first interval, CROSS is high, at the end of the second interval, CROSS i s low. Op er a tion wit h CHOP_E[1:0] = 00 does not require control of the chopping mechanism by the MPU.

In the second toggle state, CHOP_E[1:0] = 11, CROSS does not toggle at the end of the last multiplexer cycle in an accumul ation interval.

A second, low-power volt age r eference is used in the LCD system and for the comparators that support transiti ons to and from the bat tery modes.

Command

Phase Selecto r

Associated TMUXRn

Control Field

000

Invalid

---

001

Command 1

TMUXRB [2:0]

100

Reserved

101

Invalid

110

Reserved

2.2.8 71M6x01 Isolated Sensor Interface (Remote Sensor Interface)

2.2.8.1 General Description

Non-isolati ng sensors, such as shunt r esi stors, can be connected to the inputs of the 71M654x via a combination of a pulse tr ansformer and a 71M6x01 IC (a top-level block diagr am of t his sensor i nterface is shown in Figure 36). The 71M6x01 receives power directly from the 71M654x via a pulse transformer and does not require a dedicated power supply circuit. The 71M6x01 establishes 2-way communication with the 71M654x, suppl yi ng c ur r ent samples and auxiliary information such as sensor temperatur e v ia a serial data stream .

One 71M6x01 Isolated Se nsor c an be su pported by the 71M6541D/F and 71M6 542F . When remote interface IBP-IBN is enabled, the two analog current inputs pins IBP and IBN become a digital balanced differential interface to the remote sensor. See Table 3 for details.

Each 71M6x01 Isol ated Sensor consists of the following building blocks:

• Power supply for power pulses received from the 71M654x

• Digital communications interface

• Shunt signal pre-amplifier

• Delta-Sigma ADC Conv erter with precision bandgap reference (chopping amplifi er )

• Temperature sensor

• Fuse system contai ning par t-specific informati on

During an ordinar y multiplexer cycle, the 71M654x internally determines which other channels are enabled with MUX_DIV[3:0] (I/O RAM 0x2100[7:4]). At the same time, it decimates the modulator output from the 71M6x01 Isolated Sensors. Eac h r esul t is written to CE RAM duri ng one of its CE acc ess time slots. See Table 3 for the CE RAM locations of the sampled signals.

2.2.8.2 Communication between 71M654x and 71M6x01 Isolated Sensor

The ADC of the 71M6x01 derives its timing from the power pulses generated by the 71M654x and as a result, o perates its ADC slaved to the frequency of the power pulses. The generation of power pulses, as well as the communication protocol between the 71M654x and 71M6x01 Isolated Sensor is automatic and transparent to the user. Details are not covered in this data sheet.

2.2.8.3 Control of the 71M6x01 Isolated Sensor

The 71M654x can read or write certain types of information from each 71M6x01 isolated sensor. The data to be read is selected by a combination of the RCMD[4:0] and TMUXRn[2:0]. To perform a read

transaction from one of the 71M6x01 devices, the MPU first writes the TMUXRn[2:0] field (where n = 2, 4, 6, located at I/O RAM 0x270A[2:0], 0x270A[6:4] and 0x2709[2:0], respectively). Next, the MPU writes RCMD[4:0] (SFR 0xFC[4:0]) with the desi r ed c ommand and phase select ion. When the RCMD[4:2] bits have cleare d to zero, the trans ac tion has been complete d and the requested data is av ailabl e in

RMT_RD[15:0] (I/O RAM 0x260 2[ 7:0] is the MSB and 0x2603[7:0] is the LSB). The read parity error bit, PERR_RD (SFR 0xFC[6]) is also updated during the transaction. If the MPU writes to RCMD[4:0] before a

previously init iated read transacti on is completed, the command is ignored. Therefore, the MPU must wait for RCMD[4:2]=0 before proceeding to issue the next remote sensor read command.

The RCMD[4:0] field is divided into two sub-fields, COMMAND=RCMD[4:2] and PHASE=RCMD[1:0], as shown in Table 5.

Table 5. RCMD[4:0] Bits

RCMD[4:2]

RCMD[1:0]

IBP-IBN

111

Reserved

Notes:

is invalid and must not be used.

TRIMT[7:0]

Notes:

The CHOP settings for the isolated sensors.

11 – Same as 00

1. Only two codes of RCMD[4:2] (SFR 0xFC[4:2]) are relevant for normal operation. These are RCMD[4:2] = 001 and 010. Codes 000 and 101 are invalid and will be ignor ed if used. The remaining codes are reserved and must not be used.

2. For the RCMD[1:0] control field, codes 01, 10 and 11 are valid and 00

Table 6 shows the allowable combinations of val ues i n RCMD[4:2] and TMUXRn[2:0], and the

corresponding data ty pe and format sent back by the 71M6x01 isolated sensor and how the data is stored in RMT_RD[15:8] and RMT_RD[7:0]. The MPU selects which of the three phase s i s read by asserting the proper code in the RCMD[1:0] field, as shown in Table 5.

Table 6: Remote Interface Read Commands

RCMD[4:2] TMUXRn[2:0] Read Operation RMT_RD [15:8] RMT_RD [7:0]

001 00X

010 00X 010 01X 010 10X

1. TRIMT[7:0] is the VREF trim value for all 71M6x01 devices. Note that the TRIMT[7:0] 8-bit v alue i s for med by RMT_RD[8] and RMT_RD[7:1]. See the 71M6 xxx Data shee t f or more information on TRIMT[7:0]

2. See the 71M6xxx Data Sheet for the equation to calculate temperature from the the 71M 6x 01.

3. See the 71M6xxx Data Sheet for the equation to calculate temperature from the the 71M 6x 01.

(trim fuse for all 71M6x01)

STEMP[10:0]

(sensed 71M6x01 temperature)

VSENSE[7:0]

(sensed 71M6x01 supply v oltage)

VERSION[7:0]

(chip version)

TRIMT[7]=RMT_RD[8] TRIMT[6:0]=RMT_RD[7:1]

STEMP[10:8]=RMT_RD[10:8]

(RMT_RD[15:11] are sign ext en ded )

All zeros VSENSE[7:0]

VERSION[7:0] All zeros

STEMP[7:0]

STEMP[7:0] value read from VSENSE[7:0] value read from

With hardware and trim-related information on each c onnected 71M6x01 Isolated Sensor available to the 71M6541D/F, the MPU can implement temperature compensation of the energy measurement based on the individual t em per ature characteristic s of the 71M6x01 Isolated Sensor. See 4.7 M etrology Temperature

Compensation on page 97 for details. Table 7 shows all I/O RAM registers used for c ontrol of the external 71M6x01 Isol ated Sensors. See the

71M6xxx Data Sheet for addi tional details.

Table 7: I/O RAM Control Bits for Isolated Sensor

Name Address

RST

Default

WAKE

Default

R/W Description

When the MPU wr ites a non-zero value to RCMD, the 71M654x issues a command to the cor-

RCMD[4:0]

SFR

FC[4:0]

0 0 R/W

responding isol ated sensor selected with RCMD[1:0]. When the command is complete, the 71M654x clears RCMD[4:2]. The command code itself is in RCMD[4:2].

The 71M654x sets these bits to i ndicate that a

PERR_RD

PERR_WR

SFR FC[6] SFR FC[5]

0 0 R/W

parity error on the i sol ated sensor has been detected. Once set, the bits are remember ed until they are cleared by the MPU.

CHOPR[1:0]

2709[7:6] 00 00 R/W

00 – Auto chop. Change every multiplexer frame. 01 – Positive 10 – Negative

Default

TMUXRB[2:0]

270A[2:0]

000

R/W

The TMUX bits for control of the isolated sensor.

RMT_RD[15:8]

2602[7:0]

Refer to Table 76 start ing on page 111 for more complete details about these I/O RAM locations.

Name Address

RMT_RD[7:0]

RFLY_DIS

RMTB_E

RST

2603[7:0]

210C[3]

2709[3] 0 0 R/W

0 0 R The read buffer for 71M6x01 read operations.

0 0 R/W

WAKE

R/W Description

Controls how the 71M654x drives the 71M6x01 power pulse. When set, the power pulse i s driven high and low. When cleared, it is driven high followed by an open circ uit flyback interval.

Enables the isolated remote sensor interface and re-configures pins IBP-IBN as a balanced pair digital remote interface.

2.3 Digital Computation Engine (CE)

The CE , a dedicated 32-bit signal pro cess or, per forms the preci sion computati ons necessary to ac curately measure energy. The CE cal c ulations and processes include:

• Multiplicati on of each current sample with its associated voltage sample to obtain the energy per sample (when multi plied with the constant sample time).

• Frequency-insensitive delay cancellation on all four channels (to compensate for the delay between samples caused by the multiplexing scheme).

• 90° phase shifter (for VAR calc ulations).

• Pulse generation.

• Monitoring of the input signal frequency (for frequenc y and phase i nformation).

• Monitoring of the input signal amplitude (for sag detec tion).

• Scaling of the processed sam ples based on calibration coefficients.

• Scaling of sampl es based on temperature compensation information.

2.3.1 CE Program Memory

The CE program resides in flash memory. Common access to flash memory by the CE and MPU is controlled by a memory share circuit. Each CE instr uc tion word is two bytes long. Allocated flash space for the CE program cannot exceed 4096 16-bi t words (8 KB). The CE program counter begins a pass through the CE code each time multi plex er state 0 begins. The code pass ends when a HALT instruction is executed. For proper operation, the code pass must be completed before the multiplexer cycle ends.

The CE program must begin on a 1 KB boundary of the flash addre ss. The I/O RAM con trol field CE_LCTN[5:0] (I/O RAM 0x2109[5:0]) def i nes whic h 1 KB boundary contains the CE code. Thus, the first CE instruction i s l oc ated at 1024*CE_LCTN[5:0].

2.3.2 CE Data Memory

The CE and MPU share data memory (RAM). Common access to XRA M by the CE and MP U is con tro lled by a memory share circuit. The CE can access up to 3 KB of the 3 KB data RAM (XRAM), i.e., from RAM address 0x0000 to 0x0C00.

The XRAM can be accessed by the FIR filter block, the RTM circuit, the CE, and the MPU. Assigned time slots are reserved for FIR and MPU, respectively, to prevent bus contention for XRAM data access by the CE.

The MPU reads and writ es the XRAM shared between the CE and MPU as the primary m eans of data communicati on between the two processors.

Table 3 shows the CE addresses in XRAM al located to analog input s from the AFE.

The CE is aided by support hardware to facilitate implementation of equations, pulse counters, and accumulators. This hardware is controll ed through the I/O RAM contro l field EQU[2:0], equation assist

(I/O RAM 0x2106[7:5]), bit DIO_PV (I/O RAM 0x2457[6]), bit DIO_PW, pulse count assist (I/O RAM 0x2457[7]), and SUM_SAMPS[12:0], accumulation assist (I/O RAM 0x2107[4:0] and 0x2108[7:0]).

1. Optionally , I B may be used to m easure neut r al c ur r ent

SUM_SAMPS[12:0] supports an accumulation scheme where the incremental energy values from up to SUM_SAMPS[12:0] multiplexer frames are added up over one accumulation interval. The integr ation time for each energy output is, for example, SUM_SAMPS[12:0]/2520.6 (with MUX_DIV[3:0] = 011, I/O RAM 0x2100[7:4] and FIR_LEN[1:0] = 10, I/O RAM 0x210C[2:1]). CE hardware issues the XFER_BUSY interrupt

when the accumulation is complete.

2.3.3 CE Communication with the MPU

The CE outputs six signals to the MPU: CE_BUSY, XFER_BUSY , XPULSE, YPULSE, WPULSE and VPULSE. These are connected to the MPU interrupt servic e. CE_B USY indicates that the CE is actively processing data. This signal occurs once every multiplexer frame. XFER_BUSY indicates that the CE is updating to the ou t put region of the CE RAM, whic h oc c urs whenever an accumulation cycle has been completed. Both, CE_BUSY and XFER_BUSY are cleared when the CE executes a HALT instruction.

XPULSE, YPULSE, VPULSE and WPULSE can be configured to interrupt the MP U and indic ate sag failures, zero crossings of the mains voltage, or other significant ev ents. Additionally, these signals can be connected direc tly to DIO pins to provide direct outputs f or the CE. Interrupt s associated with these signals always occur on t he leading edge (see “External” interrupt source No. 2 in Figure 16).

2.3.4 Meter Equations

The 71M6541D/F and 71M6542 F provide hardware as s istance to the CE in order to support var ious meter equations. This assistance is controlled through I/O RAM register EQU[2:0] (equation assist). The Compute Engine (CE) firmwa re fo r industrial configurat ions can im ple men t the equations listed in Table 8. EQU[2:0] specifies the equat ion to be used based on the meter configurati on and on the number of phases used for metering.

Table 8: Inputs Selected in Multiplexer Cycles

Wh and VARh formula Recommended

EQU

1-element, 2-W, 1φ with

neutral curr ent sense

1-element, 3-W, 1φ

2 †

Note:

† 71M6542F only

2-elem ent, 3-W, 3φ Delta

Description

Element 0 Element 1 Element 2

VA ∙ IA VA ∙ IB1 N/A IA VA IB1

VA(IA-IB)/2 N/A N/A IA VA IB

VA ∙ IA VB ∙ IB N/A I A VA IB VB

Multiplexer

Sequence

2.3.5 Real-Time Monit or (RTM)

The CE contains a Real-Time Monitor (RTM), which can be programm ed to monitor four selectable XRAM locations at full sample rate. The four monitored locati ons, as select ed by the I/O RAM registers RTM0[9:8], RTM0[ 7:0], RTM1[9:8], RTM1[7:0] , RTM2[ 9:8], RTM2[7:0], RTM3[9:8] , and RTM3[7:0], are serially output to the TMUXOUT pin via the digital output multiplexer at the beginning of each CE code pass. T he RTM c an be enabled and disabl ed with c o nt rol bit RTM_E (I/ O RAM 0x 2106[1] ). T he RTM output is clocked by CKTEST. Each RTM word is clocked out in 35 CKCE cycles (1 CKCE cycle is equivalent to 203 ns) and cont ains a leading flag bit. See Figure 10 for the RTM output format. RTM is low when not in use.

Figure 11 summariz es the timing relationships between the input MUX states, the CE_BUSY signal, and

the RTM serial output str eam . In this example, MUX_DIV[3:0] = 4 (I/O RAM 0x2100[7:4]) and FIR_LEN[1:0] = 10 ( I/O RAM 0x210C [1]), (384), resulting in 4 ADC conversi ons. A n ADC conver si on always consumes an integer num ber of CK32 cl oc k s. Followed by the conversions is a single CK 32 cycle.

Figure 11 also shows that the RTM serial data stream begins transmitting at the beginning of state S.

RTM, consisting of 140 CK cycl es, always f inishes before the next CE c ode pass starts.

CK32

MUX STATE

MUX_DIV Conversions, MUX_DIV=4 is shown

Settle

ADC MUX Frame

ADC EXECUTION

MUX_SYNC

CE_EXECUTION

RTM

140

MAX CK COUNT

0 450

150

900 1350 1800

ADC0 ADC1 ADC2 ADC3

CK COUNT = CE_CYCLES + 1CK for e ach ADC transfer

NOTES:

1. ALL DIMENSIONS ARE 5 MHZ CK COUNTS.

2. THE PRECISE FREQUENCY OF CK IS 150*CRYSTAL FREQUENCY = 4.9152MHz.

3. XFER_BUSY OCCURS ONCE EVERY SUM_SAMPS CODE PASSES.

CE_BUSY

XFER_BUSY

INITIATED BY A CE OPCODE AT END OF SUM INTERVAL

ADC TIMING

CE TIMING

RTM TIMING

1 2 3

CKTEST

RTM

FLAG

RTM DATA0 (32 bits)

LSB

SIGN

LSB

SIGN

RTM DATA1 (32 bits)

LSB

SIGN

RTM DATA2 (32 bits) RTM DATA3 (32 bits)

0 1 30 31 0 1 30 31

0 1

30 31 0 1 30 31

FLAG FLAG FLAG

MUX_STATE S

MUX_SYNC

CK32

Figure 10: R TM Timing

Figure 11: Timing relationship between ADC MUX, CE, and RTM Serial Transfer

2.3.6 Pulse Generators

The 71M6541D/F and 71M6542F provide four pulse generators, VPULSE, WPULSE, XPULSE and YPULSE, as well as hardware support for the VPULSE and WPULSE pulse generator s. The pulse generators can be used to output CE status indic ators, SAG for example, to DIO pins. All pul ses can be configured to generate inter r upts to the MPU.

The polarity of the pulses may be inverted with control bit PLS_INV (I/O RAM 0x2 10C[0]). When this bit is set, the pulses are active high, rather than the more usual active low. PLS_INV i nverts all the pulse output s.

The function of each pulse generator is determined by the CE code and t he MPU code m ust c onfigure the corresponding pulse outputs in agreement with the CE code. For example, s tandard CE code produces a mains zero-crossing pulse on XPULSE and a SAG pulse on YPULSE.

A common use of the zero-crossing pulses is to generate interrupt in order to drive real-time clock software in places where the mai ns fr equenc y is sufficiently accurate to do so and also to adjust for crystal aging. A common use for the SAG pulse is to generate an interrupt that alerts the MPU when mains power is about to fail, so that the MPU code can stor e ac c um ulated energy and other data to EEPROM before t he V3P3SYS supply voltage actually dr ops.

2.3.6.1 XPULSE and YPULSE

Pulses generated by the CE may be ex ported to the XPULSE and YPULSE pulse output pins. Pin s SEGDIO6 and SEGDIO7 are used for these pulses, respectively. Generally, the XPULSE and YPULSE outputs can be updated once o n each pa s s of the CE code.

See 5.3 CE Interface Description on page 125 for detail s.

2.3.6.2 VPULSE and WP U LSE

Referring to Figure 12, duri ng each CE code pa s s the hardware stores export ed WPULSE and VPULSE sign bits in an 8-bit FIFO and outputs them at a specified interval. This permits the CE code to calculate the VPULSE and WPULSE outputs at the beginning of its code pass and to rely on hardware to spread them over the multiplexer frame. As seen in Figure 12, the FIFO is reset at the beginning of each m ultiplexer frame. As also seen in Figure 12, the I/O RAM register PLS_INTERVAL[7:0] (I/O RAM 0x210B[7:0]) controls the delay to th e first puls e update and t he interv al between subs equent updat es. The LSB of the PLS_INTERVAL[7:0] register is equivalent to 4 CK_FIR cycles (CK_FIR is typically 4.9152MHz if PLL_FAST=1 and ADC_DIV=0, but other CK_FIR frequencies are possible; see the ADC_DIV definition in

Table 76.) If PLS_INTERVAL[7:0]=0, the FIFO is deactivated and the pulse outputs are updated immediately.

The MUX frame duration in units of CK_FIR clock cycles is given by: If PLL_FAST=1:

MUX frame dur ati on in C K_FI R c y cles = [1 + (FIR_LEN+1) * (ADC_DIV+1) * (MUX_DIV)] * [150 / (ADC_DIV+1)]

If PLL_FAST=0:

MUX frame dur ati on in C K_FI R c y cles = [3 + 3* (FIR_LEN+1) * (ADC_DIV+1) * (MUX_DIV)] * [48 / (ADC_DIV+1)]

PLS_INTERVAL[7:0] in units of CK_FI R clock cyc les i s calc ulated by:

PLS_INTERVAL[7:0] = floor (Mux frame duration in CK_F IR cyc les / CE pulse u pdat es per Mux frame / 4 )

Since the FIFO resets at t he beginning of each multiplexer frame, t he user must specify PLS_INTERVAL[7:0] so that all of the possible pulse updates occurri ng in one CE execution are output

the multiplexer f rame complet es. For instance, the 71M654x CE code outputs six updates per

before multiplexer int erval, and if the multiplexer interval is 1950 CK_FIR clock cycles long, the ideal value for the interv al is 1950/6/4 = 81.25. However, if PLS_INTERVAL[7:0] = 82, the sixth out put occ urs too late and would be lost. In this case, the proper value for PLS_INTERVAL[7:0] is 81 (i.e., round down the result).

Since one LSB of PLS_INTERVAL[7:0] is eq ual to 4 CK_FIR clock cycles, the p ulse t i me in terval TI in u nit s of CK_FIR clock cycle s is:

= 4*PLS_INTERVAL[7:0]

CK32

MUX_DIV Conversions (MUX_DIV=4 is shown)

Settle

ADC MUX Frame

MUX_SYNC

150

WPULSE

S0S

2S3

CE CODE

RST

W_FIFO

4*PLS_INTERVAL

2. If WPULSE is low longer than (2*PLS_MAXWIDTH+1) updates, WPULSE will be raised until the next low-going pulse begins.

3. Only the WPULSE circuit is shown. The VARPULSE circuit behaves identically.

4. All dimensions are in CK_FIR cycles (4.92MHz).

5. If PLS_INTERVAL=0, FIFO does not perform delay.

4*PLS_INTERVAL

1. This example shows how the FIFO distributes 6 pulse generator updates over one MUX frame.

If the FIFO is enab led (i.e ., PLS_INTERVAL[7:0] ≠ 0), hardware also provides a maximum pulse width feature in control register PLS_MAXWIDTH[7:0] (I/O RAM 0x210A) . By default, WPULSE and VPULSE are negative pulses ( i. e . , low level pu lses, designed to s ink c ur r ent through an LED) . PLS_MAXWIDTH[7:0] determines the maximum negative pul se wi dt h T

in uni t s of CK_FI R cl oc k cy cl es bas ed on t he p ul s e interv al TI

MAX

accordi ng to the form ula:

= (2 * PLS_MAXWIDTH[7:0] + 1) * TI

MAX

If PLS_MAXWIDTH = 255 or PLS_INTERVAL=0, no pulse width checking is perf ormed, and the pulses default to 50% duty cycl e. T

is typicall y program m ed to 10 ms., which works well with most cali br ation

MAX

systems. The polarity of the pulses may be inverted with the control bit PLS_INV (I/O RAM 0x210C[0]). When

PLS_INV is set, the pulses are active high. The default value for PLS_INV is zero, which selects active low pulses.

The WPULSE and VPULSE pulse generator outputs are available on pins SEG DIO 0/W P ULSE and SEGDIO1/VPULSE, respect ively (pins 45 and 44). The pulses can also be output on OPT_TX pin 53 (see OPT_TXE[1:0], I/O RAM 0x2456[3:2] for details).

Figure 12. Pu ls e Ge ne r a tor FIFO Timing

2.3.7 CE Functional Overview

The 71M654x provi des an ADC and multiplexer to sample the analog curr ent s and voltages as seen in

Figure 2 and Figure 3. The VA and VB voltage sensors ar e formed by resistive voltage dividers directly

connected to the 71M 654x dev ic e, and t her efore always use the ADC and multiplexer facilities in the 71M654x device. Cur r ent sensors, however, may be connected dir ec tly to the 71M654x or remotely connected through an isolated 71M6x01 device. The remote 71M6x01 sensor has its own separate ADC and voltage ref er enc e. W hen a current sensor is connected via a 71M6x01 isolated sensor, the 71M654x places the sampl e data rec eiv ed digitally over the isolation interface (via t he pulse transformer) in the appropriate CE RAM location, as shown in Figure 3. The ADCs (i.e., ADC in the 71M 654x and the ADC in the 71M6x01) process their corresponding sensor channels providing one sample per channel per multiplexer cycle.

Figure 14 (71M6541D/F) and Figure 15 (71M6542F) show the sampli ng sequence when both curr ent

XFER_BUSY

Interrupt to MPU

20ms

833ms

channel is a 71M6x01 isolated sensor, the sample data does not pass through the 71M6541D/F multiplexer, as seen in Figure 3. In this case, the sample i s tak en duri ng the second half of the multipl ex er cycle and the data is dir ectly stor ed in the corresponding CE RAM loc ation as indicated in Figure 3. The timing relati onshi p between the remote current sensor c hannel and its corresponding voltage is precisely defined so that delay c om pensation can be properly appli ed by the CE.

Referring to Figure 15, the 71M6542F feat ur es an additional voltage input (VB) permitting the implementati on of a t wo-phase met er . As with VA, the VB voltage divider is directly connect ed to the 71M6542F and uses the ADC and multi plexer faciliti es in the 71M6542F. MUX_DIV[3:0] = 4 configures the multiplex er to pr ov ide an additional time slot to accommodate the additional VB voltage sam ple. As with the 71M6541D/F , IA sam ples are obt ained from a current sensor that i s di r ectly connected to the 71M6542F, while IB samples may be obtained from a directly connected CT or a remotely connected shunt using a 71M6x01 isolated device as seen in Figure 2 and Figure 3.

The number of samp les pro ces s ed dur ing one ac cu mu lation cycle is con tro lled by the I/ O RAM register

SUM_SAMPS[12:0] (I/O RAM 0x2107[4:0], 0x2108[7:0]). The integration time for each energy output is:

SUM_SAMPS / 2520.6, where 2520.6 is the sample rate in Hz

For exam ple, SUM_SAMPS = 2100 establishes 2100 samples per accumul ation cycle, wh ich has a duration of 833 ms. After an accum ulation cycle is completed, the XFER_B US Y i nterr upt signals to the MPU that accumulated data are available.

The end of each multiplexer cycle is signaled to the MPU by the CE_BUSY interrupt. At the end of each multiplexer cycle, status information, such as sag data and the digitized input signal, is available to the MPU.

Figure 13 shows the accum ulation interval r esul ting from SUM_SAMPS = 2100, consisti ng of 2100

samples of 397 µs each, followed by the XFER_BUSY interrupt. The sampling in this example is appli ed to a 50 Hz signal. There is no correlation between the line signal frequenc y and the choice of SUM_SAMPS. Furthermore, sampling does not have to start when the li ne v oltage crosses the zero line, and the length of the accumulation interval need not be an integer multiple of the signal cycles.

Figure 13: Accumulation Interval

MUX STATE

CK32

(32768 Hz)

0 1 2

MUX_DIV[3:0] = 3 Conversions

Settle

Multiplexer Frame (13 x 30.518 µs = 396.7 µs -> 2520.6 Hz)

30.5 µs

122.07 µs

122.07 µs 122.07 µs

MUX STATE

CK32

(32768 Hz)

0 31 2

MUX_DIV[3:0] = 4 Conversions

Settle

Multiplexer Frame (13 x 30.518 µs = 396 µs à2520Hz)

30.5 µs

91.5 µs

91.5 µs 91.5 µs

91.5 µs

Figure 14: Samples from Multiplexer Cycle (MUX_DIV[3:0] = 3)

Figure 15: Samples from Multiplexer Cycle (MUX_DIV[3:0] = 4)

+ 132 hidden pages