Rainbow Electronics Т7024 User Manual

Features

• Single 3-V Supply Voltage

• High Power-added Efficient Power Amplifier (P

• Ramp-controlled Output Power

• Low-noise Preamplifier (NF Typically 2.1 dB)

• Biasing for External PIN Diode T/R Switch

• Current-saving Standby Mode

• Few External Components

• PSSO20 Plastic Package with Down-set Padd le Heat Slug or HP-VFQFP-N20 with

Extended Performance and Flipchip Version

Electrostatic sensiti ve device. Observe precautions for handling.

Typically 23 dBm)

out

Bluetooth™/ISM

2.4-GHz FrontEnd IC

T7024

Description

The T7024 is a monolithic SiGe transmit/receive front-end IC with power amplifier, low-noise amplifier and T/R switch driver. It is especially designed for operation in TDMA systems like Bluetooth

™

, DECT, and many other IS M app li ca tio ns acc ordi ng to

FCC part 15. Due to the ramp-control feature and a very low quiescent current, an exter nal switch

transistor for V

is not required.

S

Figure 1. Block Diagram

T U

N

U P

TX/RX/ standby control

TX

O _

O _ X

R

D

A

N

N L

G

LNA

A

N

I

P

_

A

1

P

V

A

P

D

_

N

2

G

V

PA

P

M

_

A

2

R

V

SiGe Front End

T7024

Preliminary

H C

T

I W

S _

R

D

T

N

U

G

O _

H C T

I W

S

A

N

I

N

_

L

A

_

N

S

L

V

T

D

U

N

O

G

_ A P _ 3 V

T

T U O

_ A P _ 3 V

D

U

N

O

G

_ A P _ 3 V

Rev. 4533A–BLURF–09/02

1

Pin Configuration

Figure 2. Pinning PSSO20 Figure 3. Pinning HP-VFQFP-N20

20

19

18

17

16

15

14

13

12

11

RX_ON

LNA_OUT

GND

PA_IN

V1_PA

GND

V2_PA

RAMP

GND

10

1

2

3

4

5

T7024

6

7

8

9

R_SWITCH PU

SWITCH_OUT

LNA_IN

VS_LNA

V3_PA_OUT

Pin Description

Pins PSSO20 Pins N20 Symbol Function

1 4 R_SWITCH Resistor to GND sets the PIN diode current 2 5 SWITCH_OUT Switched current output for PIN diode 36GNDGround 4 7 LNA_IN Low-noise am plifier input 5 9 VS_LNA Supply voltage input for low-noise amplifier 68GNDGround 7 11 V3_PA_OUT Inductor to power supply and matching network for power amplifier output 8 12 V3_PA_OUT Inductor to power supply and matching network for power amplifier output

9 13 V3_PA_OUT Inductor to power supply and matching network for power amplifier output 10 10 GND Ground 11 15 RAMP Power ramping control input 12 16 V2_PA Inductor t o power supply for power amplifie r 13 17 V2_PA Inductor t o power supply for power amplifie r 14 14 GND Ground 15 19 V1_PA Supply voltage for power amplifier 16 20 PA_IN Power amplifier input 17 18 gnd Ground 18 1 LNA_OUT Low-noise amplifier output 19 2 RX_ON RX ac tive high 20 3 PU Power-up active high

Slug Slug GND Ground

V3_PA_OUT V3_PA_OUT V3_PA_OUT

GND

RAMP

D N G

10 6789 11 12 13

T7024

14 15

16 2019

17

A P _ 2 V

A

N

I

N

_

L _ S V

A P _ 2 V

D

A

N

G

L

G

5

SWITCH_OUT

4

R_SWITCH

3

PU

2

RX_ON

1

A P _ 1 V

N

I _ A P

LNA_OUT

18

D N G

2

T7024

4533A–BLURF–09/02

Figure 4. Pad Location, Thickness: 450 µm

T7024

3180 µm

19

LNA_OUT

m

µ 0

0

6

1

20

12

R_SWITCH SWITCH_OUT

3

GND LNA_IN GND

18

21

17

PURX_ON

16

15

14

GNDGNDV1_PAPA_INGND

Pad diameter 180 µm Ball diameter 200 µm

4

56 7

VS_LNA

GND GND V3_PA_OUT

8

13

V2_PA

9

12

RAMP

11

GND

10

GND

Pad Description

X-Coordinate of

Pad Symbol Function

Pad

(1)

(µm)

1 R_SWITCH Resistor to GND sets the PIN diode current 0 400 2 SWITCH_OUT Switched current output for PIN diode 400 400 3 GND Ground 0 0 4 LNA_IN Low-noise amplifier input 400 0 5 GND Ground 800 0 6 VS_LN A Supply volta ge input for low-noise amplifier 1200 0 7 GND Ground 1600 0 8 GND Ground 2000 0 9 V3_PA_OUT Inductor to power supply and matching network for

2400 0

power amplifier output 10 GND Ground 2780 150 11 GND Ground 2780 550 12 RAMP Power ramping control input 2780 950 13 V2_PA Inductor to power supply for power amplifier 2450 1200 14 GND Ground 2050 1200 15 GND Ground 1650 1200 16 V1_PA Supply voltage for power amplifier 1250 1200 17 PA_IN Power amplifier input 850 1200 18 GND Ground 400 1200 19 LNA_OUT Low-noise amplifier output 0 1200 20 RX_ON RX active high 0 800 21 PU Power-up active high 400 800

Note: 1. Relative to center of Pad 3.

Y-Coordinate of

Pad

(1)

(µm)

4533A–BLURF–09/02

3

Absolute Maximum Ratings

Parameters Symbol Value Unit

Supply voltage

V

S

6V

Pins VS_LNA, V1_PA, V2_PA, V3_PA_OUT Junction tem p erature T Storage temperature T RF input power LNA P RF input power PA P

j

stg

inLNA

inPA

150 °C

-40 to +125 °C 5dBm

10 dBm

Thermal Resistance

Parameters Symbol Value Unit

Junction ambient PSSOP20, slug soldered on PCB R Junction ambient HP-VFQFP-N20, slug soldered on PCB R

thJA thJA

19 K/W 27 K/W

Operating Range

All voltages are referred to ground (Pins GND and slug). Power supply points are VS_LNA, V1_PA, V2_PA, V3_PA_OUT. The table represents the sum of all supply currents depending on the TX/RX mode.

Parameters Symbol Min. Typ. Max. Unit

Supply voltage Pins V1_PA, V2_PA and

V3_PA_OUT Supply voltage Pin VS_LNA V Supply current TX PSSO20

N20

RX Standby current PU = 0 I Ambient temperature T

V

S

I

S

I

S

I

S

S_standby

amb

2.7 3.0 4.6 V

2.7 3.0 5.5 V 190

165

8

mA mA mA

10 µA

-25 +25 +70 °C

4

T7024

4533A–BLURF–09/02

Electrical Characteristics

T7024

Test conditions (unless otherwise specified): VS = 3.0 V, T

Parameters Test Condit ions Power Amplifier

Supply voltage Pins V1_PA, V2_PA, V3_PA_OUT V Supply current TX PSSO20

Standby curren t Standby I

(1)

N20

RX (PA off), V

£ 0.1 V I

RAMP

amb

= 25°C

Symbol Min. Typ. Max. Unit

S

I

S_TX

I

S_TX S_RX

S_standby

2.7 3.0 4.6 V 190

165

mA

mA 10 µA 10 µA

Frequency range TX f 2.4 2.5 GHz Gain-control ra nge TX

DGp 60 42 dB

Power gain maximum TX, Pin PA_IN to V3_PA_OUT Gp 28 30 33 dB Power gain minimum TX, Pin PA_IN to V3_PA_OUT Gp -40 -17 dB Ramping voltage maximum TX, power gain (maximum)

Pin RAMP

Ramping v o ltage minimum TX, power gain (minimum)

Pin RAMP

Ramping current maximum TX, V

= 1.75 V, Pin RAMP I

RAMP

Power-added efficiency TX PSSO20

N20

Saturated output power TX, input power = 0 dBm referred to

Pins V3_PA_OUT

Input matching

Output matching

(2)

TX, Pin PA_IN Load

TX, Pins V3_PA_OUT Load

V

RAMP max

V

RAMP min

RAMP max

PAE PAE

P

sat

VSWR

1.7 1.75 1.83 V

0.1 V

0.5 mA

30 35

35 40

22.0 23 24.0 dBm

<1.5:1

Harmonics at P 1dBCP TX, Pins V3_P A_OUT 2 fo -30 dBc

TX, Pins V3_PA_OUT 3 fo -30 dBc

T/R Switch Driver (Current Programming by External Resistor from R_SWITCH to GND)

Switch-out current output Standby, Pin SWITCH_OUT I

RX I

W I

¥ I

Low-noise Amplifier

TX at 100 TX at 1.2 k TX at 33 k TX at

(3)

S_O_standby

S_O_RX S_O_100 S_O_1k2 S_O_33k

S_O_R

Supply voltage All, Pin VS_LNA V Supply current RX I Supply current

(LNA and control logic)

TX (control logic active) Pin VS_LNA

1.7 mA 7mA

17 mA 19 mA

S

I

S

2.7 3.0 5.5 V 89mA

1µA 1µA

0.5 mA

Notes: 1. Power amplifier shall be unconditionally stable, maximum duty cycle 100%, true CW operation, maximum load mismatch

and duration: load VSWR = 10:1 (all phases) 10 s, Z

2. With external matching network, load impedance 50

= 50 W.

C

W.

3. Low-noise amplifier shall be unconditionally stable.

4. With external matching components.

% %

4533A–BLURF–09/02

5

Electrical Characteristics (Continued)

Test conditions (unless otherwise specified): VS = 3.0 V, T

Parameters Test Condit ions

Standby curren t Standby, Pin VS_LNA I

amb

= 25°C

Symbol Min. Typ. Max. Unit

S_standby

110µA

Frequency range RX f 2.4 2.5 GHz Power gain RX, Pin LNA_IN to LNA_OUT Gp 15 16 19 dB Noise figure RX, PSSO20

N20

Gain compression RX,

referred to PinLNA_OUT

rd

-order input interception point RX IIP3 -16 -14 -13 dBm

3 Input matching Output matching

(4)

RX, Pin LNA_IN VSWRin 2:1 RX Pin LNA_OUT VSWRout 2:1

NF NF

2.5

2.1

2.8

2.3

dB

O1dB -9 -7 -6 dBm

Logic input levels (RX_ON, PU)

High input level = ‘1’ Pins RX_ON and PU V Low input level = ‘0’ V High input current = ‘1’ V

= 2.4 V I

iH

Low input current = ‘0’ I

iH

iL iH iL

2.4 V

S, LNA

00.5V 40 60 µA

0.2 µA

Notes: 1. Power amplifier shall be unconditionally stable, maximum duty cycle 100%, true CW operation, maximum load mismatch

and duration: load VSWR = 10:1 (all phases) 10 s, Z

2. With external matching network, load impedance 50

= 50 W.

C

W.

3. Low-noise amplifier shall be unconditionally stable.

4. With external matching components.

V

Control Logic for LNA and T/R Switch Driver

Operation Mode PU RX_ON

Standby 0 0

TX 1 0 RX 1 1

6

T7024

4533A–BLURF–09/02