Rainbow Electronics Т7023 User Manual

Features

• Single 3-V Supply Voltage

• High Power-added Efficient Power Amplifier (P

• Ramp-controlled Output Power

• Current-saving Standby Mode

• Few External Components

• HP-VFQFP-N16 Package

Electrostatic sensiti ve device.
Observe precautions for handling.

Description

Typically 23 dBm)

out

ISM/Bluetooth™

2.4-GHz Power
Amplifier

The T7023 is a monolithic SiGe power amplifier. It is especially designed for operation
in TDMA systems like Bluetooth, DECT , and many other ISM applications according to
FCC part 15.

Due to the ramp-control feature and a very low quiescent current, an exter nal switch
transistor for V

is not required.

S

Figure 1. Block Diagram

GND

PA_IN

GND

A
P

_

1
V

D
N
G

A
P

_

2
V

A
P

_

2
V

GND

Ramp

GND

SiGe PA

GND

T7023

GND

T7023

Preliminary

D
N
G

T
U
O

_
A
P

_

3
V

T
U
O

_
A
P

_

3
V

T
U
O

_
A
P

_

3
V

Rev. 4532A–BLURF–09/02

1

Pin Configuration

Figure 2. Pinning HP-VFQFP-N16

T

T

T

U

U

U

O

O

O

_

_

_

A

A

A

P

P

P

D

_

_

N

3

3

V

V

G

GND

4

GND

3

PA_IN

2

GND

1

A

A

D

P

P

N

_

_

G

1

2

V

V

GND

GND

Ramp

GND

_
3

V

8 7 6 5

9

10

11
12

13 14 15 16

A
P
_
2
V

Pin Description

Pin Symbol Function

1 GND Ground
2 PA_IN Power amplifier input
3 GND Ground
4 GND Ground
5 GND Ground
6 V3_PA _OUT Inductor to power supply and matching network for power amplifier output
7 V3_PA _OUT Inductor to power supply and matching network for power amplifier output
8 V3_PA _OUT Inductor to power supply and matching network for power amplifier output

9 GND Ground
10 GND Ground
11 RAMP Power ramping control input
12 GND Ground
13 V2_PA Inductor to power supply for power amplifier
14 V2_PA Inductor to power supply for power amplifier
15 GND Ground
16 V1_PA Supply voltage for power amplifier

Slug GND Ground

2

T7023

4532A–BLURF–09/02

Absolute Maximum Ratings

All voltages are referred to ground (Pins GND and slug), no RF

Parameters Symbol Value Unit

Supply voltage

Pins V1_PA, V2_PA and V3_PA_OUT
Junction temperature T
Storage temperature T
RF input power PA P

V

S

j

stg

inPA

6V

150 °C

-40 to +125 °C
10 dBm dBm

Thermal Resistance

Parameters Symbol Value Unit

Junction ambient HP-VFQFP-N16 R

thJA

TBD K/W

T7023

Operating Range

All voltages are referred to ground (Pins GND and slug). Power supply points are V1_PA, V2_PA, V3_PA_OUT.
The following table represents the sum of all supply currents depending on the TX mode.

Parameters Symbol Min. Typ. Max. Unit

Supply voltage Pins V1_PA, V2_PA and

V3_PA_OUT
Supply current I
Standby current I
Ambient temperature T

S_standby

V

amb

S

S

2.7 3.0 4.6 V
165 mA

10 µA

-25 +25 +70 °C

4532A–BLURF–09/02

3

Electrical Characteristics

Test conditions (unless otherwise specified): VS = 3.0 V, T

amb

= 25°C

Parameters Test Condit ions Symbol Min. Typ. Max. Unit
Power Amplifier

Supply voltage Pins V1_PA, V2_PA and

Supply current TX I

(1)

V3_PA_OUT

RX (PA off), V

³ 0.1 V I

RAMP

Standby I

V

S

S_TX
S_RX

S_standby

2.7 3.0 4.6 V
165 mA

10 µA

10 µA
Frequency range TX f 2.4 2.5 GHz
Gain-control range TX DGp 60 42 dB
Power gain maximum TX

Pin PA_IN to V3_PA_ OUT

Power gain minimum TX

Pin PA_IN to V3_PA_ OUT

Ramping voltage maximum TX, power gain (maximum)

Pin RAMP

Ramping voltage minimum TX, power gain (minimum)

Pin RAMP

Gp 28 30 33 dB

Gp -40 -17 dB

V

RAMP max

V

RAMP min

1.7 1.75 1.83 V

0.1 V

Ramping current maximum V = 1.75 V 0.5 mA
Power-added efficiency TX PAE 35 42 %
Saturated output power TX, input power = 0 dBm

referred to Pins V3_PA_OUT
Input matching
Output matching
Harmonics

= 23 dBm

at P

sat

Harmonics
at P

= 23 dBm

sat

(2)

(2)

TX, Pin PA_IN Load VSWR <1.5:1

TX, Pin V3_PA_OUT Load VSWR <1.5:1

TX, Pin V3_PA_OUT

TX, Pin V3_PA_OUT

P

2 f

3 f

sat

o

o

22.5 23 23.5 dBm

-30 dBc

-30 dBc

Notes: 1. Power amplifier shall be unconditionally stable, maximum duty cycle 100%, true CW operation, maximum load mismatch

and duration: VSWR 10:1 (all phases) 10 s, Z

= 50 W.

G

2. With external matching network, load impedance 50 W

4

T7023

4532A–BLURF–09/02

Typical Operating Characteristics

Figure 3. Output Power and PAE versus Supply Voltage

T7023

50

Pout (dBm), PAE (%)

40

30

20

10

0

PAE

I_S_TX

2.7 3.1 3.5 3 .9 4.3 4.7

Supply Voltage (MHz)

Figure 4. Output Power and PAE versus Frequency

50

PAE

Pout

I_S_TX

V

ramp

P

inPA

VS = 3 V

Pout (dBm), PAE (%)

40

30

20

10

f = 2.4 GHz

V

ramp

P

inPA

= 1.8 V

= 0 dBm

= 1.8 V

= 0 dBm

Pout

250

200

150

100

50

250

220

190

160

I_S_TX (mA)

130

100

I_S_TX (mA)

4532A–BLURF–09/02

0

2400 2420 2440 2460 2480 2500

Frequency (MHz)

Figure 5. Output Power and PAE versus Ramp Voltage

50

30

10

-10

Pout (dBm), PAE (%)

-30

-50

1.2 1.4 1.6 1.8 2.0

PAE

I_S_TX

f = 2.4 GHz

V

= 3 V

S

P

= 0 dBm

inPA

V

(V)

ramp

Pout

0

250

200

150

100

I_S_TX (mA)

50

0

5

Figure 6. Output Power and PAE versus Input Power

Figure 7. P

50

40

30

20

10

0

Pout (dBm), PAE (%), Gp (dB)

-10

-40 -30 -20 -10 0 10

Gain

I_S_TX

Pout

VS = 3 V

f = 2.4 GHz

V

= 1.8 V

ramp

P

= 0 dBm

inPA

Input Power (dBm)

versus V

out

30

20

10

Pout ( dBm )

and Temperature

ramp

f = 2.4 GHz

= 3 V

V

S

= 0 dBm

P

in

0

80

5

25

300

PAE

-15

250

200

150

100

50

0

I_S_TX (mA)

-10

-20

1.0 1.2 1.4 1.6 1.8

Figure 8. Output Power versus V

30

25

20

15

10

5
0

-5

Output Power ( dBm )

-10

-15

-20

0.1 1.0 10.0 100.0 1000.0

Ramp

-40°C

0°C

V

ramp

Current

V

current ( µA )

ramp

-40°C

( V )

40°C

80°C

6

T7023

4532A–BLURF–09/02

T7023

Input/Output Circuits

Figure 9. I versus V

200

180
160
140
120
100

80

I ( dBm )

60
40
20

0

Current

Ramp

0.1 1.0 10.0 100.0 1000.0

V

ramp

Figure 10. Input Circuit PA_IN/V1_PA

V1_PA

-40°C

0°C

current ( µA )

40°C

80°C

PA_IN

GND

Figure 11. Input Circuit RAMP/V1_PA

V1_PA

RAMP

4532A–BLURF–09/02

7

Figure 12. Input Circuit V2_PA

V2_PA

GND

Figure 13. Input/Output Circuit V3_PA_OUT

V3_PA_OUT

GND

8

T7023

4532A–BLURF–09/02

Figure 14. Application Board Schematic

T7023

PA ramp

V2_PA

PA OUT

1µ

1n1µ 10p

5p6

1p5

56p

V3_PA

15nH

harm. termination

8 7 6 5

9
10
11
12

13 14 15 16

4
3
2
1

5p6

1p5

15p1n

3p3

V1_PA

1µ

1n

PAin

15p

blocking capacitor
depending on application

4532A–BLURF–09/02

9

Figure 15. Application Board Layout

0R

1.5pF

5.6pF

15pF

3.3pF
hQ

56pF

1.5pF hQ
15nH hQ

5.6pF hQ

1µF1nF

1µF1nF15pF

1µF1nF10pF

Gerberfiles are available on request.
The application board consists of 4 layers:

1. top layer: RF-signals, 35 µm Cu

2. spacing: 490 µm FR4

3. second layer: GND, 35 µm Cu

4. spacing: 550 µm FR4

5. third layer: GND (optional), 35 µm Cu

6. spacing: 490 µm FR4

7. bottom layer: DC connection, 35 µm Cu

10

T7023

4532A–BLURF–09/02

Ordering Information

Extended Type Numb er Package Remarks

T7023-PES HP-VFQFP-N16 Tube
T7023-PEQ HP-VFQFP-N16 Taped and reeled

Package Information

T7023

4532A–BLURF–09/02

11

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© Atmel Corporation 2002.

Atmel Corporation makes no warranty for the use of its products, other than those expressly contained in the Company’s standard warranty
which is detailed in Atmel’s Terms and Conditions located on the Company’s web site. The Company assumes no responsibility for any errors
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Printed on recycled paper.

4532A–BLURF–09/02

xM