Rainbow Electronics АТ89С51 User Manual

Features

• Compatible with MCS-51

• 4K Bytes of In-System Programmable (ISP) Flash Memory

– Endurance: 1000 Write/Erase Cycles

• 4.0V to 5.5V Operating Range

• Fully Static Operation: 0 Hz to 33 MHz

• Three-level Program Memory Lock

• 128 x 8-bit Internal RAM

• 32 Programmable I/O Lines

• Two 16-bit Timer/Counters

• Six Interrupt Sources

• Full Duplex UART Serial Channel

• Low-power Idle and Power-do wn Mode s

• Interrupt Recovery from Power-do wn Mode

• Watchdog Timer

• Dual Data Pointer

• Power-off Flag

• Fast Programming Time

• Flexible ISP Programming (Byte and Page Mo de)

®

Products

8-bit
Microcontroller
with 4K Bytes
In-System
Programmable

Description

The AT89S51 is a low-power, high-performance CMOS 8-bit microcontroller with 4K
bytes of in-system programmable Flash memory. The device is manufactured using
Atmel’s high-densit y nonvolatile me mory technology and is com pati ble with t he i ndu s­try-standard 80C51 instruction set and pinout. The on-chip Flash allows the program
memory to be reprogrammed in-syst em or by a conventional n onvolatile memory pro­grammer. By combining a versatile 8-bit CPU with in-system programmable Flash on a
monolithic chip, the Atmel AT89S51 is a powerful microcontroller which provides a
highly-flexible and cost-effective solution to many embedded control applications.

The AT89S51 provides the following standard features: 4K bytes of Flash, 128 bytes of
RAM, 32 I/O lines, Watchdog timer, two data pointers, two 16-bit timer/counters, a five­vector two-level interrupt architecture, a full duplex serial port, on-chip oscillator, and
clock circuitry. In addition, the AT89S51 is designed with static logic for operation
down to zero frequency and supports two software selectable power saving modes.
The Idle Mode stops the CPU while allowing the RAM, timer/counters, serial port, and
interrupt syste m to continue fu nctioni ng. The Power-down mode saves the RAM con­tents but freezes the oscillator, disabling all other c hi p fu nctions until the next external
interrupt or hardware reset.

Flash

AT89S51

Rev. 2487A–10/01

1

Pin Configurations

PDIP

PLCC

(MOSI) P1.5
(MISO) P1.6

(SCK) P1.7

RST

(RXD) P3.0

NC

(TXD) P3.1
(INT0) P3.2
(INT1) P3.3

(T0) P3.4
(T1) P3.5

1

P1.0

2

P1.1

3

P1.2

4

P1.3

5

P1.4

RST

XTAL2
XTAL1

GND

6
7
8
9
10
11
12
13
14
15
16
17
18
19
20

(MOSI) P1.5
(MISO) P1.6

(SCK) P1.7

(RXD) P3.0

(TXD) P3.1
(INT0) P3.2
(INT1) P3.3

(T0) P3.4
(T1) P3.5

(WR) P3.6

(RD) P3.7

TQFP

P1.4

P1.3

P1.2

P1.1

P1.0 NCVCC

4443424140393837363534

1
2
3
4
5
6
7
8
9
10
11

1213141516171819202122

40
39
38
37
36
35
34
33
32
31
30
29
28
27
26
25
24
23
22
21

P0.0 (AD0)

VCC
P0.0 (AD0)
P0.1 (AD1)
P0.2 (AD2)
P0.3 (AD3)
P0.4 (AD4)
P0.5 (AD5)
P0.6 (AD6)
P0.7 (AD7)
EA/VPP
ALE/PROG
PSEN
P2.7 (A15)
P2.6 (A14)
P2.5 (A13)
P2.4 (A12)
P2.3 (A11)
P2.2 (A10)
P2.1 (A9)
P2.0 (A8)

P0.1 (AD1)

P0.2 (AD2)

P0.3 (AD3)

33
32
31
30
29
28
27
26
25
24
23

P0.4 (AD4)
P0.5 (AD5)
P0.6 (AD6)
P0.7 (AD7)
EA/VPP
NC
ALE/PROG
PSEN
P2.7 (A15)
P2.6 (A14)
P2.5 (A13)

(MOSI) P1.5
(MISO) P1.6

(SCK) P1.7

RST

(RXD) P3.0

NC

(TXD) P3.1
(INT0) P3.2
(INT1) P3.3

(T0) P3.4
(T1) P3.5

P1.4

P1.3

P1.2

P1.1

P1.0 NCVCC

P0.0 (AD0)

65432

7
8
9
10
11
12
13
14
15
16
17

1819202122232425262728

(RD) P3.7

(WR) P3.6

XTAL2

XTAL1

GND

1

NC

4443424140

(A8) P2.0

(A9) P2.1

P0.1 (AD1)

P0.2 (AD2)

P0.3 (AD3)

39
38
37
36
35
34
33
32
31
30
29

(A10) P2.2

(A11) P2.3

(A12) P2.4

P0.4 (AD4)
P0.5 (AD5)
P0.6 (AD6)
P0.7 (AD7)
EA/VPP
NC
ALE/PROG
PSEN
P2.7 (A15)
P2.6 (A14)
P2.5 (A13)

GND

GND

XTAL2

XTAL1

(A8) P2.0

(RD) P3.7

(WR) P3.6

2

AT89S51

(A9) P2.1

(A10) P2.2

(A11) P2.3

(A12) P2.4

2487A–10/01

Block Diagram

AT89S51

V

CC

GND

B

REGISTER

RAM ADDR.

REGISTER

P0.0 - P0.7

PORT 0 DRIVERS

RAM

ACC

TMP2 TMP1

PORT 0

LATCH

P2.0 - P2.7

PORT 2 DRIVERS

PORT 2

LATCH

STACK

POINTER

FLASH

PROGRAM

ADDRESS

REGISTER

BUFFER

PSEN

ALE/PROG

EA / V

RST

PC

ALU

INTERRUPT, SERIAL PORT,

AND TIMER BLOCKS

PSW

TIMING

AND

PP

CONTROL

OSC

INSTRUCTION

REGISTER

WATCH

DOG

PORT 3

LATCH

PORT 3 DRIVERS

P3.0 - P3.7

PORT 1

LATCH

PORT 1 DRIVERS

P1.0 - P1.7

ISP

PORT

INCREMENTER

PROGRAM

COUNTER

DUAL DPTR

PROGRAM

LOGIC

2487A–10/01

3

Pin Description

VCC Supply voltage. GND Ground. Po rt 0 Port 0 is an 8-bit open drain bidirectional I/O port. As an output port, each pin can sink eight

TTL inputs. When 1s are written to port 0 pins, the pins can be used as high-imped ance
inputs.

Port 0 can also be configured to be the multiplexed low-order address/data bus during
accesses to external program and data memory. In this mode, P0 has internal pull-ups.

Port 0 also recei ves the cod e bytes dur ing Flash pr ogramming and output s the code b ytes
during program verification. External pull-ups are required during program verification.

Po rt 1 Port 1 is an 8-bit bidirectional I/O port with internal pull-ups. The Port 1 output buffers can

sink/source four TTL in puts. When 1s are writte n to Port 1 pins, they a re pulled hig h by the
internal pull-ups and can be u sed as inputs . As inputs, Port 1 p ins that ar e extern ally being
pulled low will source current (I

Port 1 also receives the low-order address bytes during Flash programming and verification.

Port Pin Alternate Functions

) because of the internal pull-ups.

IL

P1.5 MOSI (used for In-System Programming)
P1.6 MISO (used for In-System Programming)
P1.7 SCK (used for In-System Programming)

Po rt 2 Port 2 is an 8-bit bidirectional I/O port with internal pull-ups. The Port 2 output buffers can

sink/source four TTL in puts. When 1s are writte n to Port 2 pins, they a re pulled hig h by the
internal pull-ups and can be u sed as inputs . As inputs, Port 2 p ins that ar e extern ally being
pulled low will source current (I

Port 2 emits the high-order address byte during fetches from external program memory and
during accesses t o e xt er nal d ata mem or y th at u se 1 6- bit ad dr es se s (MO VX @ DP T R). I n t his
application, Port 2 uses strong internal pull-ups when emitting 1s. During accesses to external
data memory that use 8-bit addresses (MOVX @ RI), Port 2 emits the contents of the P2 Spe­cial Function Register.

Port 2 also receives th e high-order addr ess bits an d some control signals durin g Flash pro­gramming and verification.

) because of the internal pull-ups.

IL

Po rt 3 Port 3 is an 8-bit bidirectional I/O port with internal pull-ups. The Port 3 output buffers can

sink/source four TTL in puts. When 1s are writte n to Port 3 pins, they a re pulled hig h by the
internal pull-ups and can be u sed as inputs . As inputs, Port 3 p ins that ar e extern ally being
pulled low will source current (I

Port 3 receives some control signals for Flash programming and verification.

) because of the pull-ups.

IL

Port 3 also serves the functions of various special features of the AT89S51, as shown in the
following table.

4

AT89S51

2487A–10/01

Port Pin Alternate Functions

P3.0 RXD (serial input port)
P3.1 TXD (serial output port)

AT89S51

P3.2 INT0
P3.3 INT1
P3.4 T0 (timer 0 external input)
P3.5 T1 (timer 1 external input)
P3.6 WR
P3.7 RD (external data memory read strobe)

(external interrupt 0)
(external interrupt 1)

(external data memory write strobe)

RST Reset input. A high on this pin for two machine cycles while the oscillator is running resets the

device. This pin drives High for 98 oscillator periods after the Watchdog times out. The DIS­RTO bit in SFR AUXR (addre ss 8EH) ca n be used to disa ble this feat ure. In the de fault stat e
of bit DISRTO, the RESET HIGH out feature is enabled.

ALE/PROG Address Latch Enable (A LE) is an outpu t pulse for latching the lo w byte of the addr ess durin g

accesses to external memory. This pin is also the program pulse input (PROG
programming.

In normal operation, ALE is e mitted a t a con stant rate of 1/ 6 the oscillator frequenc y and may
be used for external timing or clocking pur poses. Note, however, that one ALE pulse is
skipped during each access to external data memory.

If desired, ALE operation can be disabled by setting bit 0 of SFR location 8EH. With the bit set,
ALE is active only during a MO VX or MOVC ins truction. Otherwise, the pin is weakly pull ed
high. Setting the AL E-disable bit has no effect i f the micro controller is in ex ternal exec ution
mode.

) during Flash

PSEN Program Store Enable (PSEN) is the read strobe to external program memory.

When the AT89S51 is executing code from external program memory, P SEN
twice each machine cycle, except that two PSEN
to external data memory.

activations are ski pped du ring each access

is activated

EA/VPP External Access Enable. EA must be strapped to GND in order to enable the device to fetch

code from external program memory locations starting at 0000H up to FFFFH. Note, however,
that if lock bit 1 is programmed, EA

EA

should be strapped to VCC for internal program executions.

This pin also receives the 12-volt programming enable voltage (V
programming.

will be internally latched on reset.

) during Flash

PP

XTAL1 Input to the inverting oscillator amplifier and input to the internal clock operating circuit. XTAL2 Output from the inverting oscillator amplifier

2487A–10/01

5

Special Function Registers

A map of the on-chip memory area called the Special Function Register (SFR) space is shown
in Table 1.

Note that not all of the addresses are occupied, and unoccupied addresses may not be imple­mented on the chip . Read acces ses to these addre sses will in gene ral retur n random dat a,
and write accesses will have an indeterminate effect.

Table 1. AT89S51 SFR Map and Reset Values

0F8H 0FFH

0F0H

0E8H 0EFH

0E0H

0D8H 0DFH

0D0H

0C8H 0CFH

0C0H 0C7H

0B8H

0B0H

0A8H

0A0H

98H

90H

88H

80H

B

00000000

ACC

00000000

PSW

00000000

IP

XX000000

P3

11111111

IE

0X000000

P2

11111111

SCON

00000000

P1

11111111

TCON

00000000

P0

11111111

SBUF

XXXXXXXX

TMOD

00000000

SP

00000111

AUXR1

XXXXXXX0

TL0

00000000

DP0L

00000000

TL1

00000000

DP0H

00000000

TH0

00000000

DP1L

00000000

TH1

00000000

DP1H

00000000

WDTRST

XXXXXXXX

AUXR

XXX00XX0

PCON

0XXX0000

0F7H

0E7H

0D7H

0BFH

0B7H

0AFH

0A7H

9FH

97H

8FH

87H

6

AT89S51

2487A–10/01

AT89S51

User software should not write 1s to these unlisted locations, since they may be used in future
products to invoke new features. In that case, the reset or inactive values of the new bits will
always be 0.

Interrupt Registers: The individual interrupt enable bits are in the IE register. Two priorities
can be set for each of the five interrupt sources in the IP register.

Table 2. AUXR: Auxiliar y Regi ster

AUXR Address = 8EH Reset Value = XXX00XX0B

Not Bit

Addressable

– – – WDIDLE DISRTO – – DISALE

Bit 765 4 3 2 1 0

– Reserved for future expansion
DISALE Disable/Enable ALE

DISALE
Operating Mode

0 ALE is emitted at a constant rate of 1/6 the oscillator frequency
1 ALE is active only during a MOVX or MOVC instruc tion

DISRTO Disable/Enable Reset out

DISRTO
0 Reset pin is driven High after WDT times out

1 Reset pin is input only
WDIDLE Disable/Enable WDT in IDLE mode
WDIDLE
0 WDT continues to count in IDLE mode
1 WDT halts counting in IDLE mode

Dual Data Pointer Registers: To facilitate accessing both internal and external data memory,
two banks of 16-bit Data Pointer Registers are provided: DP0 at SFR address locations 82H­83H and DP1 at 84H-85H. Bit DPS = 0 in SFR AUXR1 selects DP0 and DPS = 1 selects DP1.
The user should always initialize the DPS bit to the appropr iate value before accessing the
respective Data Pointer Register .

2487A–10/01

7

Power Off Flag: The Power Off Flag (POF) is located at bit 4 (PCON.4) in the PCON SFR.

POF is set to “1” during power up. It can be set and rest under software control and is not
affected by reset.

Table 3. AUXR1: Auxiliary Register 1

AUXR1

Address = A2H

Reset Value = XXXXXXX0B

Not Bit

Addressable

––––– – – DPS

Bit76543 2 1 0

– Reserved for future expansion
DPS Data Pointer Register Select

DPS
0 Selects DPTR Registers DP0L, DP0H
1 Selects DPTR Registers DP1L, DP1H

Memory Organization

MCS-51 devices have a separate address space for Program and Data Memory. Up to 64K
bytes each of external Program and Data Memory can be addressed.

Program Memory If the EA pin is connected to GND, all program fetches are directed to external memory.

On the AT89S51, if EA
FFFH are directed to internal memory and fetches to add resses 1000H through FFFFH are
directed to external memory.

is connected to VCC, program fetches to addresses 0000H through

Data Memory The AT89S51 implemen ts 128 by tes of on- chip RAM. T he 128 byte s are acce ssi ble via direct

and indirect addr essing mo des. Stack oper ations ar e examples of indir ect addres sing, so the
128 bytes of data RAM are available as stack space.

Watchdog Timer (One-time Enabled with Reset-out)

The WDT is intended as a recover y method in s ituations where the CPU may be subjected to
software upsets. The W DT consists of a 14-bit counter an d the Watchdog Ti mer Reset
(WDTRST) SFR. The WDT is defaulted to disable from exiting reset. To enable the WDT, a
user must write 01EH and 0E1H in sequence to the WDTRST register (SFR location 0A6H).
When the WDT is enabled, it will increment every machine cycle while the oscillator is running.
The WDT timeout period is dependent on the external clock frequency. There is no way to dis­able the WDT except through reset (either hardware reset or WDT overflow reset). When
WDT overflows, it will drive an output RESET HIGH pulse at the RST pin.

Using the WDT To enable the WDT, a user mus t write 01EH and 0E 1H in seq uence to the WDTR ST reg ister

(SFR location 0A6H) . Wh en the WDT is e nabled, the user needs to s ervi ce it by writing 01EH
and 0E1H to WDTRST to avoid a WDT overflow. The 14-bit counter overflows when it reaches
16383 (3FFFH), and this will reset the device. When the WDT is enabled, it will increment
every machin e cyc le w hile th e osc illa tor is r unnin g. T his m ean s the user mu st r ese t the WD T
at least every 1638 3 machin e cycles . To res et the WDT th e user mus t write 01E H and 0E1 H
to WDTRST. WDTRST is a write-only register. The WDT counter canno t be read or written.
When WDT overflows , it will generat e an output RESET pulse at the RST pin . The RESET
pulse duration is 98xTO SC, where TOSC=1/F OSC. To make the best use of the WDT, it

8

AT89S51

2487A–10/01

AT89S51

should be serviced in those sections of code that will periodically be executed within the time
required to prevent a WDT reset.

WDT During Power-down and Idle

In Power-down m ode t he os cilla tor st ops, whic h mea ns the WDT also stop s. W hile in Po wer­down mode, the user does not need to ser vice the WDT . There are two me thods of exitin g
Power-down mode : by a hardware rese t or via a level -activated ex ternal inte rrupt, which is
enabled prior to entering Power-down mode. When Power-down is exited with hardware reset,
servicing the WDT should occur as it normally does whenever the AT89S51 is reset. Exiting
Power-down with an interrupt is significantly different. The interrupt is held low long enough for
the oscillator to st abilize. When the interrupt is br ought hig h, the interr upt is serv iced. To pr e­vent the WDT from resetting the device while the interrupt pin is held low, the WDT is not
started until the interrupt is pulled high. It is sug ges ted that the W D T be re se t du ring t he i nte r­rupt ser vice for the interrupt used to exit Power-down mode.

To ensure that the WDT does not overflow within a few states of exiting Power-down, it is best
to reset the WDT just before entering Power-down mode.

Before going into the IDLE mode, the WDIDLE bit in SFR AUXR is used to determine whether
the WDT continues to cou nt if en abled. The WDT ke eps coun tin g during IDLE (W DIDLE bi t =

0) as the default state . To preve nt the WDT from reset ting the AT8 9S51 whi le in IDLE mode ,
the user should always set up a timer that will periodically exit IDLE , service the WDT , and
reenter IDLE mode.

With WDIDLE bit enabled, the WDT will stop to count in IDLE mode and resumes the count
upon exit from IDLE.

UART The UART in the AT89S 51 operates the sa me way as the UART in the AT89C51. For further

information on the UART operation, refer to the ATMEL Web site (http://www.atmel.com).
From the home page, select ‘Products’, then ‘8051-Architecture F lash Microcontrolle r’, then
‘Product Overview’.

Timer 0 and 1 Timer 0 and Timer 1 in the AT89S51 operate the same way as Timer 0 and Timer 1 in the

AT89C51. For further information on the timers’ operation, refer to the ATMEL Web site
(http://www.atmel.com). From the home page, select ‘Products’, then ‘8051-Architecture Flash
Microcontroller’, then ‘Product Overview’.

Interrupts The AT89S51 has a total of five interrupt vectors: two external interrupts (INT0 and INT1), two

timer interrupts (Timers 0 and 1), and the serial port interrupt. These interrupts are all shown in
Figure 1.

Each of these interrupt sources can be individually enabled or disabled by setting or clearing a
bit in Special Function Register IE. IE also contains a global disable bit, EA, which disables all
interrupts at once.

Note that Table 4 sh ows tha t bit pos ition IE.6 is unimpl emente d. In the A T89S51 , bit pos ition
IE.5 is also unimplemented. User software should not write 1s to these bit positions, since they
may be used in future AT89 products.

The Timer 0 and Timer 1 flags, T F0 and TF1, ar e set at S5 P2 of the cy cle in w hich the time rs
overflow. The values are then polled by the circuitry in the next cycle

2487A–10/01

9