PowerPact6 Processors
Family Product Manual
Publication No. CP-0HH
1st Edition, October 2005
© Radstone Technology PLC
Copyright Notice
© Radstone Technology PLC 2005. All rights reserved.
This publication is issued to provide outline information only which (unless agreed by the Company in
writing) may not be used, applied or reproduced for any purpose or form part of any order or contract or
be regarded as a representation relating to products or services concerned. The Company reserves the
right to alter without notice the specification, design, price or conditions of supply of any product or
service.
Trademarks
Radstone, the Radstone logo and PowerPact6 are trademarks of Radstone Technology PLC.
All other company and product names are acknowledged as being the trademarks or registered
trademarks of their respective companies.
Document History
EDITION DATE COMMENTS
1st Edition October 2005 CP1A boards rev 1 and up
PowerPact6 Processors Family Product Manual
1st Edition Contents i
Contents
1. Introduction..............................................................................................................................1-1
PowerPact6 Family Overview.................................................................................................................. 1-1
Build Styles ..............................................................................................................................................1-1
Add-on Functionality ...............................................................................................................................1-1
Input/Output Capability............................................................................................................................1-2
Software Support...................................................................................................................................... 1-3
Built In Test ..................................................................................................................................1-3
Background Condition Screening (BCS) ......................................................................................1-3
PPCBoot Firmware .......................................................................................................................1-3
Operating System Support ............................................................................................................1-3
VxWorks/Tornado .............................................................................................................1-4
LynxOS.............................................................................................................................. 1-4
Integrity..............................................................................................................................1-4
Safety Notices ..........................................................................................................................................1-5
Safety Summary............................................................................................................................ 1-5
Ground the Equipment.................................................................................................................. 1-5
Power Supplies.............................................................................................................................. 1-5
Backplane Requirements............................................................................................................... 1-5
Flammability ................................................................................................................................. 1-5
EMI/EMC Regulatory Compliance............................................................................................... 1-5
Handling........................................................................................................................................ 1-6
Heatsink ........................................................................................................................................1-6
About This Manual...................................................................................................................................1-7
Objectives .....................................................................................................................................1-7
Audience .......................................................................................................................................1-7
Scope............................................................................................................................................. 1-7
Structure........................................................................................................................................1-7
Conventions ..................................................................................................................................1-8
Associated Documents .............................................................................................................................1-9
World Wide Web Sites............................................................................................................................. 1-9
2. Unpacking and Inspection ......................................................................................................2-1
Unpacking ................................................................................................................................................2-1
Identifying Your Board ............................................................................................................................2-1
Product Code Breakdown .............................................................................................................2-2
Board Artwork Version................................................................................................................. 2-2
Inspection .................................................................................................................................................2-2
3. Configuration and Installation................................................................................................3-1
PMC Installation ......................................................................................................................................3-1
Link Configuration................................................................................................................................... 3-2
Chassis Configuration ..............................................................................................................................3-2
Board Installation .....................................................................................................................................3-3
4. System Set-up..........................................................................................................................4-1
Connection ...............................................................................................................................................4-1
Connection Using I/O Modules.....................................................................................................4-1
Development System................................................................................................................................4-3
System Software Setup .................................................................................................................4-4
Network Settings........................................................................................................................... 4-4
Embedded Software Setup .......................................................................................................................4-5
BIT ................................................................................................................................................ 4-6
PPCBoot........................................................................................................................................ 4-7
VxWorks ....................................................................................................................................... 4-8
PowerPact6 Processors Family Product Manual
1st Edition Contents ii
5. Standard Interfaces .................................................................................................................5-1
CompactPCI Interface .............................................................................................................................. 5-1
J1 Connector Pinout...................................................................................................................... 5-2
Signal Descriptions............................................................................................................ 5-3
J2 Connector Pinout...................................................................................................................... 5-5
Signal Descriptions............................................................................................................ 5-6
Geographical Address Pin Assignments .......................................................................................5-7
PMC Interface ..........................................................................................................................................5-8
PMC Sites .....................................................................................................................................5-8
Jx1 (32-bit PCI) Connector Pinout................................................................................................5-9
Jx2 (32-bit PCI) Connector Pinout................................................................................................5-9
Jx3 (64-bit PCI) Connector Pinout..............................................................................................5-10
J14 (User I/O) Connector Pinout.................................................................................................5-11
J24 (User I/O) Connector Pinout.................................................................................................5-11
PCI/PMC Signal Descriptions.....................................................................................................5-12
AFIX Interface .......................................................................................................................................5-13
AFIX Connector Pinout ..............................................................................................................5-14
AFIX Signal Descriptions........................................................................................................... 5-15
6. Build Styles and Dimensions .................................................................................................6-1
Build Styles ..............................................................................................................................................6-1
Environmental Specifications...................................................................................................................6-2
Dimensions............................................................................................................................................... 6-3
7. Technical Support....................................................................................................................7-1
Troubleshooting .......................................................................................................................................7-2
Appendix A - CP1A ...........................................................................................................................A-1
Glossary..................................................................................................................................................i
Index........................................................................................................................................................i
PowerPact6 Processors Family Product Manual
1st Edition 1-1
1. Introduction
PowerPact6 Family Overview
Radstone’s PowerPact6 family of 6U rugged CompactPCI products builds on the established 3U
PowerPact3 family and the proven designs of its latest VME SBCs, but takes full advantage of the
enhanced features of CompactPCI, such as support for hot swap, and much higher pin count to give the
most flexible single slot solution currently in the defense and aerospace market space.
The general purpose processors feature an extensive range of I/O, coupled with two PMC sites and
Radstone’s new AFIX (Additional Flexible Interface Xtension) pluggable module. Latest generation
PowerPC processors and Integrated System Controllers, combined with Radstone’s industry-leading
software support and experience in designing and manufacturing rugged electronics for over four
decades, give the PowerPact6 family the edge in embedded computing performance.
Build Styles
Like Radstone’s VME products, the PowerPact6 family is available in a range of build styles, from
Level 1 (Standard), suitable for a benign office-like environment, right through to Level 5 (Rugged
Conduction-cooled), capable of withstanding the harshest of environments. All products are COTS/NDI,
and make maximum use of low cost plastic packaged integrated circuits to ensure the most cost effective
solution, whatever the market.
Add-on Functionality
PowerPact6 processors have two on-board IEEE P1386.1 PMC sites, with PMC I/O available through
the J3 and J5 connectors, allowing direct backplane connection to I/O.
Radstone is a key member of the VITA standards committee, setting the standards for rugged
conduction-cooled PMCs.
A range of PMCs is available from Radstone in both conduction-cooled and air-cooled build standards.
More details on these can be found at
http://www.radstone.com or product literature can be obtained
from your nearest Sales Office or Radstone directly.
$
Note: Air-cooled build levels (1, 2 and 3) can accept any build level of air- or conduction-cooled PMCs
(from Radstone or third parties), as long as adequate cooling is provided. However, conductioncooled build levels (4 and 5) can only accept conduction-cooled PMCs.
PowerPact6 Processors Family Product Manual
Introduction
1st Edition 1-2
Input/Output Capability
The PowerPact6 processor provides high-density rear I/O for systems requiring sealed box operation and
simple card replacement routines for field maintenance. Using rear I/O minimizes the effort required to
remove boards from a rack, so improving maintainability and reliability.
The PowerPact6 processors use 6-row CompactPCI J1, J2, J3, J4 and J5 connectors. PowerPact6
processor rear I/O connectivity, via the J3, J4 and J5 connectors, includes Ethernet, serial, GPIO and
access to the on-board PMC and AFIX sites. Front I/O connectivity (only available on build levels 1 to 3)
includes serial and USB, plus access to the on-board PMC sites.
To maximize the flexibility of connecting to the rear I/O, backplane modules and a range of breakout
panels are available (see below).
Figure 1-1. PowerPact6 I/O
I/O Modules
For use in chassis, Radstone offers backplane modules to convert the condensed J3/J4/J5 pinouts to
industry-standard formats, plus 3U breakout panels offering a variety of industry standard connectors
such as serial I/O. Internal cables and a basic set of external cables are available. These backplane
modules and breakout panels are intended for development use in a benign environment, and so are only
available in level 1 or 2 build standards.
For more details see the I/O Modules Manual, publication number RT5154.
PowerPact6 Processors Family Product Manual
Introduction
1st Edition 1-3
Software Support
PowerPact6 software support options include Built In Test (BIT) and PPCBoot firmware, plus BSPs and
ESPs for VxWorks/Tornado from Wind River Systems, LynxOS from LynuxWorks and Integrity from
Green Hills Software Inc.
Built In Test
BIT provides initialization test for all on-board functional areas of the PowerPact6 processors. Highest
possible coverage (95%) is achieved by the use of intrusive testing, with BIT assuming exclusive use of
device resources. BIT executes before any COTS O/S, and passes control to the O/S on completion.
Testing in conjunction with a COTS O/S is accomplished by BCS (see below).
BIT is a highly configurable component, with options for individual tests and sub-tests. System-wide
coverage to Radstone PMCs or other Radstone VME boards is supported. Custom tests for bespoke
equipment can readily be added. In addition to visual indication, test results can be stored in Flash for
later analysis by the application.
Background Condition Screening (BCS)
BCS provides continuous, on-line health monitoring. It runs as a task thread, featuring non-intrusive tests
that are specifically designed to be co-operative with the normal functioning of the COTS O/S that is
running the application. In addition to having minimal impact on system latency, this method avoids a
difficulty that arises when ‘calling back’ into a traditional, stand-alone test firmware, written in
ignorance of the O/S and probably assuming exclusive use of board resources. Such firmware may not
guarantee the restoration of the entire and complex machine state as the O/S left it. BCS works chiefly
through O/S mechanisms and does not compromise the machine state imposed by the O/S.
Radstone’s BCS for VxWorks is downloadable or can be linked to the VxWorks executable image. It can
be launched from the VxWorks shell or from an application. Configuration is via the Tornado Project
Tool. Configurable parameters include the BCS task priority, plus various test options and other
characteristics. An error log is stored in Flash, in addition to visual indication of a detected failure. An
application interface is provided for immediate invocation of individual tests in addition to the default
running of tests in background mode.
PPCBoot Firmware
The PPCBoot firmware provides a foundation layer to interface between the raw Radstone board
hardware, with its highly programmable device set-ups and flexibility, and the supported Operating
Systems, which require a straight-forward booting and device interface model.
The PPCBoot Firmware allows booting from a range of device types and includes comprehensive
configuration facilities and other valuable features for system integrators.
Operating System Support
In-house porting expertise for PowerPC based boards is focused on key operating systems, including
Wind River Systems’ VxWorks/Tornado, LynuxWorks’ LynxOS and Green Hills’ Integrity. Other
operating system ports, drivers for third party hardware and layered products are provided through
strategic partnerships with dedicated third party vendors, able to offer high quality products and services
complementary to the Radstone range. In this way, state of the art development environments and debug
tools that are part of these software-products are made available for use on Radstone’s flexible hardware
architectures.
Please contact Radstone for availability of other operating systems in addition to the standard VxWorks,
LynxOS and Integrity offerings.
PowerPact6 Processors Family Product Manual
Introduction
1st Edition 1-4
VxWorks/Tornado
Tornado: A highly scaleable and deterministic run-time system, Tornado offers distributed backplane and
networking support and has a large base of third-party support. Tornado includes a comprehensive suite
of core and optional cross-development tools and utilities, and a full range of communications options
for the target connection to the host. Support for Wind River’s next generation product VxWorks 6 with
the WorkBench IDE is available. This adds powerful new features with a focus on open standards,
performance, reliability and interoperability, and includes MMU-based memory protection and enhanced
error management.
VxWorks: Deployed in over 30 million devices, VxWorks forms the foundation for Wind River
platforms, which also include the Tornado Integrated Development Environment (IDE). The run-time
component of the Tornado embedded development platform, VxWorks is the most widely adopted realtime operating system (RTOS) in the embedded industry. With a focus on performance, scalability, and
footprint, VxWorks enables device software to run faster, better, and more reliably.
Board support packages (BSPs) containing Wind River defined support, and enhanced support packages
(ESPs) providing extra Radstone defined support, are both available direct from Radstone.
LynxOS
This fully deterministic real-time UNIX offers complete memory management support, including MMUbased protected address-spaces for tasks. With comprehensive POSIX API conformance 1003.1, .1b and
.1c, LynxOS also exhibits true linear scalability, and a Linux application binary interface (ABI)
personality. Linux binaries run unchanged on LynxOS v4.0.
Radstone provides direct support for BSPs containing LynuxWorks defined support, and ESPs providing
extra Radstone defined support.
Linux has, in recent years, formed an increasingly attractive alternative to proprietary operating systems
for underpinning applications on embedded systems. A range of Linux distributions, targeted at cut-down
embedded operation up to large-scale server operation, has increased choice still further, with free and
added-value commercial distributions sharing the market and catering for different program needs.
An Open Source package for the PowerPact6 CP1A, released under the terms of the General Public
License (GPL) and supporting the Linux 2.6.x kernel, can be downloaded from the Radstone website.
Radstone intends to provide confidence of operation with a number of free and commercial distributions,
including Yellow Dog, Fedora Core (PowerPC version) and BlueCat from LynuxWorks.
Integrity
This maximum reliability, real-time operating system is royalty-free. The Integrity RTOS uses hardware
memory protection to isolate and protect itself, and user tasks, from incorrect operation caused by
accidental errors or malicious tampering.
Support for Radstone boards including the CP1A is available direct from Green Hills Software Inc.,
Radstone’s technology partner.
PowerPact6 Processors Family Product Manual
Introduction
1st Edition 1-5
Safety Notices
Safety Summary
Observe the following general safety precautions during operation of this equipment. Failure to comply
with these precautions or with specific Warnings and/or Cautions elsewhere in this manual violates
safety standards of design, manufacture and intended use of the equipment. Radstone Limited trading as
Radstone Digital Processing assumes no liability for the user’s failure to comply with these requirements.
The safety precautions listed below represent warnings of certain dangers of which Radstone is aware.
Take note of these warnings and take all other safety precautions necessary for the safe operation of the
equipment in your operating environment.
Ground the Equipment
To minimize shock hazard, connect the equipment chassis and rack/enclosure to an electrical ground. If
AC power is supplied to the rack/enclosure, the power jack and mating plug of the power cable must
meet International Electrotechnical Commission (IEC) safety standards.
Power Supplies
! WARNING
Do not exceed the maximum rated input voltages or apply reversed bias to the assembly.
If such conditions occur, toxic fumes may be produced due to the destruction of components.
Power supply problems must only be dealt with by qualified personnel.
Backplane Requirements
" CAUTION
For optimum performance, PowerPact6 processors have been designed for use with 64-bit
CompactPCI backplanes. They may also be used with 32-bit backplanes, but with a
corresponding performance loss.
Flammability
All Radstone circuit boards are manufactured by UL-recognized/approved manufacturers and have a
flammability rating of 94V-0.
EMI/EMC Regulatory Compliance
" CAUTION
This equipment generates, uses and can radiate electromagnetic energy. It may cause or be
susceptible to electromagnetic interference (EMI) if not installed and used in a cabinet with
adequate EMI protection.
Radstone boards are designed using good EMC practices and, when used in a suitably EMC-compliant
chassis, should maintain the compliance of the total system.
Radstone boards also comply with EN60950 (product safety), which is essentially the requirement for the
Low Voltage Directive (73/23/EEC).
Air-cooled PowerPact6 processors are designed for use in systems meeting VDE class B, EN and FCC
regulations for EMC emissions and susceptibility.
Conduction-cooled PowerPact6 processors are designed for integration into EMC hardened
cabinets/boxes.
PowerPact6 Processors Family Product Manual
Introduction
1st Edition 1-6
Handling
"CAUTION
Handle PowerPact6 processors using the board edges or front panel.
Incorrect handling may cause component damage
Heatsink
"CAUTION
Do not remove the heatsink.
There are no PROMs or other user-alterable components
underneath the heatsink, so users should have no reason to
remove it.
Users should not attempt reattachment of the heatsink, as this
requires precise torque on the screws attaching the heatsink
to the PCB. Over-tightening the screws may cause the
heatsink to damage components beneath it (e.g. the main
PowerPC processor). Removal and re-attachment of the
heatsink should only be carried out by Radstone.
PowerPact6 Processors Family Product Manual
Introduction
1st Edition 1-7
About This Manual
Objectives
• To guide the reader through configuration, installation and power-up of PowerPact6 processors
• To provide the user with reference information on the specific PowerPact6 processors (CP1A etc.)
$
Note: On-board firmware and other software (e.g. drivers, BSPs, ESPs etc.) are described in separate user
guides.
Audience
This manual is written to cover, as far as possible, the range of people who will handle or use the
PowerPact6 processors including (but not limited to):
• Inspectors
• Installation technicians
• Hardware and software engineers
• System managers
While every effort has been made to keep the description of configuration, installation and power-up as
simple and user-friendly as possible, a certain amount of background knowledge on these subjects is
assumed.
Scope
This manual describes:
• All build standards of the PowerPact6 processors
• All variants of the PowerPact6 processors
This manual mentions, but does not describe in detail:
• PMCs and AFIX modules
• Carrier cards
• PowerPact6 on-board firmware
• Other firmware such as drivers, BSPs, ESPs etc.
• Application software
Structure
This manual is divided into two main parts: the first part contains all the information common to the
PowerPact6 family, and the second part (the appendices) contains the information specific to the family
constituents (CP1A etc.)
Included in the first part is a hardware set-up section that reflects the sequence of operations from receipt
of a PowerPact6 processor up to getting it working in your system.
PowerPact6 Processors Family Product Manual
Introduction
1st Edition 1-8
Conventions
All numbers are expressed in decimal, except addresses and memory or register data, which are
expressed in hexadecimal. Where confusion may occur, decimal numbers have a ‘D’ subscript and
binary numbers have a ‘b’ subscript. The prefix ‘0x’ shows a hexadecimal number, following the ‘C’
programming language convention. Thus:
One dozen = 12
D
= 0x0C = 1100b
The multipliers ‘k’, ‘M’ and ‘G’ have their conventional scientific and engineering meanings of *10
3
,
*10
6
and *109 respectively. The only exception to this is in the description of the size of memory areas,
when ‘K’, ‘M’ and ‘G’ mean *2
10
, *220 and *230 respectively.
$ Note: When describing transfer rates, ‘k’ ‘M’ and ‘G’ mean *10
3
, *106 and *109 not *210, *2
20
and *230.
In PowerPC terminology, multiple bit fields are numbered from 0 to n, where 0 is the MSB and n is the
LSB. PCI and VMEbus terminology follows the more familiar convention that bit 0 is the LSB and bit n
is the MSB.
Signal names follow the PICMG 2.0 R3.0 CompactPCI Specification. Signal names ending with a hash
(~) are active low; all other signals are active high.
This manual uses the following types of notice:
1) Notes call attention to important features or instructions, and are shown as follows:
$ Note: This is an example note entry.
2) Cautions call attention to actions that may cause system damage or loss of data, and are shown as
follows:
"CAUTION
This is an example caution entry.
3) Warnings call attention to actions that may cause risk of personal injury, and are shown as follows:
!WARNING
This is an example warning entry.
4) Recommendations give guidance on procedures that may be tackled in a number of ways, and are
shown as follows:
£RECOMMENDATION
This is an example recommendation
entry.
PowerPact6 Processors Family Product Manual
Introduction
1st Edition 1-9
Associated Documents
CompactPCI Bus Specification PICMG 2.0 R3.0.
ANSI/VITA 30.1-2002 – 2mm Connector Equipment Practice for Conduction-Cooled Eurocards.
IEEE P1386 Draft Standard for a Common Mezzanine Card Family.
IEEE P1386.1 Draft Standard Physical and Environmental Layers for PCI Mezzanine Cards.
ANSI/VITA 20 – 2001 Standard for Conduction-cooled PMCs.
Associated Radstone Documents
I/O Modules Manual, publication number RT5154.
PMC Installation Note, publication number HN4/3-99.
PPCBIT User Guide, publication number PPCBIT-0HU.
PowerPact6 User Guide (Tornado/Platforms/VxWorks Edition), publication number CPBSP-TOR0HU.
VxWorks ESP for PowerPact6 Manual, publication number CPESP-TOR0HU.
LynxOS BSP for PowerPact6 Installation Manual, publication number CPBSP-LNXxHL.
LynxOS ESP for PowerPact6 Manual, publication number CPESP-LNX0HL.
PPCBoot User Guide, publication number PPCBOOT-0HL.
World Wide Web Sites
The Radstone Product Manuals CD-ROM allows privileged access to an Internet resource containing the
latest updated documents.
Radstone on the world-wide-web is available at
http://www.radstone.com
Manufacturers of many of the devices used on the PowerPact6 processors maintain FTP or world-wideweb sites. Some useful sites are:
http://www.picmg.org CompactPCI data is available through this site.
http://www.freescale.com Freescale PowerPC data is available through this site.
http://www.marvell.com Marvell data is available through this site.
$
Note: At the time of writing, Discovery GT64460 data is under NDA (Non-Disclosure Agreement). Contact
Marvell for more details.
PowerPact6 Processors Family Product Manual
1st Edition 2-1
2. Unpacking and Inspection
Unpacking
• When you receive the shipping container, inspect it for any evidence of physical damage
• If you see any damage, refer to the Terms and Conditions of Sale (provided with your delivery)
for further instructions. If you need to return the product, please contact your local Radstone Sales
Office or Agent
PowerPact6 processors are sealed into an antistatic bag and housed in a padded cardboard box. Retain
this packaging and use it whenever the board is stored or shipped. Failure to use the correct packaging
may invalidate the warranty.
Box contents checklist:
1) PowerPact6 Single Board Computer in antistatic packaging.
2) Manual CD-ROM (colour may vary).
3) Embedded Software License Agreement (RT5087).
4) Where to find the latest product manuals leaflet (only included
with the very latest hardware products).
$ Note: Configuration links (jumpers) may be separately packaged inside
the box.
Identifying Your Board
PowerPact6 processors are identified by labels at strategic positions. You can cross-check these against
the Advice Note provided with your delivery.
Identification labels, similar to
this, attached to the shipping box
and the antistatic bag provide
identical information:
PowerPact6 product code,
product description, equipment
number and board revision.
On the board within the antistatic bag, there is an identifying label
similar to this attached to the printed wiring board.
On conduction-cooled versions of the board (build levels 4 and
5), there is also a label similar to this attached to the front panel.
A label, similar to this, giving the board’s hardware Ethernet or MAC address is also attached
to the printed wiring board.
00-80-8E
00-50-93
PowerPact6 Processors Family Product Manual
Unpacking and Inspection
1st Edition 2-2
Product Code Breakdown
Referring to the example labels shown previously, an alpha-numeric code (CP1A-100040 in the above
examples) is printed on the top line of the packaging label, the top middle line of the board mounted
label and the metal label (build level 4 and 5). This indicates the board’s build specification and
configuration. Relevant code details are shown below:
CP1A-100040
See also the Product Codes section in the appropriate appendix.
Board Artwork Version
The board artwork version may be identified as follows:
• The numeric prefix given in the product label’s Rev code - see previous page
• The revision number given in BIT and PPCBoot startup banners
• The revision number given when a VxWorks -->sysBoardShow command is executed
Inspection
"CAUTION
PowerPact6 processors are subject to damage by static electricity. Observe antistatic
precautions (wear an antistatic wrist-strap connected to an Earth point and work at an
approved antistatic work station) when handling the board.
1) Visually inspect the board for any damage and loose or dislodged components.
2) As soon as possible, report to Radstone any defects you detect.
3) Referring to the specific appendix, visually inspect the board to ensure that the default
configuration is correct and that there are no loose or missing jumpers.
"CAUTION
Handle PowerPact6 processors using
the board edges or front panel. Incorrect
handling may cause component
damage.
PowerPact6
Board T
yp
e
Embedded Software
(5th character)
3 = VxWorks
4 = BIT/VxWorks
5 = PPCBoot
6 = BIT/PPCBoot
Build Level
(1st character)
PowerPact6 Processors Family Product Manual
1st Edition 3-1
3. Configuration and Installation
PMC Installation
Two single width (or one double-width) PMCs may be fitted to the PowerPact6 processor. There are no
PMC keying pins, as the board can be user-configured for 5V or 3.3V signaling. Figure 3-1 shows the
positions of the PMC sites.
$
Note: PowerPact6 processors provide protection so that if a PMC card is fitted that shorts the +5 Volt rail to
the VIO supply, this is detected and the supply of 3.3 Volts to the VIO rail is inhibited. This protects
both the PowerPact6 processor and the PMC from burning up tracks or destroying parts.
Each PMC is supplied with a full kit of parts for mounting it, full fitting instructions and a manual. For
Radstone products, the PMC Installation Note, publication number HN4/3-99 contains the fitting
instructions. PMCs ordered with a PowerPact6 processor can be supplied factory fitted by Radstone, if
required.
It will usually be necessary to install driver software or implement other firmware configuration to
achieve full functionality of a PMC (see the specific PMC manual for the exact procedure).
Figure 3-1. PMC Position
£RECOMMENDATION
Where PMCs are not pre-installed,
prove PowerPact6 operation before
PMC installation.
PowerPact6 Processors Family Product Manual
Configuration and Installation
1st Edition 3-2
Link Configuration
Board configuration is carried out by the insertion and removal of jumpers (configuration links). Where
these links are factory fitted, a default setting is used. For link ID, default and recommended settings,
refer to appropriate appendix, BSP, BIT and/or PPCBoot manual(s) - listed below.
Appendix A – CP1A
PPCBIT User Guide, Publication No. PPCBIT-0HU
PPCBoot Firmware User Manual, Publication No. PPCBOOT-0HL
LynxOS BSP Manual
VxWorks BSP Release Notes
All available manuals can be found via the Manuals CD-ROM.
Chassis Configuration
Unlike VME backplanes, the CompactPCI backplane does not use daisy chains for bus requests or
interrupt acknowledgements, so no configuration of the backplane is required before use.
However, the position of the PowerPact6 processor in the backplane determines whether it is System
Controller (providing CompactPCI clocks and arbitration) or a peripheral. If the PowerPact6 processor is
required to be System Controller, fit it in the dedicated System Controller slot. If the PowerPact6
processor is required to be a peripheral, it can be fitted in any slot except the System Controller slot. The
following symbols are used to indicate CompactPCI device capabilities:
The position of the PowerPact6 processor in the backplane also determines its Board ID using
geographical addressing.
PowerPact6 Processors Family Product Manual
Configuration and Installation
1st Edition 3-3
Board Installation
Before installing the PowerPact6 processor, review the following warning and caution notices:
!WARNING
Do not exceed the maximum rated input voltages or apply reversed bias to the assembly.
If such conditions occur, toxic fumes may be produced due to the destruction of
components
Use extreme caution when handling, testing and adjusting this equipment. This device can
operate in an environment containing potentially dangerous voltages, capable of causing
death.
Refer to warnings contained in associated system equipment manuals before operating this
device. All warning instructions must be followed
Employ all other safety precautions that are deemed necessary for the safe operation of the
equipment in your operating environment.
Ensure that all power to the system is removed before installing any device.
"CAUTION
Before fitting your PowerPact6 processor into a CompactPCI rack, consult the
rack/enclosure documentation to ensure that the backplane power specifications are
compatible. PowerPact6 processors require power on both J1 and J2 backplane connectors.
Use of backplanes supplying power to the J1 connector alone may cause excessive current
to be drawn through the power pins.
This equipment generates, uses and can radiate electromagnetic energy. It may cause or be
susceptible to electromagnetic interference (EMI) if not installed and used in an enclosure
with adequate EMI protection.
Ensure that your PowerPact6 processor receives sufficient air-flow, even when operating on
an extender card – at least 300 foot/minute for build levels 1 and 2, 600 foot/minute for build
level 3. If you need to operate a conduction-cooled (level 4 or 5) board on an extender card,
maintain airflow of at least 300 feet/minute over it.
£RECOMMENDATION
To prove operation of your PowerPact6 processor and avoid any system configuration
issues, initially fit the board into a rack or enclosure in isolation.
To prove operation of your PowerPact6 processor and avoid any board configuration
issues, use the default link configuration initially.
$ Notes:
1) Ensure that the chassis power supply is within CompactPCI Specification limits (+5V +5% -3%, +3.3V +5% 3%) and sufficient for the PowerPact6 processor’s requirements (typically 1.9A @ 3.3V and 4.1A @ 5V for
the CP1A).
2) Although the PowerPact6 processor does not use the ±12V supply lines, it will not work without these
supplies being present. This is because the hotswap device monitors all four (5V, 3.3V, +12V, -12V) supply
rails and holds the PowerPact6 processor in reset until they are within specified tolerances. It is a
requirement for CompactPCI systems to provide ±12V anyway.
PowerPact6 Processors Family Product Manual
Configuration and Installation
1st Edition 3-4
Observing all antistatic and handling precautions, carry out the following installation procedure:
1) Insert the processor into the required slot of the CompactPCI rack or enclosure.
$ Notes:
a. If the PowerPact6 processor is required to be System Controller (providing CompactPCI
clocks and arbitration), fit it in the dedicated System Controller slot. If the PowerPact6
processor is required to be a Peripheral, it can be fitted in any slot except the System
Controller slot. The following symbols indicate CompactPCI device capability:
b. The position of the PowerPact6 processor in the backplane also determines its board ID using
geographical addressing.
2) Push the board firmly home to ensure that backplane connectors mate correctly.
3) For air-cooled boards, tighten the captive screws at the top and bottom of the front panel to secure
the board in position.
$
Note: Pulling on any front panel cable connections could inadvertently disconn ect the board
if it is not secured.
4) For conduction-cooled boards, tighten the
3
/32” (2.38 mm) hexagon-head screw-driven wedgelocks
at the top and bottom of the board to secure it in position and ensure a correct mechanical/thermal
interface. Use a calibrated torque wrench set to between 0.6 and 0.8 Nm.
5) To ensure optimum EMC performance, maintain ground continuity when taking I/O connections
from the front/rear panel connectors, or when the board is operating on a bus extender card.
Your PowerPact6 processor should now be installed into a CompactPCI rack or enclosure.
PowerPact6 Processors Family Product Manual
1st Edition 4-1
4. System Set-up
Connection
To interact with embedded software (BIT, PPCBoot or VxWorks), an RS232 connection needs to be
made to a serial terminal or computer system (PC or XWindows host) running terminal emulation
software. To enable interaction with host system cross-development software (Tornado), an Ethernet
connection is also required.
For cross-development systems, connect the terminal or terminal emulator to the PowerPact6 processor’s
serial debug port (COM1). Connect the network to the PowerPact6 processor’s Ethernet
(10/100/1000BaseT) port (channel 0). Connection may be achieved with a rear I/O module that uses the
backs of the P3, P4 and P5 connectors - see the I/O Modules Manual. Documents are available through
the Manuals CD-ROM.
Connection Using I/O Modules
For detailed I/O module installation instructions, see the I/O Modules Manual. Observe antistatic and
safety precautions when handling and/or installing I/O Modules.
Figure 4-1 overleaf shows a typical cross-development system set-up. This example is for guidance only
and is not definitive of I/O connection. The following items are used:
• A CompactPCI rack/enclosure with P3/P4/P5 backplane pins projecting through the backplane
structure
• The PowerPact6 processor (CP1A)
• A suitable backplane module (CPCI6UX600). This must be installed directly behind the target
PowerPact6 processor and presents available PowerPact6 I/O ports as PCB male headers or
interface standard connectors. COM1 and Ethernet channel 0 are presented via industry standard
9-way D-type and RJ-45 connectors respectively. See the I/O Modules Manual for more details
• A suitable serial cable (i.e. a null-modem 9-way micro D to 9-way micro D-type cable) for
connection between the backplane module and a PC
$ Note: Connection to COM1 may also be made via the front panel on build levels 1 to 3.
• A suitable Ethernet cable (RJ-45 connector terminated at one end at least) for connecting the
backplane module to the network
PowerPact6 Processors Family Product Manual
System Set-up
1st Edition 4-2
Figure 4-1. I/O Connections
PowerPact6 Processors Family Product Manual
System Set-up
1st Edition 4-3
Development System
The PowerPact6 family supports the cross-development method of application development, as shown in
the diagram below.
$ Note: IP addresses shown are for illustration purposes only.
This allows development system tools to run on a host computer (PC or UNIX). The development
environment interacts with the target (the PowerPact6 system) via a network. Direct interaction with
PowerPact6 embedded software is via serial links to a suitable terminal or terminal emulator.
All system interconnections should be made using suitable standard or Radstone specific cables.
Connections shown indicate possible options, some of which may not be suitable or possible on all
systems.
The system shown is the minimum required for checking PowerPact6 operation and for carrying out
software development. For further descriptions of system components and other concepts refer to the
relevant documentation.
Recommended minimum development system specification is as follows:
• A 400 MHz+ PC with 64 MBytes of RAM running Microsoft Windows NT4/2000 or an
UltraSPARC machine running Solaris 2.6 or later and XWindows
• 750 MBytes of free hard disk drive space (Tornado 2), 1 Gbyte free (X11)
• A CD-ROM drive
• Ethernet interface
• 2 free RS232 serial ports
• Suitable monitor, keyboard and mouse
PowerPact6 Processors Family Product Manual
System Set-up
1st Edition 4-4
System Software Setup
Software requirements for application development and/or PowerPact6 operational checks are as follows:
• Application Development Software (Tornado 2, LynxOS) – provides application development
tools
• Board Support Package (BSP) - installed as a supplement to the Application Development
Software, the BSP provides specific support for the PowerPact6 family
• Terminal Emulator (HyperTerminal, Kermit, Tip, Cu etc.) or stand-alone terminal
• An FTP, TFTP or RSH server - provides target system access to host resident files
$
Note: Some of these software development packages may be incorporated into the application software
distribution or the host operating system, e.g. Tornado 2 includes terminal emulator and FTP server
software.
Once installed, terminal emulator and (T)FTP/RSH software must be configured.
Terminal emulation software should be set to communicate with the appropriate serial port as follows:
Bits per second: 9600
Data bits: 8
Parity: None
Stop bits: 1
Flow control: None
Since the COM port is Tx/Rx only, turn off any handshaking options on the terminal/terminal emulation
software.
(T)FTP/RSH settings should allow sufficient target system access to host system directories/files.
Installation and configuration of the host software should be completed before operation of the target
system. For detailed installation and configuration instructions refer to the relevant software package
documentation.
Network Settings
The network may use Domain Name Service (DNS), Dynamic Host Configuration Protocol (DHCP),
Windows Internet Name Service (WINS), Boot Protocol (BOOTP), Reverse Address Resolution
Protocol (RARP), Sub-networks and Gateways. The development system can be configured to use any or
all of these protocols.
£RECOMMENDATION
In a DHCP-enabled network, allocate fixed IP addresses to host and target systems, at least
initially.
Network information and problem diagnosis may be carried out from the host system using standard OS
commands ipconfig, ifconfig, ping, etc.
For relevant system IP addresses and protocol details, consult your system administrator or refer to
suitable development environment documentation.
PowerPact6 Processors Family Product Manual
System Set-up
1st Edition 4-5
Embedded Software Setup
Having configured and installed your
PowerPact6 processor; installed, set up and
started host system software – terminal
emulator, FTP server etc.; and determined
relevant TCP/IP network settings, you are
now ready to start your processor for the
first time.
On power-up, assuming no chassis
problems, the processor should auto-boot its
embedded software package. Boot sequence
details are displayed in the terminal emulator
window (terminal screen or monitor). If the
boot sequence appears not to initiate, power
down the system and check all RS232 and
monitor connections. Also check that the
PowerPact6 processor is inserted into the
appropriate slot correctly. PowerPact6 LED
illumination does not necessarily indicate
that the board is correctly installed.
As previously described, PowerPact6
processors may be supplied with different
types/combinations of pre-installed
embedded software. To identify the software
shipped with your PowerPact6, see the
Product Code Breakdown section. Initial
startup conditions and default setup
information for each embedded software
type are given in subsequent sub-sections.
PowerPact6 Processors Family Product Manual
System Set-up
1st Edition 4-6
BIT
Radstone’s Built In Test (BIT) software comprises a suite of self-test programs designed to run on the
full range of boards and systems manufactured by Radstone Technology.
On power up or hard reset, BIT displays a start banner detailing the BIT version, PowerPact6 type
(CP1A in the example below), available memory etc. This is followed by the first tests - BIT checksum
and MPE (Minimum Processing Environment) tests. A typical full BIT start sequence is shown below:
Radstone Technology Plc PPCBIT V3.0.0.0 ALPHA
=======================================
Board Type : CP1A Mem Bus Speed 133Mhz ; MPC7447A 1133MHz Revision : 1A
Memory : 512 Mb DRAM, ECC Disabled
Cache : 1024 Kb L2,
Flash : 8 Mb System FLASH : 248 Mb User FLASH
CPCI : System Board Slot ID = 5,
PCI : PMC2 IO = 3.3V ; PMC1 IO = 3.3V
Ports : COM 3-6
Ethernet : Ch1 Gigabit Ethernet ; Ch2 Gigabit Ethernet
Modules :PMC1 : OUT PMC2 : OUT AFIX : OUT
BIT : Master
Boot Mode : MAIN
PPCBIT Details
==============
Version No: V3.0.0.0 ALPHA
Part No. : TB0712-001
Built : Aug 18 2005 15:40:55
.....
BIT Checksum = d98ca94e
MPE tests successful
Restored System Description...
Copy of System Description Table at ffa82200
============================================
SDE CIIN ROUTINE ADDRESS BUS AM METHOD LENGTH GRAN SKP TESTMASK
--- ---- ------- ------- --- -- ------ ------ ---- --- -------000 CP1A 0006339c 00000000 LOCAL SELF_TEST 0100 NO 00000000
CP1A (00000000 LOCAL SELF_TEST )
Passed TM 00000001 [Timebase & Decrementer Test]
Passed TM 00000002 [ISA Bridge Test ]
Passed TM 00000004 [Hardware Register Test ]
Passed TM 00000008 [Main DRAM Test ]
Passed TM 00000010 [PowerPC Cache Test ] L1 Only
Passed TM 00000020 [PowerPC MMU Test ]
Passed TM 00000040 [PowerPC FPU Test ]
Passed TM 00000080 [PCI Bus Test ]
Passed TM 00000100 [Discovery Timer Test ]
Passed TM 00000200 [Discovery COM 3/4 Test ]
Passed TM 00000400 [Discovery Ethernet 1 Test ]
Passed TM 00000800 [Discovery Ethernet 2 Test ]
Passed TM 00001000 [Discovery I2C TEMP Test ]Temperature 29.18C
Passed TM 00002000 [Discovery I2C RTC Test ]
Passed TM 00004000 [HB6 Bridge 1 Test ]
PowerPact6 Processors Family Product Manual
System Set-up
1st Edition 4-7
Passed TM 00008000 [HB6 Bridge 2 Test ]
Passed TM 00010000 [HB6 Bridge 3 Test ]
Passed TM 00020000 [PCI USB2 Test ]
Passed TM 00040000 [GPIO/Floppy/LPT Test ] GPIO
Passed TM 00080000 [PS2 Keyboard + Mouse Test ]
Passed TM 00100000 [Serial Port COM1 Test ]
Passed TM 00200000 [Serial Port COM2 Test ]
Passed TM 00400000 [Serial Port COM5 Test ]
Passed TM 00800000 [Serial Port COM6 Test ]
Passed TM 01000000 [System Flash (Main) Test ] Checksum Only
Passed TM 02000000 [System Flash (Ext) Test ] Checksum Only
Passed TM 04000000 [System Flash (Alt) Test ] Checksum Only
Passed TM 08000000 [System Flash (Bank) Test ] Checksum Only
Ignored TM 10000000 [User Flash Test ] Ignored on power up
Passed TM 20000000 [NVRAM Test ] PPCBOOT No Test
Passed TM 40000000 [Dummy Test ]
Passed TM 80000000 [Beep Test ]
CP1A (00000000 LOCAL SELF_TEST ) passed
Default action is Options Menu
Press any key to abort default action...
Options Menu
============
1. System Description.
2. Special Functions
3. Comprehensive BIT.
4. Default BIT, Application.
5. Execute Application.
6. Interactive BIT.
7. Edit Configuration.
8. Debug.
Select option >
PPCBoot
PowerPact6 processors do not support SCSI disks, so PPCBoot’s primary role here is to boot crossdevelopment operating systems (such as LynxOS) across a network. Consult the documentation supplied
with the software (e.g. LynxOS) for more details. An example of booting LynxOS across a network is
given below.
On startup, PPCBoot displays a start banner that identifies the PowerPact6 system configuration - see
below.
PPCBoot 2.0.0 (Aug 24 2005 - 11:15:13), Build: 31590 Radstone Version 1.1b booted
from Alt boot area
CPU: MPC7447A v1.1 @ 1133.333 MHz
Board: CP1A Rev 1A #12345678 Slot ID: 0x01
I2C: ready
Temp: board: 31 C, 37 C cpu: 56 C
DRAM: 512 MB
FLASH: 256 MB
In: serial
Out: serial
Err: serial
AFIX: not fitted
CPCI: System Controller
SCSI: disabled
Net: mv_enet0 [PRIME], mv_enet1
=>
PowerPact6 Processors Family Product Manual
System Set-up
1st Edition 4-8
VxWorks
When booting the target with a VxWorks program image provided over a network, the VxWorks boot
program must be configured to include information about the location of the VxWorks image on the host
computer’s hard disk drive. The boot program must be set to communicate via a network, and requires
the correct host and target IP addresses, the full path and name of the file to be booted, the user name etc.
When the target system is powered up (and each time it is hard reset), the target system executes the boot
program from ROM; the target uses the serial ports to communicate with a terminal or the host computer
terminal emulation software (HyperTerminal, tip, cu or Kermit). The boot program first displays a
banner page, and then starts a seven-second countdown, visible on the screen as shown below. Unless
stopped by a key-press within the seven-second period, the boot loader attempts to proceed with the
specified configuration.
VxWorks System Boot
Copyright 1984-2005 Wind River Systems, Inc.
CPU: Radstone CP1A-7447A
Version: VxWorks 6.1
BSP version: 2.0/1.0
Creation date: Sep 14 2005, 15:59:49
Press any key to stop auto-boot...
0
auto-booting...
boot device : rsNet
unit number : 0
processor number : 0
host name : dfppcpc
file name : /GPP3.1/work/pp6gpio/default/vxworks
inet on ethernet (e) : 192.168.164.100:ffffff00
host inet (h) : 192.168.3.57
gateway inet (g) : 192.168.164.1
user (u) : tor22
ftp password (pw) : tor22
flags (f) : 0x8
other (o) :
Attaching interface lo0... done
Started End Device : 1000 Base-T Full Duplex
Started End Device : 1000 Base-T Full Duplex
Attached IPv4 interface to rsNet unit 0
Loading... 1637924 + 164568
Starting at 0x100000...
Attaching interface lo0... done
Started End Device : 1000 Base-T Full Duplex
Started End Device : 1000 Base-T Full Duplex
Attached IPv4 interface to rsNet unit 0
Attached IPv6 interface to rsNet unit 0
Loading symbol table from dfppcpc:/GPP3.1/work/pp6gpio/default/vxworks.sym ...do
ne
PowerPact6 Processors Family Product Manual
System Set-up
1st Edition 4-9
VxWorks
Copyright 1984-2005 Wind River Systems, Inc.
CPU: Radstone CP1A-7447A
Runtime Name: VxWorks
Runtime Version: 6.1
BSP version: 2.0/1.0
Created: Sep 22 2005, 14:38:40
ED&R Policy Mode: Deployed
WDB Comm Type: WDB_COMM_END
WDB: Ready.
->
PowerPact6 Processors Family Product Manual
Standard Interfaces
1st Edition 5-1
5. Standard Interfaces
CompactPCI Interface
The PowerPact6 processors implement a 64-bit, 66 MHz CompactPCI interface, conforming to the
PICMG 2.0 R3.0 specification. Hot-Swap (PICMG 2.1) is also implemented. 3.3V signaling voltage is
used, with tolerance of 5V inputs.
The PowerPact6 processors may operate either as System Controller (providing CompactPCI clocks and
arbitration) or as a Peripheral card. The following symbols are used to indicate CompactPCI device
capabilities:
Figure 5-1. CompactPCI Bus Connector Positions and Numbering
PowerPact6 Processors Family Product Manual
Standard Interfaces
1st Edition 5-2
J1 Connector Pinout
PIN ROW A ROW B ROW C ROW D ROW E ROW F
25 +5V REQ64~ ENUM~ +3.3V +5V GND
24 AD(1) +5V V(IO) AD(0) ACK64~ GND
23 +3.3V AD(4) AD(3) +5V AD(2) GND
22 AD(7) GND +3.3V AD(6) AD(5) GND
21 +3.3V AD(9) AD(8) M66EN CBE(0)~ GND
20 AD(12) GND V(IO) AD(11) AD(10) GND
19 +3.3V AD(15) AD(14) GND AD(13) GND
18 SERR~ GND +3.3V PAR CBE(1)~ GND
17 +3.3V No Connection No Connection GND PERR~ GND
16 DEVSEL~ GND V(IO) STOP~ LOCK~ GND
15 +3.3V FRAME~ IRDY~ BD_SEL~ TRDY~ GND
14
13
12
Keying Area
11 AD(18) AD(17) AD(16) GND CBE(2)~ GND
10 AD(21) GND +3.3V AD(20) AD(19) GND
9 CBE(3)~ IDSEL AD(23) GND AD(22) GND
8 AD(26) GND V(IO) AD(25) AD(24) GND
7 AD(30) AD(29) AD(28) GND AD(27) GND
6 REQ~ GND +3.3V CLK AD(31) GND
5
BRSVP1A5/
PRI_AUTOWR
No Connection RST~ GND GNT~ GND
4 No Connection HEALTHY~ V(IO) INTP INTS GND
3 INTA~ INTB~ INTC~ +5V INTD~ GND
2 TCK +5V TMS TDO TDI GND
1 +5V -12V TRST~ +12V +5V GND
PowerPact6 Processors Family Product Manual
Standard Interfaces
1st Edition 5-3
Signal Descriptions
SIGNAL DESCRIPTION
+5V +5V power connection
+3.3V +3.3V power connection
-12V -12V power connection. Not used by the PowerPact6 processor, but fed to the PMC site
+12V +12V power connection. Not used by the PowerPact6 processor, but fed to the PMC site
GND Signal Ground connection
V(IO) PCI bus I/O voltage reference (+3.3V or +5V)
AD(0) to AD(31) PCI Multiplexed Address/Data bits 0 to 31
CBE(0)~ PCI Command/Byte Enable 0 for AD(7:0)
CBE(1)~ PCI Command/Byte Enable 1 for AD(15:8)
CBE(2)~ PCI Command/Byte Enable 2 for AD(23:16)
CBE(3)~ PCI Command/Byte Enable 3 for AD(31:24)
INTA~ to INTD~ PCI Interrupt A to Interrupt D signals
REQ~ PCI Master request to system arbiter
SERR~
PCI system Error signal; may be pulsed by any PCI device to report address parity errors, data parity
errors during a Special Cycle, and critical errors other than parity
FRAME~
Cycle Frame is driven by the current initiator and indicates the start (when first asserted) and duration
(the duration of its assertion) of a transaction. To determine that bus ownership has been acquired,
the master must sample FRAME~ and IRDY~ both de-asserted and GNT~ asserted on the same
rising edge of the PCI CLK signal. A transaction may consist of one or more data transfers between
the current initiator and the currently-addressed target. FRAME~ is de-asserted when the initiator is
ready to complete the final data phase
IRDY~
Initiator Ready is driven by the current bus master (the initiator of the transaction). During a write,
IRDY~ asserted indicates that the initiator is driving valid data onto the data bus. During a read,
IRDY~ asserted indicates that the initiator is ready to accept data from the currently addressed target.
To determine that bus ownership has been acquired, the master must sample FRAME~ and IRDY~
both de-asserted and GNT~ asserted on the same rising edge of the PCI CLK signal. See also
TRDY~
GNT~ PCI Grant signal
CLK PCI clock signal (33 or 66MHz)
TRDY~
Target Ready is driven by the currently addressed target. It is asserted when the target is ready to
complete the current data phase (data transfer). A data phase is completed when the target is
asserting TRDY~ and the initiator is asserting IRDY~ at the rising edge of the CLK signal. During a
read, TRDY~ asserted indicates that the target is ready to accept data from the master. Wait states
are inserted in the current data phase until both TRDY~ and IRDY~ are sampled asserted.
PAR
Parity Signal. Driven by the initiator one clock after completion of the address phase or one clock after
the assertion of IRDY~ during each data phase of write transactions. It is driven by the currently
addressed target one clock after the assertion of TRDY~ during each data phase of read
transactions. One clock after completion of the address phase, the initiator drives PAR either high or
low to ensure even parity across the address bus, AD(31:0), and the four Command/Byte Enable
lines, CBE(3:0)~
DEVSEL~
Device Select is asserted by a target when the target has decoded its address. It acts as an input to
the current initiator and the subtractive decoder in the expansion bus bridge. If a master initiates a
transfer and does not detect DEVSEL~ active within six CLK periods, it must assume that the target
cannot respond or that the address is unpopulated. A master-abort results
IDSEL
Initialization Device Select is an input to the PCI device and is used as a chip select during an access
to one of the device's configuration registers
LOCK~
Used by the initiator to lock the currently-addressed target during an atomic transaction series (e.g.
during a semaphore read/modify/write operation)
STOP~ The target asserts STOP~ to indicate that it wishes the initiator to stop the transaction in progress
PERR~ Parity Error signal
M66EN PCI 66 MHz operation signal
PowerPact6 Processors Family Product Manual
Standard Interfaces
1st Edition 5-4
SIGNAL DESCRIPTION
REQ64~ Request a 64-bit transfer
ACK64~ Acknowledge 64- bit transfer
ENUM~ System Enumeration signal. This is an optional signal used in hot-swap applications
RST~ CompactPCI backplane reset signal
TDI
JTAG Test Input. Used (in conjunction with TCK) to shift data out of the Test Access Port in a serial
bit stream
TDO JTAG Test Output. Used (in conjunction with TCK) to shift data into the TAP in a serial bit stream
TCK
JTAG Test Clock - used to clock state information and data into and out of the TAP during boundary
scan
TMS JTAG Test Mode Select. Used to control the state of the TAP controller
TRST~ JTAG Test Reset - Used to force the TAP controller into an initialized state
INTP Legacy Interrupt Input. Not used on PowerPact6 processors
INTS Legacy Interrupt Input. Not used on PowerPact6 processors
BRSVP1A5/
PRI_AUTOWR~
Link selection between bused reserved signal BRSVP1A5 and JTAG AutoWrite Enable signal
HEALTHY~ Board Healthy. Hot swap signal
BD_SEL~ Board Select. Hot swap signal
PowerPact6 Processors Family Product Manual
Standard Interfaces
1st Edition 5-5
J2 Connector Pinout
PIN ROW A ROW B ROW C ROW D ROW E ROW F
22 GA4 GA3 GA2 GA1 GA0 GND
21 CLK6 GND No Connection No Connection No Connection GND
20 CLK5 GND No Connection GND No Connection GND
19 GND GND No Connection No Connection No Connection GND
18 No Connection No Connection No Connection GND No Connection GND
17 No Connection GND RST~ REQ6~ GNT6~ GND
16 No Connection No Connection DEG~ GND No Connection GND
15 No Connection GND FAL~ REQ5~ GNT5~ GND
14 AD(35) AD(34) AD(33) GND AD(32) GND
13 AD(38) GND V(IO) AD(37) AD(36) GND
12 AD(42) AD(41) AD(40) GND AD(39) GND
11 AD(45) GND V(IO) AD(44) AD(43) GND
10 AD(49) AD(48) AD(47) GND AD(46) GND
9 AD(52) GND V(IO) AD(51) AD(50) GND
8 AD(56) AD(55) AD(54) GND AD(53) GND
7 AD(59) GND V(IO) AD(58) AD(57) GND
6 AD(63) AD(62) AD(61) GND AD(60) GND
5 CBE(5) 64EN~ V(IO) CBE(4)~ PAR64 GND
4 V(IO) No Connection CBE(7)~ GND CBE(6)~ GND
3 CLK4 GND GNT3~ REQ4~ GNT4~ GND
2 CLK2 CLK3 SYSEN~ GNT2~ REQ3~ GND
1 CLK1 GND REQ1~ GNT1~ REQ2~ GND
" CAUTION
For optimum performance, PowerPact6 processors have been designed for use with 64-bit
CompactPCI backplanes. They may also be used with 32-bit backplanes, but with a
corresponding performance loss.
PowerPact6 Processors Family Product Manual
Standard Interfaces
1st Edition 5-6
Signal Descriptions
SIGNAL DESCRIPTION
AD(32) to AD(63) Multiplexed Address/Data bits 32 to 63 respectively
CBE(4)~ Command/Byte Enable for AD(32:39)
CBE(5)~ Command/Byte Enable for AD(40:47)
CBE(6)~ Command/Byte Enable for AD(48:55)
CBE(7)~ Command/Byte Enable for AD(63:56)
CLK1 to CLK6 Clocks to slots 3 to 8 respectively
REQ1# to REQ6# Bus Request from slots 3 to 6 respectively
GNT1# to GNT6# Bus Grant to slots 3 to 6 respectively
GA0 to GA4 CompactPCI geographical address bits 0 to 4 respectively
V(I/O) PCI I/O voltage reference (+3.3V or +5V)
GND Signal Ground
SYSEN# CompactPCI System Slot Enable signal
FAL# CompactPCI Power supply fail signal (not supported by PowerPact6 processors)
DEG# CompactPCI power supply de-rating signal (not supported by PowerPact6 processors)
PRST# Push Button Reset (to System card)
64EN~ Self-configure for 64-bit operation
PAR64 Similar function to 32-bit PAR signal for address bus AD(63:32) and CBE(7:4)~
PowerPact6 Processors Family Product Manual
Standard Interfaces
1st Edition 5-7
Geographical Address Pin Assignments
SLOT
GA4
PIN J2-A22
GA3
PIN J2-B22
GA2
PIN J2-C22
GA1
PIN J2-D22
GA0
PIN J2-E22
1 GND GND GND GND Open
2 GND GND GND Open GND
3 GND GND GND Open Open
4 GND GND Open GND GND
5 GND GND Open GND Open
6 GND GND Open Open GND
7 GND GND Open Open Open
8 GND Open GND GND GND
9 GND Open GND GND Open
10 GND Open GND Open GND
11 GND Open GND Open Open
12 GND Open Open GND GND
13 GND Open Open GND Open
14 GND Open Open Open GND
15 GND Open Open Open Open
16 Open GND GND GND GND
17 Open GND GND GND Open
18 Open GND GND Open GND
19 Open GND GND Open Open
20 Open GND Open GND GND
21 Open GND Open GND Open
22 Open GND Open Open GND
23 Open GND Open Open Open
24 Open Open GND GND GND
25 Open Open GND GND Open
26 Open Open GND Open GND
27 Open Open GND Open Open
28 Open Open Open GND GND
29 Open Open Open GND Open
30 Open Open Open Open GND
31 Open Open Open Open Open
$
Note: Geographical addressing is accessed and controlled via software (BSP), the function of which
requires configuration before it may be used – see the appropriate BSP documentation.
PowerPact6 Processors Family Product Manual
Standard Interfaces
1st Edition 5-8
PMC Interface
PMC Sites
The PowerPact6 family has two sets of connectors (J11/J12/J13/J14 and J21/J22/J23/J24) that allow
industry-standard PMCs to be fitted to the PowerPact6 processor, routed to the J3 and J5 connectors. The
PMC PCI interfaces are independent from the Compact PCI interface. For Host card layout information,
see Figure 5-2.
The PMC sites are connected to the processor via PCI buses with user-selectable 5V or 3.3V signaling.
One bus uses the PCI-X protocol (backward compatible with standard PCI), and supports 32- or 64-bit
data widths and bus speeds up to 133 MHz. Running at 64-bit/133 MHz gives a maximum burst transfer
data rate of 1024 MBytes/second. The other bus can run at 66 or 33MHz and 64 or 32-bits wide,
depending on the PMC fitted. Running at 64-bit/66 MHz gives a maximum burst transfer data rate of
528 MBytes/second, compared with 132 MBytes/second for 32-bit/33 MHz. This combination of PCI
and PCI-X allows a state of the art and a legacy PMC to be run simultaneously with no loss of
performance.
Front panel I/O is fully supported on levels 1 to 3, and with reduced functionality, on levels 4 and 5
product. While a level 4 or 5 PowerPact6 processor can only accept conduction-cooled PMCs, levels 1 to
3 PowerPact6 processors can accept either air-cooled or conduction-cooled PMCs, as long as adequate
cooling is provided. Air-cooled PMCs are defined in the IEEE 1386 Standard, and rugged conductioncooled PMCs are defined in the ANSI/VITA 20 – 2001 Standard for Conduction-cooled PMCs.
A range of PMCs is available both from Radstone and third parties. Radstone PMCs are supplied with a
full kit of parts for mounting them, a manual and full fitting instructions (see the PMC Installation Note,
publication number HN4/3-99). PMCs ordered with a PowerPact6 board can be supplied factory fitted by
Radstone, if required.
The additional signals defined by VITA32 (Processor PMC Standard) are also implemented. A Processor
PMC may only operate in non-monarch mode on the PowerPact6 processor.
Figure 5-2. PMC Connector Positions and Numbering
PowerPact6 Processors Family Product Manual
Standard Interfaces
1st Edition 5-9
The IEEE P1386.1 standard defines four connectors with pin assignments shown in the following tables.
In the tables ‘J’ is the host board connector ID (PMC mating connectors have a ‘P’ prefix); the next digit
is ‘1’ for PMC site number 1 or ‘2’ for PMC site number 2, and the final number element defines the
four possible connectors.
Jx1 (32-bit PCI) Connector Pinout
Jx2 (32-bit PCI) Connector Pinout
PIN SIGNAL PIN SIGNAL PIN SIGNAL PIN SIGNAL
1 TCK1 2 -12V 1 +12V 2 TRST~
3 GND 4 IRQ 3 TMS 4 TDO
5 IRQ 6 IRQ 5 TDI 6 GND
7 BUSMODE1 8 +5V 7 GND 8 Reserved (PCI)
9 IRQ 10 Reserved (PCI) 9 Reserved (PCI) 10 Reserved (PCI)
11 GND 12 Reserved 11 BUSMODE2~ 12 3.3V
13 CLK0 14 GND 13 HARDRESET~ 14 BUSMODE3~
15 GND 16 GNT_A~ 15 3.3V 16 BUSMODE4~
17 REQ_A~ 18 +5V 17 Reserved 18 GND
19 VIO 20 AD(31) 19 AD(30) 20 AD(29)
21 AD(28) 22 AD(27) 21 GND 22 AD(26)
23 AD(25) 24 GND 23 AD(24) 24 3.3V
25 GND 26 CBE(3)~ 25 IDSEL_A 26 AD(23)
27 AD(22) 28 AD(21) 27 3.3V 28 AD(20)
29 AD(19) 30 +5V 29 AD(18) 30 GND
31 VIO 32 AD(17) 31 AD(16) 32 CBE(2)~
33 FRAME~ 34 GND 33 GND 34 IDSEL_B
35 GND 36 IRDY~ 35 TRDY~ 36 3.3V
37 DEVSEL~ 38 +5V 37 GND 38 STOP~
39 40 LOCK~ 39 PERR~ 40 GND
41 No Connection 42 No Connection 41 3.3V 42 SERR~
43 PAR 44 GND 43 CBE(1)~ 44 GND
45 VIO 46 AD(15) 45 AD(14) 46 AD(13)
47 AD(12) 48 AD(11) 47 M66EN 48 AD(10)
49 AD(9) 50 +5V 49 AD(8) 50 3.3V
51 GND 52 CBE(0)~ 51 AD(7) 52 REQ_B~
53 AD(6) 54 AD(5) 53 3.3V 54 GNT_B~
55 AD(4) 56 GND 55 Reserved (PMC) 56 GND
57 VIO 58 AD(3) 57 Reserved (PMC) 58 EREADY
59 AD(2) 60 AD(1) 59 GND 60 GND
61 AD(0) 62 +5V 61 ACK64~ 62 3.3V
63 GND 64 REQ64~ 63 GND 64 GND
IRQX~ on J11, IRQW~ on J21
IRQY~ on J11, IRQX~ on J21
IRQZ~ on J11, IRQY~ on J21
IRQW~ on J11, IRQz~ on J21
GND on J11, XCAP on J21
PowerPact6 Processors Family Product Manual
Standard Interfaces
1st Edition 5-10
Jx3 (64-bit PCI) Connector Pinout
PIN SIGNAL PIN SIGNAL
1 Reserved (PCI) 2 GND
3 GND 4 CBE(7)~
5 CBE(6)~ 6 CBE(5)~
7 CBE(4)~ 8 GND
9 VIO 10 PAR64
11 AD(63) 12 AD(62)
13 AD(61) 14 GND
15 GND 16 AD(60)
17 AD(59) 18 AD(58)
19 AD(57) 20 GND
21 VIO 22 AD(56)
23 AD(55) 24 AD(54)
25 AD(53) 26 GND
27 GND 28 AD(52)
29 AD(51) 30 AD(50)
31 AD(49) 32 GND
33 GND 34 AD(48)
35 AD(47) 36 AD(46)
37 AD(45) 38 GND
39 VIO 40 AD(44)
41 AD(43) 42 AD(42)
43 AD(41) 44 GND
45 GND 46 AD(40)
47 AD(39) 48 AD(38)
49 AD(37) 50 GND
51 GND 52 AD(36)
53 AD(35) 54 AD(34)
55 AD(33) 56 GND
57 VIO 58 AD(32)
59 Reserved (PCI) 60 Reserved (PCI)
61 Reserved (PCI) 62 GND
63 GND 64 Reserved (PCI)
PowerPact6 Processors Family Product Manual
Standard Interfaces
1st Edition 5-11
J14 (User I/O) Connector Pinout
J14 is mapped to the J5 backplane connector
as follows:
J24 (User I/O) Connector Pinout
J24 is mapped to the J3 backplane connector
as follows:
J14 PIN J5 PIN J14 PIN J5 PIN J24 PIN J3 PIN J24 PIN J3 PIN
1 E22 2 D22 1 E13 2 D13
3 C22 4 B22 3 C13 4 B13
5 A22 6 E21 5 A13 6 E12
7 D21 8 C21 7 D12 8 C12
9 B21 10 A21 9 B12 10 A12
11 E20 12 D20 11 E11 12 D11
13 C20 14 B20 13 C11 14 B11
15 A20 16 E19 15 A11 16 E10
17 D19 18 C19 17 D10 18 C10
19 B19 20 A19 19 B10 20 A10
21 E18 22 D18 21 E9 22 D9
23 C18 24 B18 23 C9 24 B9
25 A18 26 E17 25 A9 26 E8
27 D17 28 C17 27 D8 28 C8
29 B17 30 A17 29 B8 30 A8
31 E16 32 D16 31 E7 32 D7
33 C16 34 B16 33 C7 34 B7
35 A16 36 E15 35 A7 36 E6
37 D15 38 C15 37 D6 38 C6
39 B15 40 A15 39 B6 40 A6
41 E14 42 D14 41 E5 42 D5
43 C14 44 B14 43 C5 44 B5
45 A14 46 E13 45 A5 46 E4
47 D13 48 C13 47 D4 48 C4
49 B13 50 A13 49 B4 50 A4
51 E12 52 D12 51 E3 52 D3
53 C12 54 B12 53 C3 54 B3
55 A12 56 E11 55 A3 56 E2
57 D11 58 C11 57 D2 58 C2
59 B11 60 A11 59 B2 60 A2
61 E10 62 D10 61 E1 62 D1
63 C10 64 B10 63 C1 64 B1
$
Note: The PowerPact6 processors do not implement the additional signals defined by VITA32 (Processor PMC
Standard).
PowerPact6 Processors Family Product Manual
Standard Interfaces
1st Edition 5-12
PCI/PMC Signal Descriptions
MNEMONIC DESCRIPTION
AD(0) to AD(63) Address/Data bits. Multiplexed address and data bus
CBE(0)~ to
CBE(7)~
Command/Byte Enables. During the address phase, these signals specify the type of cycle to carry
out on the PCI bus. During the data phase the signals are byte enables that specify the active bytes
on the bus
FRAME~ FRAME. Driven low by the current master to signal the start and duration of an access
DEVSEL~
Device Select. Driven low by a PCI agent to signal that it has decoded its address as the target of the
current access
PAR Parity. Parity protection bit for AD(0) to AD(31) and CBE(0)~ to CBE(3)~
IRDY~ Initiator Ready. Driven low by the initiator to signal its ability to complete the current data phase
LOCK~
LOCK. Driven low to indicate an atomic operation that may require multiple transactions to complete.
Pulled high by the PowerPact6 processor and not used
BUSMODE1
Bus Mode 1. When driven low by a PMC, this indicates that a PMC is fitted. The PMC presence can
be read from the PLD register
BUSMODE2~ to
BUSMODE4~
Bus mode. Driven by the host to indicate the bus mode. On the PowerPact6 processor this is always
PCI. BUSMODE2_1~ is pulled high by the PowerPact6 processor. BUSMODE3~ and BUSMODE4~
are pulled low by the PowerPact6 processor
HARDRESET~ Reset. Driven low to reset the PCI bus
TRDY~ Target Ready. Driven low by the current target to signal its ability to complete the current data phase
PERR~ Parity Error. Driven low by a PCI agent to signal a parity error
SERR~ System Error. Driven low by a PCI agent to signal a system error
STOP~ STOP. Driven low by a PCI target to signal a disconnect or target-abort
IRQW~ to IRQZ~ Interrupt lines. Level-sensitive, active-low interrupt requests
CLK0
66.667 or 33.333 MHz clock, according to M66EN. All PCI bus signals except HARDRESET~ are
synchronous to this clock
REQ_A/B~
Request. Driven low by a PCI agent (first [A] or second [B] device on PMC) to request ownership of
the PCI bus
GNT_A/B~
Grant. Driven low by the arbiter to grant PCI bus ownership to a PCI agent (first [A] or second [B]
device on PMC)
IDSEL_A/B
Initialization Device Select. First (A) or second (B) device on PMC chip select during configuration
cycles
REQ64~ Request 64 Bit. Driven low by a PCI master to request 64-bit transfer
ACK64~ Acknowledge 64 Bit. Driven low by PCI agent in response to REQ64
PAR64 Parity. Parity protection bit for AD(32) to AD(63) and CBE(4)~ to CBE(7)~
M66EN
66 MHz Operation. If this is left open by a PMC, PCI will operate at 66.667 MHz. If it is connected to
GND by a PMC, PCI will operate at 33.333 MHz
TCK Test Clock. Clock for the PMC JTAG
TMS Test Mode Select. Select Test Mode for PMC JTAG
TRST Test Reset. Reset any PMC JTAG devices
TDI Test Data In. Ou tput data from the board JTAG chain
TDO Test Data Out. Input data to the board JTAG chain
3.3V +3.3V DC power
+5V +5V DC power
VIO
The supply rail for the PCI bus I/O voltage. For I/O signaling only, not main supply Can be linked for
+5V or +3.3V operation
EREADY Driven low by the PMC until it is ready to be enumerated
XCAP Determines PCI-X capability
-12V -12V DC power
+12V +12V DC power
GND Signal ground connection
PowerPact6 Processors Family Product Manual
Standard Interfaces
1st Edition 5-13
AFIX Interface
For enhanced I/O flexibility, the PowerPact6 processors offer a ‘plug-on’ module interface that adds rear
I/O functionality via J4 and J5. The Additional Flexible Interface Xtension (AFIX) card is a factory fitted
option and is fully rugged.
Figure 5-3. AFIX Connector Position and Numbering
PowerPact6 Processors Family Product Manual
Standard Interfaces
1st Edition 5-14
AFIX Connector Pinout
PIN K J H G F E D C B A
1 GND PCI2_AD(18) GND HDI_G1 GND TCK GND GND AFIX I/O GND
2 PCI2_AD(0) PCI2_AD(19) HDI_H2 HDI_G2 CLK1 TRST PLD_DATA(0) AFIX I/O AFIX I/O AFIX I/O
3 PCI2_AD(1) +5V HDI_H3 +5V CLK2 +5V PLD_DATA(1) AFIX I/O GND AFIX I/O
4 +3V3 PCI2_AD(20) +3V3 HDI_G4 +3V3 TDI +5V GND AFIX I/O GND
5 PCI2_AD(2) PCI2_AD(21) HDI_H5 HDI_G5 CLK3 TMS PLD_DATA(2) AFIX I/O HDO_H2 AFIX I/O
6 PCI2_AD(3) GND HDI_H6 GND CLK4 GND PLD_DATA(3) AFIX I/O GND HDO_H3
7 GND PCI2_AD(22) GND HDI_G7 GND TDO GND GND AFIX I/O GND
8 PCI2_AD(4) PCI2_AD(23) HDI_H8 HDI_G8 POWER_OK EREADY AFIX I/O AFIX I/O HDO_H5
9 PCI2_AD(5) +3V3 HDI_H9 +3V3 HARDRESET~ +3V3 AFIX I/O GND HDO_H6
10 +3V3 PCI2_AD(24) +3V3 HDI_G10 +3V3 I2C_CLK +3V3 GND +5V GND
11 PCI2_AD(6) PCI2_AD(25) HDI_H11 HDI_G11 IDSEL1 I2C_DATA +12V GND -12V
12 PCI2_AD(7) GND HDI_H12 GND IDSEL2 GND GND HDO_H8 GND
13 GND PCI2_AD(26) GND PCI2_CBE(0) GND PCI2_ACK64~ GND AFIX I/O HDO_H11 HDO_H9
14 PCI2_AD(8) PCI2_AD(27) HDI_H14 PCI2_CBE(1) IDSEL3 PCI2_REQ64~ CARD_FITTED~ AFIX I/O GND HDO_H12
15 PCI2_AD(9) +2V5 HDI_H15 +2V5 IDSEL4 +2V5 ALEN GND AFIX I/O GND
16 +2V5 PCI2_AD(28) +2V5 PCI2_CBE(2) +2V5 PCI2_PAR +2V5 AFIX I/O HDO_H15 HDO_H14
17 +3V3 PCI2_AD(29) +3V3 PCI2_CBE(3) +3V3 PCI2_PAR64 IOR~ AFIX I/O GND HDO_H20
18 +3V3 GND +3V3 GND +3V3 GND IOW~ GND AFIX I/O GND
19 GND PCI2_AD(30) GND HDI_G19 GND IRQW~ GND +12V AFIX I/O -12V
20 PCI2_AD(10) PCI2_AD(31) HDI_H20 HDI_G20 PCI2_FRAME~ IRQX~ IO(0) GND GND GND
21 PCI2_AD(11) +5V HDI_H21 +5V PC2I_TRDY~ +5V IO(1) AFIX I/O HDO_H23 HDO_H21
22 +3V3 HDI_J22 +3V3 HDI_G22 +3V3 IRQY~ +3V3 AFIX I/O AFIX I/O HDO_H24
23 PCI2_AD(12) HDI_J23 HDI_H23 PCI2_IRDY~ IRQZ~ IO(2) GND GND GND
24 PCI2_AD(13) GND HDI_H24 GND PCI2_STOP~ GND IO(3) AFIX I/O HDO_H27 HDO_H26
25 GND HDI_J25 GND PCI2_PERR~ GND GNT0~ GND HDO_J22 HDO_H30 HDO_H29
26 PCI2_AD(14) HDI_J26 HDI_H26 PCI2_SERR~ REQ0~ GNT1~ IO(4) GND GND GND
27 PCI2_AD(15) +2V5 HDI_H27 +3V3 REQ1~ +3V3 IO(5) AFIX I/O HDO_J25 HDO_J23
28 +2V5 ISA_IO_FIT~ +2V5 PCI2_DEVSEL~ +3V3 GNT2~ +2V5 HDO_J26 GND HDO_J29
29 PCI2_AD(16) HDI_J29 HDI_H29 PCI2_LOCK~ REQ2~ GNT3~ IO(6) GND AFIX I/O GND
30 PCI2_AD(17) GND HDI_H30 GND REQ3~ GND IO(7) AFIX I/O GND AFIX I/O
PowerPact6 Processors Family Product Manual
Standard Interfaces
1st Edition 5-15
AFIX Signal Descriptions
MNEMONIC DESCRIPTION
PCI Bus
PCI_AD(0) to
PCI_AD(31)
Multiplexed address and data bus
PCI_CBE(0) to
PCI_CBE(3)
Command/Byte Enables. During the address phase, these signals specify the type of cycle to carry
out on the PCI bus. During the data phase the signals are byte enables that specify the active bytes
on the bus
PCI_PERR~ Parity Error. Driven low by a PCI agent to signal a parity error
PCI_SERR~ System Error. Driven low by a PCI agent to signal a system error
PCI_DEVSEL~ Device Select. Driven low by a PCI agent to signal that it has decoded its address as the target of
the current access
PCI_LOCK~ Lock. Driven lo w to indicate an atomic operation that may require multiple transactions to complete
PCI_FRAME~ Frame. Driven low by the current master to signal the start and duration of an access
PCI_TRDY~ Target Ready. Driven low by the current target to signal its ability to complete the current data
phase
PCI_IRDY~ Initiator Ready. Driven low by the initiator to signal its ability to complete the current data phase
PCI_STOP~ Stop. Driven low by a PCI target to signal a disconnect or target-abort
PCI_PAR Parity. Parity protection bit for AD0 to AD31 and BE0 to BE3
IRQW~, IRQX~,
IRQY~, IRQZ~
PCI interrupts
REQ0~ to REQ3~ PCI bus request by (up to 4) devices on the AFIX module
GNT0~ to GNT3~ PCI bus grant to (up to 4) devices on the AFIX module
CLK1 to CLK4 PCI clocks to (up to 4) devices on the AFIX module
RESET~ PCI reset signal generated by the host card
IDSEL1 to IDSEL4 Chip Select for PCI Configuration accesses to (up to 4) devices on the AFIX module
EREADY Enumeration Ready. Driven low by the AFIX module until it is ready for PCI enumeration
AFIX Control and Data
CARD_FITTED~ Connected to Signal Ground on the AFIX module to indicate presence of the card
IO(7:0) These signals should be pulled high on the host card and are tied low on the AFIX module to
indicate the Card Identifier
ISA_IO_FIT~ Connected to Signal Ground on the AFIX module when configured for basic I/O, to indicate to the
host that I/O is being routed to the backplane
PLD_DATA(0) to
PLD_DATA(3)
Control data to the AFIX module
ALEN Address Latch Enable
IOR~ I/O Read strobe
IOW~ I/O Write strobe
I2C_CLK,
I2C_DATA
System I2C bus
AFIX I/O
AFIX I/O See the individual AFIX modules for definitions of these pins
HDO_H/Jnn These pins may also be used for AFIX I/O (see the individual AFIX modules for definitions). If used
by the AFIX module, then they route to the J5 connector
PowerPact6 Processors Family Product Manual
Standard Interfaces
1st Edition 5-16
MNEMONIC DESCRIPTION
JTAG
TDI JTAG Test Data Input
TDO JTAG Test Data Output
TCK JTAG Test Clock
TMS JTAG Test Mode Select
TRST JTAG Test Reset
Power and Ground
+2V5 +2.5V DC power
+3V3 +3.3V DC power
+5V +5 Volts DC power
+12V +12 Volts DC power
-12V -12 Volts DC power
GND The DC voltage reference for the system
POWER_OK Power supplies good signal from the host
PowerPact6 Processors Family Product Manual
Build Styles and Dimensions
1st Edition 6-1
6. Build Styles and Dimensions
Build Styles
The PowerPact6 family is available in Radstone’s five electrically compatible build levels. These have
two basic mechanical configurations:
¾ Air (convection)-cooled (build levels 1 to 3) in accordance with PICMG 2.0 R3.0 specification,
designed to be used in standard industrial chassis
¾ Conduction-cooled (build levels 4 and 5) in accordance with ANSI/VITA 30.1-2002 – 2mm
Connector Equipment Practice for Conduction-Cooled Eurocards, for use in sealed ATR chassis
and other conduction-cooled environments
In addition to these COTS configurations, PowerPact6 processors may be supplied to meet the
mechanical and thermal requirements of specific platforms with the addition of mission specific, to-type
mechanics.
Radstone uses advanced thermal and mechanical design in the PCB, metal work and assembly process to
build-in the required levels of ruggedness. Build level 2 and higher circuit card assemblies include
conformal coating as standard.
All five styles fully support the power and versatility of the CompactPCI bus, so no matter how large or
diversified your project, absolute compatibility is assured at all stages of development.
A brief description of each build style follows:
Level 1
Intended for use in benign environments, level 1 also provides the ideal cost effective method of
complete system development. The level 1 assembly comprises a Eurocard size printed wiring board
with high quality commercial (plastic encapsulated) components.
As software compatibility throughout the build styles is absolute, a system intended for final
implementation in a severe tactical environment can be developed and debugged at low cost, switching
over to target style only in the final stages of system integration.
Level 2
As level 1, but tested in manufacture to provide an extended operating range.
Level 3
Level 3 boards are intended for applications that have extended temperature, shock and vibration
requirements, but can be served by conventional, forced-air cooled, racking systems. These rugged
boards comprise a Eurocard size printed wiring board fitted with wide temperature range components.
Level 4
The level 4 board features wide temperature range devices and an integral thermal management layer. It
also incorporates a central stiffening bar for additional strength.
Cooling is achieved through conduction of heat from the thermal management layer to the cold wall of
the rack to which the boards are secured by screw driven wedgelocks. Level 4 boards are temperature
characterized during manufacture.
Level 5
As level 4, but tested in manufacture to provide an extended operating range.
PowerPact6 Processors Family Product Manual
Build Styles and Dimensions
1st Edition 6-2
Environmental Specifications
Convection-cooled Boards
BUILD
STYLE
OPERATING
TEMP (°C)
STORAGE
TEMP (°C)
VIBRATION SHOCK HUMIDITY COMMENTS
Level 1
0 to +55 with
airflow of 300
feet/minute
-50 to +100
0.002g2/Hz from
10 to 2000 Hz
random, and 2g
sinusoidal from
5 to 500 Hz
20g peak
sawtooth,
11ms duration
Up to 95%
RH
Commercial grade
cooled by forced air, for
use in benign
environments and
software development
applications.
Level 2
-20 to +65 with
airflow of 300
feet/minute
-50 to +100
0.002g2/Hz from
10 to 2000 Hz
random, and 2g
sinusoidal from
5 to 500 Hz
20g peak
sawtooth,
11ms duration
Up to 95%
RH with
varying
temperature.
10 cycles,
240 hours
As Standard but
conformally coated and
temperature
characterized.
Level 3
-40 to +75 with
airflow of 600
feet/minute
-50 to +100
0.04g2/Hz from
10 to 2000 Hz
with a flat
response to
1000 Hz.
6db/Octave rolloff from 1000 to
2000 Hz
20g peak
sawtooth,
11ms duration
Up to 95%
RH with
varying
temperature.
10 cycles,
240 hours
Wide temperature
rugged, cooled by
forced air. Conformally
coated for additional
protection.
Conduction-cooled Boards
BUILD
STYLE
OPERATING
TEMP (°C)
STORAGE
TEMP (°C)
VIBRATION SHOCK HUMIDITY COMMENTS
Level 4
-40 to +75 at
the thermal
interface
-50 to +100
Random
0.1g2/Hz from 5
to 2000 Hz per
MIL-STD-810E
40g peak
sawtooth,
11ms duration
Up to 95%
RH with
varying
temperature.
10 cycles,
240 hours
Mechanically compliant
with IEEE 1101.2-
1992. Designed for
severe environment
applications with high
levels of shock and
vibration, small space
envelope and restricted
cooling supplies.
Conformally-coated as
standard. Optional
ESS.
Level 5
-40 to +85 at
the thermal
interface
-50 to +100
Random
0.1g2/Hz from 5
to 2000 Hz per
MIL-STD-810E
40g peak
sawtooth,
11ms duration
Up to 95%
RH with
varying
temperature.
10 cycles,
240 hours
Mechanically compliant
with IEEE 1101.2-
1992. Designed for
severe environment
applications with high
levels of shock and
vibration, small space
envelope and restricted
cooling supplies.
Conformally-coated as
standard. Optional
ESS.
PowerPact6 Processors Family Product Manual
Build Styles and Dimensions
1st Edition 6-3
Dimensions
All build standards of the PowerPact6 processors are PICMG 2.0 R3.0 CompactPCI Bus Specification
compatible. This allows all styles of assembly to be fitted into any commercial CompactPCI Bus
development chassis. Level 4 and 5 boards also comply with ANSI/VITA 30.1-2002 2mm Connector
Equipment Practice on Conduction Cooled Euroboards.
The following diagrams are included for guidance only. For full details, refer to the appropriate
specifications. All dimensions are in millimeters, with inch equivalents shown in parentheses.
Figure 6-1. Convection-cooled CompactPCI Board Dimensions
PowerPact6 Processors Family Product Manual
Build Styles and Dimensions
1st Edition 6-4
Figure 6-2. Additional Requirements of ANSI/VITA 30.1
PowerPact6 Processors Family Product Manual
Technical Support
1st Edition 7-1
7. T echnical Support
In the unlikely event that you experience problems with your PowerPact6 processor, contact Radstone’s
Technical Assistance.
The preferred method is to register support requests using the Technical Support Request Form available
through the Radstone web site at
http://www.radstone.com - this form looks like:
If you do not have web access, the next preferred method is by e-mail to support@radstone.co.uk. Please
provide the information required in the above form.
If you do not have either web or e-mail access, you can still telephone for technical support on:
+44 (0)1327 322760
Please be prepared to provide the same information as required above.
Your query will be logged on Radstone’s Technical Support database and allocated a unique Call
Reference Number (CRN) for use in future correspondence.
If you need to return a product, there is an RMA fault report form available via the Product Manuals
CD-ROM that can be printed out and filled in. Do not return products without first contacting Radstone.
PowerPact6 Processors Family Product Manual
Technical Support
1st Edition 7-2
Troubleshooting
If you are experiencing a problem with your PowerPact6 processor, there follow some general
suggestions of actions you may take that may resolve the problem without the need to contact Radstone’s
technical support. As well as these general suggestions, there are specific suggestions in the appropriate
appendix.
• Check the links on your PowerPact6 processor. If you are unsure of which link configurations to
use, try the suggested configuration initially
• Check that the power supply is within CompactPCI limits on +3.3V, +5V, +12V and -12V with a
digital volt meter
!WARNING
Power supply problems are to be dealt with only by qualified personnel
• Ensure that your PowerPact6 processor is firmly seated and secured in the rack and that all
male/female connectors mate together correctly
• Check that there is only one board configured as system controller in a system and that this is in
the appropriate System Controller slot in the chassis
• Prove the PowerPact6 processor’s operation in isolation before adding it into a multi-board system
• If you have made your own cables, e.g. for serial connection to terminal/hyperterminal, check that
pinouts are correct
• Check that the terminal/hyperterminal is set up for DTE (9.6 kbaud, 8 bits/character, 1 stop bit,
parity disabled)
• Ensure that air-cooled PowerPact6 processors receive sufficient airflow - 300 feet/second for build
levels 1 and 2, 600 feet/second for build level 3. If you need to operate your PowerPact6 processor
on an extender card, this requires an additional fan to supply the necessary air flow
• Ensure that conduction cooled PowerPact6 processors are fully installed in the conduction cooled
chassis and that the wedgelocks are correctly tightened. The recommended torque value is 0.6 to
0.8 Nm and the hexagon size is
3
/32” (2.38 mm). If you need to operate a conduction cooled
PowerPact6 processor on an extender card, you must maintain airflow of at least 300 feet/minute
over it
PowerPact6 Processors Family Product Manual
1st Edition Glossary i
Glossary
$
Notes:
1) The PCI Bus signals are detailed in the PCI Bus Signal Descriptions section and the PMC signals are
explained in the PMC Signal Descriptions section.
2) This glossary only features terms special to this manual. Explanations of more general terms can be found
in the Radstone Glossary, publication number RT5116.
AFIX
Additional Flexible Interface Extension.
Backplane (CompactPCI)
A backplane developed by the PICMG and defining a ruggedized version of PCI to be used in industrial
and embedded applications. With regard to electrical, logical and software functionality, it is 100%
compatible with the PCI standard. The cards are rack mounted and use standard Eurocard packaging.
Cards can be either 6U or 3U in height.
DDR
Double Data Rate.
GPIO
General Purpose Input/Output.
O/S
Operating System.
PICMG
PCI Industrial Computer Manufacturer’s Group
System Controller
A board in the System Controller slot of the CompactPCI backplane. The system controller provides a
separate clock to each of the peripheral cards in the backplane and also a PCI arbiter.
TAP
Test Access Point.
PowerPact6 Processors Family Product Manual
1st Edition Index i
Index
A
AFIX
Connector .....................................................5-14
Interface........................................................ 5-13
Signal Descriptions....................................... 5-15
Antistatic Precautions......................................... 2-2
Associated Documents .......................................1-9
B
BCS ....................................................................1-3
BIT...............................................................1-3, 4-6
Board Configuration........................................... 3-1
Board Installation ...............................................3-3
Build Styles .................................................1-1, 6-1
C
Cautions.............................................................. 1-5
Chassis Configuration......................................... 3-2
CompactPCI Interface ........................................5-1
Connection.......................................................... 4-1
Connectors
AFIX............................................................. 5-14
Signal Descriptions................................... 5-15
CompactPCI Bus .....................................5-2, 5-5
J1 .................................................................... 5-2
Signal Descriptions..................................... 5-3
J11 ..................................................................5-9
J12 ..................................................................5-9
J13 ................................................................5-10
J14 ................................................................5-11
J2 .................................................................... 5-5
Signal Descriptions..................................... 5-6
J21 ..................................................................5-9
J22 ..................................................................5-9
J23 ................................................................5-10
J24 ................................................................5-11
PMC................................................................ 5-8
Positions .........................................................5-1
D
Development System.......................................... 4-3
Dimensions......................................................... 6-3
Documentation Audience ...................................1-7
Documentation Conventions ..............................1-8
Documentation Objectives..................................1-7
Documentation Scope......................................... 1-7
Documentation Structure.................................... 1-7
E
Embedded Software Setup..................................4-5
EMI/EMC........................................................... 3-4
Regulatory Compliance ..................................1-5
Environmental Specification ..............................6-2
Equipment Number.............................................2-1
F
Flammability.......................................................1-5
G
Geographical Addressing....................................5-7
H
Handling .............................................................1-6
Heatsink ..............................................................1-6
Humidity .............................................................6-2
I
I/O Capability .....................................................1-2
I/O Modules ........................................................1-2
Inspection............................................................2-2
Integrity...............................................................1-4
Introduction.........................................................1-1
L
Label ...................................................................2-1
Link Configuration..............................................3-2
LynxOS...............................................................1-4
N
Network Settings.................................................4-4
O
Operating Environment.......................................6-2
Operating Systems ..............................................1-3
P
PMCs ..................................................................1-1
Connector Positions ........................................5-8
Connectors ......................................................5-8
Installation ......................................................3-1
Signal Descriptions .......................................5-12
Sites.................................................................5-8
PowerPact6 Family Overview ............................1-1
PPCBoot .............................................................4-7
PPCBoot Firmware .............................................1-3
Problems .............................................................7-1
Product Codes............................................. 2-1, 2-2
Product Identification..........................................2-1
R
Revision State .....................................................2-1
PowerPact6 Processors Family Product Manual
1st Edition Index ii
S
Safety Notices..................................................... 1-5
Shock .................................................................. 6-2
Signal Descriptions
AFIX............................................................. 5-15
J1 .................................................................... 5-3
J2 .................................................................... 5-6
PMCs ............................................................ 5-12
Size .....................................................................6-3
Software Support................................................ 1-3
Storage Environment.......................................... 6-2
System Set-up..................................................... 4-1
System Software Setup....................................... 4-4
T
Technical Help Contact Details .......................... 7-1
Tornado ..............................................................1-4
Troubleshooting.................................................. 7-2
U
Unpacking...........................................................2-1
V
Vibration .............................................................6-2
VxWorks..................................................... 1-4, 4-8
W
Warnings.............................................................1-5
Workbench..........................................................1-4
World Wide Web Sites .......................................1-9
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