RadiSys EPC-5A Hardware & Software Reference Manual

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EPC-5A

Hardware & Software

Reference Manual

RadiSys Corporation

5445 NE Dawson Creek Drive

Hillsboro, Oregon 97124

Phone: (503) 615-1100

Fax: (503) 615-1150

http://www.radisys.com

____________________________________________________________________

07-0870-01 October 1998

EPC-5A Hardware & Software Reference Manual

EPC, iRMX, INtime, Inside Advantage and RadiSys are registered trademarks of RadiSys Corporation. Spirit, DAI, DAQ, ASM, Brahma and SAIB are trademarks of RadiSys Corporation.

All other trademarks, registered trademarks, service marks, and trade names are the property of their respective owners.

October 1998

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EPC-5A Hardware & Software Reference Manual

Hardware Warranty

RadiSys Corporation ("RadiSys") warrants the EPC system and component modules to the original purchaser for two years from the product’s shipping date. If an EPC product fails to operate in compliance with its specification during this period, RadiSys will, at its option, repair or replace the product at no charge. The customer is, however, responsible for shipping the product; RadiSys assumes no responsibility for the product until it is received. This warranty does not cover repair of products that have been damaged by abuse, accident, disaster, misuse, or incorrect installation.

RadiSys’ limited warranty covers products only as delivered. User modification, such as the addition of memory arrays or other devices, may void the warranty, and if the product is damaged during installation of the modifications, this warranty does not cover repair or replacement.

This warranty in no way warrants suitability of the product for any specific application.

IN NO EVENT WILL RADISYS BE LIABLE FOR ANY DAMAGES, INCLUDING LOST PROFITS, LOST SAVINGS, OR OTHER INCIDENTAL OR CONSEQUENTIAL DAMAGES ARISING OUT OF THE USE OR INABILITY TO USE THE PRODUCT EVEN IF RADISYS HAS BEEN ADVISED OF THE POSSIBILITY OF SUCH DAMAGES, OR FOR ANY CLAIM BY ANY PARTY OTHER THAN THE PURCHASER.

THE ABOVE WARRANTY IS IN LIEU OF ANY AND ALL OTHER WARRANTIES, EXPRESSED OR IMPLIED OR STATUTORY, INCLUDING THE WARRANTIES OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE OR USE, TITLE AND NONINFRINGEMENT. Repair or replacement as provided above shall be the Purchaser’s sole and exclusive remedy and RadiSys’ exclusive liability for any breach of warranty.

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EPC-5A Hardware & Software Reference Manual

Table of Contents

1. Product Description................................................................................................1

Purpose..................................................................................................................1

About this Manual.................................................................................................1

Notational Conventions.........................................................................................2

Product Overview..................................................................................................3

Specifications........................................................................................................4

Differences Between EPC-5 and EPC-5A.............................................................4

2. Before Installation ...................................................................................................7

Configuring the EPC-5A.......................................................................................7

Selecting the EPC-5A Slot Location.....................................................................8

Installing the VMEbus Backplane Jumpers...........................................................10

Jumpers .................................................................................................................14

3. Installation................................................................................................................15

Subplane Installation.............................................................................................15

EXP-BP2 Subplane.......................................................................................16

EXP-BP4 Subplane.......................................................................................17

EXP-BP3A Subplane.................................................................................... 18

EXP-BP5 Subplane.......................................................................................19

EXP-BP4A Subplane.................................................................................... 20

EXP-BP6 Subplane.......................................................................................21

EPC-5A Insertion..................................................................................................22

EXP-MC Module Carrier Insertion.......................................................................23

EXP-MX Mass Storage Module Insertion.............................................................24

EXM Module Insertion .........................................................................................24

Connecting Peripherals to the EPC-5A .................................................................25

Monitor.........................................................................................................25

Keyboard ......................................................................................................25

Serial Ports....................................................................................................26

Parallel Printer Port ......................................................................................26

EXP-MX Ports..............................................................................................26

4. BIOS Configuration.................................................................................................27

Introduction...........................................................................................................27

BIOS Setup Screens..............................................................................................27

Main BIOS Setup Menu........................................................................................29

IDE Adapter Sub-menus...............................................................................31

Memory Shadow Sub-Menu.........................................................................33

Boot Options Sub-menu................................................................................34

Keyboard Features Sub-menu.......................................................................36

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EPC-5A Hardware & Software Reference Manual

Advanced Menu ....................................................................................................37

EXM Menu............................................................................................................39

VME Menu............................................................................................................42

Exit Menu..............................................................................................................44

5. Theory of Operation...............................................................................................47

Processor board.....................................................................................................47

Processor and Coprocessor...........................................................................47

Core Logic.............................................................................................................47

Memory ........................................................................................................48

Memory Map................................................................................................48

Peripheral Components .........................................................................................50

Real Time Clock....................................................................................................50

Keyboard Controller..............................................................................................51

ROM and ROM Shadowing..................................................................................51

Embedded Shadow................................................................................................51

Bootable Device Precedence.................................................................................51

Battery...................................................................................................................52

Video Controllers..................................................................................................53

Front Panel LEDs..................................................................................................53

Resetting the EPC-5A ...........................................................................................54

EXM Expansion Interface.....................................................................................54

6. The VMEbus Interface...........................................................................................57

Connectivity..........................................................................................................57

VMEbus System (Slot-1) Controller Functions.....................................................57

Concepts................................................................................................................58

Memory Map................................................................................................58

Direct VMEbus Accesses .............................................................................59

Byte Ordering...............................................................................................60

Slave Accesses from the VMEbus................................................................63

Self Accesses Across the VMEbus...............................................................64

Read-Modify-Write Operations....................................................................64

VMEbus Interrupt Response.........................................................................65

Registers Specific to the EPC-5A..........................................................................66

VMEbus Mapped Registers..........................................................................77

Supported Address Modifiers................................................................................78

Low-Level Programming the VMEbus Interface ..................................................79

VMEbus Accesses........................................................................................79

Low-Level Handling of VMEbus Interrupts.................................................82

7. Connectors...............................................................................................................87

Serial Ports............................................................................................................87

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EPC-5A Hardware & Software Reference Manual

Parallel Port...........................................................................................................88

Keyboard...............................................................................................................88

Speaker Header .....................................................................................................89

Battery Header ......................................................................................................89

8. Upgrades..................................................................................................................91

Memory.................................................................................................................91

9. Troubleshooting & Error Messages ......................................................................93

Troubleshooting ....................................................................................................93

Common Error Messages......................................................................................95

Boot Failures.........................................................................................................101

Phoenix NuBIOS Checkpoints ..........................................................................102

10. Support and Service..............................................................................................107

In North America ..................................................................................................107

Technical Support.........................................................................................107

World Wide Web..........................................................................................107

Repair Services.............................................................................................108

Warranty Repairs..........................................................................................108

Non-Warranty Services.................................................................................108

Arranging Service.........................................................................................109

Other Countries.....................................................................................................110

Appendix A: Chip Set & I/O Map..............................................................................A-1

Appendix B: Interrupts and DMA Channels ............................................................B-1

Interrupts...............................................................................................................B-1

DMA Channels......................................................................................................B-2

Appendix C: Flash Boot Device..................................................................................C-1

Flash Boot Device Reflashing...............................................................................C-3

Reflashing using REFLASH.EXE.........................................................................C-6

User BIOS Extensions...........................................................................................C-8

PicoCard Flash File System...................................................................................C-9

Appendix D: PFormat .................................................................................................D-1

Appendix G: Glossary

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EPC-5A Hardware & Software Reference Manual

List of Illustrations

Figure 2-1. Slot-1 Jumper Location............................................................................... 8

Figure 2-2. Daisy-Chain Signal Concept ....................................................................... 10

Figure 2-3. Backplane Jumpers Required for EPC-5A Subsystem................................ 11

Figure 2-4. VMEbus Backplane Jumper Examples ....................................................... 12

Figure 2-5. VMEbus Jumpers on Rear Wirewrap Pins.................................................. 13

Figure 2-6. VMEbus Jumpers on Front Stake Pins........................................................ 13

Figure 3-1. EXP-B2 Backplane ..................................................................................... 16

Figure 3-2. EXP-BP4 Subplane ..................................................................................... 17

Figure 3-3. EXP-BP3A Subplane .................................................................................. 18

Figure 3-4. EXP-BP5 Subplane ..................................................................................... 19

Figure 3-5. EXP-BP4A Subplane .................................................................................. 20

Figure 3-6. EXP-BP6 Subplane ..................................................................................... 21

Figure 3-7. EXP-MC Module Carrier (side view) ......................................................... 23

Figure 4-1. BIOS Setup Menu Map............................................................................... 28

Figure 4-2. Main BIOS Setup Menu.............................................................................. 29

Figure 4-3. IDE Adapter Sub-menu .............................................................................. 31

Figure 4-4. Memory Shadow Menu............................................................................... 33

Figure 4-5. Boot Options Sub-Menu.............................................................................. 34

Figure 4-6. Keyboard Features Sub-menu ..................................................................... 36

Figure 4-7. Advanced Menu .......................................................................................... 37

Figure 4-8. EXM Menu.................................................................................................. 39

Figure 4-9. Slot Numbering........................................................................................... 40

Figure 4-10. VME Setup Menu...................................................................................... 42

Figure 4-11. Exit Menu.................................................................................................. 44

Figure 6-1. Source of VMEbus Address Lines (Via E-page)......................................... 58

Figure 6-2. Source of VMEbus Address Lines (Via Direct Mapping)........................... 60

Figure 6-3. Little-Endian Byte Order............................................................................. 61

Figure 6-4. Big-Endian Byte-swapping.......................................................................... 62

Figure 8-1. SIMM Memory Location ............................................................................ 92

Figure C-1. Flash Boot Device Memory Map................................................................C-2

Figure C-2. Flash Boot Device Recovery Mechanism...................................................C-5

Figure C-3. PicoCard Flash File System........................................................................C-9

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EPC-5A Hardware & Software Reference Manual

List of Tables

Table 1-1. EPC-5A Environmental and Electrical Specifications.................................. 4

Table 2-1. VME Slots Available.................................................................................... 9

Table 2-2. EPC-5A Jumpers .......................................................................................... 13

Table 5-1. R400EX Features ......................................................................................... 48

Table 6-1. Direct Mapping............................................................................................. 59

Table 7-1. Serial Port Pinout ......................................................................................... 87

Table 7-2. Parallel Port Pinout....................................................................................... 88

Table 7-3. Keyboard Connector Pinout ......................................................................... 88

Table 7-4. Speaker Header Pinout................................................................................. 89

Table 7-5. Battery Header Pinout .................................................................................. 89

Table 9-1. Phoenix NuBIOS Checkpoint Codes............................................................104

Table 9-2. Phoenix NuBIOS Auxiliary Checkpoint Codes............................................105

Table 9-3. Phoenix NuBIOS Boot Block Checkpoint Codes.........................................105

Table B-1. Interrupts......................................................................................................B-1

Table B-2. DMA Channels ............................................................................................B-2

Table C-1. FBD Object Placement ................................................................................C-3

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1. Product Description

Purpose

This manual was written to provide detailed hardware reference information for OEMs, system integrators, and other engineers using the EPC-5A as a component of their VMEbus systems. The reader should be able to install the EPC-5A and configure the system based on the information in this manual.

About this Manual

This manual assumes that the reader has good familiarity with PC systems based on the Intel x86 architecture and familiarity with VMEbus architecture. For more information about EPConnect, which is the RadiSys programming interface to the Microsoft Windows APIs, consult the appropriate EPConnect/VME manual.

The information in this manual is organized into the following sections:

Front Matter Warranty Information, Table of Contents, List of Figures and Tables. Chapter 1 Product Description. Provides an introduction to the EPC-5A, a brief

description of the features provided, and a table of specifications.

Chapter 2 Before Installation. Covers the details of configuring the EPC-5A,

selecting the proper slot location, and installing backplane jumpers.

Chapter 3 Installation. Describes the process installing the EPC-5A in a VME

mainframe using a subplane, and connecting peripherals.

Chapter 4 Configuring the BIOS Setup. Provides detailed information about

how to configure the EPC-5A’s BIOS.

Chapter 5 Theory of Operation. Describes the processor board, memory, ROM

shadowing, video, front panel LEDs, and EXM expansion.

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EPC-5A Hardware & Software Reference Manual

Chapter 6 Programming the VMEbus Interface. Describes Slot-1 controller

functions, slave- and self-accesses, and initializing and programming the VMEbus interface.

Chapter 7 Connectors. Describes pinouts for the serial and parallel port

connectors, plus the keyboard, speaker, and battery headers.

Chapter 8 Upgrades. Lists possible memory upgrades for the EPC-5A. Chapter 9 Troubleshooting and Error Messages. Describes various error

conditions and recovery procedures.

Chapter 10 Support and Service. Provides contact information for RadiSys

Technical Support.

Appendix A Chipset and I/O Map. Appendix B Interrupts and DMA Channels. Appendix C Flash Boot Device. Appendix D Pformat. For use with EXM-2A. Appendix G Glossary. A guide to terminology and acronyms used in this manual.

Notational Conventions

The following notational conventions are used throughout this manual.

FFh Hexadecimal numbers are indicated by an “h” suffix.

* In signal definitions, the asterisk (*) following a signal name

indicates an active low signal; for example IOCHECK*.

✏ Note

Notes are used to provide the reader with important information or explanatory information.

▲

! WARNING

▲

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CAUTION

Cautions are used to indicate the potential for equipment damage, software failure, or minor personal injury.

Warnings are used to indicate potential risk of serious physical harm or injury.

Chapter 1: Product Description

Product Overview

The EPC-5A is a PC/AT compatible embedded CPU module containing the following:

• 100 MHz Intel486 DX4 processor

• RadiSys R400EX chipset

• 16 Kbytes of cache and math co-processor on-chip

• 4 MB to 256 MB of DRAM memory

• Keyboard interface

2 standard 9-pin DTE serial ports (COM1 & COM2)

•

1 standard output-only parallel port (LPT1)

•

Time-of-day clock with user-replaceable battery

•

Phoenix 486 BIOS version 4.05

•

VMEbus interface

•

EXM expansion interface

•

The EPC-5A form factor has been designed to the VMEbus specification (6U). It provides direct communication to all three VMEbus address spaces (A32, A24, & A16). The EPC-5A DRAM permits dual-ported access from both the PC side and the VME side.

The EXM expansion interface is electrically similar to the 16-bit PC/AT ISA bus. Video is provided through an add-in card called an EXM (EXpansion Module). Mass storage can be added via the EXP-MX Mass Storage module inside the VME chassis or externally via other EXMs that provide an IDE or a SCSI interface. Other EXMs are available to provide additional peripherals such as serial ports (RS232 or RS422), an internal modem, flash memory (and accompanying flash file system drivers), timer/counter, PCMCIA adapter and Ethernet controllers. Also, an adapter module (EXP-AM) can be used to install a single 8-bit PC/AT add-in short card.

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EPC-5A Hardware & Software Reference Manual

Specifications

Environmental

Temperature operating 0° to 60° C

storage -40° to 85° C

Humidity operating 5 - 95% (non-condensing)

storage 5 - 95% (non-condensing)

Vibration operating .015"PP 2.5g (max) 5-2000 Hz

storage .030"PP 5g (max) 5-2000 Hz

Shock operating 30g 11 msec duration

storage 50g 11 msec duration

Electrical

+5V +12V -12V

100 MHz - DX4 maximum 6.5 A * 100 mA 100 mA

typical 5.5 A * 100 mA 100 mA

* Use of the P2 connector is recommended to support the current requirements of

the EPC5A.

Table 1-1. EPC-5A Environmental and Electrical Specifications.

Differences Between EPC-5 and EPC-5A

The EPC-5A differs from the EPC-5 in the following ways:

1. The System BIOS is based on Phoenix Technologies NuBIOS revision

4.05. The EPC-5 uses an Award BIOS.

2. The EXP-MS SCSI module is not supported.

3. BIOS setup configuration is available only during the boot sequence, it is not available after the OS boots. The CTRL-ALT-ESC key sequence no longer invokes setup.

4. The EPC-5A supports CMOS Save and Restore (CSR) that allows backup and restoration of the contents of CMOS RAM to and from the Flash Boot Device (FBD).

5. Flash File System (FFS) support for flash EXMs is based on Phoenix Technologies PicoFlash and includes read /write capability. The Xformat

based FFS is no longer supported for flash. It is still used for SRAM and VME boot image creation.Use the Pformat utility that ships with this product.

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Chapter 1: Product Description

6. Support for “User BIOS Extensions” which allows, through BIOS extensions, booting from VME or EXM-2A, etc. Note that EXM-2A’s are supported while the EXM-2 is not.

7. The System BIOS supports disk autotyping and disks larger than 528MB capacity.

8. The Flash File System can be installed as a DOS device driver, therefore flash can be installed as the second drive even when SCSI is the boot device (EXM-16).

9. IRQ 12 is only available to the EXMBus as a build-time option.

10. Slave memory is mapped to the VME bus in the following increments: 2MB, 4MB, 8MB, 10MB, 16MB, 32MB, 64MB. However, system memory increments are no longer restricted to this set.

11. AT bus mastering is not supported.

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EPC-5A Hardware & Software Reference Manual

NOTES

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2. Before Installation

Unpack the EPC-5A and inspect it for shipping damage.

▲

The EPC-5A, like most electronic devices, is susceptible to electrostatic discharge (ESD) damage. ESD damage is not always immediately obvious. It can cause a partial breakdown in semiconductor devices that might not result in immediate failure.

CAUTION

Do not remove the EPC-5A module from its anti-static bag unless you are in a static-free environment.

Configuring the EPC-5A

The EPC-5A can be user-configured to provide standard VMEbus Slot-1 functionality. The Slot-1 configuration option is enabled (default) by installing the Slot-1 shunt (jumper) on the processor board (see Figure 1, page 4). Removing the jumper disables Slot-1 functionality. When the EPC-5A is configured as the Slot-1 controller, it performs all the standard VMEbus system control functions. See Chapter 5, Theory of Operation, for more details on Slot-1 controller functions.

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EPC-5A Hardware & Software Reference Manual

Jumpers

Slot-1 C ontroller

Jumper

Front Panel

JP1

Figure 2-1. Slot-1 Jumper Location.

Additionally, the EPC-5A has another jumper (see Figure 2-1 above) that rarely needs to be changed - the MODID jumper on JP1. The EPC-5A uses pin 30, Row A of the P2 connector for module identification. If the J2 backplane is other than a standard VME or VXI backplane (e.g., a VSB backplane) or Pin 30, Row A is defined for another purpose, remove this jumper.

Selecting the EPC-5A Slot Location

There are two main considerations in determining where the EPC-5A should be positioned in the chassis.

When used as a Slot-1 controller, and per the VMEbus specification (Rule

•

3.3), a Slot-1 controller must be in Slot 1. All other boards must be to the right of the Slot-1 controller.

The EPC-5A connects to its peripherals via a subplane which extends to the

•

right of the EPC-5A. Make sure that the location you choose provides sufficient room for all the attached peripherals (EXMs and mass storage module).

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Chapter 2: Before Installation

The EPC-5A plus EXM expansion modules plus any mass storage module can be considered together as a single subsystem. Use the following worksheet to determine the total number of VME expansion interface slots your particular subsystem configuration requires.

Product VME Slots Total

EPC-5A (Includes first two EXM modules) 2 Additional EXP-MC(s) (Holds additional two EXM modules) EXP-AM 2 Mass Storage Module (EXP-MX including EXP-MX200A and greater) 2 or EXP-MX200 3

Total VMEbus slots used ...........................

Table 2-1. VME Slots Available.

Once you have determined where the EPC-5A subsystem will be physically located in the chassis, the VME backplane must be jumpered appropriately.

each

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EPC-5A Hardware & Software Reference Manual

Installing the VMEbus Backplane Jumpers

The VMEbus specification provides four bus grant signals (BG0 - BG3) and one interrupt acknowledge signal ( specifications, all boards (that plug into the backplane) are required to correctly handle these signals. All slots that do not have a board plugged into the backplane (i.e. empty slots and slots occupied by EXMs or mass storage modules), need to be jumpered to allow the signals to pass through to other boards in the system.

IACK) via daisy-chain lines. Per the VMEbus

xxxIN

xxxOUT

xxxIN

xxxOUT

xxxIN

xxxOUT

xxxIN

xxxOUT

VMEbus Slots

Figure 2-2. Daisy-Chain Signal Concept.

The Slot-1 controller board initiates each daisy-chain signal. Each VMEbus slot to the right of the Slot-1 controller must pass through each of the daisy-chain signals. For each VMEbus slot, pin (e.g. BG0In to BG0Out, BG1In to BG1Out,...,IackIn to IackOut) either through the board in that slot or by jumpers. Some boards correctly pass all of these signals, some boards handle some of these signals and not others, and some

boards (typically “dumb” slave boards) may not handle any of these signals. Check the manual for each board to be installed to determine if these signals are passed through correctly. If they are not, or if the VMEbus slot is empty, all (or some) of these signals must be jumpered. See the following figures for examples.

xxxIn pin must be connected to its corresponding xxxOut

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Chapter 2: Before Installation

indicates jumper needed

Figure 2-3. Backplane Jumpers Required for EPC-5A Subsystem.

The figure above shows the EPC-5A subsystem. Note that the left-most slot does not require any jumpers. All other slots occupied by the subsystem require all five jumpers be installed.

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EPC-5A Hardware & Software Reference Manual

BG0

BG1

BG2

BG3

IACK

Single Board Computer

that only handles

IACK & BG3

"Dumb" Slave

Does not handle

any of the signals

Figure 2-4. VMEbus Backplane Jumper Examples.

Once you have determined where the jumpers need to be, you must determine how to jumper your particular backplane. Different backplane manufacturers handle this in different ways; some provide stake pins on the rear of the backplane while others provide stake pins on the front of the backplane. These stake pins can be located in several different places.

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Chapter 2: Before Installation

J1 Connector

BG0 BG1 BG2 BG3

IACK

Figure 2-5. VMEbus Jumpers

on Rear Wirewrap Pins.

Figure 2-6. VMEbus Jumpers

J1 Connector

BG0 BG1 BG2

BG3

IACK

on Front Stake Pins.

If the stake pins are on the rear of the backplane, the most common location is in the middle of the J1 connector as shown in Figure 2-5 below. This can be just these pins extended or all pins extended for wirewrapping.

The stake pins (front or rear) can also be located adjacent to the slot being jumpered as shown in Figure 2-6 above. Typically, the stake pins are located between the slot being jumpered and the next lower-numbered slot (e.g. jumpers for Slot 6 would be located adjacent to Slot 6 between Slots 5 and 6).

Consult your VME chassis reference manual or contact the chassis manufacturer if you are unsure where to jumper your particular system.

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EPC-5A Hardware & Software Reference Manual

Jumpers

The complete table of EPC-5A jumpers is shown below. Jumpers are shown in Figure 2-1.

Jumper Function Description

POST

(JP1 [1-2])

FFLASH

(JP1[3-4])

BBEN

(JP1 [5-6])

FWEN

(JP1 [7-8])

MODID

(JP1 [9-10])

SPEAKER

(H2)

SLOT1

(H5)

Manufacturing loop enable Force BIOS recovery Install this jumper to force a BIOS

FBD boot block write enable FBD write enable (except boot block)

Mod ID routing Remove this jumper for non-

Speaker Speaker header.

Slot 1 Functionality Install this jumper to enable Slot 1

Install this jumper to enter the manufacturing POST loop.

recovery during the boot process. Install this jumper to enable writes to the boot block of the FBD. Install this jumper to enable writes to the FBD main blocks #1, #3, and #4 and parameter blocks #1 and #2.

standard VME backplanes.

functionality.

Page 14

Table 2-2. EPC-5A Jumpers.

3. Installation

▲

The EPC-5A is not designed to be inserted or removed while the chassis is powered up.

▲

Do not remove any modules from their anti-static bags unless you are in a static-free environment. The EPC-5A module, like most other electronic devices, is susceptible to electrostatic discharge (ESD) damage. ESD damage is not always immediately obvious. It can cause a partial breakdown in semiconductor devices that might not result in immediate failure.

▲

CAUTION

During all of this installation process, make sure that power to your system is OFF.

CAUTION

Make sure that the installation process described here is performed in a static-free environment.

CAUTION

The EXP-MX mass storage module contains a delicate hard disk. Use care during installation.

Subplane Installation

Subplanes are printed-circuit boards with connectors on both sides. A subplane provides several functions. Primarily it acts as the PC/AT bus. Additionally, it provides power from the VMEbus backplane to the EPC-5A and expansion modules. How subplanes function is discussed in detail in Chapter 5, Theory of Operation.

Locate the appropriate subsection for the subplane you are using either by name or by picture. Follow the directions in the appropriate subsection. A small bag of bolts, nylon washers, and nuts is provided for optionally securing the subplane to the VME backplane. If these are used, be careful not to over tighten the bolts. Over-tightening causes the subplane to bend and may cause EXM failure due to poor contact.

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EPC-5A Hardware & Software Reference Manual

EXP-BP2 Subplane

This subplane is used in the smallest configuration, where only the EPC-5A processor module occupies VME slot space. It provides connectivity for two EXM modules within the EPC-5A (e.g., a graphics controller and a network or disk controller). The EXP-BP2 is an L-shaped board with three connectors on each side.

After jumpering the backplane, plug the subplane into the VMEbus backplane such that the P2 connector on the back of the 4-row DIN is pressed into the J2 connector of the left-most VMEbus slot that the EPC-5A subsystem will occupy.

The subplane has holes for optional bolting to the VMEbus backplane using the screws included.

The lower EXM connector is denoted as EXM slot 0 and the upper as slot 1 as shown in the diagram. This information will be needed later when configuring the installed EXMs.

Page 16

Figure 3-1. EXP-BP2 Subplane.

Chapter 3: Installation

EXP-BP4 Subplane

The EXP-BP4 subplane is used to couple an EPC-5A processor module with an EXP-MX Mass Storage module. The EXP-BP4 is a T-shaped board with four connectors on the front side and three on the rear.

The subplane has holes for optional bolting to the VMEbus backplane using the screws included.

The EXM slot numbers are shown in the drawing.

Figure 3-2. EXP-BP4 Subplane.

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EPC-5A Hardware & Software Reference Manual

Figure 3-3. EXP-BP3A Subplane.

EXP-BP3A Subplane

The EXP-BP3A subplane is used to add an EXP-MC Module Carrier for the addition of one or two more EXM modules to an EPC-5A processor module. The EXP-BP3A has five connectors on each side.

The subplane has holes for optional bolting to the VMEbus backplane using the screws included.

The EXM slot numbers are shown in the drawing.

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Chapter 3: Installation

EXP-BP5 Subplane

The EXP-BP5 subplane is used in a configuration to couple an EPC-5A processor module with an EXP-MC Module Carrier and an EXP-MX Mass Storage module. The EXP-BP5 has six connectors on the front side and five on the rear.

The subplane has holes for optional bolting to the VMEbus backplane using the screws included.

The EXM slot numbers are shown in the drawing.

Figure 3-4. EXP-BP5 Subplane.

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EPC-5A Hardware & Software Reference Manual

EXP-BP4A Subplane

The EXP-BP4A subplane is used to add either

• two EXP-MC Module Carriers

• one EXP-AM Adapter Module.

The EXP-BP4A has seven connectors on each side.

The subplane has holes for optional bolting to the VMEbus backplane using the screws included.

The EXM slot numbers are shown in the drawing.

Page 20

Figure 3-5. EXP-BP4A Subplane.

Chapter 3: Installation

EXP-BP6 Subplane

The EXP-BP6 subplane is used in a configuration to couple an EPC-5A processor module with an EXP-MX Mass Storage module and either

• two EXP-MC Module

Carriers

one EXP-AM

•

Adapter Module.

The EXP-BP6 has eight connectors on the front side and seven on the rear.

Plug the subplane into the VMEbus backplane such that the P2 connector on the back of the 4-row DIN is pressed into the J2 connector of the leftmost VMEbus slot that the EPC-5A subsystem will occupy.

The subplane has holes for optional bolting to the VMEbus backplane using the screws included.

Figure 3-6. EXP-BP6 Subplane.

The EXM slot numbers are shown in the drawing.

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EPC-5A Hardware & Software Reference Manual

EPC-5A Insertion

After installing the subplane, the EPC-5A processor module can be inserted into the VMEbus chassis.

▲

q Make sure the ejector handles are in the normal (non-eject) position. (Push

the top handle down and the bottom handle up so that the handles are no t tilted.)

q Slide the EPC-5A module into the left-most slot occupied by the subplane.

Use firm pressure on the handles to mate the module with the connectors.

q Tighten the retaining screws in the top and bottom of the front panel to

ensure proper connector mating and prevent loosening of the module due to vibration.

CAUTION

Make sure that power to your VME system is off. The EPC-5A module is not designed to be inserted or removed from a live backplane.

CAUTION

When inserting the EPC-5A module, avoid touching the circuit board and connector pins, and make sure the environment is static-free.

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Chapter 3: Installation

EXP-MC Module Carrier Insertion

If one or more EXP-MC Module Carriers are part of the configuration, they are inserted into the slot(s) immediately to the right of the EPC-5A. The Module Carrier can only be used in a VMEbus slot where the subplane has both EXM connectors. Simply slide the Module Carrier into place and tighten the two top and bottom retaining screws.

The following figure shows a side view of an EXP-MC containing two EXMs plugged into a subplane that is plugged into a VMEbus backplane.

VMEbus

EXP-MC Module Carrier Subplane

EXM

Expansion Module

EXM

Expansion Module

Figure 3-7. EXP-MC Module Carrier (side view).

Backplane

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EPC-5A Hardware & Software Reference Manual

EXP-MX Mass Storage Module Insertion

▲

The EXM-MX Mass Storage module is always inserted as the rightmost module of the EPC-5A subsystem. Insert it so that its rear connector mates with the lower rightmost connector of the subplane. Insert it using adequate continuous force rather than tapping or hammering on it. Tighten the top and bottom front-panel screws to hold it firmly in place.

CAUTION

Handle the mass storage module with care. Avoid sudden drops or jolts.

CAUTION

When inserting the module, avoid touching the circuit board and connector pins, and make sure the environment is static-free.

EXM Module Insertion

One or two EXMs may be installed through the front panels of the EPC-5A and each EXP-MC Module Carrier. To install an EXM:

q Remove and save the blank face plate from the desired slot.

q Slide the EXM into place in the card guides. Push firmly on the EXM front

panel until the EXM card-edge connector is firmly seated in the subplane connector.

q Tighten the thumb screws on the EXM’s face plate.

Each EXM must be configured in the EPC-5A’s BIOS to set how the EXM should be initialized on power-up. This information is slot specific. Although EXMs can be installed in any available carrier slot, once an EXM is installed, it cannot be moved without re-configuring the BIOS setup. Configuring the BIOS setup is discussed in the next chapter.

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Connecting Peripherals to the EPC-5A

▲

The final step of installation is connecting peripherals, typically a video display and keyboard, but also perhaps a mouse, modem, printer, etc. Unless otherwise noted, all connectors are compatible with those found on IBM-compatible desktop PCs, and therefore pin-by-pin details are not given in this chapter. Pin-outs are specified in Chapter 7, Connectors.

CAUTION

Do not plug in any cable connector into the front panel connectors while the system is powered on. In general, electronic equipment is not designed to withstand potential damage that could arise from fluctuations in power. Never plug in a serial or parallel device, keyboard, transceiver, monitor, or other component while the system is on.

Monitor

Connection of a monitor requires the use of an EXM video controller. Consult the video controller manual for details.

The monitor should be attached and powered on prior to applying power to the EPC-5A. If this is not done, the EPC-5A cannot detect the monitor type and the video adapter may not be initialized correctly.

Keyboard

The front panel contains a round 6-pin mini-DIN jack for connecting a keyboard. The jack is compatible with that of some newer PCs, and is not compatible with the previous style of larger 5-pin PC/AT keyboard connectors. However, an adapter cable is provided with the EPC-5A so either type of PC keyboard can be used with the EPC-5A.

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EPC-5A Hardware & Software Reference Manual

Serial Ports

The front panel contains two DB-9 DTE serial-port connectors. They are standard RS-232 serial communication ports that are 16C450-compatible. Many current PC/AT computers now incorporate 16C550 UARTs.

The EPC-5A serial ports may be used for connecting a mouse, modem, serial printer, RS-232 link, etc.

Parallel Printer Port

The output-only parallel port on the front panel is a DB-25 connector that is completely compatible with the corresponding LPT1 connector on IBM PCs and compatibles. Typically it is used to connect printers and software security keys.

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4. BIOS Configuration

Introduction

The EPC-5A uses the Phoenix NuBIOS to configure and select various system options. This section details the various menus and sub-menus that are used to configure the system. This section is written as though you are setting up each field in sequence and for the first time. Your system may be pre-configured and require very little setup.

Some error messages might occur during the execution of the BIOS initialization sequence. If errors occur during the power-on self-test (POST), the BIOS will display the error on the appropriate line of the screen display and, depending on how your system is configured, will either pause or attempt to continue.

BIOS Setup Screens

The EPC-5A’s BIOS contains a setup function to display and modify the system configuration. This information is maintained in the EPC-5A’s nonvolatile CMOS RAM and is used by the BIOS to initialize the EPC-5A hardware.

The BIOS Setup can only be entered during the system reset process, following a power-up, front panel reset, or equivalent. Press the F2 key when prompted to enter Setup.

Note

✏

BIOS setup is accomplished by making selections from a series of menus, as shown in the following figure.

The “Press F2 to Enter Setup” prompt may be suppressed (see Boot Options Sub-menu, Setup Prompt), but the F2 key still invokes the BIOS Setup program during system reset.

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EPC-5A Hardware & Software Reference Manual

Main BIOS Setup Menu

EXIT

Exit Menu

IDE Adapter

Sub-Menu

Memory Shadow

Sub-Menu

Boot Sequence

Sub-Menu

Keyboard Features

Sub-Menu

MAI

ADVANCE

Advanced Menu

EXM

EXM Menu

VME

VME Menu

Figure 4-1. BIOS Setup Menu Map.

Use the up and down cursor (arrow) keys to move from field to field. Use the right and left arrows to move between the menus shown in the menu bar at the top of the screen. If you use the arrow keys to leave a menu and then return, your active field is always at the beginning of the menu. If you select a sub-menu and then return to the main menu, you return to that sub-menu heading.

Fields with a triangle to the left are actually sub-menu headings; press Enter when the cursor rests on one of these headings to reach that sub-menu. For most fields, position the cursor at the field and from the numeric keypad, press the + and - keys to rotate through the available choices. Certain numeric fields can also be entered via the keyboard. Once the entry has been changed to appear as desired, use the up and down arrow to move to the next field.

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Chapter 4: BIOS Configuration

Main BIOS Setup Menu

The Main BIOS Setup Menu is shown below.

Main Advanced EXM VME Exit

System Time: [16:17:18]

System Date: [03/01/96] Diskette A: [Not Installed] Diskette B: [Not Installed]

IDE Adapter 0 Master: (C: 704 Mb) IDE Adapter 0 Slave: (None)

Video System: [EGA / VGA]

Memory Shadow Boot Sequence: [A: then C:] Numlock: [Off]

System Memory: 640 KB Extended Memory: 31 MB

F1 Help Select Item -/+ Change Values F9 Setup Defaults ESC Exit Select Menu Enter Select Sub-Menu F10 Previous Values

Figure 4-2. Main BIOS Setup Menu.

Item Specific Help

<Tab>, <Shift-Tab>, or <Enter> selects field.

The fields in each menu and sub-menu are explained below. Additional help information is available in the help area on the Setup screen.

System Time:/System Date

These values are changed by moving to each field and typing in the desired entry. Use the Tab key to move from hours to minutes to seconds, or from months to days to years.

Diskette A:/Diskette B

This field identifies the type of floppy disk drive installed as the A:/B: drive. Possible settings are Not Installed, 360 KB, 5¼", 720 KB, 3½", 1.2 MB, 5¼", 1.44 MB, 3½", and 2.88 MB, 3½". The BIOS defaults to Not Installed for drives A: and B:.

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EPC-5A Hardware & Software Reference Manual

IDE Adapter 0 Master/Slave: Sub-menus

These fields are headings for menus that allow entering complete disk drive information. Once the information is entered for the drive, the entry in the Main Menu shows the drive selected. See IDE Adapter Sub-Menus for more information.

Video System

Use this field to select among the different video options available. Select from EGA/VGA, CGA 80x25, or monochrome. The default is “EGA/VGA”. The

EPC-5A’s video is VGA, supplied by an EXM Video Module.

Memory Shadow Sub-menu

The term “Memory Shadow” refers to the technique of copying information from an extension ROM into DRAM and accessing it in this alternate memory location. See Memory Shadow Sub-Menu for more information.

Boot Sequence Sub-menu

The Boot Sequence Sub-menu allows you to change the boot delay, the boot sequence, and to disable several displays during the boot process, such as the SETUP prompt, POST errors, floppy drive check, and summary screen. When the boot sequence has been specified in the Boot Sequence sub-menu, the sequence is displayed in the Boot Sequence field of the Main menu.

Keyboard Features (Numlock) Sub-menu

Use this menu to enable or disable various keyboard features, including the Numlock key, the key click, and the keyboard auto-repeat rate and delay. The Numlock entry in the Main Menu displays the Numlock setting.

System Memory

This field is not editable and displays the amount of conventional memory (below 1MB). No user interaction is required.

Extended Memory

This field is not editable and displays the amount of extended memory (above 1MB). No user interaction is required.

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Chapter 4: BIOS Configuration

IDE Adapter Sub-menus

There are a total of two IDE adapter sub-menus for the primary hard disk controller, in a master and slave drive configuration. The EPC-5A hard disk is controlled by the settings for IDE Adapter 0 Master. To see or reconfigure the detailed characteristics of the primary hard disk, select the IDE Adapter 0 Master item from the Main BIOS Setup. The IDE Adapter 0 Master sub-menu is shown below.

IDE Adapter 0 Master (C: 704Mb)

Autotype Fixed Disk: [Press Enter]

Type: [User] 704 Mb Cylinders: [ 1365] Heads: [ 16] Sectors/Track: [ 63] Write Precomp: [None]

LBA Mode Control: [Disabled]

F1 Help Select Item -/+ Change Values F9 Setup Defaults ESC Exit Select Menu Enter Select Sub-Menu F10 Previous Values

Item Specific Help

<Tab>, <Shift-Tab>, or <Enter> selects field.

Figure 4-3. IDE Adapter Sub-menu.

Autotype Fixed Disk

Use this option when setting up new disks. This option allows the BIOS to determine the proper settings of the disk based on information on the disk, which is detected by the EPC-5A BIOS for drives that comply with ANSI specifications. Press the Enter key to invoke this function.

Existing (formatted) disks must be set up using the same parameters that were used originally when the disk was formatted. You must enter the specific cylinder, head, and sector information. This information is usually listed on the label attached to the

drive at the factory. Select the “User” type described below to describe an existing formatted disk.

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EPC-5A Hardware & Software Reference Manual

Type

If you are using a pre-configured system, you probably have an IDE hard disk drive.

Select “None” if you are not using an IDE hard disk drive. In the case for which you have an IDE disk but cannot employ the “Autotype” feature, then select “User” for the Type and enter the correct drive values for cylinders, heads, sectors/track, and write precompensation from the label attached at the factory. For disks not supplied by RadiSys, consult the disk drive’s documentation.

If you specify “Auto” for the hard disk type, the BIOS will query the hard disk for its parameters whenever the POST runs. If a hard disk type is set to “Auto”, but no hard disk is actually present, the BIOS will continue to query the (non-existent) hard disk until it times out, adding a number of seconds to the duration of the POST.

Note that there are some restrictions when setting up devices on the EPC-5A. If you plan to boot from a non-IDE device, such as a SCSI hard disk, set the C: drive type as “None” and use the BIOS extension.

LBA Mode Control

When enabled, this option allows the System BIOS to reference hard disk data as logical blocks instead of using the traditional Cyliners/Heads/Sectors (CHS) method. This option can only be used if both the hard disk being configured and the operating system support Logical Block Addressing (LBA). If disabled, then CHS mode is used. Note that autotyping may change this value if the hard disk reports that it supports LBA. The default is “Disabled.”

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Chapter 4: BIOS Configuration

Memory Shadow Sub-Menu

The term “shadowing” refers to the technique of copying BIOS extensions from ROM into DRAM and accessing them from DRAM. This allows the CPU to access the BIOS extensions much more quickly and generally increases system performance if many calls to the BIOS extensions are made. The Memory Shadow Sub-menu is shown below.

Memory Shadow

System Shadow: Enabled Video Shadow: Enabled

Regions with Legacy Expansion ROMs: C800-CBFF: [Disabled] CC00-CFFF: [Disabled] D000-D3FF: [Disabled] D400-D7FF: [Disabled] D800-DBFF: [Disabled] DC00-DFFF: [Disabled]

Item Specific Help

<Tab>, <Shift-Tab>, or <Enter> selects field.

F1 Help Select Item -/+ Change Values F9 Setup Defaults ESC Exit Select Menu Enter Select Sub-Menu F10 Previous Values

Figure 4-4. Memory Shadow Menu.

The shadow regions should be used only if an EXMbus card is installed in the system that contains a BIOS extension (ROM) although there is no effect on the system if a region is shadowed that does not contain a BIOS extension. Note that each shadow region in the setup menu is 16KB in size. Multiple shadow regions may have to be enabled if the BIOS extension to be shadowed is larger than 16KB.

System Shadow/Video Shadow

These options are not editable since the System and VGA BIOS are always shadowed.

Shadow Memory Regions

These options enable or disable shadowing for the associated memory region. The default is “Disabled”.

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EPC-5A Hardware & Software Reference Manual

ppy

]

Boot Options Sub-menu

Use the Boot Options sub-menu to change the boot sequence options. Select the Boot Options sub-menu by clicking on the Boot Sequence item in the Main BIOS Setup screen. The Boot Options Sub-menu is shown below.

Boot Options

Item S

ecific Hel

Boot Delay: [0] Boot Se SETUP Prom POST Errors: [Enabled] Flo Summary Screen: [Enabled]

F1 Help Select Item -/+ Change Values F9 Setup Defaults ESC Exit Select Menu Enter Select Sub-Menu F10 Previous Values

uence: [A: then C:

t: [Enabled]

Check: [Enabled]

<Tab>, <Shift-Tab>, or <Enter> selects field.

Figure 4-5. Boot Options Sub-menu.

Boot Delay

Use this option to set the system to delay booting for a time period from 0 through 255 seconds. This allows for long start up times on boot devices that spin up slowly. The

default is “0” seconds.

Boot Sequence

This option is used to define how the system treats floppy drive A: when booting. Booting can occur from a floppy in the A: drive or directly from the fixed disk drive. To reduce the amount of time required to boot, the boot sequence should be set to “C: only”. Note that the C: drive may be either an IDE, VME or Flash drive. The options are as follows:

1. A: then C: Used to boot from the floppy drive, or if no floppy disk is present in the A: drive, boot from the C: drive.

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Chapter 4: BIOS Configuration

2. C: then A: Used to boot from the C: drive, or if none is present, boot from the A: drive.

3. C: only: Used to boot from the C: drive without searching for an A: drive.

The default is “A: then C:”.

The setting chosen here displays in the Boot Sequence Sub-Menu prompt in the Main BIOS Setup screen.

Setup Prompt

This option is used to enable or disable the message “Press F2 to enter Setup.” Even if the message is disabled, the F2 key can still be pressed at the appropriate time to enter the Setup Menu. The default is “Enabled”.

POST Errors

This option is used to stop during the boot process if the POST encounters errors. Otherwise, the system continues to attempt to boot despite any startup error messages that display. Note that this option only affects those errors defined as boot failures. See Chapter 9, Troubleshooting and Error Messages, for a list of those failures defined as boot failures that are configured to halt the system. The default is “Enabled”.

Floppy Check

This option is used to enable or disable the floppy drive search during the boot. To speed up booting, the floppy check should be disabled. It is still possible to boot from the A: drive even with the floppy check disabled. The default is “Enabled”.

Summary Screen

This option is used to enable or disable a summary of the system configuration, which displays before the operating system starts to load. To speed up booting, disable the summary screen. The default is “Enabled”.

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EPC-5A Hardware & Software Reference Manual

]

Keyboard Features Sub-menu

The Keyboard Features Sub-menu allows you to enable or disable various keyboard features. To access the keyboard Features menu, select Numlock in the Main BIOS Setup screen. The Keyboard Features Sub-menu is shown below.

Keyboard Features

Item S

ecific Hel

NumLock: [On

Click: [Disabled]

board auto-repeat rate: [30/sec]

Ke Ke

board auto-repeat delay: [1/4 sec]

F1 Help Select Item -/+ Change Values F9 Setup Defaults ESC Exit Select Menu Enter Select Sub-Menu F10 Previous Values

<Tab>, <Shift-Tab>, or <Enter> selects field.

Figure 4-6. Keyboard Features Sub-menu.

Numlock

Use this option to enable or disable the Numlock feature of the keyboard. Numlock on

enables the use of the keypad numbers. The default is “Auto.”

Key Click

Use this option to enable or disable the key click feature on the keyboard. If enabled, the keyboard produces an audible click each time a key is pressed. The default is “Disabled”.

Keyboard auto-repeat rate

Use this option to set the auto-repeat rate if you hold a key down on the keyboard. The rate can be set to one of: “2/sec”, “6/sec”, “10/sec”, “13.3/sec”, “18.5/sec”, “21.8/sec”, 26.7/sec”, and “30/sec”. The default rate is “30/sec”.

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Chapter 4: BIOS Configuration

Keyboard auto-repeat delay

Use this option to set the delay between when a key is pressed and when the auto-

repeat feature begins. The options are “1/4 sec”, “1/2 sec”, “3/4 sec”, and “1 sec” . The default delay is “1/4 sec”.

When you are finished with this menu, press ESC to exit back to the Main BIOS Setup screen.

Advanced Menu

This menu controls advanced setup features, such as the 486 internal L1 cache , large disk access modes, and user BIOS extension addresses. You access this menu by selecting Advanced from the Main BIOS Setup menu.

Main Advanced EXM VME Exit

Warning!

Setting items on this menu to incorrect values may cause your system to malfunction.

L1 Cache [Enabled]

Large Disk Access Mode: [DOS] User BIOS Extensions

BIOS Extension 1 BIOS Extension Offset in FBD: [Disabled] Destination Address: [D0000H]

BIOS Extension Size: [2000H]

F1 Help ↑↓ Select Item -/+ Change Values F9 Setup Defaults ESC Exit ←→ Select Menu Enter Select Sub-Menu F10 Previous Values

Figure 4-7. Advanced Menu.

Item Specific Help

<Tab>, <Shift-Tab>, or <Enter> selects field.

L1 Cache

This option controls the internal cache. The default is enabled. Disabling the internal cache can negatively impact system performance.

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EPC-5A Hardware & Software Reference Manual

Large Disk Access Mode

If a hard disk larger than 528MB is being used, this selection should be set to “DOS” if running MS-DOS, or set to “Other” if using a different operating system. When set to “DOS”, this selection causes the System BIOS to perform cylinder/head translation if the drive is configured in Setup to have more than 1024 cylinders. The default is “DOS”.

User BIOS Extensions

These items control the loading (shadowing) of BIOS extensions contained in the FBD main block #3. Note that there are actually three groups of Setup items to control the shadowing of up to three BIOS extensions. The screen graphic only shows the first group.

Two extensions ship with the EPC-5A. The PicoFlash BIOS offset is 48000h, and the size is 2000h. The vRom BIOS offset is 4A000h, and the size is 4000h.

BIOS Extension Offset in FBD

This option selects the source address of the BIOS extension located in the FBD. The address is an offset from the base of the FBD. The offset range is between 46000h through 5FFFFh in 8KB increments. The default is “Disabled”.

Destination Address

This option selects the target address of the BIOS extension which can range from C0000h through DFFFFh in 8KB increments. The default is “C8000h”.

BIOS Extension Size

This option selects the number of bytes to copy from the FBD into shadow memory. BIOS extension sizes can be selected in 8KB increments from 2000h through 10000h. The default is “2000h”.

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Chapter 4: BIOS Configuration

EXM Menu

Use the options in this menu to select and configure the available EXM slots.

The required configuration information is found in the hardware reference manual shipped with each EXM expansion module.

Main Advanced EXM VME Exit

EXM Slot 0 ID: [FF] Option Byte 1 [00] Option Byte 2 [00] EXM Slot 1 ID: [FF] Option Byte 1 [00] Option Byte 2 [00] EXM Slot 2 ID: [FF] Option Byte 1 [00] Option Byte 2 [00] EXM Slot 3 ID: [FF] Option Byte 1 [00] Option Byte 2 [00]

The EXM Menu is shown below.

Item Specific Help

<Tab>, <Shift-Tab>, or <Enter> selects field.

F1 Hel ESC Exit ←→ Select Menu Enter Select Sub-Menu F10 Previous Values

↑↓ Select Item -/+ Change Values F9 Setup Defaults

Figure 4-8. EXM Menu.

This option is used to select the EXM ID byte value for the EXM card intended to reside in this slot. If the BIOS finds that the ID set with this option does not agree with the ID of the card actually installed in the slot, an EXM configuration error occurs and the card is not configured. For a slot with no EXM card installed, enter FFh, the default value.

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EPC-5A Hardware & Software Reference Manual

Option Byte 1

This option is used to select the first option byte value for the EXM card intended to reside in this slot. Option byte 1 typically defines bit 0 as the card enable bit. Other bits in the option byte are defined by the particular EXM card installed. The proper value of this option for a slot with no EXM card installed is not defined. The value typically used is 00h, the default value.

Option Byte 2

This option is used to select the second option byte value for the EXM card intended to reside in this slot. Option byte 2 is defined by the particular EXM card installed. The proper value of this option for a slot with no EXM card installed is not defined. The value typically used is 00h, the default value.

35 P U

0124

Figure 4-9. Slot Numbering.

All slots not occupied by an EXM module should show an ID of FF and OB1/OB2 of 00 00 indicating that no EXM is present.

Consult the appropriate EXM manual for the correct configuration information for each EXM expansion module installed. Note: Most EXM hardware reference manuals depict a different BIOS Setup Screen than the one shown here. The ID/OB1/OB2 information is still valid.

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Chapter 4: BIOS Configuration

When using EXMs with configurable interrupts, DMA channels, I/O addresses, and/or memory addresses, avoid conflicts with built-in functions of the EPC-5A. Guidelines are:

1. If an interrupt is needed, use IRQ3, IRQ4, IRQ5, IRQ9, or IRQ15. IRQ7 can be used if the printer port is not being used. IRQ3 should not be used if the COM B port is being used. IRQ4 should not be used if the COM A port is being used.

2. Use DMA channels 1, 3, 6, and 7.

3. Do not select I/O addresses that conflict with those in the EPC-5A. A complete list appears in Appendix A. For instance, I/O addresses in the 300-33F range can be used.

4. If the EXM needs to use upper memory addresses, they must be in the C8000h-DFFFFh range. Note that E0000h - 0EFFFFh is used for VMEbus access and is not available.

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EPC-5A Hardware & Software Reference Manual

VME Menu

The options in the VME menu are used to configure the EPC-5A’s VME interface. The VME Menu is shown below.

Main Advanced EXM VME Exit

Arbitration Priority: [0] Arbitration Mode: [Round Robin] Bus Release: [RONR] ULA: [FE00(F8)] VME Boot Scan Range: [A24 FF000000h-FFF00000h] Slave Memory Offset: [Disabled]

F1 Help Select Item -/+ Change Values F9 Setup Defaults ESC Exit Select Menu Enter Select Sub-Menu F10 Previous Values

Item Specific Help

Figure 4-10. VME Setup Menu.

Arbitration Priority

This option is used to select among the four (0 through 3) VMEbus priority levels used when the EPC-5A requests the bus for a VME access. Priority level 0 is the lowest priority while priority level 3 is the highest priority. The default is priority level “0”.

Arbitration Mode

This option is used to select the arbitration algorithm that the EPC-5A’s VMEbus arbiter uses when the EPC-5A is the slot 1 controller. Selecting “Round Robin” configures the arbiter to “scan” the bus request lines from highest priority down to lowest priority and grant the bus to the first requester it finds. Selecting “Priority” configures the arbiter to grant the bus to the highest priority requester at any time. The default is “Round Robin”.

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Chapter 4: BIOS Configuration

Bus Release

This option is used to select the method that the EPC-5A uses to release the VMEbus

for other bus masters to use. Selecting “ROR” (Release on Request) allows the EPC-5A to perform better since it releases the VMEbus only if another bus master requests the bus. Selecting “RONR” (Request on No Request – also known as VXI fair-requester mode) causes the EPC-5A to release the VMEbus when its current bus access has completed. This has the effect of increasing the performance of other bus masters. The default is “ROR (VME)”.

Unique Logical Address

This option is used to select the ULA for the EPC-5A. This logical address is used to uniquely identify and access the EPC-5A in a VXI system. The default is ULA “F8”.

VME Boot Scan Range

This option is used to select the scan range when booting from VME (vROM). The ranges are as follows:

A24SD searches from FF000000h - FFF00000h on 100000h boundaries A24SD searches from 00000000h - 00F00000h on 100000h boundaries A32SD searches from 00000000h - FFF00000h on 100000h boundaries

Slave Memory Offset

This option is used to select the slave memory of the EPC-5A. Possible selections are:

18000000h (A32) 19000000h (A32) 1A000000h (A32) 1B000000h (A32) 1C000000h (A32) 1D000000h (A32) 1E000000h (A32) 1F000000h (A32) 000000h (A24) 400000h (A24) 800000h (A24) C00000h (A24) disabled (default)

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EPC-5A Hardware & Software Reference Manual

Exit Menu

The options in this menu allow saving settings and exiting, or abandoning changes and exiting to the system, or controlling the backup and restoration of CMOS RAM to the FBD. The Exit Menu is shown below.

Main Advanced EXM VME Exit

Save Changes & Exit Discard Changes & Exit Get Default Values Backup CMOS to Flash Restore CMOS from Flash Restore Condition [Never] Load Previous Values Save Changes Exit & Update BIOS

F1 Help Select Item -/+ Change Values F9 Setup Defaults ESC Exit Select Menu Enter Select Sub-Menu F10 Previous Values

Item Specific Help

<Tab>, <Shift-Tab>, or <Enter> selects field.

Figure 4-11. Exit Menu.

About CMOS Backup and Restore

You can save and restore your setup configuration in preparation for an event such as battery failure or corrupt CMOS RAM. This feature also allows systems without batteries to boot properly while still allowing you to configure the system via Setup, which stores user settings in CMOS RAM. This feature allows automatic or manual restoration, and selective CMOS RAM restore conditions.

The CMOS RAM configuration backup is stored in FBD parameter block #2. This entire block is reserved for this purpose and cannot be shared.

The available selections from the Exit setup menu that would force a CMOS restoration are: Always restore, Never restore, and restore on Corrupt CMOS. The default setting is to restore on Corrupt CMOS.

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Chapter 4: BIOS Configuration

The System BIOS software searches the FBD for the unterminated string

“RadiSysCMOS--->” at power-up. This footprint marks the beginning of the CMOS parameter block storage structure. The structure contains a 16-bit CRC of the CMOS RAM data that is calculated at backup time and recalculated at restoration time. If the CRC verification fails, the restoration is skipped.

If the System BIOS succeeds in restoring a backup image to CMOS RAM, the system beeps 1 long and 5 short tones.

Restoration is inhibited for warm boots (CTRL-ALT-DEL from DOS) and when a restore is attempted but no valid CMOS image exists in the FBD.

Save Changes & Exit

This option is used to save into CMOS the values that have been entered, then reboot.

Discard Changes & Exit

This option is used to discard the changes just made and revert to the state when Setup was entered. The system reboots with the old values.

Get default values

This option is used to reset the Setup values to the original, default values that were set at the factory, before any suppliers or other end users made changes.

Backup CMOS to Flash

This option is used to immediately save current Setup settings from CMOS into flash. This is useful for backing up complicated setups.

Restore CMOS from Flash

This option is used to immediately restore CMOS settings from flash.

Restore Condition

This option is used to determine under what conditions the System BIOS restores CMOS RAM from the FBD when booting. The restore conditions are: “Always”, “Never”, and “Bad CMOS”. The default is “Bad CMOS”.

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EPC-5A Hardware & Software Reference Manual

Load previous values

This option is used to load the system with the previous values before an editing session started.

Save Changes

This option is used to save the edits made during a session.

Exit & Update BIOS

This option is used to initiate a System BIOS update.

Note

✏

If you select this option by mistake, any changes made to the BIOS are lost unless you have already saved them using the Save Current Values option. The system automatically begins searching for the update program that should be on the floppy disk inserted in drive A. If there is no floppy, you get two series of beep codes: a long and two short beeps, followed by three short beeps that repeat. Cycle the power to reset the system to its previous state.

Do not select this exit option unless you have already obtained BIOS update replacement software from your supplier and have reviewed the documentation and procedures provided with that distribution.

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5. Theory of Operation

The EPC-5A is a PC/AT compatible processor. Most of the standard functions of the PC architecture is embodied in the RadiSys R400 chip set. In addition, the EPC-5A has two proprietary interfaces: one for the EXM expansion interface and the other for the VMEbus.

Processor board

The EPC-5A processor board conforms with the VMEbus standard 6U form-factor.

Processor and Coprocessor

The processor in the EPC-5A is an Intel486-DX4 running internally at 100 MHz with an external interface at 33 MHz.

The 486 has a built-in math coprocessor and 16K cache.

Core Logic

The system uses the RadiSys R400EX system controller. The R400EX was developed by RadiSys to provide flexibility (of different system designs), ease of use, and low system cost. It is intended as a long-life core logic solution for the 486.

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EPC-5A Hardware & Software Reference Manual

The core logic system support provided by the R400EX includes the following:

RadiSys R400EX PCCompatible Features

RadiSys R400EX Core System Support Features

Real Time Clock Provides Motorola 146818A-

compatible real time clock and alarm with 114 bytes of batterybacked CMOS memory. The RTC also generates a periodic interrupt. Access to the CMOS memory is through registers 070h and 071h in

an index/data fashion. Keyboard/Mouse Controller Cache Supports L1 write-through cache. Shadow Shadow BIOS in DRAM. PC Speaker/Port B Functionality DRAM Refresh Controller

Power Management Support Programmable Chip Select Units (4) IDE Interface This interface is not used on the

Table 5-1. R400EX Features.

Implements a 8042-Compatible

keyboard controller.

Port B register is located at 061h.

Supports two banks of SIMMs as

Fast Page Mode (FPM), Extended

Data Out (EDO) or Flash SIMMs.

Second bank start address is

configurable. Supports EDO/FPM

memory type detection. SIMM

types cannot be mixed.

This interface is not used on the

EPC-5A.

This interface is not used on the

EPC-5A.

Memory

The following memory options are available: 4 MB, 8 MB, 16 MB, 32 MB and 64 MB. (Check with RadiSys Technical Support for 128 MB and 256 MB configurations.) Two SIMM sockets are available. See Chapter 8, Upgrades, for memory upgrade instructions.

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Chapter 5: Theory of Operation

Memory Map

The 232 byte physical address space seen by the Intel486 occupies three areas:

1. Addresses between 0 and 1 MB, which are largely defined by the IBM PC/AT architecture.

2. Addresses between 1 MB and 256 MB, which largely depend on how much DRAM is installed in the EPC-5A.

3. Addresses above 256 MB, which provide direct mapping to the VMEbus with a variety of address modifiers and byte orderings. See Chapter 6, The VMEbus Interface, for more information about this feature.

Memory at addresses between 0 and 1 MB (0FFFFFh) is mapped as follows:

Range Content 000000 - 09FFFF DRAM (first 640 KB) 0A0000- 0BFFFF Mapped to EXM interface; almost always used by a

video controller as video RAM

0C0000 - 0C7FFF Write-protected DRAM containing video BIOS 0C8000 - 0DFFFF* Uncommitted; mapped to EXM interface 0E0000 - 0EFFFF User-mappable hardware window onto VMEbus 0F0000 - 0FFFFF Write-protected DRAM containing BIOS

* 0C8000 - 0DFFFF may be used either as page frames (i.e. for Ethernet, etc.) or may be used by DOS as upper memory blocks if an EMM driver is installed or may be used for BIOS extensions.

For a 4 MB EPC-5A, the extended memory address space is defined as

00100000 003FFFFF 3 MB DRAM extended memory 00400000 00FEFFFF Uncommitted; mapped to EXM interface

For an 8 MB EPC-5A, the extended memory address space is defined as

00100000 007FFFFF 7 MB DRAM extended memory 00800000 00FEFFFF Uncommitted; mapped to EXM interface

For a 16 MB EPC-5A, the extended memory address space is defined as

00100000 00FFFFFF 16384 KB DRAM extended memory

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EPC-5A Hardware & Software Reference Manual

For a 32 MB EPC-5A, the extended memory address space is defined as

00100000 01FFFFFF 32764 KB DRAM extended memory

For a 64 MB EPC-5A, the extended memory address space is defined as

00100000 20000000 65536 KB DRAM extended memory

Note that since the EXM expansion interface has 24 address lines, some of the

“uncommitted; mapped to EXM interface” address areas map repeatedly, or wraparound, in the EXM interface's address space.

Peripheral Components

The EPC-5A uses the TI-16C452 controller to provide legacy I/O device support. This chip provides two NS16C450-compatible serial ports and a parallel port. Since LPTOEN ties to low, this port is output-only.

The serial ports signal interrupts on IRQ3 and IRQ4 and are accessible at the standard PC-AT architecture I/O base addresses of 3F8h and 2F8h respectively. The parallel port signals interrupts on IRQ7 and is accessible at the standard PC-AT architecture I/O base address of 378h.

Real Time Clock

The system contains a real time clock module that is compatible with the Motorola 146818A. The RTC is implemented in the R400EX and contains 114 bytes of CMOS RAM. The RTC and PC/AT CMOS RAM are addressable at the standard PC/AT architecture I/O addresses of 70h and 71h and interrupts are signaled on IRQ8. The System BIOS initializes the RTC on coldstarts if the RTC contains bad values.

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Chapter 5: Theory of Operation

Keyboard Controller

The R400EX contains an Intel 8042-compatible keyboard controller. The keyboard controller is addressable at the standard PC-AT architecture I/O addresses of 60h and 64h. Keyboard interrupts are signaled on IRQ1.

ROM and ROM Shadowing

The EPC-5A contains a 28F004-B*-T Flash Boot Block. The Flash device is mapped into the top of the processor’s 32-bit address space. The Flash device contains the PC BIOS, some peripheral BIOS code, and user extensions.

For best possible performance, the BIOS initialization software copies the ROM contents into DRAM (called shadowing) at addresses 0F0000-0FFFFF. The BIOS also searches for the existence of a video adapter containing a video BIOS (e.g., an EXM-13A). If a video BIOS is found, it is copied into the 0Cxxxx area of DRAM. After copying into these areas, the BIOS write-protects them. Subsequent writes to these areas complete successfully but do not alter the data.

Embedded Shadow

The EPC-5A supports several different boot methods and operating systems. In order to boot from VME or flash, it is necessary to first load and execute a BIOS extension. The FBD has an unused 96KB region in main block #3 that lies between the end of the PicoFlash extension and start of the System BIOS that can be used for BIOS extension storage. In order to use this area for BIOS extensions, it is necessary to first program the image into the FBD (using REFLASH.EXE) and then, at run time, copy the BIOS extension from the FBD into DRAM, and have the System BIOS scan that region for BIOS extensions. Multiple BIOS extensions can be programmed into the user block of the FBD. Setup items allow the user to select up to 3 BIOS extensions in the FBD and load them into DRAM between C8000h through DFFFFh.

Bootable Device Precedence

There are several bootable devices for the EPC-5A. Depending on the configuration, either the EXM-2A, VME, SCSI or IDE can be the boot device. This section documents the order in which these devices are installed in the boot chain. BIOS extensions supersede IDE as a bootable device.

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EPC-5A Hardware & Software Reference Manual

If there is more than one BIOS extension, the extension that is located at the highest physical memory location is the first device in the boot chain.

Only two drives are visible as BIOS extensions. The following denotes which devices are installed in the system when the devices are

enabled.

VME Booting: When booting from VME, the second BIOS recognized may be SCSI. If SCSI is selected as the second BIOS recognized device, Flash can be accessed under DOS by loading an OS-based driver. With this configuration, IDE drives are not visible to the system.

SCSI Booting: If the boot device is SCSI, either VME or Flash can be selected as the second BIOS recognized device. If VME is selected as the second BIOS recognized device, Flash can be accessed under DOS by loading an OS-based driver. IDE drives are not visible to the system.

Flash Booting: If the boot device is Flash, either VME or SCSI can be selected as the second BIOS recognized device.

IDE Booting: If the boot device is IDE, either VME or Flash can be used only after loading the device driver. SCSI can be selected as the second BIOSrecognized device.

Battery

The battery powers the CMOS RAM and TOD clock when system power is not

present. At 60°C, the battery should have a shelf life of over four years at 50% duty cycle. In a system that is powered on much of the time and where the ambient poweroff temperature is less than 60°C, the battery is estimated to have a life of 10 years.

The battery supplied with the EPC-5A is mounted on the underside of the metal frame and connected to a header on the processor board. Should the battery fail, you may obtain and install a replacement from RadiSys Technical Support.

Replacing the battery is a simple task. However, removing the battery will invalidate the CMOS setup parameters. It is recommended that all setup parameters be written down while the battery is still good. Additionally, use the Backup CMOS to Flash feature in the BIOS Exit Menu.

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Chapter 5: Theory of Operation

Video Controllers

The EPC-5A can operate with or without a video controller (such as the EXM-13B or EXM-13A). The BIOS searches for an EXM having an EXM ID in the range E8h-EFh (a range reserved for video controllers). The search is done by EXM slot number, beginning at slot 0. If no EXM video adapter is found, the BIOS looks for a PC add-in card video controller in an EXP-AM Adapter module. The error message

EXM CONFIGURATION ERROR may appear if the video controller EXM or the EXP-AM

has not been configured via the setup screen.

In either case, the BIOS automatically initializes and uses the first one found. If no video controller is present, the BIOS operates without one. Programs that use the standard operating system and BIOS character output functions can be run successfully (the output is ignored). However, programs that rely on specific video modes, that write directly into the video RAM, or that directly call video BIOS functions will fail.

Front Panel LEDs

The EPC-5A has five LEDs in the top left corner of the front panel. These LEDs are described below:

RUN This LED is lit whenever the EPC-5A’s CPU is performing bus cycles.

It first comes on at power-up and should remain lit as long as the system is running.

SYSFAIL This LED is only active when this EPC-5A is jumpered to be the

Slot-1 controller. It comes on whenever the system receives a hardware reset and remains on until the initial power-on self-tests have completed. It also comes on whenever the VMEbus SysFail line is asserted.

TEST This LED is lit whenever the system is running its power-on

self-test. This only occurs during a hardware reset.

MASTER The Master LED is lit whenever the EPC-5A is accessing the

VMEbus.

SLAVE The Slave LED is lit whenever another master on the VMEbus is

accessing the EPC-5A’s memory.

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EPC-5A Hardware & Software Reference Manual

Resetting the EPC-5A

There are a number of ways to reset (reboot) the EPC-5A.

Power-off, Power-on

This causes all boards in the VMEbus to reset. The system runs the poweron self-tests and reboots the operating system.

Front-panel Reset button

The Reset button causes the EPC-5A to perform a hardware reset. The system runs the power-on self-tests and reboots the operating system.

Ctrl+Alt+Del

This keyboard sequence is called a “warm boot”. The EPC-5A does not reinitialize all of the processor's hardware. The power-on self-test does not run. However, the operating system is reloaded.

VMEbus SysReset

The EPC-5A can be software-configured to respond or not respond to the VMEbus SysReset line. Asserting this bit causes a hard reset of the system if the VME YSRESET bit is asserted. See bit 7 (SRIE), register 8144h.

VMEbus Register Reset

The EPC-5A can also reset another master asserting the reset bit of a register mapped to the VMEbus. Asserting this bit causes a hard reset of the system. See bit 0 (RSTP), register 8144h.

EXM Expansion Interface

The EXM expansion interface is electrically similar to the PC/AT ISA (16-bit data) bus. In addition, it contains a signal configuration of EXMs. EXMs respond to one or more I/O addresses in the range 100h - 107h only when their unique EXM ID byte in response to a read from I/O address 100h.

This ID byte is the same identification byte discussed earlier in Chapter 4, Configuring the BIOS Setup, in the section on the EXM Setup Menu.

The EXM expansion interface is provided on rows A, C, and D of the EPC-5A's 4-row DIN P2 connector. The subplane carries the EXM interface to other modules, such as to EXM modules and the EXP-MX Mass Storage module. These EXM interface signals are not passed through to the VMEbus.

Further information on the EXM expansion interface, its connectors, and standards for building EXMs is available upon request.

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-EXMID line is asserted. EXMs are required to return a

-EXMID used for dynamic recognition and

6. The VMEbus Interface

This chapter describes the EPC-5A VMEbus interface as seen by a program. Users should avoid direct use of most of these facilities. Whenever possible, the VMEbus interface should be accessed through the EPConnect software, an easy-to-use, high-level interface that frees you from most machine-dependent considerations.

Connectivity

The EPC-5A module connects to the VMEbus J1 connector directly and uses all of the defined VMEbus lines except to the J2 connector is through the subplane’s 4-row DIN connector B row. The only connections to the VME J2 backplane on the B row are power and ground, address

A31-A24, and data lines D16-D31. Pin 30, Row A, the VXI-defined module

lines identification ( input and an 825-ohm pull-down resistor. It may be disabled by removing the MODID jumper on the EPC-5A. If necessary, see Chapter 2, Configuring the EPC-5A.

MODID

) line is also connected. Pin A30 is an input driving one gate

SERCLK, SERDAT, and +5V STDBY. Connection

VMEbus System (Slot-1) Controller Functions

Every VMEbus system must have a System (Slot-1) Controller. The Slot-1 controller provides the following functionality:

Serves as the bus arbiter (priority or round-robin)

•

Drives the 16 MHz SYSCLK signal

•

Starts the IACK daisy chain

•

Provides Bus Timer function

•

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EPC-5A Hardware & Software Reference Manual

When configured as the Slot-1 controller, the EPC-5A detects and terminates data transfer bus timeouts. Once it sees either the started. If the counter expires before both EPC-5A asserts the VMEbus

BERR signal until both data strobes are deasserted. The

DS0 or DS1 lines asserted, a counter is

DS0 and DS1 are deasserted, the

duration of the VMEbus timeout counter is 100-120 µsecs. When the EPC-5A is configured as the slot-1 controller, this timeout cannot be disabled and the duration cannot be changed.

Although the EPC-5A provides the required timeout function for data transfer timeout, it does not provide the optional bus grant timeout. If another master has been granted permission to use the data bus but does not access (or relinquish) the data bus,

the bus will be “hung” indefinitely.

Concepts

Memory Map

VMEbus accesses are available by mapping a 64K segment of the VMEbus through the 0E0000h -0EFFFFh window or by direct mapping above 256 MB. The following summarizes the source of the VMEbus address lines for accesses through the VME memory window.

A32

31 2423 2221 1615 0

From port 8150

From port 8151

From port 8130

From

486 address

bits 15-0

A24

23 2221 1615 0

From port 8151

From port 8130

From

486 address

bits 15-0

A16

15 0

From

486 address

bits 15-0

Figure 6-1. Source of VMEbus Address Lines (Via VME memory window).

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Chapter 6: The VMEbus Interface

It should be noted that the EPC-5A drives all 32 address lines even when performing an A24 or A16 access. Therefore, all the above registers (8150, 8151, 8130) should be set for every access using the VME memory window. Make sure that those

registers not directly supplying address lines are set to “FF” values in the appropriate bit positions.

Direct VMEbus Accesses

An alternate way to perform VMEbus accesses, provided that the EPC-5A is running in protected mode, is to perform reads and writes at 486 addresses above 10000000h (256 MB). For instance, a 4-byte read at address 40000000h will result in a 4-byte VMEbus read access at address 00000000 with an address modifier specifying A32, supervisory data and no byte-swapping (little-endian mode).

With the EPC-5A, addresses above 256 MB, with one exception for PC compatibility, map onto the VMEbus. When direct “protected-mode” addressing of A24 or A16 space, the high-order nibble is used to define the access mode and byte ordering. For A32 space, the high-order 2 bits define the access mode leaving 30 bits available for addressing. Thus, only the first 1 Gigabyte of VMEbus A32 space is directly addressable. All A24 and A16 space is directly addressable. The chart following shows how this direct mapping is used.

Address Range Access Mode Byte Order

1xxx0000 - 1xxxFFFF VME A16 supervisory data little endian 2x000000 - 3xFFFFFF VME A24 supervisory data little endian 40000000 - 7FFFFFFF VME A32 supervisory data

(mapped to VME 00000000-3FFFFFFF)

80000000 - BFFFFFFF VME A32 supervisory data

(mapped to VME 00000000-3FFFFFFF) Cxxx0000 - DxxxFFFF VME A16 supervisory data big endian Ex000000 - ExFFFFFF VME A24 supervisory data big endian

F0000000 - FFFEFFFF Mapped to EXM expansion interface

FFFF0000 - FFFFFFFF 486 upper ROM area

little endian

big endian

Table 6-1. Direct Mapping.

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When accessing the VMEbus in this manner, the source of the VMEbus address lines is defined below.

A32

31 3029 0

00 From 486 address bits 29-0

A24

23 0

From 486 address bits 23-0

A16

15 0

From 486 address bits 15-0

Figure 6-2. Source of VMEbus Address Lines (Via Direct Mapping).

The main purpose of the direct VMEbus access mechanism, as opposed to the VME memory window mechanism, is for multitasking 32-bit operating-system environments, where multiple tasks need to make VMEbus accesses. Without this, the tasks would have to coordinate their use of the VME memory window mapping registers.

When using the EPC-5A this way to perform VMEbus accesses, one would typically set up the VME memory window for interrupt acknowledge accesses. Also note that the direct access mappings do not cover the entire VMEbus A32 address range and do not provide all VMEbus-defined address modifier encodings, but one can use the VME memory window mechanism if needed to provide these.

Byte Ordering

There are two fundamentally different ways of storing numerical values in byte locations in memory:

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• Little endian, characteristic of Intel microprocessors, where the

least-significant data byte (LSB) is stored in the lowest byte address.

Address + 3 Address + 2 Address + 1 Address

Byte 3 Byte 2 Byte 1 Byte 0

MSB LSB

Chapter 6: The VMEbus Interface

• Big endian, characteristic of Motorola microprocessors and the VMEbus

environment in general, where the mo st-significant data byte (MSB) is stored in the lowest byte address.

Address + 3 Address + 2 Address + 1 Address

Byte 3 Byte 2 Byte 1 Byte 0

LSB MSB

The EPC-5A contains programmable byte-swapping hardware to allow programs to read or write VMEbus memory in either byte order. When using the VME memory window to access the VMEbus, the order is selected by bit 5 (BORD) in the VME modifier register (8151).

When using direct memory mapping, the order is address-range dependent (e.g., E0000000-E0FFFFFF accesses the A24 space with big endian byte ordering, and 20000000-20FFFFFF accesses the A24 space with little endian byte ordering).

When performing a single byte (D08) access, the byte order makes no difference. However, word (D16) or double-word (D32) accesses may require byte-swapping.

When little-endian is selected, bytes pass straight through unchanged. Little endian should only be used when reading or writing data between two Intel processor systems. The results of using little-endian byte ordering to transfer a double-word integer between an Intel processor and a Motorola processor are shown below.

486

Address

Motorola

Address

Addr+3

5476

AddrAddr+1Addr+2

1032

AddrAddr+1Addr+2

= 76543210h

LSB

= 10325476h

MSB

Figure 6-3. Little-Endian Byte Order.

Since the 486 processor uses Addr as the least-significant byte and the Motorola processor uses Addr as the most-significant byte, the processor receiving the data gets a “scrambled” value.

When big-endian is selected, the bytes are swapped between the 486 and VME. See the diagram below.

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EPC-5A Hardware & Software Reference Manual

486

Address

Motorola

Address

AddrAddr+1Addr+2

Addr+3

AddrAddr+1Addr+2

Addr+3

LSB

MSB

1032

32 54 76

Addr

Addr+1

AddrAddr+1

LSB

MSB

D16

Access

D32

Access

Figure 6-4. Big-Endian Byte-swapping.

When using big-endian byte ordering, care must be taken to assure that the VME address is aligned on a boundary; for D16 accesses the VME address must be on a word boundary (address evenly divisible by 2) and for D32 accesses the VME address must be on a double-word boundary (evenly divisible by 4).

If this is not done, the results will be “scrambled” data. Although the VMEbus address must be boundary-aligned to match the data width (word or double-word), the 486 address does not need to be boundary-aligned.

Another consideration is the compiler being used. Some compilers produce two 16-bit accesses when a 32-bit access is desired. When this occurs, again the data will be “scrambled.”

When transferring a 32-bit floating-point number, special care must be taken to assure that both processors use the same floating-point format; and that both systems expect the mantissa and exponent in the same byte locations. As long as this is correct, transferring a floating-point number will work correctly. Since transferring a 64-bit floating-point number is not supported in hardware, two 32-bit transfers must be used with little-endian byte order and then byte-swapping must be accomplished in software.

▲

CAUTION

Byte swapping applies only to EPC-5A initiated (master) accesses; it does not apply to slave accesses from other VMEbus masters to the EPC-5A’s DRAM.

The EPConnect Bus Manager software provides a means of selecting the byte ordering during memory-copy operations.

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Chapter 6: The VMEbus Interface

Slave Accesses from the VMEbus

When SLE (Slave Enable) in the status/control register (8145h) is set, the EPC-5A’s dual-ported memory will respond to accesses from other VMEbus masters.

All types of VME accesses (reads, writes, and read-modify-writes of all lengths) are supported, except for block transfer cycles. The EPC-5A responds to supervisory, non-privileged, program, or data access modes.

The amount of memory that will be dual-ported is limited to the first (lowest address) 4 MB in A24 space or all available memory in A32 space. In both cases, the slave memory’s local (PC) address starts at Segment 0000, Offset 0000. This, of course, means that it is possible to overwrite the memory space occupied by the operating system. As such, care must be taken in writing to the EPC-5A’s memory.

When such an access is fielded by the EPC-5A, the EPC-5A’s A24 or A32 base address is effectively subtracted from the VMEbus address value, and the result is treated as if the access came from the 486.

However, note the following:

1. Any access that maps to local addresses 000A0000h - 000BFFFFh, 000D0000h 000EFFFFh, to addresses mapped to the EPC-5A’s EXM expansion interface, and to addresses beyond the extent of the installed DRAM cause the EPC-5A to respond with BERR (bus error).

2. Write accesses to write-protected DRAM terminate normally (DTACK response), but with no effect on the DRAM.

Enabling of the EPC-5A as a slave and specification of the address space (A24 or A32) and the base address is controlled by the registers discussed in the following section, Registers Specific to the EPC-5A. The easiest way to set up these registers is to do so via the BIOS setup screen.

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EPC-5A Hardware & Software Reference Manual

Self Accesses Across the VMEbus

Since the EPC-5A’s DRAM can be mapped into the VMEbus A24 or A32 address space, the EPC-5A can access its DRAM in an alternate way - by generating VMEbus accesses to addresses mapped as the EPC-5A’s VME slave memory. This can be of use in multiple-processor systems where some of the EPC-5A’s DRAM is used as shared global memory; it means that the EPC-5A can access the global memory with the same addresses as used by other processors without needing to understand that the memory is actually on-board.

This ability is also useful in system checkout (i.e., checking operation of the backplane) and in giving an EPC-5A program the ability to view its memory in big endian format.

A24 and A32 slave accesses result in accesses to the on-board DRAM and never to the cache. Because the EPC-5A’s cache is a write-through cache, there is never a discrepancy between data in the cache and the DRAM. When a slave access results in a write into the DRAM, the EPC-5A automatically purges the cached entry, if it exists.

Given the above, another subtle use for the ability of the EPC-5A to access its own DRAM via a VMEbus access is selective purging of the cache. For instance, if the EPC-5A is mapped at address base 18000000h in the A32 space and a program is meant to purge location 0000AB00h from the cache, a read from 0000AB00h followed by a write of the read data back to 1800AB00h will accomplish the task.

Read-Modify-Write Operations

VMEbus RMW (read-modify-write) cycles can be performed through use of the LOCK instruction prefix with certain instructions. All of these instructions perform a read followed by a write. When such a read occurs that is mapped to the VMEbus, the EPC-5A treats it as the start of a VME RMW cycle. The next VME access from the CPU is treated as the write that terminates the RMW cycle. Keep in mind that accesses that cross a 32-bit boundary are actually performed as two accesses. For this reason, RMW accesses that cross a 32-bit boundary will not behave as expected.

The EPC-5A provides synchronization integrity in its local DRAM between accesses from the CPU into the DRAM and RMW VME accesses from other masters into the DRAM.

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Chapter 6: The VMEbus Interface

When a VMEbus slave read access occurs to the local DRAM, the EPC-5A watches the VMEbus data and address strobes to determine if the cycle is an RMW cycle. If it is, accesses by the CPU are held up until the terminating access of the RMW cycle occurs.

When the CPU performs a locked access (e.g., via an instruction using the LOCK instruction prefix) to the local DRAM or the cache, VMEbus slave accesses are held up until the last locked access completes.

One more case of interest is when the EPC-5A performs a locked access that results in a self access. These function correctly (i.e., as if the access was not a self access), providing that operating-system tables (e.g., page tables) that are accessed by the CPU by implicit locked accesses are not mapped into VME. This would only be a concern for user-written operating systems.

VMEbus Interrupt Response

When the EPC-5A’s Interrupt Generator register (815F) is used to assert an interrupt, the EPC-5A formulates a status/ID value that is transmitted on the bus as the response to a matching interrupt acknowledgment cycle. The EPC-5A acts as both a D08(O) and D16 interrupter. For D08 interrupt acknowledge cycles, the status/ID value is the EPC-5A’s logical address (11111aaa, where aaa is the value of ULA as defined in port 814A). For D16 and D32 interrupt acknowledge cycles, the status/ID value consists of 16 bits. The upper eight bits are the upper half of the response register (the value in I/O port 814B) and the lower eight bits are the logical address.

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EPC-5A Hardware & Software Reference Manual

Registers Specific to the EPC-5A

Registers in the I/O space that are specific to the EPC-5A are defined below.

Bit7Bit6Bit5Bit4Bit3Bit2Bit1Bit

0 I/O Port

Res Res Res MEMSIZE VME Res 8104h

VMEbus and Memory Controller Configuration

VMEbus Address bits 21-16 Res Res 8130h

VME A21-16 Address Register

11101100 8140h

ID Register, lower

100A321111 8141h

ID Register, upper

11000100 8142h

Device Type Register, lower

0 Slave Size 11111 8143h

Device Type Register, upper

SRIE RELM ARBPRI READY PASS NOSF RSTP 8144h

Status/Control Register, lower

SLE MODID SYSR SYSF ARBM 1 1 1 8145h

Status/Control Register, upper

11111111 8146h

Slave Offset Register, lower

00011 SLAVE BASE 8147h

Slave Offset Register, upper

11111111 8148h

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Chapter 6: The VMEbus Interface

Protocol Register, lower

01011111 8149h

Protocol Register, upper

LOCK 1 ABMH 1 1 ULA 814Ah

Response Register, lower

00001RRDY WRDY 1 814Bh

Response Register, upper

RAM 814Ch

Message High Register, lower

RAM 814Dh

Message High Register, upper

RAM 814Eh

Message Low Register, lower

RAM 814Fh

Message Low Register, upper

VMEbus Address bits 31-24 (WA31-24) 8150h

Message A31-24 Address Register

VME WA23-22 BORD IACK AM5 AM4 AM2 AM1 8151h

VME Modifier Register

IRQ7 IRQ6 IRQ5 IRQ4 IRQ3 IRQ2 IRQ1 MSGR 8152h

VME Interrupt State Register

IRQ7 IRQ6 IRQ5 IRQ4 IRQ3 IRQ2 IRQ1 MSGR 8153h

VME Interrupt Enable Register

11111ACFA BERR SYSF 8154h

VME Event State Register

11111ACFA BERR SYSF 8155h

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VME Event Enable Register

DONE AS DS0 DS1 1 1 (res.) 1 8156h

Module Status/Control Register

11111 INTERRUPT-OUT 815Fh

Interrupt Generator Register

Where a bit position has been described by a 0 or 1, the bit is a ROM bit, and writing to it has no effect. Unless otherwise noted below, all registers and bit values are readable and writeable.

VMEbus and Memory Controller Configuration (8104h)

MEMSIZE VME

This register controls the DRAM memory controller and certain aspects of BIOS write protection and the VMEbus interface. The bits in this register are cleared by an “AT

reset” (that is, when the RESET button is pushed or power is applied to the system).

MEMSIZE Memory Size. These bits tell the memo ry controller how much SIMM

DRAM memory is present on the EPC-5A. This field is set by the BIOS when power is applied to the EPC-5A, and contains one of the following values: 001 = 4 MB, 010 = 8 MB, 111 = 16 MB, 110 = 32 MB. Larger memory sizes are not yet defined.

VME If set (1), this bit allows VME accesses through the DOS window or

through shared memory above 256 MB in protected mode. When clear (0), the VMEbus cannot be accessed. This bit is automatically set by the BusManager software when using EPConnect.

✏ Note

Except for the VME access bit, the bits in this register are manipulated by the BIOS. User software should manipulate only the VME access bit in this register.

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VME A21-16 Address Register (8130h)

VMEbus Address bits 21-16 Res Res

When an access is performed by the EPC-5A in its window (address range 0E0000h0EFFFFh), the access is mapped onto the VMEbus. The least-significant 16 of the VME address bits are provided directly (from the 486), and the remaining 8 (for an A24 access) or 16 (for an A32 access) bits must come from somewhere else. Six of them come from this register. Bit 7 of this register is used as VME address bit 21, bit 6 as VME address bit 20, and bit 2 as VME address bit 16.

The two low-order bits are reserved RAM bits. On writes, assign them the value 0.

For compatibility with EPC-1, this register is aliased at I/O port addresses 8132h, 8134h, and 8136h.

ID Register (8140h & 8141h)

11101100 Lower

100A321111 Upper

This read-only register adheres to the VXIbus specification. It defines the EPC-5A as a message-based device and the manufacturer as RadiSys Corporation.

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A32 If set (1), the EPC-5A’s DRAM is mapped into the VMEbus A32 address

space. If clear, the DRAM is mapped into the A24 address space. This readonly bit is influenced by the value stored in the SLAVE-SIZE field of the next register.

Device Type Register (8142h & 8143h)

11000100 Lower

0 Slave Size 11111 Upper

This register adheres to the VXIbus specification. Only bit 6 is writeable. Bit 5 is automatically set to match bit 6. If bit 6 is set, the value of the register is 7Fh and the A32 bit in the previous register is 1. This denotes that the EPC-5A responds to a 16 MB range in the A32 space.

If bit 6 is clear, the value of the register is 1Fh and the A32 bit in the previous register is 0. This denotes that the EPC-5A responds to a 4 MB range in the A24 space.

The remaining ROM bits define the EPC-5A as having a model code of 4036.

Status/Control Register (8144h & 8145h)

SRIE RELM ARBPRI READY PASS NOSF RSTP Lower

SLE MODID SYSR SYSF ARBM 1 1 1 Upper

This register adheres to the VXIbus specification and also contains EPC-5A specific bits.

SRIE SYSRESET input enable. If set, assertion of VME SYSRESET generates a

reset of the EPC-5A. One use of this bit is having EPC-5A software reset other VME devices (via bit SYSR) without resetting the EPC-5A.

RELM Bus release mode. If set, the bus release mode is ROR (release on request);

otherwise it is the VXI RONR “fair requester” mode (request on no

request). Altering this bit via the VME-mapped location of this register has no effect.

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ARBPRI Arbitration priority. This defines the level at which the EPC-5A arbitrates

for the VMEbus. 11 means 3, 10 means 2, 01 means 1, 00 means 0. Like for RELM, altering this field via the VME-mapped location of this register has no effect.

READY This is a RAM bit defined by the VXI specification. In a VXIbus software

environment, if READY=1 and PASS=1, the EPC-5A is ready to accept VXI-defined messages. In the EPC-1 and in early versions of the EPC-3

manual, this bit was named EXTE. Its implementation hasn’t changed, but it was renamed to correspond to the renaming of the bit in revision 1.3 of the VXIbus specification.

PASS If set (1), the EPC-5A has completed its self test successfully. If this bit is

clear, the Test LED on the EPC-5A front panel is lit.

NOSF SYSFAIL inhibit. If set, the EPC-5A cannot assert the VMEbus SYSFAIL

line. RSTP Reset EPC. Setting this bit resets the EPC-5A. SLE Slave enable. If set, the EPC-5A responds to certain A24 or A32 accesses

on the VMEbus. MODID This readable bit is connected to pin 30 in row A of the VMEbus P2 con-

nector. If clear (0), it denotes that the pin is being pulled high. (This is

used in VXI systems for module identification.) SYSR SYSRESET. The EPC-5A asserts the VME SYSRESET line while this bit

is 1. When using this bit, it is the software’s responsibility to ensure that

the VME-specified minimum assertion time of SYSRESET is met. SYSF SYSFAIL. The EPC-5A asserts the VME SYSFAIL line while this bit is 0.

(The polarity of the bit is reversed from that of SYSRESET so that an

EPC-5A reset - which clears this bit - causes SYSFAIL to be asserted until

the BIOS stores a 1 in this bit.) ARBM Arbitration mode. This bit is pertinent only if the EPC-5A is jumpered to

be the VMEbus system controller. If set, the EPC-5A is a priority arbiter;

otherwise it is a round-robin arbiter. Like for RELM, altering this field via

the VME-mapped location of this register has no effect.

Slave Offset Register (8146 & 8147)

11111111 Lower

00011 SLAVE BASE Upper

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If A32 and SLE are set, the value in port 8147 defines the base address of the EPC-5A’s memory in the VMEbus A32 address space. This register can hold the values 18 - 1F, which correspond to the base addresses 18000000h - 1F000000h.

If A32 is clear and SLE is set, the two low-order bits of SLAVE BASE define the base address of the EPC-5A’s memory in A24 as follows: 00 - 000000h, 01 - 400000h, 10 - 800000h, 11 - C00000h.

Protocol Register (8148h & 8149h)

11111111 Lower

01011111 Upper

This read-only register is defined by the VXIbus specification. In VXI systems, it defines the EPC-5A as being a servant and commander, having no signal register, being a bus master, and not providing fast handshake mode.

Response Register (814Ah & 814Bh)

LOCK 1 ABMH 1 1 ULA Lower

00001RRDY WRDY 1 Upper

With the exception of LOCK, this register is defined by the VXIbus specification. It contains control bits associated with the message registers.

LOCK If set, the message register can be locked for the sending of a message.

If clear, the message register has been locked.

ABMH This bit is cleared when the message high register is read or written. It

serves as a location monitor for determining whether a message is 16 or 32 bits in length.

ULA Unique logical address. This determines the base of the registers in the

VMEbus A16 space. 0 denotes FE00h, 1 denotes FE40, 2 denotes FE80h, 3 denotes FEC0h, 4 denotes FF00h, 5 denotes FF40h, 6 denotes FF80h, and 7 denotes FFC0h.

RRDY Read ready. As defined by VXI, a 1 denotes that the message registers

contain outgoing data to be read by another device. RRDY is cleared when the message low register is read.

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WRDY Write ready. If set, the message registers are armed for an incoming mes-

sage. When a write occurs into the message-low register, WRDY is cleared

and the MSGR interrupt condition is asserted.

When the response register is read from the VMEbus, the current value of the register is read, and then LOCK is cleared. The protocol for sending a message to the EPC-5A, if there are multiple potential senders, is the following. The sender first reads the response register. If both WRDY and LOCK are 1, the sender may then proceed to send the message. For a 16-bit message, the sender writes into the message-low register. For a 32-bit message, the sender writes first into the messagehigh register and then the message-low register.

Message High Register (814Ch & 814Dh)

RAM Lower

RAM Upper

This register is an extension of the following register for 32-bit messages. An access to this register clears flag ABMH in the response register.

Message Low Register (814Eh & 814Fh)

RAM Lower

RAM Upper

This register is typically used as an incoming message register by doing a D16 write into it from the VMEbus (this register, as are many others, is mapped into the VMEbus A16 address space, as discussed later).

VME A31-24 Address Register (8150h)

VMEbus Address bits 31-24 (WA31-24)

This register is one of several that supply the VMEbus address bits when the EPC-5A makes an access in its memory window. This register supplies VME address bits A31A24.

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VME Modifier Register (8151h)

VME WA23-22 BORD IACK AM5 AM4 AM2 AM1

This register is also used when the EPC-5A makes an access through its VME memory window to the VMEbus. Bits 7 and 6 provide VME address bits A23 and A22, respectively. Bits 3-0 define the value placed on the associated VMEbus address-modifier lines. Register bits are not defined for the VMEbus addressmodifier AM3 and AM0 lines since, for all defined address-modifier values in the VMEbus specification, AM3 is 1 and AM0 is the inverse of AM1. Therefore these two bit values are generated by hardware. Note that because AM3 and AM0 are hardware generated, the EPC-5A does not support user-defined address-modifiers.

BORD Byte order. This bit controls the ordering of data bytes for D16 and D32

VMEbus accesses. If 0, the bytes are transmitted in little endian (Intel) order; if 1, byte-swapping hardware transmits the bytes in big endian (Motorola) order. Refer to the previous section in this chapter on byte ordering.

IACK This bit, when set, is used to define the VMEbus access as an interrupt

acknowledge cycle. The interrupt being acknowledged must be encoded by software as a value on VME address lines A1-A3.

VME Interrupt State Register (8152h)

IRQ7 IRQ6 IRQ5 IRQ4 IRQ3 IRQ2 IRQ1 MSGR

This read-only register defines the state of the VMEbus and message interrupts.

IRQx If clear (0), the associated VMEbus interrupt line is asserted. MSGR If clear (0), a message interrupt is being signaled. MSGR is clear if both bits

RRDY and WRDY in the response register are clear.

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VME Interrupt Enable Register (8153h)

IRQ7 IRQ6 IRQ5 IRQ4 IRQ3 IRQ2 IRQ1 MSGR

This is a mask of the interrupt conditions in the interrupt state register. A 1 denotes that the corresponding interrupt is enabled. If any bit in this register is a 1 and the corresponding bit in the interrupt state register is a 0, the EPC-5A IRQ10 interrupt is asserted. Software may then examine the interrupt and event state registers to determine the cause.

VME Event State Register (8154h)

11111ACFA BERR SYSF

Similar to the interrupt state register, this register defines additional conditions that may result in an IRQ10 interrupt. If the bit is 0, the condition is present.

ACFA VMEbus ACFAIL is asserted. BERR An access from the EPC-5A to the VMEbus was terminated with a BERR

(bus error).

SYSF VMEbus SYSFAIL is asserted.

All bits are read-only except BERR. BERR is a sticky bit that is cleared whenever an access from the EPC-5A is terminated by a bus error, and remains clear (0) unless changed by software (by writing any value to this register).

VME Event Enable Register (8155h)

11111ACFA BERR SYSF

This is a mask of the interrupt conditions in the event state register. A 1 denotes that the corresponding event is enabled as an interrupt. If any bit in this register is a 1 and the corresponding bit in the event state register is a 0, the EPC-5A IRQ10 interrupt is asserted. Software may then examine the interrupt and event state registers to determine the cause.

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Module Status/Control Register (8156h)

DONE AS DS0 DS1 1 1 (res.) 1

This register contains miscellaneous status and control bits.

DONE This read-only bit is 0 whenever the EPC-5A has a VMEbus access

outstanding. It is used for determining when a pipelined VMEbus write is complete.

AS T his read-only bit is 1 whenever the VMEbus AS (address strobe) signal is

asserted. It may be used for bus monitoring.

DS0 This read-only bit is 1 whenever the VMEbus DS0 (data strobe) signal is as-

serted. It may be used for bus monitoring.

DS1 This read-only bit is 1 whenever the VMEbus DS1 (data strobe) signal is as-

serted. It may be used for bus monitoring.

(res.) This bit should always be set (1).

The EPC-3 contains two additional bits in this register - ENMI and DEAD - for breaking deadlock situations on its dual-port DRAM. These situations cannot exist in the EPC-5A so the signals are not implemented.

VME Interrupt Generator Register (815Fh)

11111 INTERRUPT-OUT

This register is used to assert one of the VMEbus interrupt signals. If the INTERRUPT-OUT bits are zero, no interrupt line is asserted by the EPC-5A. If the lower three bits are set to 001, VMEbus IRQ1 is asserted. If set to 010, VMEbus IRQ2 is asserted, and so on. If and when an interrupt acknowledge cycle is sent to the EPC-5A, the INTERRUPT-OUT bits are cleared.

You can also deassert a previously asserted interrupt by writing 0 into the register.

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VMEbus Mapped Registers

The EPC-5A follows the lead of the VXIbus specification in defining a standard set of configuration registers that are mapped into the VMEbus A16 space and thus accessible by other VMEbus modules. These registers are 16-bit registers occupying 64 bytes of A16 space at a base address defined by the EPC-5A’s logical address. The base address is

1111 111a aa00 0000

where aaa is the value of the ULA field in the response register at I/O port 814A.

The VME-mapped registers are a subset of those defined previously as I/O ports in the EPC-5A. The registers are dual-ported in that they are accessible both from VME and from within the EPC-5A as ports in its I/O space. The VME mapped registers are defined below.

Offset from

ULA

0 ID (8141h) ID (8140h) 2 Device type (8143h) Device type (8142h) 4 Status/control (8145h) Status/control (8144h) 6 Slave offset (8147h) Slave offset (8146h)

8 Protocol (8149h) Protocol (8148h) A Response (814Bh) Response (814Ah) C Message high (814Dh) Message high (814Ch) E Message low (814Fh) Message low (814Eh)

The registers occupy the first 16 bytes of the 64-byte space; the remainder of the space is undefined. (Actually, the registers are mapped into each 16-byte chunk of the 64-byte space.)

Reads and writes of the registers from VME and as I/O ports have identical results and effects except for the following:

1. Changing the RELM, ARBPRI, and ARBM fields of the status/control register from VME will appear to have changed the fields (i.e., if the register is then read), but the new values will not effect the EPC-5A’s buscontrol logic. To use these fields for their intended purpose, they must be set by I/O port accesses.

Upper byte Lower byte

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2. A read of the response register from VME clears the LOCK bit (immediately after the current value of the response register is returned).

Register State after Reset

A hardware reset of the EPC-5A (not a keyboard CTRL+ALT+DEL reset) clears all of the register bits to 0, except for RELM, ARBM, ARBPRI, and the registers at ports 8130h, 8150h, and 8151h, which may be in an undefined state. (All bits, however, are cleared by a power-on reset.) However, this may not be apparent because the BIOS initialization sequence then reinitializes values in these register fields, largely as a result of the non-volatile configuration information specified in the setup screen.

The BIOS clears the interrupt enable and event enable registers.

Supported Address Modifiers

2Dh A16 supervisor

39h A24 non-privileged data 3Ah A24 non-privileged program 3Dh A24 supervisor data 3Eh A24 supervisor program

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09h A32 non-privileged data 0Ah A32 non-privileged program

0Dh A32 supervisor data 0Eh A32 supervisor program

Table 6-3. Support Address Modifiers.

Chapter 6: The VMEbus Interface

Low-Level Programming the VMEbus Interface

It is recommended that rather than performing accesses in this low-level hardware dependent form, the Bus Manager component of the EPConnect software package be used instead.

VMEbus Accesses

Two examples are given here including both a verbal description and the Microsoft C source code for performing VMEbus accesses through the memory window.

Example #1 performs a 16-bit read from the VMEbus A16 space.

1. Set the VME access bit in Register 8104h.

2. Determine the correct address modifier for A16 supervisory access (2Dh).

3. The unused address lines A31-A16 may float when not being used. Registers 8150h and 8130h must be set so that each line is a 1.

Set register 8130h to FCh and register 8150h to FFh.

4. Set the access mode in the VME Modifier Register (8151h) as follows:

VME WA23-22 BORD IACK AM5 AM4 AM2 AM1

(Note that register bits are not defined for the VMEbus address modifier lines AM3 and AM0 since, for all defined address modifier values in the VMEbus specification, AM3 is 1 and AM0 is the inverse of AM1. Therefore these two bit values are generated by hardware.)

Bits 7 & 6 Since the A16 space does not use VMEbus address lines A23 &

A22, set these values to 1.

VME WA 23-22 = 11

Bit 5 Set the byte order to “little endian”.

BORD = 0

Bit 4 Clear the IACK bit so this is not an interrupt acknowledge cycle.

IACK = 0

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Bits 3-0 Use the address modifier (in binary form) to determine the

appropriate values for these bits. 2Dh = 0010110

Bit 3 (Address Modifier bit 5) = 1 Bit 2 (Address Modifier bit 4) = 0 Bit 1 (Address Modifier bit 2) = 1 Bit 0 (Address Modifier bit 1) = 0

Thus, 8151h should be set to 1100 1010 or CAh.

5. Map the address.

Add the A16 address to the memory window address

Addr ← E0000000h + A16 address

6. Read the data.

Data ← value pointed to by Addr

Microsoft C code for Example 1 -

#define WORD unsigned short #define LWORD unsigned long

WORD addr; /* 16-bit A16 address */ WORD data; WORD far * wptr;

outp(0x8104,(inp(0x8104)|2)); /* set VME access bit */ outp(0x8130,0xFC); outp(0x8150,0xFF); outp(0x8151,0xCA); /* Set address modifier to A16 supervisory access */ wptr = (WORD far *) (0xE0000000L + addr); data = *wptr; /* Read through window */

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Example #2 performs a byte (8-bit) write into the VMEbus A32 space. Here the upper 16 bits of the VME address need to be stored in the appropriate registers.

1. Set the VME access bit in register 8104h.

2. Set register 8150h with the value corresponding to the 8 high-order address bits.

VMEbus Address bits 31-24 WA31-24

3. Determine the correct address modifier for A32 supervisory access.

4. Calculate the value and set register 8151h as follows:

VME WA23-22 BORD IACK AM5 AM4 AM2 AM1

Bits 7 & 6 VME address bits 23-22 Bit 5 BORD = 0 Bit 4 IACK = 0 Bits 3-0 Bit 3 (Address Modifier bit 5)

Bit 2 (Address Modifier bit 4) Bit 1 (Address Modifier bit 2) Bit 0 (Address Modifier bit 1)

5. Set register 8130h with the value corresponding to bits 21-16 of the VMEbus address with the two low order bits of the register set to 0.

VMEbus Address bits 21-16 Res Res

6. Map the address.

7. Write the data.

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Microsoft C code for Example 2 -

LWORD addr; /* 32-bit A32 address */ BYTE data; BYTE far * wptr;

outp(0x8104,(inp(0x8104)|2)); /* set VME access bit */ outp(0x8150,(WORD)(addr >> 24)); /* A31-A24 */ outp(0x8151,2 | (((addr << 8) >> 30) << 6)); /* A23-A22 and address modifier for A32 supervisory data access */ outp(0x8130,(WORD)((addr << 10) >> 24); /* A21-A16 */ wptr = (BYTE far *) (0xE0000000L + (addr & 0X0000FFFFL)); *wptr = data; /* Write through window */

The success of the access can be checked either by enabling BERR as an interrupt or by looking at the BERR bit in the event state register (8154h) after each access. Since writes are pipelined, software that looks at the BERR bit should first wait until the DONE bit is set.

Low-Level Handling of VMEbus Interrupts

The following is a description of how VMEbus interrupts (IRQ1-IRQ7), VXIbus message interrupts and error interrupts (BERR, ACFAIL, WDTG, etc.) should be handled on the EPC-5A. Note that, in general, the use of EPConnect is highly recommended to handling interrupts.

Enable the appropriate registers (VME Interrupt enable (8153h) and VME Event

•

enable (8155h) registers) to allow the interrupts you want to respond to.

Enable IRQ10 on the EPC’s equivalent of the 8259h interrupt controller.

•

A VXIbus message interrupt is generated when a master (this EPC-5A or another

•

master) writes to the Message Low register (16-bit) or the Message High and Message Low registers (32-bit) from the VMEbus. A message interrupt does not occur when the EPC-5A writes to its own message register(s) from the PC I/O space.

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• Keep in mind that while PC/AT interrupts are edge sensitive, VMEbus interrupts are level sensitive. As such, you must ensure that

1) The 8259 interrupt controller is enabled to capture interrupts before a VMEbus interrupt occurs (otherwise VMEbus interrupts will be totally missed) and

2) You must handle all pending VMEbus interrupts before returning from the interrupt handler.

• When an interrupt occurs, first acknowledge the interrupt to the PC/AT 8259

interrupt controllers by sending both interrupt controllers an End-of-Interrupt (EOI).

You must make sure that your interrupt handler code is not re-entered while

•

dispatching interrupts. Either all interrupts should be disabled or IRQ10 should be masked after doing the EOI to the interrupt controller. Remember to re-enable them prior to leaving the interrupt handler.

If you are using DOS, you may need to switch to an internal stack. This may or

•

may not be necessary in other environments and applications. You should also store the state of the VMEbus (i.e., current byte ordering, bus mappings and address modifiers) if you expect the state to change. Be sure to restore the state before leaving the interrupt handler.

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Start of Loop

• Determine the source of the interrupt or event. This can be done by reading the

VME Interrupt State register which should be ANDed with the VME Interrupt Enable register. As described above, the VME Event State register and VME Event enable register may also be potential sources for the generation of IRQ10. Keep in mind that all pending interrupts must be handled.

• If the interrupt is a VMEbus interrupt 1-7;

Acknowledge the interrupt to the VMEbus device generating the interrupt as follows:

1. Set the IACK bit in the VME Modifier register

2. Establish a byte-ordering for the status/ID to be read. Whether this is an 8-bit or 16-bit read is dependent on the card issuing the interrupt

3. The address modifiers and transfer length are dependent on the hardware generating the interrupt.

4. Perform a read of the VMEbus where the address being read reflects the interrupt level being responded to. Address lines A3-A1 must reflect the interrupt level in binary form. Multiply the interrupt level by 2 and use that as the address of the read operation.

5. After the read operation, clear the IACK bit in the VME Modifier register.

If the interrupt is a VXIbus message interrupt, the interrupt is acknowledged and

•

cleared by reading the appropriate register(s), followed by setting the WRDY bit in the VME Response register.

Call your interrupt handling routine.

•

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• Upon returning from the interrupt handling routine, go back to the beginning of

the loop until no more interrupts are active. In other words, you must handle all other active interrupts. This includes all other interrupts and errors which come in prior to calling the interrupt handling routine as well as any new interrupts and errors which may occur during this process. Only when all interrupts and error conditions are handled may you return from the overall interrupt handler. Again, if you miss any interrupts or errors, no other interrupts or errors are recognized.

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NOTES

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7. Connectors

This chapter specifies the details of the connectors on the EPC-5A. Please note, however, that all the connectors adhere to existing standards. The EXM expansion interface connectors are not defined here; their definition is available upon request. Connectors on EXMs and the EXP-MX are described in the separate manuals for those products.

All but the battery and speaker headers are on the front panel. Pins are labeled from the point of view of looking into the front of the connector on the EPC-5A.

Serial Ports

The COM1 and COM2 serial ports are DB-9 DTE connectors defined in the following table.

Pin Signal Pin Signal

1 Carrier detect 6 Data set ready 2 Receive data 7 Request to send 3 Transmit data 8 Clear to send 4 Data terminal ready 9 Ring indicator 5 Signal ground

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Table 7-1. Serial Port Pinout.

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Parallel Port

The DB-25 LPT1 parallel port connector is an Output-Only device defined as:

Pin Signal Pin Signal

1 Strobe 14 Auto line feed 2 DB0 15 Error 3 DB1 16 Initialize printer 4 DB2 17 Select in 5 DB3 18 Signal ground 6 DB4 19 Signal ground 7 DB5 20 Signal ground 8 DB6 21 Signal ground

9 DB7 22 Signal ground 10 Acknowledge 23 Signal ground 11 Busy 24 Signal ground 12 Paper end 25 Signal ground 13 Select

Table 7-2. Parallel Port Pinout.

Keyboard

The keyboard connector is a 6-pin DIN defined as:

Pin Signal Pin Signal

1 Data 4 +5V

2 not used 5 Clock

3 Ground 6 not used

Table 7-3. Keyboard Connector Pinout.

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1 2

Chapter 7: Connectors

Speaker Header

The speaker header is located on the EPC-5A circuit board and is defined as:

Pin Signal Pin Signal

1 Reference voltage 2 Speaker tone

Table 7-4. Speaker Header Pinout.

Battery Header

The battery header is located on the EPC-5A circuit board and is defined as:

Pin Signal Pin Signal

1 VBATT 3 Ground 2 (key) 4 Ground

Table 7-5. Battery Header Pinout.

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NOTES

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8. Upgrades

▲

CAUTION

Do not handle the EPC-5A module unless you are in a static-free environment.

Memory

The EPC-5A can be configured for various memory sizes. The 100 MHz EPC-5A memory configurations use SIMMs with the following specifications:

72 pin

•

fast page mode

•

60 nanosec. (or better)

•

single-sided

•

For 8 MB: Use 2 each 1M x 36 SIMMs

RadiSys P/N 70-0074

For 16 MB: Use 1 each 4M x 36 SIMMs

RadiSys P/N 70-0075

For 32 MB: Use 2 each 4M x 36 SIMMs

RadiSys P/N 70-0075

For 64 MB: Use 2 each 8M x 36 SIMMs

RadiSys P/N 70-0150

The SIMMs used in the EPC-5A are publicly available. Contact RadiSys Technical Support for more information.

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Figure 8-1. SIMM Memory Location.

After upgrading the memory, power up the machine and press F2 to enter the Main BIOS Setup Menu. Verify that the top line of this screen shows the correct amount of memory. Save and reboot. The system reboots and no error messages should be displayed.

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9. Troubleshooting & Error Messages

Troubleshooting

This section deals with problems that you may encounter that do not provide an error message. If an error message is displayed, see the next section of this chapter, Common Error Messages. Always attempt to solve the problem yourself. If you are unable to solve the problem, call RadiSys Technical Support. Make sure you have detailed system configuration available before starting your phone call.

Symptoms Possible cause(s) Solution

System appears to boot (evidenced by RUN LED being on, floppy and hard disk being accessed) but provides no video.

Video adapter not fully seated in subplane.

Remove the video adapter. If the subplane is secured to the VMEbus backplane by retaining screws, check for over tightening of the screws. Reinsert the video adapter and verify seating into the subplane.

Monitor or cable problem.

Video adapter failure.

Subplane failure.

EPC-5A cannot talk to EXM expansion interface.

Verify that the cable pins are not bent and the cable is fully seated in the video adapter. Try the monitor on another system to verify that the monitor is good.

Call RadiSys Technical Support.

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EPC-5A Hardware & Software Reference Manual

Symptoms Possible cause(s) Solution

System fails at power-up will not run power-on selftest.

The system is not getting power.

Check the backplane and verify that +5V power is good. Verify that the subplane is fully seated in the VME backplane and the EPC-5A is fully seated in the subplane.

Hardware failure.

Serial port(s) do not work. Bad power.

Interrupt conflicts

Port hardware failure. System will not talk across VMEbus.

The VMEbus backplane

may not be jumpered

correctly.

More than 1 master may

be set to provide Slot-1

functions.

EPC-5A or subplane may

have bent pins.

This cannot be diagnosed in the field. Call RadiSys Technical Support. Verify that backplane +12V and

-12V are good.

An EXM module is using the same interrupts as COM1 and/or COM2. Verify that no other card in the EPC-5A subsystem is using IRQ3 or IRQ4.

Call RadiSys Technical Support. See the section Installing the VMEbus Backplane Jumpers, in Chapter 2.

Make sure that only 1 system is configured as the Slot-1 controller and that it is the left-most system in the chassis.

Remove the EPC-5A and the subplane and verify that no pins are bent. Then reinsert the subplane and the EPC-5A.

Page 94

VMEbus interface failure.

Call RadiSys Technical Support.

RadiSys EPC-5A Hardware & Software Reference Manual

Specifications and Main Features

Frequently Asked Questions

User Manual

Hardware Warranty

List of Illustrations

List of Tables

Purpose

About this Manual

Notational Conventions

Product Overview

Specifications

Differences Between EPC-5 and EPC-5A

Configuring the EPC-5A

Selecting the EPC-5A Slot Location

Installing the VMEbus Backplane Jumpers

Jumpers

Subplane Installation

EXP-BP2 Subplane

EXP-BP4 Subplane

EXP-BP3A Subplane

EXP-BP5 Subplane

EXP-BP4A Subplane

EXP-BP6 Subplane

EPC-5A Insertion

EXP-MC Module Carrier Insertion

EXP-MX Mass Storage Module Insertion

EXM Module Insertion

Connecting Peripherals to the EPC-5A

Monitor

Keyboard

Serial Ports

Parallel Printer Port

Introduction

BIOS Setup Screens

Main BIOS Setup Menu

IDE Adapter Sub-menus

Memory Shadow Sub-Menu

Boot Options Sub-menu

Keyboard Features Sub-menu

Advanced Menu

EXM Menu

VME Menu

Exit Menu

Processor board

Processor and Coprocessor

Core Logic

Memory

Memory Map

Real Time Clock

Keyboard Controller

ROM and ROM Shadowing

Embedded Shadow

Bootable Device Precedence

Battery

Video Controllers

Front Panel LEDs

Resetting the EPC-5A

EXM Expansion Interface

Connectivity

VMEbus System (Slot-1) Controller Functions

Concepts

Memory Map

Direct VMEbus Accesses

Byte Ordering

Slave Accesses from the VMEbus

Self Accesses Across the VMEbus

Read-Modify-Write Operations

VMEbus Interrupt Response

Registers Specific to the EPC-5A

VMEbus Mapped Registers

Register State after Reset

Supported Address Modifiers

Low-Level Programming the VMEbus Interface

VMEbus Accesses

Low-Level Handling of VMEbus Interrupts

Serial Ports

Parallel Port

Keyboard

Speaker Header