Radio Shack Tandy 200, 26-3861 Technical Reference Manual

Tandy

200 Technical

Reference

Manual

26-3861

TERMS

AND CONDITIONS

OF SALE AND LICENSE

OF TANDY

COMPUTER EQUIPMENT

AND

SOFTWARE

PURCHASED FROM RADIO

SHACK

COMPANY-OWNED

COMPUTER CENTERS, RETAIL

STORES

AND RADIO SHACK

FRANCHISEES OR

DEALERS AT

THEIR AUTHORIZED

LOCATIONS

LIMITED

WARRANTY

I. CUSTOMER

OBLIGATIONS

„ ,„ j

A. CUSTOMER

assumes

full responsibility that

this computer

hardware purchased

(the "Equipment'

),

and

any

copies of software

included with the

Equipment or licensed

separately

(the "Software") meets the

specifications,

capacity,

capabilities, versatility, and

other requirements

of CUSTOMER.

B. CUSTOMER assumes

full

responsibility for the condition

and effectiveness

of the operating

environment in which

the Equipment and

Software are to

function, and for its

installation.

II.

LIMITED WARRANTIES

AND CONDITIONS

OF SALE

A. Foraperiod

of ninety

(90)

calendar days from the

date of the

Radio Shack sales

document received upon

purchase of the

Equipment.

RADIO SHACK

warrants to the

original CUSTOMER that

the Equipment and the

medium upon

which the

Software is stored is free

from

manufacturing defects. This

warranty It only applicable

to purchases

ol Tandy

Equipment by tha

original

customer from Radio Shack

company-owned

computer

centers, retail

stores, and Radio

Shack franchisees

and dealers at

their authorized locations

The warranty is

void if the

Equipment's case or

cabinet has been opened,

or if the

Equipment or Software

has been subjected to

improper or

abnormal use. If

a

manufacturing defect is

discovered dunng

the stated warranty period,

the defective

Equipment must be

returned to a

Radio Shack Computer

Center, a

Radio Shack retail store, a

participating Radio

Shack franchisee

or a

participating Radio Shack

dealer for repair,

along with a copy of

the sales document or

lease

agreement. The

original CUSTOMER'S

sole and

exclusive remedy in the

event of

a

defect is

limited

to

the

correction

of the defect by

repair, replacement,

or refund of the

purchase price,

at RADIO SHACK'S election and

sole expense.

RADIO

SHACK has no

obligation

to

replace or

repair expendable items.

B. RADIO

SHACK makes no

warranty as to the

design,

capability, capacity, or

suitability for use of the

Software,

except as

provided in this

paragraph. Software is

licensed on an AS

IS" basis, without

warranty. The original

CUSTOMER'S

exclusive remedy,

in the event of a

Software

manufacturing defect, is

its repair or replacement

within thirty

(30)

calendar days of the

date of the Radio

Shack sales

document received upon

license of the

Software. The

defective Software

shall

be

returned to a

Radio Shack

Computer Center, a Radio

Shack retail store,

a

participating

Radio Shack

franchisee or Radio

Shack dealer along

with the sales document.

C. Except as

provided herein no

employee,

agent, franchisee,

dealer or other

person is authorized to give

any

warranties of any

nature on

behalf of RADIO SHACK.

.„

D. EXCEPT AS

PROVIDED HEREIN,

RADIO

SHACK MAKES NO

EXPRESS WARRANTIES,

AND ANY IMPLIED

WARRANTY OF

MERCHANTABILITY

OR FITNESS FOR A

PARTICULAR

PURPOSE IS LIMITED IN

ITS DURATION

TO THE

DURATION OF

THE WRITTEN

LIMITED WARRANTIES SET

FORTH

HEREIN.

E. Some

states do not

allow limitations

on how long an

implied warranty

lasts,

so

the above

limitation(s) may not

apply to

CUSTOMER.

A. EXCEPT AS PROVIDED

HEREIN,

RADIO SHACK SHALL

HAVE NO

LIABILITY OR

RESPONSIBILITY TO CUSTOMER

OR ANY

OTHER PERSON OR

ENTITY WITH

RESPECT TO ANY

LIABILITY, LOSS OR

DAMAGE CAUSED

OR

ALLEGED TO BE

CAUSED

DIRECTLY OR

INDIRECTLY BY

"EQUIPMENT' OR

"SOFTWARE" SOLD. LEASED.

LICENSED

OR FURNISHED BY

RADIO SHACK.

INCLUDING. BUT

NOT LIMITED TO,

ANY

INTERRUPTION OF

SERVICE. LOSS OF

BUSINESS OR

ANTICIPATORY PROFITS OR

CONSEQUENTIAL

OAMAGES

RESULTING FROM

THE USE

OR OPERATION

OF THE

"EQUIPMENT" OR "SOFTWARE."

IN NO

EVENT SHALL RADIO

SHACK

BE

LIABLE

FOR LOSS OF

PROFITS. OR

ANY INDIRECT. SPECIAL.

OR

CONSEQUENTIAL DAMAGES

ARISING OUT OF

ANY

BREACH OF THIS

WARRANTY OR

IN ANY MANNER

ARISING OUT OF OR

CONNECTED WITH THE SALE.

LEASE,

LICENSE, USE

OR ANTICIPATED USE

OF THE

"EQUIPMENT' OR "SOFTWARE."

_

NOTWITHSTANDING

THE ABOVE

LIMITATIONS AND

WARRANTIES. RADIO

SHACK'S LIABILITY

HEREUNOER FOR

DAMAGES INCURRED

BY CUSTOMER OR

OTHERS SHALL NOT

EXCEED THE

AMOUNT PAID BY

CUSTOMER FOR

THE

PARTICULAR

"EQUIPMENT" OR

"SOFTWARE" INVOLVED.

B. RADIO SHACK

shall not be liable

for any damages caused by

delay in

delivering or furnishing

Equipment and/or

Software.

C.

No action

arising out of any

claimed breach of this

Warranty or

transactions under this

Warranty may be brought

more than two

(2)

years after the cause

of action has

accrued or more

than four

(4)

years

after the date of the

Radio

Shack sales

document for the Equipment or

Software, whichever

first occurs.

D. Some

states do

not allow the

limitation or exclusion of

incidental or

consequential damages, so

the above

limitation(s) or

exclusion(s) may not

apply to CUSTOMER.

IV. SOFTWARE

LICENSE

RADIO SHACK grants to

CUSTOMER a

non-exclusive, paid-up

license to use the

TANDY Software on one

computer,

subject to the following

provisions:

A. Except as

otherwise provided

in this Software License,

applicable

copyright laws shall apply to

the Software.

B. Title to the

medium on which the

Software is recorded

(cassette and/or

diskette) or stored (ROM) is

transferred to

CUSTOMER,

but not title to the

Software.

C.

CUSTOMER may use Software

on

a

multiuser or

network system only if

either, the

Software

is

expressly labeled

to be

for use on a

multiuser or network system,

or one copy

of this software is

purchased for each node or

terminal on which

Software is to be used

simultaneously.

D.

CUSTOMER shall not use,

make, manufacture,

or reproduce copies

of Software except

for

use

on one computer

and as

is specifically

provided in this

Software License.

Customer is expressly

prohibited from disassembling

the

Software.

E. CUSTOMER is

permitted to make

additional copies of the

Software only

for backup or archival

purposes or d

additional copies

are required in the

operation of one

computer with the

Software, but only to the

extent the

Software allows a

backup copy to be

made. However,

for TRSDOS

Software, CUSTOMER is permitted

to make

a

limited

number of additional copies

for CUSTOMER'S

own

use.

F.

CUSTOMER may resell or

distribute unmodified

copies of the

Software provided

CUSTOMER has purchased one

copy

of the

Software for each one sold or

distributed. The

provisions of

this Software License

shall also

be

applicable to

third parties

receiving copies of the

Software from

CUSTOMER.

G. All

copyright notices

shall

be

retained on

ail copies of the

Software.

V APPLICABILITY OF

WARRANTY

A. The

terms and

conditions of this

Warranty are applicable as

between RADIO

SHACK and CUSTOMER

to either a

sale of

the Equipment

and/or Software License

to CUSTOMER or

to

a

transaction whereby

Radio Shack

sells or

conveys such

Equipment to a third

party for lease to

CUSTOMER.

B. The

limitations of liability and

Warranty provisions

herein shall inure to

the benefit of RADIO SHACK,

the author,

owner and

or licensor ofthe

Software and any

manufacturer of the

Equipment

sold by

Radio

Shack.

VI. STATE LAW

RIGHTS

„..„

The warranties granted

herein give the

original CUSTOMER

specific legal rights,

and the original

CUSTOMER may

have other rights

which vary from

state to state.

8/85

Chip specifications are reprinted by

permission

of Hitachi

America,

Ltd.,

Semiconductor and I.C. Sales and Service

Division.

Tandy 200

Technical Reference Manual:

°1986,

Tandy Corporation

Reproduction or

use, without express written permission

from Tandy Corporation and/or its licensor,

of

any portion

of

this

manual

is prohibited. While

reasonable efforts

have

been

taken

in the

preparation of this

manual

to

assure its

ac-

curacy,

Tandy Corporation assumes no liability resulting

from any errors or omissions in this

manual,

or

from

the use

of the information contained herein.

Tandy

and Radio Shack are registered trademarks of Tandy

Corporation.

10 987654321

CONTENTS

INTRODUCTION

1-1

External

View

,

1-1

Internal

View

,

1-4

Specifications

1-6

THEORY

OF

OPERATION 2-1

General

2-1

Block

Diagram

,

2-2

CPU

2-4

Memory

2-4

Address

Decoding

and Bank

Selection Circuit

2-7

I/O Map

2-8

Keyboard

2-11

Cassette Interface

Circuit

2-12

Printer

Interface

Circuit

2-13

Bar

Code Reader Interface Circuit

2-14

Buzzer

Control

Circuit 2-15

Clock Control

Cirucit

2-16

Serial

Interface Circuit

2-20

LCD

2-30

Power

Supply

and Auto-Power ON/OFF

Circuit 2-39

APPENDIX

A/ INSTALLATIONS

A-1

Installation

of Operational RAMs

and

ROM

A-1

Installation

of Nickel-Cadmium

Batteries

A-1

APPENDIX

B/ KEYBOARD LAYOUT,

CONNECTOR PIN

ASSIGNMENTS AND

CHARACTER

CODE TABLE .... B-1

Keyboard

Layout

B-1

Connector Pin

Assignments

B-2

Character Code Table

B-7

APPENDIX

C/

TECHNICAL INFORMATION

C-1

80C8SA

C-1

81C55

C-13

82C51

C-19

Basic

Construction

of LCD

C-29

HM6264LFP-12

C-31

HM6264LP-10

C-37

HN613256P

C-45

HN61364P

,

C-49

MC14412

C-51

RP5C01

C-57

APPENDIX D/

200

ROM INFORMATION

D-1

List of

Illustrations

FIGURE

PAGE

NUMBER

DESCRIPTION

NUMBER

1 Front View

1-2

2 Rear View

1-2

3 Bottom

View

1-3

4 Main PCB

1-4

5 LCD PCB

1-5

6 Memory PCB

1-5

7 Organization

2-1

8 Biock Diagram

2-3

9

Functional Block

Diagram of Bus Separation

Circuit

2-4

1 Memory Map

2-5

1

Internal Wiring Diagram of RAM

Package

2-6

12 Bank Selection

Circuit

2-7

13 I/O Address

Decoding

Circuit

2-8

14

I/O Map

and I/O Port Description

2-9

1

Condition of Pressing "T" Key

2-11

16 Write Circuit of Cassette

interface

2-12

17

Read

Circuit

of Cassette

Interface

2-12

18 Remote

Circuit of Cassette Interface

2-13

1

Printer Interface Circuit

2-14

20 Bar Code Reader Interface

Circuit

2-15

21 Buzzer Control

Circuit

2-15

22

RP5C01

Internal Block Diagram

2-16

23

Flowchart for the TIMER IC

2-18

24 Functional Block Diagram

of the Serial

Interface

2-21

25

RS-232C/MODEM Selection

Circuit

2-23

26 RS-232C

Interface Circuit

2-24

27 MODEM IC and Peripheral Circuit

2-25

28 Transmission Filter Circuit

2-26

29 Reception

Filter

Circuit

2-27

30 MODEM Connector Interface

Circuit

2-28

31

Tone

Signal Generator Circuit

2-29

32 Internal Block Diagram

of

HD61830B

2-31

33 Internal

Block

Diagram

of

HD61103

2-33

34

Output

Waveform of HD61103

2-34

35 Internal Block Diagram of HD61100

2-35

36 Output Waveform of HD61100

2-36

37 Driving

Waveform of

LCD

2-38

38

Power Distribution

2-40

39

DC/DC

Converter and Low Power

Detection

Circuit

2-42

40 Power Contra! and Reset

Circuit

2-45

41

Power-Up/Down Sequence

2-46

FIGURE

PAGE

NUMBER

DESCRIPTION

NUMBER

A-1

Memory PCB

A-1

A-2

Installation of

Nickel-Cadmium

Batteries

A-2

B-1

Keyboard

Layout

B-1

B-2

System Bus

Connector

B-3

RS-232C Connector

B-4

B-4 Printer

Connector

B-5

Cassette

Connector

B-5

B-6

Modem Connector

B-5

B-7

Bar

Code Reader

Connector

B-6

C-1 Functional Block

Diagram

C-2

Configuration

of

80C85A

C-3

C-3 Trap

and RESET IN

C-8

C-4 80C85A

Basic

System Timing

C-12

C-5 Functional Block

Diagram

C-1

C-6 Pin

Configuration of

81C55

C-13

C-7

Internal

Register ot

81C55

C-15

C-8 Programming

the Command/Status

Register

C-16

C-9

Reading the

C/S

Register

C-17

C-10 Bit

Assignments to the Timer

Counter

C-18

C-1

Functional

Block Diagram

C-1

C-12 Pin Configuration

of 82C51A

C-20

C-13

Function-Setting

Sequence

C-24

C-14 Bit

Configuration

of

Mode Instruction

(Asynchronous)

C-25

C-15 Bit

Configuration

of Mode Instruction

(Synchronous)

C-26

C-16 Bit Configuration

of Command

C-27

C-17 Bit

Configuration

of

Status Word

C-28

C-18

Construction of LCD Panel

C-29

C-19 Operation Theory

of LCD Panel

C-30

List

of Tables

TABLE

PAGE

NUMBER

DESCRIPTION

NUMBER

1 Port Assignment

of

the 81 C55

2-10

2 RP5C01

I/O Port Address

Assignment 2-17

B-1

System Bus Connector Pin

Assignments

B-2

RS-232C

Connector

Pin Assignments

B-3

Printer

Connector Pin

Assignments

B-4

C-1 Interrupt

Priority,

Restart

Address

and Sensitivity

C-6

C-2

80C85A Machine

Cycle Chart

C-10

C-3

80C85A Machine

State Chart

C-1

C-4

I/O Address

of 81C55

C-15

C-5 Port

Control

Assignment

C-16

C-6 Operation

between

82C51A and

CPU

C-23

in

INTRODUCTION

Tandy 200

portable

computer is an

enhanced version

of

the Radio Shack

Model

100 Portable

Computer. The Tandy

200

is software

compatible with the Mode!

100

in BASIC so that both

system

users can take

advantage of the

large

number of

programs

available.

One

important difference

between

the Model 100

and

Tandy 200 is

the size of

the LCD screen. The

Tandy

200's LCD

screen

is double the

size of

the Model

100's. That is, the

Model

100's display

capability is 40

x

8

characters while the

Tandy 200 has

a display

capability of

40

x

1

6

characters.

The Tandy

200 has

the following

applications programs

in

the

standard ROMs:

BASIC, TEXT,

ADDRSS,

SCHEDL,

TELCOM,

MSPLAN,

and ALARM.

External

View

1 Keyboard.

Can

be used like

the

standard

typewriter.

However, the

Tandy

200

does

have a few

special

keys. (See

Appendix

B of this

manual

for more

details.)

2 LCD Unit. The Tandy

200

display has

sixteen

lines that

allows 40

characters on

each

line.

3

POWER Switch.

Push this

switch to

turn the

power ON or

OFF. To

conserve the

batteries, the Tandy 200

automatically

turns

the power off

if

you do not use

it for 10 minutes.

4 Low Battery

Indicator.

Before the

Tandy 200's

operational batteries

become

exhausted, this

indicator

will illuminate.

5 Display

Adjustment Dial.

This control adjusts

the

contrast of the LCD

display

relative to the

viewing angle.

6 External

Power

Adapter

Connector. Connect

the

appropriate end

of

Radio Shack's

AC

Power Supply

(Catalog

Number

26-3804,

optional/extra)

to

this connector.

Connect

the other end

of

the power

supply to

a

standard

AC wall

outiet or

approved

power

strip.

1-1

Figure 1. Front View

DIR/ACP Selector.

This selector allows you to select

either

a

direct or

acoustic

coupler connection. If you are

communicating

with another

computer over the phone

Sines via the built-in, direct-connect modem, set

this switch to the

DIR position. If

you

are using the optional/extra Model

1

00

Acoustic Coupler

(26-3805),

set this selector to the ACP

positron.

RESET Switch,

if the

Tandy

200 "locks up" (i.e., the display "Ireezes"

and

all

keys seem to

be inoperative), press this

button

to

return

to

the

Main

Menu (start-up). It is not likely that the

Tandy

200 will lock-up when you are

using the built-in

applications programs,

however, it may occur with

customized

programs.

RS-232C

Connector.

Attach

a

DB-25 cable (such as Radio

Shack

Catalog

Number

26-1408) to this connector when you need to

receive or

transmit

serial information. When

communicating

directly with another Radio Shack

computer, a Null MODEM

Adapter (26-1496) is

required. An

8"

Cable

Extender

(26-T497)

may also

be required.

SYSTEM BUS

Connector. Connect

this connector to the Disk/Video

Interface

(26-3606),

using the system bus cable.

PRINTER Connector.

For

hard-copy

printouts of information,

attach

any

Radio

Shack

parallel printer to this connector,

using an optionai/extra

printer

cable.

Direct-Connect MODEM (PHONE) Connector.

When communicating with

another computer via the

Tandy

200's

built-in MODEM, connect the round

end

of the

optional/extra modem

cable to this connector.

CASSETTE Recorder Connector.

To save or load information on a

cassette tape, connect

the cassette recorder here. An

optional/extra

cassette recorder (and cable) is required.

Bar

Code

Wand

Connector. Attach the optional/extra

bar

code

wand

to

this connector. Note that special bar code

reader software is required.

o

O

o

O

O o

(D ® ®

Figure 3. Bottom View

1-3

1

MEMORY

POWER Switch. This switch is

used to

prevent

discharge of the

internal Nickel-Cadmium

battery, which is

used

for RAM back-up.

The Tandy

200 will operate

only when the power switch is

set to ON. Set this switch to

the OFF position

when the Tandy 200 will not

be used

for

a

long

period of

time.

Note that the RAM will not

be backed up when this switch is set

to

the

OFF

position.

2

Optional

ROM and RAM Compartment. An optional/extra

ROM and

RAMs can

be

inserted into

this compartment to enhance Tandy

200

capabilities.

3

Battery

compartment. When not

connected to an AC power source, the

Tandy

200 gets its power from four AA size batteries that

must be installed

in

this compartment. If the

Tandy 200 has the modification jumper

module

installed Bar Nickel-Cadmium

batteries, the battery cover is fixed

by a

tapping screw and covered

by a black sticker.

Internal

View

The Tandy

200 consists of four printed

circuit boards:

•

LCD PCB

•

Keyboard PCB

•

Main PCB

•

Memory

PCB

Potentiometer

VR1

for

MODEM

Transmitting

Level

Tone Dialer IC

Xtal

for Tone

Dialer IC

Gate Array

(SLA5080F0U)

LCDC

(HD61830B)

CPU

(80C85A)

PIO(81C55)

ROM

(BASIC,

etc.)

ROM (MSPLAN)

RAM for LCDC

Battery for

Memory

Back-up

USART

(82C51A)

Figure

4. Main

PCB

1-4

Segment Driver

Common Driver

Segment Driver

OP

Amp. for Power Supply

Figure 5. LCD PCB

Standard

RAMs

(8

K-byte

x

3)

xtal for Timer IC

Timer

IC

Reserved through

Holes

for

Modification

Jumper Module

IC Sockets for

IC

Socket for Optional ROM

Memory

Power

Switch

Optional

RAMs

Figure

6. Memory PCB

1-5

Specifications

Main

Components

Keyboard

71

keys

(9x8

matrix)

Alphabet keys

27

Number keys

10

Picture-control keys

7

Function

keys 8

Special

symbol keys 8

Mode keys

5

Other special-use

keys 6

LCD

display

Dot pitch

240

x

128

full-dot matrix

1/64

duty

1/9 bias

Dot pitch

0.8x0.8

mm

Dot

size

0,73x0.73 mm

Effective display area

191.2

(W}x101.6(D)

mm

Operation batteries

Batteries

Four type AA

Alkaline-manganese batteries

Operation time 7 days

(at

two hours/day)

(Note:

Without I/O units at normal

temperature)

Memory

protection battery (on

Main PCB)

Battery

Rechargeable battery

Back-up time About 15 days (24

KB)

About 5

days

(72

KB)

Recharge method

Trickle charge by AC adapter

or

operation

batteries

LSIs

CPU

ROM

RAM

Dimensions

Weight

80C85A

Code

and

pin compatible with 8085

Maximum 104 KB

Standard 72 KB

Option 32 KB

Maximum 72 KB

Standard

24 KB RAM

Incremental 24 KB RAM on

the

memory PCB

11 -4/5"{L)

x

8-4/9"(D)

x 2"(H)

4 lbs. 4 oz.

1-6

I/O

Interface

RS-232C

Conforms

to E1A

Standard

Signal

Communications

Protocol

Word length

Parity

Stop Bit

length

Baud rate

Maximum

transmission

distance

Drive maximum

voltage output

Drive

minimum

voltage

output

Receive

maximum

voltage

input

Receive minimum

voltage

input

MODEM/Coupler

Conforms

to BEL103

Standards

Data length

Parity

Stop bit

Full

duplex

Other

functions

Audio

cassette interface

Data Rate

Printer

interface

Conforms

to Centronics

interface

standards

Handshake

Signal

TXR {Transmit

Data)

RXR (Receive

Data)

RTS (Request to

Send)

CTS

(Ciear to Send)

DSR (Data

Set

Ready)

DTR (Data Terminal

Ready)

6,

7

or

8

bits

NON, EVEN,

ODD or IGNORE

1 or 2 bits

75, 110,

300, 600, 1200,

2400, 4800,

9600, 19200

BPS

5 meters

±

5

volts

±3.5

volts

±18 volts

±3

volts

6,

7 or 8 bits

NON,

EVEN, ODD

or IGNORE

1

or

2

bits

Answer

mode/originate

mode,

switchable

by software

Hang-up

function

Auto-diafer

function

1500 BPS

(MARK:

2400

Hz, SPACE:

1200

Hz)

STROBE,

BUSY,

BUSY

1-7

THEORY

OF OPERATION

General

This section

describes

the

theory of operation

for

the Tandy

200. Figure 7

shows how this section is organized and highlights significant

areas.

I*

CO

CJJ

III ji!

—til

lis

id

11

(6 u

5_ HI

So

li

r

^

h

Q

(J

b

I,

si

i

l, si

i

91

1

ii

j

c

I

O

s

2-1

Block

Diagram

The

Tandy

200 has

four

principal LSis:

•

60C85A

CPU

This is the Central

Processing

Unit which

controls

all functions.

•

61

CSS

PIO

This

is

the Parallel Input/Output

Interface

controller

which controls the printer

interface, keyboard,

buzzer,

clock, LCD

interface

and data input of

BCR

interface.

•

82C51AUSART

This

is the

Universal

Synchronous/Asynchronous

Receiver/Transmitter

which

controls the

serial interface such as

the

RS-232C and

MODEM.

•

SLA5080FOU

Gate

Array

This

LSI

consists of the large

number of

general-purpose

gates

which are

used for the I/O

addressing,

bank selection and

other control circuits.

The

input/output

for a cassette

recorder

and the

interruption

from the BCR for

the starting data are

controlled

by

the CPU directly

through

its SOD, SID and

RST 5.5 terminals.

2-2

J/D DON TROLL Eft

E

£

8

m

3

en

2-3

CPU

The

CPU

is an 80C85A thai

runs

at a clot* speed

of 2.4576 MHz.

It is an 8-bit,

parallel

Central Processing

Unit

using C-MOS technology.

The Instruction

set is

fully compatible with the 8085A microprocessor. The 80C85A uses

a

multiplexed

data bus. The CPU bus is divided into two sections

—

the 8-bit

address bus named the A8-A15, and the 8-bit address and data bus named the

AD0-AD7,

The address and data bus are

separated

in

the SLA5080FOU

by

using the ALE signal. The functional block diagram of this circuit in the

SLA5080FOU is shown in Figure 9.

AL.E

^»

TNTA

o-

H>

x>

D

Q

H>>

<h

Figure 9.

Functional

Block Diagram of Bus Separation Circuit

Memory

The

Tandy 200

uses a 32K-byte

ROM

for the MSPLAN, 40K-byte

ROM for

BASIC and the other

application programs, and

24K-byte static

RAM to store

the data and programs.

The 40K-byte ROM

consists

of an 8K-byte ROM (M13)

and

32K-byte

ROM (M15). The 24K-byte

RAM consists of three

8K-byte

RAMs.

Furthermore, a

32K-byte

ROM and two 24K-byte

RAM packages can be used

optionally.

The 24K-byte RAM package

consists of

three 8K-byte

RAMs and

one decoder IC

{40H138), mounted

on

a

ceramic

substrate.

Figure

10 shows

the memory map

and

Figure 11 shows the

interna!

wiring

diagram of the RAM

package.

2-4

QQDD

RDM 9*NK>]

JOKE

3EK"9

W J

-

J

&FFF

ADPP

DFFF

EGDQ

8HS_

RAM &*"***..

8KB.

.„

24K_B

8KB.

8KB

JKB

SAW

AANK#5

JKB

^^

JK|_

_2jlK_B

_3KB

STANDARD

Figure

10- Memory Map

2-5

cs2

Si

go

04—

1£.

HC

_L

end

vcc

29

m

T

AD

Al

A2

4—

Al

i A2

«(

4

—

-A3

-S

A4 Ab AS AT AB

A9

A 10

An

A12

4—

A5

J—

AG

"35

A7

Ijwr- AID

^aii

^¥

Nt

-nn

N

9-r-

nc-S—

I

mc

-

a c

Q2A

028

0]

X

Figure 11.

Internal

Wiring diagram

of

RAM

package

2-6

Address

Decoding and

Bank

Selection

Circuit

Selection

of

RAMs and ROMs

are determined by

the address and bank signals

generated

in the SLA5080F0U.

Figure

12

shows the bank

selection circuit

in

the

SLA5080FOU.

The latch AA0036

stores

the bank selection data

sent

from the CPU with the Y5

and WR signal.

The decoder AA0038 is

enabled

by the memory address

0O00H

to 9FFFH for ROMs and the

decoder

AA0037 is enabled by

the

memory

address A00OH to FFFFH

for RAMs.

JD/M

AJS

A02

AD3

T>

O

=£>

AAD03G

ID 10

20 2ti

2D 3B

40 40

o

f-4

4 fl

^

BAHKfS

A*0037

Figure 12. Bank Selection Circuit

2-7

I/O Map

Figure

13

shows the I/O address decoding circuit included in the

SLA508OF0U

that decodes

address signals

AD4-AD6.

The AD7

signal

acts as the enable

signal for the decoder AA0024 with the IO/M signal.

At the

latch AA0063, the

chip

enable

terminals G1 and G2 are connected to the ALE signal

passing

through

the inverter,

because the AD0-AD7 signals are the multiplexed

bus.

The

I/O

map and I/O port description are shown In Figure 14.

The

port

assignment of the 81C55 is shown In

Table

1.

H

<

§3

n

O

<u

<

Q Q~JtQ Q Q-ln a 0.

—

CM

>• >-

>-

>

>-

a a —

(SI

o

a

n

"«

—

CM

goo

T3

Q

ID

a

<

a

<

I

£ 3

2-8

0".Q

—

Q

—

O—

XXXXXXXX

w n

h-

<

H

Q Z

<

< m o

o

_i

X

U

x

O

HI

a

IY

^J ^

Ji

l- K

(-

ui til

3 « a &

T

7

1-

H

o a o

a o O

u 0. a. a. K t~ z z

Ul t-

ut

a> ^

r^

H

o

<

X

*-t

z

"=

.

,

8

w

t-

^

a:

o

>-

£

Ul <w

z

o

u

X

_JI-

in

<

ui£

z

t-

£

S

o

<<

o

(J

-JO!

5

•«

Q

^

o

3°

in

z

o H

CO

(D

z<

Ctun

UJ i_

*

5

CO

IS

-V

Ul

si a

_l

U,o

t-oo

U.O

u.o U-O

U.O

LLO

<n<

<CD m(j ua

Ul

Ulli.

u.

Figure

14.

I/O Map

and I/O

Port Description

2-9

in in

O

oo

•»-

o

c

»

E c

» w

< £

CD

C

a>

cz

O

*c

a

.£

CD

<D

s:

c

0)

o

cz

"(D

<"

o

2

CD CO

cz

o

Li

>

2.

a

O

o

E

O

<

'c

,-.

N-"

U)

<

i-

u

3

to

S

X

Z

N

J

<

co

a>

I

'"5

£—

o

Li

CZ

=

—

LO

1

oc

>

a>

CO

<u

=

1

O

H

=

<

>

<

en

>

<S <

5

CQ

S

O Li

—

3

x

S

eg

5

«

CD

VJ

3

a

B

cz

—

o

z>

O

a

X

"l

CD

4M

Q

a

c

O

5

><

o

c

CO

cz(0cz

to

m *t

in

to r--

cz cz cz cz cz

co co co

co

CO

cz

CO

O

z

1

a

-( x

CD

l_J

! =

Zl

Q.

CZ

ier

Detect

Break

Do'

:k

Output

and

Melod

o o o o o o o o o

-

"dd. LU

JO

^^

to to CO W WBW W co

5<or

5

.£

"""*

CD

ti

<B > >

Q

>> >> >,

>s

>* >. >1 >1 >1

Q.

*•

2

«

"

O = +=

•^-^

O

CD CD a> CD CD CD CD CD CD

—

3 , CZ

Q>

< CZ O O "ti

o

m*m

(0

4—

1

^ ^ *: ^ ¥

cr>

•*

m to r«-

CO

CO CO

(0 to

*^ +j +j *j

*-i

CO

eg

°

=

X

CO

"3

a

3

«

CI

LU

"

«

< <

g

co

—

Zl

>

CL CL

O o

c c

ZJ

a

c

t3

Q

co m CO CO CO CO <0 CO to

<

rS

o

<-»

o

E m

(0

o O Q Q O Q Q D D

>

LU

CO

<D

_l

CL

>

a

k_

CD

c cz cz cz cz c cz

c

cz «

S

_r

T3 -J

J

CO

EC

t

°

t. L*

l~.

w t— h» V* h» l»

£

3

CO

o

LU

o

5

o

D D o

(0 « £

fl. a.

0-

a. a. a. a. a. Cu O £Q CC CL CQ 2 Q _j CQ CQ CO

O o o

O

O o O OOOOOOOOOO o O O

-

o

1

o

T^

CvJ n *

to

<o s

o

t-

OJ CO

<*

w u> N

O t- CM

ro

*

lO

t-

< < < < < < < <

CD CO DO DO CQ CD CQ CQ

O O O O o

o

Q.

Q-

(L a. a. o. q_ a.

a. a. a. a. cl a. a. a. a. a. cl CL CL CL

h-

Table 1. Port Assignment

of

trie

81C55

2-10

Keyboard

Key

strobe

signals

are

emitted

from

the PBO

and PA0-PA7

terminals

of the

81C55,

and the

return

signals

from

the

keyboard_pass

through

the

octal bus

buffer

(M27) which

is

enabled

by

NANDing

the

RD

and STB/K

signals

at M29,

and then

the return

signafs are

sent to the

CPU.

The

STB/K

signal

is

generated

in the

SLA5080F0U

when the

CPU

assigns

EO-

EFH to

the I/O

port

address.

The CPU

starts the

key

scan

operation

when

the

RST

7.5 interruption

is

accepted.

This

interruption

(TP

signal)

is

generated

about

every

3.3 msec,

at M34 by

dividing

the

CLK signal

(2.4576 MHz).

Condition

ol

pressing

"T"

key is

shown

in Figure

15.

&-I

fl-

I a. I fl. i o_ .a*

a. a.

a,

Hf

m|

u>y c-y

Jj uij

»["[

<*l

_L

3

*

=

i

=

3

Z3

Z)

ZJ

^>

=

3

r

<

a.

< <

a.

< <

0. 0-

Figure

15.

Condition

of Pressing

"T" Key

2-11

Cassette

Interface

Circuit

The

cassette

interface circuit

Is subdivided

Into three

sections:

•

Write

Circuit

•

Read

Circuit

•

Remote

Circuit

Write

Circuit

The

write

circuit

is accomplished in

several steps. First, the

serial data from the

SOD terminal

of the CPU

Is Inverted

by M1. Then,

the

DC component

Is

removed

by

C3.

And

finally,

the data

passes through an integrator

consisting

of

R8

and

C2,

and

after voltage division,

out to a cassette

recorder

AUX jack.

Figure

16

shows

the

write circuit

of

the

cassette interface.

-oo

I—

SIOD

PUI

rLTLTLn

Figure

16. Write Circuit of

Cassette Interface

Read

Circuit

The

signal

input from the

earphone

jack of the cassette recorder

passes

through

the clamp circuit

consisting

of D1 and D2, and then is input

to

the

comparator

circuit

consisting of M2.

Finally, the

signal is converted

into the digital signal

and sent

to

the SID

terminal

of the

CPU. Figure 17 shows the

read circuit.

In

the circuit,

DS clamps the negative

voltage

output

of

the comparator.

CN2

VDO

rLTLTLTI

Figure

17.

Read Circuit

of

Cassette Interface

2-12

Remote

Circuit

By writing-in data

"1

" into bit 1 of the output

port specified

by EO-EFH, the

REMOTE

terminal

of

the SLA5O8OF0U Is

changed

to "H." Then T1

1

Is switched

ON and

RY1

Is

energized. This

controls

the motor of the cassette

recorder.

AADOZ*

i5E

51

TO

c

v5

TO

75

rS

o o

3

D

-.)

eTcss

9TBP

lS5

|*s

W

AAOtHfl

C Q

D Q

5?

L>

ffEWOTE

Dt

Gat*

Arraj

SLA50BOFou

Figure

18. Remote Circuit of

Cassette

Interface

Printer Interface

Circuit

The printer Interface

circuit conforms to

Centronics

standards. As

shown in

Figure

19,

the

BUSY

signal from the

printer is

read from the PC2

of

the 81C55.

If

the

condition Is

not busy (PC2

=

"L"), the 8-bit

parallel data

(PA0-PA7

from

81C55)

is

sent to the

printer.

Then, by writing-in

data

"1"

into bit 1 of

the output

port specified by I/O

address

EO-EFH, the

PSTB

signal is generated

in the

SLA5080FOU

and sent

to the

printer.

As soon as the

printer

receives this PSTB

signal, the BUSY

signal is

changed

to

"H" indicating that the

printer is

busy.

The CPU

then

waits lor a while

until

this BUSY

signal becomes "L"

As soon

as the

printer

prints the one

character

specified

by

the 8-bit

paralle! data,

the BUSY

signal

becomes "L"

Then, the

CPU sends the

If the printer is in

ON

LINE condition, the

BUSY

signal is "H" and

sent to

the

CPU,

passing

through the PC1

of the

81C55.

But,

when in the

OFF LINE

condition, the BUSY

signal is "L" and

transmission of

print

data to

the printer is

inhibited by the CPU.

2-13

YO

y

Y

2

>

—

--....

V3

5

^»-

Gale

Array

SLASOBGFQU

#

Figure 19.

Printer

Interface Circuit

Bar Code Reader Interface

Circuit

The input signal Irom the bar code

reader is subjected to

waveform shaping,

inverted

by the

Schmitt-type

inverter (M1),

and

then sent to the PC3 terminal of

the

81C55

and the

RST

5.5

terminal of the CPU.

When the

bar code

reader reads

the first white part of the bar code, a "L" level

signal

is generated,

then inverted by M1

.

As soon as RST 5.5 interruption

occurs, the CPU starts the data input operation,

passing

through

the PCS of the

81C55. As the bar code reader is moved

across the bars,

"H"

and

"L"

signals

(which

correspond

to

white

and

black bars respectively) are generated

continuously

and

Inversion signals are sent to the PC3 of the 81C55 as the

serial input data. Refer to Figure 20.

2-14

SLACK

LINE

\

WHITE

LI

LruV

ME

,

BLACK

LINE

^WNITE

LINE

-^ecw

I

BICS5-PC3}

RST9.5

[CPU)

Figure 20. Bar Code

Reader

Interface Circuit

Buzzer

Control Circuit

There are two ways to operate the buzzer. One is to sound the buzzer with the

specified frequency

by

emitting

a

signal

from

the

PB5 terminal of

the

8iC55

and the

other,

by

using

timer output

(TO) and

the BUZZER signal (P82)

of

the

81C55. In addition, the BELL signal also acts as the control signal

of

the DC/

DC converter circuit during the power-up sequence {refer to the Power Control

Circuit).

BELL

PB2

(BUZZER)

Figure 21.

Buzzer

Control Circuit

2-15

Signal

from the PB5

of the 81C55

When

the PB2 of the

81C55 is "H," the buzzer

sounds

by repeated

switching

of

the buzzer

driving

transistor. This

is

caused by "H", "L",

"H", "L" . . .

output

signals

from

the PB5 synchronizing

with the frequency for

sounding the

buzzer.

This

method

is

used for the BEEP command

in BASIC.

Using

the 81C55 Timer

Output

In this

method,

the buzzer is

made

to sound by setting

the

81C55 timer in

the

square

wave

output mode. To write

the value corresponding

to the sound

frequency,

the

CPU

assigns B4, B5,

BC or

8D to the I/O port

address.

This

frequency

is assigned by the first

parameter of the

SOUND command in

BASIC.

If the

above procedures

are

completed, the

TO terminal

of

81C55 outputs the

square

waves,

and the PB2

of

the

81C55 controls the

length

of the sound

whenever the

PBS

is "L" How long

the

sound is heard

depends

on the

second

parameter

of

SOUND

command in BASIC.

Clock

Control Circuit

A TIMER

IC (RP5C01)

on the memory

PCB is used in the

clock

control circuit

so that the

current time

and alarm time

can

be set and read by the

commands

in BASIC.

To

set and

read

the time,

the CPU assigns

90-9FH to the I/O port

address.

In

addition,

because the

back-up power VB

is supplied

to the TIMER

IC,

the

clock

and alarm functions

are

enabled even when

the Tandy

200

is

in the

power-off

condition.

Figure

22 shows the internal

block

diagram, and

Table

2 shows the

I/O

port

address

assignment

of each function. An

internal 26

x

4-bit RAM

is

used as a

buffer

memory when

the

data is transmitted

between RAM banks.

GSCIM-

OSCOUf*

=Oi

i/WU/W/'M/'V/M

gflKB

M

*]»

I

1

j

'I'

I

*

1/-

'9—

-9—

*—

16

if

U

,*a

i3e*i

*

t~

4 I

lit laf

ul

la

i i [

ALARM ffEU»TE*

i i r

CQUPA*ATO*

mtnwm

Q,WII.W»ElO

1 T T T f—»

lus

J

rrn

7>MEl

J-i

KTffrHAI

BUI

buffe*

ALAftU

OUTPUT

Figure

22. RP5C01

Internal Block Diagram

2-16

o O

10

a. CO

c

d>

E c

C>

0}

«

<

CO (0 (U

1-

a a

<

r

a

—

4J

5

' '

•»

-

S

f 1

o

a

2

Sx"

I

i J

o

lii

Q

o 2

o a

XX

5

TestO

Alarm

fie

set

5

XX

XXX

i

Testi

Timer

Reset

CM

XX

X xxxxx

UJ

g

<

z

a

XX X

XX

xxxxx

UJ

Be

E

1-

J

c

o

£1

a

2||£

•

|

£

,_

<s

»

s,

a

«

.£

u i;

er ,5

K

" *

n:

03=1

U

d=3

™

»

>,

«rS

«

£

a

o

» «

n

«0

»

c£c

>.

gj

c

es

O(-O £ O O

"

-

1

-

>-

g

E E E E E E ^ a

5

CD ffl t5

HJ

8 5

ruS

<<<<<<<

T-_J

o

LU

o o

s

o

TestO

Alarm

Reset

a

X

i

Testi

Timer

Reset

C\J

o

X XX

z

UJ

E

<

IN

O

V X

1-

ic

CO

a

X X XX

X X

Z

UJ

Si

E

i-

2§

o

a

t> en

a

One

sec.

Counter

Ten

sec.

Counter

One

min.

Counter

Ten

min.

Counter

One

hour

Counter

Ten

hours

Counter

Day

Counter

One

day

Counter

Ten

days

Counter

One

month

Counter

Ten

month

Counter

One

year

Counter

Ten

years

Counter

w

tc

m o

S

Test

Register

Reset

Controller

etc.

UJ

<

1

<

OT-wn^io<Dsa)a><flJL)|

1 UJ u- I

CD

c

A)

c

£

5

b

1

n

tS

Tfcbfe 2. RP5C01

I/O Port

Address Assignment

2-17

To set and read the time and alarm information, the CPU proceeds in the

following

sequence.

Write or Read the timer

X: Don't care

(

,

SrARr

J

ST DP THC Tlrifft AMD

SF

T

THE

MODf.

REGISTER TO

-fla

L

-A3

*2

A]-A&

!d3 02 onto!

ftOrfft

js_ 1 Q .1

Q

X

i\;:

1 o

ftfSFT THF TlUFfl

>_3_M

aJ

ArJ

01I02

dsIdo S

WRITE THE CUfiflEMT

TIME

anG OaT£

1*1

AZAI

AD

jo o jo &

\f

a.2

AL^AC

D3Jcjjpj|

VALUE' U-H

£ACH 3TEk

START THF TJfciFR

J jJ

|p

I- I

li in

I*

\*

I |]InI

PEAD

The TIME

ANO UA "E

AdAdAiJAfjl

j^D^Dljoa

a

Jq

[ [o

!

VALUE

OF

*

•

EACH

time

*

*3a^mUd

|

(

mo

j

Figure 23. Flowchart for the TIMER IC

2-18

Write

or

Read

the alarm time

X:

Don't

care

( START

J

DISABLE THP AL.AHL*

OUTPUT AMD SET

T^E

MODE

PEGJSTE.R-

TO 'Dl'.

ff^SFT TrtE ALApu

PEG1&TER

Id.3 L Hfj

u

WRITE THF

ALARM TTME.

Mti DA 1 E

A]

AH

D3jDg|pi[

Dq

£qj^

VALUE QF

EACH ITEk.

kJAJA] AtJ

ENABLE

T

HE

A^AfiM QljTRljT

]

l.'.klU C

f

FNn

J

READ THE

ALARW TJME ANQ DATE

fiojwfil

2[D2|Dt[DD

JALUE

DF

EACH TiriE

[ALjA^A i[Ag|

Figure 23.

Flowchart

for the TIMER

IC

(continued)

2-19

Serial Interface

Circuit

The serial interface circuit

supports

asynchronous serial transmission/reception.

The heart of this circuit is the

82C51A

(USART). It performs the job of

converting the

parallel

byte data

from the CPU to a serial data stream

including

start,

stop and

parity bits.

For

a

more detailed description

of how this IC performs these

functions,

refer

to

Appendix C of this manula.

Figure 24

shows

the functional block diagram of the

serial interface

circuit. In

this figure, the TO signal, basic

timing

clock

for the USART, defines the

transmission/reception baud rate.

To transmit and receive the

serial

data

from externa! devices, the RS232C

signal

selects either

MODEM

or

RS-232C interface. During the MODEM

operation, the ORGIS

signal switches either the originate

mode or answer mode

for the MODEM IC.

The serial interface circuit is subdivided into the

following

circuits:

•

RS-232C/MODEM Selection Circuit

•

RS-232C Interface Circuit

•

MODEM IC

•

Transmission

Filter Circuit

•

Reception

Filter circuit

•

MODEM Connector Circuit

•

Tone Signal Generator Circuit

2-20

I

5

3Z£2

"

SM

1

_ i

u

waaow

•f'V

-

D

£

a.

,1

i- a

e g

1 z

I

£

°

r?lj

i

2

i

'

S

3

pS-f

i

|

9.

I-J

V

7

°

2

IAW

SI

/\

-

r-i

*

i&,

£

a

o

z

i

f>

o Q D

.

4$^

^

1

U*^

L

I »-Vft-t-WMs

!r 1

Vh-t

L*i

_

g

"

w

\-^

o

""

1

y

O

"

|

3

i

I

5

8 1

-n

*

E IL

5

3

u

o

ini

5

s

^

— 1

3

«

°

£

a

„

o"

*

V

n

o

«

O

J 2

»|

J

r

iu

a

o

j

D S

o

u

<

Q.

^

o

^

a. 3d

Figure 24. Functional Block Diagram of the Serial Interface

2-21

RS-232C/MODEM

Selection Circuit

The

RS232C signal (PB3 terminal

of

the 81C55) determi nes whether the

serial

port is

to

be used as RS-232C or as MODEM. When th

e

RS232C

signal is "L,"

the serial

port

is

used as RS-232C. When the RS232C signal

is

"H,"

the

port is

used as MODEM.

The reception signal,

including

the control signal, is demultiplexed

at

M23.

The

transmission signal

is multiplexed

at M22.

During the RS-232C

mode, the

CD (Carrier Detect) signal is not

used. To make

this

condition, pin 14 of M23

is connected

to the ground.

During

the MODEM mode, the RTS signal

is

used as the self-loopback signal

and it

is

sent back to the CTS terminal. The DSR signal

is not

used in the

Tandy

200 USA

version,

since

the TD signal is always fixed

to

"H" level

by the

hardware. The

CD

signal

selects

the CDD signal from the RXCAR terminal

of

the

MODEM IC. Because the

CPU

detects the carrier signal by counting the

frequency

of the

CDD signal corresponding with the originate

mode or answer

mode.

When

a customer uses the tone dialer function, the DTR

signai

acts as

the enable signal for the

tone

dialer

IC.

2-22

x

H a

o

a a:I-o

-=

w n ^^

o

(M

n

12^J^?T'

RS232C

Figure 25, RS-232C/MODEM

Selection

Circuit

RS-232C

Interface Circuit

In the

RS-232C

transmission circuit, after the

DC component is removed

from

the signals

by

the

coupling

capacitors, the signals are leveled

to

± 5V

signals

by the inverters

connected

in

parallel, and then are output as

RS-232C

transmission

signals. In the

RS-232C reception circuit,

the DSRR, CTSR, and

RXR

signals from

the external RS-232C line

are subjected

to

waveform

shaping

and inverted

by

M33,

and then converted to + 5V or ground level

signals

by

the

diodes.

The signals

are then demultiplexed

at M23 and converted

to CTS,

DSR

and

RXD

signals which are input

to

the

82C51A.

The

CD signal is not used in

the

Tandy

200.

2-23

S/s*

^

k

*-

I

i I

L

A

MW

W

in

tt^S

-Kf-fe

"

—

Kf-

fc

(V

CO

o

Cl

CVJ

(VJ a

to

w

._.

(M

1

<

)

c

^

~

m

Q-O

£1

C»I

O

CO

fO

CM

—

N

5

2

s

£

s

Figure

26.

RS-232C Interface

Circuit

2-24

MODEM

tC

The Tandy

200 employs the IC MC14412 as a MODEM

control

device. This SC

modulates/demodulates

data to be transmitted/received in

accordance with

frequencies

suitable for

originate or

answer mode respectively.

The RXRATE and TYPE terminals

ol MC1441

2

(M8) are pulled

up

to VDD.

The baud

rate is

set to 300 bps, and the

U.S.

Standard

is selected.

Since the

ECHO and SELF TEST terminals

are

not needed, they are connected

to

ground.

The

PF36

terminal of the

81C55 outputs

the

enable signal (MEN) for the

MODEM

iC until the unit is in the

MODEM

mode.

In

addition, the signal designated

by

the

ORIG-ANS parameter in TELCOM

mode is

input to MODE input terminal,

and it switches

between the originate

mode

or

the answer mode. This signal is output from the

PB1

terminal of the

81C55.

R7I I5M

VDO

TO TRANSMISSION

FILTER

CIRCUIT

uuinr

FROM RECEPTION

FILTER

CIRCUIT

»-

i

RS-232C/MODEM

SELECTION

CIRCUIT

RESET

MS

(MC 14412)

Figure

27, MODEM IC and Peripheral Circuit

Transmission Filter Circuit

The DC component of the carrier

output

from the TXCAR terminal

is removed

by C50. The signal level is adjusted by the potentiometer VR1 . The signal then

passes

through the transmission band-pass filter and is sent to the telephone

line

or

the

acoustic

coupler.

The

transmission filter

circuit is composed ot an active filter (consisting of an

operation amplifier)

and

the

intermediate frequency of the active

filter

is 1200

Hz which covers both originate

mode and

the

answer mode.

2-25

/

A

v%

R4

620tl

DIR

0T1

—

Yft

Q

^

CN3

p«"-5

Rise

22n

- »—

-Vft

f

TXMC

ACP

C31

220jj

Figure

28.

Transmission

Filter

Circuit

Reception

Filter

Circuit

As

shown in Figure 29,

the reception

input

signal is

amplified when

passing

through coupling

capacitor

(C11),

and

amplified

again

as it passes

through the

3-stage band-pass

filter

(composed

of an

active

filter).

The signal then passes

through the

comparator, and

after being

changed

to a

square

wave, is input

at

the

RXCAR

terminal of MC14412.

Also, to

check a

carrier signal,

this

signal is

input to the

demultiplexer

M23 as

the CDD

signal

in the RS-232C

interface

circuit.

Intermediate

frequencies

of the

3-stage active

filter are

shown

below. The

switching of

intermediate

frequency

for the

originate and

answer

modes is

accomplished

by

switching

T1 , T2 and

T3 ON or

OFF

according to

ORIG-ANS

parameter in

TELCOM

mode, thus

changing the

input resistance

of

the filters.

On

the other hand,

three

comparators

consisting

of

M5 act as the

carrier break

down detector.

The output of

this

circuit is "H"

when a carrier

signal has not

been detected

for the time

specified by the C38

and R66.

2-26

2nd *tagi

1150 hi

RXMC

CN3 Pin-4

Figure 29. Reception Filter Circuit

MODEM

Connector

Interface Circuit

When

the acoustic

coupler is

used,

the transmission and reception signals

are

directly connected to the connector (TXMC, RXMC).

When

the

MODEM cable is

used, they are connected to the secondary side

of the driver transformer. The

primary side of this transformer is connected to the

telephone line via the

connector

(TXMD, RXMD).

The ACP-DIR switch is

used

in the MODEM mode,

relay RY2 separates the

telephone receiver audio inut signal (TL) to prevent

interference. RY3, another

relay,

separates the

modem circuit and the telephone at the conclusion of use

in the

MODEM mode and

is also

used as

an automatic

dialer

for the pulse type

telephone line.

2-27

D

li-

fe o

<J CD

O

Figure 30. MODEM

Connector Interface

Circuit

2-28

Tone Signal Generator

Circuit

The function of this circuit is to

send

tone-dial signals to the tone-type

telephone

tine when the Tandy

200 is

connected to that type of

telephone

line.

These functions described

above are

controlled by the SC TCM5089.

The

enable

(

TNE)

signal input

to

this IC is created by

NANDing the

DTR signal and

RS232C

signal. That is, when the DTR

signal becomes

"H" during MODEM

mode, this IC will be in the enable state.

Then the

CPU

writes the data to be dialed to

the I/O

port assigned by AOH

-

AFH.

*1

^

CM

3ZX-^"

r

i.

10 i<-

jfM

im

ftf |u~i

iui

f-

,>- |> i> ?>

\y-

\>

\>-

—

^>

.

r\im

h-

or

-

-r

m

O

±

S

*

^

Si

8 g

to n

*

o

L_)r\j

A-

O O

Q

Q O O O

^j

rn *

in id n ro

a?

<\

Figure 31

. Tone

Signal Generator Circuit

2-29

LCD

The LCD

used

in

the

Tandy

200

is

composed

of

electrodes

in a matrix

arrangement

(128

common

signals

and 480

segment

signals).

Because

this LCD

operates

on

a

1/64-duty

time

division

drive, the

upper

64

and

lower

64

common

signals

are

performed

by

the

same

timing.

This

part is

subdivided

into

following

four

sections:

•

LCD

Control

Circuit

•

LCD

Common

Driver

•

LCD

Segment

Driver

•

LCD

Waveform

For a more

detailed

description of

how the

LCD

operates

and its

basic

construction,

refer to

Appendix C

of

this

manual.

LCD

Control

Circuit

The LCD

Control

Circuit

of the

Tandy

200

consists

of the

LCDC

(HD61830B)

and 8K-byte

RAM.

The LCDC

generates

driving

signals

for LCD by

receiving

the

instructions

and

data

from

the CPU.

The driving

signals for

LCD

are

divided into two

groups:

one is

the timing

signal for the

segment

driver and

common

driver, another

is

the

data to

display.

The CLKL

signal,

divided

2.4576 MHz

clock

signal

by

two at M34,

is

supplied

to

the

RC

terminal of

the LCDC.

One bit value

of

the 8K-byte

RAM

connected to

LCDC

corresponds

to

one

dot

of

illumination or

non-illumination on

the

LCD

screen.

These

data are

converted

into the

serial

data D1

and D2 at

the

LCDC,

and

then

sent

to the

segment

driver.

Figure

32 shows the

interna!

block

diagram

of

HD61830B.

2-30

a

Illi

2

3

a

/ A

A

a

'

oc

a:

UJ

o _

hi-

3

<

ARAC

NERA

ROM

CORO

CK

X

PdS

?dF

1

o a

a.

<*5

<^

h-

o=5z

«;z

*3x3idI

± "inn

.

~

Z>

3

wo.

u

uia.

a

_

*o

— 1

CO

,j

ilLs

a

—

u

>

<n

<

:

l

-

a

A

o

a:

<

Q,

iS

ij

o

£

s>-

o

h-

01

o

^ !M

3

ft

o

ft

o

=) O

S

u

!

u

u o

J

CD

-

L

,

a:

*

r-

Z

£

u,

^

o

g

s

1

O

°

UJ

3

Q

O

CD

(_)

o

*

-1

r-

t

o

0:1

1

Z

o

(J

CK

a.

m at

2jS

a

o

a:

Z

r

,.

/I

~*

~

<J

>

C3

'L

1

-

id 2

33V3M31NI

0/1

f t

Figure 32.

Internal Block Diagram

of HD61830B

2-31

The

Common Driver (HD61103)

The

Tandy 200 uses two common driver

ICs:

M507

and

M508, M507 controls

the upper

half of the

LCD screen and M508 controls the lower half

of

the

LCD

screen.

The FRM

signal defines the periodic

frequency of one-screen

display, and

determines

80 Hz for the Tandy 200.

The MB

signal is used for changing the driver signal

to

AC,

because the

continuous

application

of DC to the LCD would shorten the

LCD element life.

The CL1

signal

is used for the shift clock of the internal shift

register.

Figures

33 and 34 show the internal

block diagram of

HD61 103 and output

waveform

of HD61103.

2-32

Figure 33.

Internal

Block Diagram of HD61103

2-33

Figure

34. Output

Waveform of HD61103

2-34

Segment

Driver (HD61100)

The Tandy 200

uses

six segment driver ICs (HD61

100),

and each IC has

80

output drivers.

HD61100 is

a

driver IC for the LCD display. It receives and latches the serial

display

data from the LCDC, and generates the segment driver signals.

The

CL1

,

CL2, D1

,

D2 and MB signals are supplied from the LCDC. The CL1

signal

is

used

for the latch clock of the internal 80 latches. Synchronizing with

the fall

of CL1 , the segment driver signals corresponding to the display

data

are

output.

The

CL2 signal is used for the shift clock of the display data. The MB signal

changes output signals to AC.

The D1 signal is the

data to

display

on

the upper half of

the LCD

screen

and

the D2

signal is the data to display on the lower half of the LCD screen.

Figures

35 and 36 show the internal block diagram

of

HD61 100 and output

waveform

of

HD61100.

VILV2LV3LV*.

Y1Y2-

—

Yen VmVwVwVm

M(MB>-

DL(D1)« DRID2)-

SHL

CL2

12

3 4 5 6 7 8

LCD

DRIVER

77 78 79

80

LATCH CIRCUIT

2

80SITS

S/P

t r i""

1

i

2

i

3

I

4

3

:=tZ.

T 1 T

5i6i7ie

r?E

LATCH

CIRCUIT

1

4BITS X

20

^T

SELECTOR 20

-?>

—

INPUT

FOR TEST

!

H^Df

-tr

U

1

COUNTER

S

CONTROL CIRCUIT

-VCC

-GND

-VEE

Figure 35. Internal Block Diagram of HD61100

2-35

n

«

Figure

36.

Output Waveform

of HD61100

2-36

LCD

Waveform

In

order

to drive

the liquid-crystal

elements

by the 1/64

duty tine-sequential

drive

method,

the LCD

of

the Tandy

200

makes

sequential selection

of the 64

scanning

electrodes.

For

each

dot, the display

signal

passes

through the

signal

electrodes

and is

applied 64

times

for one

display.

At

this

point,

the signal

is necessary

at each dot only

one time, and

the signal

for the

other

63

times

corresponds

to other

dots on the

same signal

electrode.

The

maximum

voltage

applied

to the

common

electrode

and segment

electrode

is the

potential

difference

between

V1 and V2.

In

addition,

"a"

is

the bias

coefficient which

determines from

the

standpoint

of

contrast,

the maximum

ratio

between

the illumination

voltage

and

the non-

illumination

voltage.

When

that

ratio is

greatest

in relation

to the effective

ON and OFF

voltages

"a"

=

9.0.

Thus,

for V1,

V2, V3, V4,

V5 and V6:

V1=VDD(

+ 5V}

V2

=

V0(approximateiy

-7Vto -10V)

V3

=

VDD

-2V/a

V4

=

VDD

-(1-2/a}V

V5

=

VDD

-(1-1/a)V

V6

=

VDD

-V/a

Note:

Absolute

value

of

"V" equal

absolute value

of "VDD"

plus

absolute

value

of "V0".

Figure

37 shows the driving

waveform

for illumination

and

non-illumination.

2-37

VI

V2

1J

VE

V5

COMMON

LINE

V3

V^

V]

NON-ILLUMINATION

SEGMENT

LINE

ILLUMINATION

SEGMENT

LINE

Figure 37. Driving Waveform of LCD

2-39

Power

Supply

and

Auto-Power

ON/OFF Circuit

The

power supply

circuit develops

the

following voltages:

•

VDD(

+

5voltsDC)

•

VEE (-5 volts DC)

•

VLCD(-IOvoitsDC)

•

VB

•

VIN

•

VD

•

Vfl

• VNICD

VDD is supplied to

ali

of

the ICs except the

main

memory, TIMER (RP5C01),

M24, M25 and

M26.

VEE is used as a

negative power source

for the

operational amplifiers.

VLCD is

supplied

to

the

LCD PCB through

T27 for the LCD driving voltage.

VB is supplied to the main

memory, TIMER, M24, M25

and

M26.

VR is

used

for the input voltage to

the DC/DC

converter

circuit. When the

internal circuit is modified

for

use

of

Nickel-Cadmium

batteries,

VIN is supplied

to the four

Nickel-Cadmium

batteries

installed

into the battery

compartment.

This power source

charges the

Nickel-Cadmium

batteries

whenever an AC

adapter is connected

to

the Tandy 200.

Power Distribution

Figure 38 shows the

power

distribution of the Tandy

200.

In this circuit, R165 is

used as the current

limiter during the charge. D1 1

protects the power

supply

from the

reverse

current. The power

control circui

t controls the DC/DC

converter circuit corresponding with the

POWER, ALM, PCS

and

BELL signals.

2-39

Figure

38. Power

Distribution

2-40

DC/DC

Converter

CT2 is

a

converter transformer which oscillates T20 and T21 and generates

voltages at the secondary side of the

transformer.

At the

same

time the

power

is switched ON, a very slight

collector current

flows

to

T20 and T21

.

Also,

voltage between

3

and

6

of

the converter transformer is generated, and

the T21

base

potential becomes positive. In other words, the base polarity

becomes biased in the forward direction. This voltage causes

the

T20

and

T21

base

current

to

flow, and the coilector

current

is

increased. When the current

can no

longer

increase,

because

of

transistor saturation and converter coil

resistance, the voltage between pins 3 and 6 begins to attenuate, causing T20

and

T21

to be cut off

all

at once because

of

the reverse playback action. Until

immediately

before the

transistor is cut

off, excitation current flows to the

transformer.

Because

the current is suddenly dropped as a result of the

transistor cut-off, a counter voltage is generated, the distributed capacity of the

coil is changed, and, as a result, an

oscillation voltage is generated at

the

base

coil. Then, when the

base

potential

progresses to

a half cycle of the oscillation

voltage, it is biased

in the forward direction, T20 and T21 are switched ON once

again. In this

way,

AC voltage corresponding to the number of windings is

generated at the secondary side of the converter,

and this voltage is

rectified

and smoothed by D13, D14, D15, C62, C63 and C64.

Low Power Detection Circuit

The low-power detection circuit illuminates an LED warning lamp when the

battery

voltage decreases. If it continues

decreasing,

the

system power

will

be

switched

OFF just

before the voltage becomes

so

low that the converter cannot

operate.

There

are about 20

minutes

between

the time when the LED lamp illuminates

and the

system

is switched OFF.

Battery

voltage is detected

by

splitting the resistance of R91

,

R92, R94 and

R95. When battery voltage (VR) becomes 4.2V ±0.1V, T18 is switched OFF.

T19 is switched ON, T23 is driven, and the LED

illuminates.

(The LED

is

located

on the keyboard PCB.}

In addition, the value of the

detected

voltage is changed by

R93 because of a

difference between the output

voltage of

Alkaline-manganese

and Nickei-

Cadmlum batteries.

The R1 and R2

signals are

shorted on the

memory

PCB when the internal

circuit is

modified

for use of

Nickel-Cadmium

batteries.

2-41

Figure

39. DC/DC

Converter and Low

Power Detection

Circuit

2-42

Power Control Circuit

This

circuit controls

the oscillation of the DC/DC

converter

circuit

by

using

T25.

There are tour methods to

control the power

ON/OFF. In this circuit, the VDD

terminals of M24, M25

and

M26

are

connected to VB, since these ICs must

operate in

power-off condition.

1. Power-up using the

POWER switch

If a customer presses

the

POWER switch on the keyboard during

power-off

condition,

the

following events

occur:

a.

A

positive

short pulse is

sent to the base of T32 through C70,

then

T32

is

switched on.

b.

On

the

other hand,

the Belt and RESET signals are "L"

during power-off

condition, but the input pin 8 of the gate

M24

is

pulled up to VB, Thus the

output pin 10 of the gate M24

becomes

"L," which enables the gate M25.

c. T31 is switched on. This "H"

Sevel signal

is

supplied to the RESET terminal

of the flip-flop M26 and then

the

flip-flop M26

is

reset.

d. The output pin 13 of the

flip-flop

M26

becomes

"L" and T25 is switched

off.

e. The DC/DC converter circuit

starts the

oscillation, if the proper DC level of

VR is supplied to

this circuit.

f. VDD reaches the specified DC leve),

T16

is

switched off. At the same time,

the

LPS

signal becomes

"H" and

is

sent to the TRAP terminal of the CPU

after inverted

at

M35.

g.

When

VDD

reaches

a

constant

DC level t o operate the

CPU,

T28

is

switched on and

T29 is switched off. The

RESET

signal

becomes

"H," then

the

CPU

begins the "Warm-Start" process.

After

completion of the "Warm-

Start," the CPU drops the BELL

signal.

h. The output pin 10 of the gate M24 becomes

"H"

and

the output pin 10 of

the gate M25

becomes

"L,"

then

the

Tandy

200 will be able to operate.

2. Power-down using the

POWER

switch

If a customer presses the POWER

switch on

the keyboard during power-on

condition, the following

events occur:

a. A positive short pulse is

sent

to

the base

of the T32 through C70,

and then

T32 is switched on.

b. On the other

hand, the cross-couple

consisting of the gate

M24

was set

by

the BELL signal in the

last power-on

sequence. Thus the

output

pin 11

of

the gate M25

becomes

"H."

c.

The

flip-flop

M26

is clocked

by this "H" level

signal. The output pin

2

of flip-

flop M26 becomes "L."

d.

The

LPS

signal

goes

"L" and is sent to the

TRAP terminal of the CPU after

being inverted at M35.

e.

This signal notifies the CPU when the

customer

presses the POWER

switch. The CPU starts the

internal

power-down process.

After

completion

of this process, the

CPU sends

the PCS signal

passing through

the PB of

the81C55.

2-43

f.

Receiving the

PCS signal,

the output pin 4 of the gate M24

becomes

"L,

:

g.

The flip-flop M26

is set. The output pin 13 of M26

becomes

"H"

and T25 is

switched on.

h.

This causes the

DC/DC converter

to stop the oscillation. Then the

Tandy

200

will not be able to operate.

3.

Power-up

using the ALM signal

The ALM

signal

becomes "L" when the time matches the value set by the

POWER

command

in BASIC. The

ALM

signal is gene rated by the TIMER IC on

the

memory PCB. T31 is switched on

by

the "L" level ALM signal.

The remaining

sequence

follows

the power-up using the

POWER switch.

4. Power-down

using

the

PCS signal

To control

the power

supply, the CPU sends the PCS signal if the automatic

Power-Off

limit reaches the

value corresponding

with

the

1st parameter of the

POWER

command in BASIC.

The

remaining sequence follows the Power-Down

using the POWER

switch.

Reset

Circuit

This circuit

supplies

the

CPU RESET

signal and also the RAMRST signal as

the RAM protecting signal when

the power decreases,

R113 and C66 delay the

introduction

of input power so that T28

is

swit

ched on and

T29

is

switched off

after VDD

is activated, with

the result that the RESET signal changed from "L"

to "H." In

the

same

way,

the RAMRST signal is generated by T30 and

changes

from

"H" to "L." Thermistor TH3

suppresses the

RESET signal fluctuations due

to

temperature. T27 receives the signal during

automatic powe

r

OFF, short-

circuiting

both end of C66, and resets the system. The RESET signal

is active

"L" and the

RAMRST signal

is active "H."

2-44

Figure 40. Power Control and Reset Circuit

2-45

/-CA\..

J-

i=

i

l<

a.

>

°

(s

n

M

x

/

X

ET

LU

CM

E

10

CM

to

(VJ

(L

«*-

^_

t. V-

^

o

O

o

-

o

C\J

|W

CM

1-i

>

Figure

41.

Power-Up/Down

Sequence

2-46

APPENDIX

A/INSTALLATIONS

Installation of Optional

RAMs and ROM

•

Using the coin, remove the optional

RAM and ROM cover on the bottom

case.

•

Insert

the optional

RAMs into the IC sockets

marked M306 and M307. In this

case, the IC socket

M307 is

used

for the RAM #1

and M306 is RAM #2.

•

Insert

the

optional ROM into the IC socket

marked M308.

Installation of Nickel-Cadmium

Batteries

•

Remove the memory PCB (Refer to

Section II, Disassembly Instruction).

•

Install the

modification jumpers into the through

holes marked

J301

and

J302.

•

Re-assemble the

unit.

IC

Socket for

Optional

RAM

#2

_•

*is

stsN

i $

«wt «

*

fw

s

m

2

**

* «w*

«

*

«SN

s

-**

I

C3CM

4)

1* &

•7

.

777777/"

OPTION

Rv

j

*7

•

S ! f !

;

*

]

*

• «

*

-

•

r

i

«

o^rsc^ Rv

1M

1

M302

_

*"*V.ii-,

\

IC

Socket

for

Optional

RAM

#1

IC Socket for

Optional ROM

Figure A-1. Memory PCB

A-1

•

Remove the battery

cover and instaif

the four Nickel-Cadmium

batteries

into

the

battery compartment.

•

Drill the

screw

hole on the battery cover using the tapping

screw

® and

secure the

battery cover

and bottom case.

•

Stick the red iabel

®

on the

battery cover.

Figure A-2.

Installation of Nickei-Cadmium

Batteries

A-2

APPENDIX

B/KEYBOARD

LAYOUT,

CONNECTOR

ASSIGNMENTS

AND

CHARACTER

CODE

TABLE

Keyboard

Layout

f

r~

"I

}

I

a

-™

]

A

HZ

°

D*r

°

C-

T

1"*"

j

1

r

ESC

12 3 4

%

At

*

(

J

}

5

s

tg

U

91

1 1

+

DEL

8KSP

|

TAB

W E

R

T

Y U

n

l

B B

P

[

ENTE

ER

CTRL

A

s

D

G H J„

K

H

L

B

:

"

CAPS

LOCK

SHIFT

Z

X C

v e n

m

f

J

SHIFT

GRPH

CODE

NtJM

*-

-J

Figure B-1 . Keyboard Layout

B-1

Connector

Assignments

System

Bus

Interface

Pin No.

Symbol

Description

1

2 3 4 5

6 7 8 9

10

11

12 13

14 15 16

17 18 19

20

21

22 23 24 25 26 27 28 29 30

31

32

33 34 35 36 37

3fl

39 40

VDD

TOD

GND

DO

D1

D2

D3 D4

D5

D6 D7 A8 A9

A10

A11

A12

A13 A14 A15

GND

RD

WR_

10/

50

ALE

SI

CLK

iOCONT

E

RESET

1NTR INTA

GND GND

RAMRST

NC NC NC

Address Address

Address Address Address Address

Address Address Address

Address Address Address Address

Address Address Address

and data and data and

date

and

dala

and data and data and data

and data

signal

bit

signal bit signal

bit

signal bit

signal

bit

signal

bit

signal

bit

signal

bit

signal

bitO

signal

bit 1

signal bit

2

signal

bit 3

signal bit 4

signal

bit 5

signal bit 6

signal

bit 7

8 9

10

11

12 13 14

15

Read

enable signal

Write

enable

signal

I/O

or memory select signal

Status signal

Address

latch enable signal

Status 1 signal

CLock

signal

I/O controller

select

signal

I/O

or memory access

enable

signal

Reset signal

Interrupt

request signal

Interrupt acknowledge

signal

RAM

enable

signal

Table

B-1. System

Bus

Connector Pin Assignments

B-2

c=

1

2

4 6 8

10 12 14 16 18

20 22 24

26 28 30 32 34

36 38 40

1

3 5 7 9

11 13 15 17 19 21

23 25 27

29

31

33

35

37

39

Figure

8-2.

System

Bus Connector

RS-232C

Interface

No.

Symbol

Description

1

GND

2

TXR

Transmit

Data

3

RXR

Receive Data

4

RTS

Request

to send

5

CTS

Clear to send

6

OSR Data

set

ready

7

GND

8

CD Carrier

detect

9

NC

10

NC

11

NC

ia

NC

13

NC

14

NC

15

NC

16

NC

17

NC

18

NC

19

NC

20

DTR

Data terminal

ready

21

NC

22

NC

23

NC

24

NC

25

NC

Table B-2.

RS-232C

Connector Pin

Assignments

B-3

13

12 11 10 9

8 7 6 5 4

3

2

1

25

24 23

22

21

20 19

18

17 16 15

14

Figure

B-3. RS-232C Connector

Printer Interface

No. Symbol

Description

1

STROBE

STFOBE

Pulse

2 GND 3 PDO Bit

of

Print

Data

4

GND

5 PD1 Bit 1

of

Print

Data

6 GND 7 PD2 Bit 2 of Print Data a GND 9 PD3 Bit 3 of Print Data

10

GND

11

PD4 Bit 4 of Print Data

12

GND

13

PD5 Bit 5

of Print

Data

14 GND 15

PD6 Bit 6

of Print

Data

16

GND

17

PD7 Sit 7 of Print

Data

18

GND

19

NC

20 GND

21

BUSY Busy

signa!

for Computer

22

GND

23 NC 24

GND

25 BUSY Select signal 26

NC

Table

B-3.

Printer Connector Pin Assignments

B-4

HHHEHHHEHHHHS

25

23

21 19 17

15 13

11

9

7 5 3 1

26

24

22 20

18

16 14

12

10

8

6 4 2

HHBHHHHHHEBHH

Figure

B-4. Printer

Connector

Cassette

Interface

Figure B-5.

Cassette Connector

MODEM

Interface

Figure B-6.

MODEM

Connector

B-5

Bar

Code

Reader Interface

Ptn No. Symbol

Description

1 NC

2 R x DB Receive data from bar code

reader

3 NC 4 NC 5 NC 6 NC 7 GND 8

NC

9 VDD

1

2 3 4 S

O G O O

O

6 7

8 9

Figure B-7. Bar Code Reader Connector

B-6

Character

Code

Table

Decimal Ha*

«»v

gKS

Keyboard

Character

00 00 oooooooo

S

*'

1 01 00000001

[««.|

a

2 M 0O0O0010

jciptj

B

3 03 00OO0011

|gm

j

C

4 04 D0000100

ED

D

5 OS O0O0O1O1

fcTTtL

j

£

6

06 0000011 fcTBk

F

7

07 oocoom

[cwil|

G

e 08 OOO010OO

[tim|

H

9 09 00001001

Q

10 OA OOO01D1O [cm.| J

11

OB

00001011

B

K

12

oc OOO0110C L

13

00

00O011O1

B

M

14 OE 00001110

[™J

N

15

OF 90001111

E3

°

16 10 OOO

1

oooo

B

p

17 11 OO01DO01

[™J

IB 12 0001 0010

jCTBt

R

19 13 OOO 10011

(™|

S

20 14 0O01010O

[c™.|

T

21 15

00010101

[c™]

U

22

IB

0O01O110

['""-]

V

23 17 00010111

[™]

W

24 IS 00011000

B

*

Decimal

Hn

Binary

Dilplayid

CiiBricter

Keyboard

Character

26 19 00011001

[™[

Y

26 tA 00011010 pjT|

z

27 te

00011011

28 1C 00011100

29 ID 00011101

B

30 IE 00011110

t

31 IF 00011111

t

20 0010000032 [p»*CI*i»

33

21 00100001

!

1

34

22

001 OOO 10

II

35 23 001 OOO 11

ft

*

36 24 00100100

*

$

37

26 O01O0101

•s.

%

38 26

00100110

&

39 27 00100111

f

40 2B 00101000

<

(

41

20 00101 001

>

J

42

2A 00101010

*

"

43

2B 00101011

+

•

44

2C 00101100

I

45

2D 00101101

- -

46

26

00101110

m

47 2F

00101111

/

48

30 001 1 0000

49 31 001 10001

1

B-7

Decimal Han Binary

Splayed

Character

Keyboard

Character

SO 32

oonooio

2

51 33 001 1001

3

52 34

oonoioo

4

53 35

00110101

5

6

54 36 0OMO110

6

55 37

00110111

?

7

56 38 1X1111000

8

57 39 00111001

9

58 3A 00111010

53 3B

00111011

J

60 3C

001

11

100

<

61

30

00111101 =

=

62

3£

00111110

>

63 3F

00111111

?

1

64 40 01 oooooo

3

@

65 41 010O0O01

A

66 42 01 00001

B

67 43 01 00001

c

C

68

44 01000100

D

69 45

010O01O1

E

70 46

010O011O

F

71

47

010001

11

G

n

48

01001000

H

73 49

01001001

I

4A

01001010

Decimal

Max

Binary

Display

Character

Keyboard

Character

75 4B 01001011

K

76 4C 010O110O

L

77 40 O1OO1101

M

78 4F. 01001110

N

79 4F 01001111

60 50 0101DO00

P

81 51 01010001

Q

O

82 52 01010010

R

S3 53 01010011

S

84 54 01010100

T

85 55 01010101

U

tl

86 56 01010110

y

V

87 57

01010111

u

VI

88 SB

01011000

X

89 59 01011001

V

90 5A

01011010

z

91 58

01011011

c

[

92 5C 01011100

\

s

-

93 50 01011101

]

1

94 5E 01011110

A

95 5F

01011111

<*» _

96 60 01100000

\

B

E

97 61 01100001

a

98 62 01100010

b

99

63 01100011

c

B-8

Dactmal Hen

Binary

Diapiayad

Chiracter

Keyboard

Character

100

64

01100100

d

101 m

01100101

e

102

66

01100110

f

103 67

01100111

3

a

104

58

01101000

h

105

69

D1101001

i

106

6A

01101010

J

i

107 6B

01101011

k

108 6C

01101100

1

109 6D

01101101

m

110 6E 01101110

n

111 6F 01101111

D

111 70

01 1 10000

p

P

113 71

01110001

q

114 72 omooto

r

i

115 73

01110011

s

116 74

01110100

t

117 75

01110101

u u

118

76

01110110

y

V

119 77 01110111

w

120 7B

01111000

X

121 79 01111001

y

122 7A O111101O

z

£

123

7B

01111011

<.

s

•

124

7C

01111100

1 1 -

Decimal

Hai Binary

Diiplayed Cheractar

Keyboard

Character

12b

70 01111101

> °

126

7E 01111110

*V

i

127 7F

01111111

S

128

80

100O0O0O

8 p

129 81

10O0O001

a

-

130 62

10O0O01O

* *

131 83

1O0O0O1

1? "

132 84

1OOOO10O

*

Q

«

133

85

100001

01

*

ft

a

134 86 10ODO11O

Q

h

136 67 10000111

a

1

136 38 10001000

Tt

B

1

137

89

10001001

r

'

133

8A 100O1O10

*

B

'

139 BB 10001011

1

-

140 BC 10001100

141 BD 10O01101 +

142 B£

10001110

J

s

143 BF 10001111

4

•

144

90

1001

0000

ft

v

145 91

10010001

a

«

146

92

10010010

*

:

147

93

10010011

&

a

148

94

1O01O1DO

*

w

149 95 10010101

J

>

B-9

Decimal Han Biliary

Displayed

Character

Keyboard

Character

150

96 10010110

t

n

151

97 10010111

%

B

151

38 10011000

t

1S3

99 10011001

+

154

9A 10011010

+

1

155

9B 1001101

*

B

k

156

9C 10011100

G

2

157

90 10011101

«

B

3

158 9E 10011110

<?

B B

4

159

9F 1001111!

<?

5

160

A0 101000O0

*

161 Al

1

01

0O0O1

&

S

Z

162

A2 1010OO1O

c

s

f

163

A3 10100011

t

8

154

A4 toiooioo

\

165

166

167

AS

101 001

01

A6

101001

tO

A.7

10100111

A3

1O1O10O0

10101001

10101010

1

B

«

171 AB

10101011

13

y

17?

AC 10101

100

K

p

173

AO 1010110!

K

174

AE

10101110

%

/

Decimal

Hen

Binary

Ditplayad Character

KeybodrtJ

Character

175

AF

1 01 01 1 1

n

"

176

BO

10110000

¥

'

177

B1 10110001

&

Q

178 B2

10110010

B

°

179 83 10110011

u

180

B4

10110100

*

e

181

B5 10110101 >Y

>

182

B6 10110110

a 1

183 B7

10110111

6

-

184

B8

B9

1 01

1 1 ooo

u

fatij

U

185

10111001

S

«

186

BA 101

11010

T m

T

187

ae

10111011

e

«

138 BC

10111100

Ci

™

IBS

190

10111101

10111110

BF

CO

10111111

C6

11000! 10

B

«

193

CI

C2

I10O0OO1

£

3

194

11000010

1

B

195

C3

11000011

a

B

9

196

C4

C5

110O010O

7

197

11OO010!

-

0_

B-10

219

220

Decimal Hei

Binary

Displayed Character

Keyboard

Character

200 C8

11001OOO

£

B

a

201

C9

11O010O1

£

B

k

202

CA

t 1 001

01

*

©

B

1

203 CB

11001011

B

i

204 CC

11001100

i

B

i

205 CD

11001101

w

B

fi

206 CE

11001

110

3

B

V

207 CF

11001111

S b

20B

DO

11010OO0

ft

B

X

209

D1 1 1

01 0001

*

B

X

210 02

11010010

A

B

W

311 03

11010011

a

B

w

212 D4

11010100

B

>

213 05

11010101

a

B

214

06

11010110

H

B

N

214

D7

11010111

tt

B

D

216

08

11O110O0

A

217

09

11011001

1

B

K

21B

DA

11011010

6

B

L

DB

DC

B

221 DD

11011101

s

M

222 D£

11011110

fe

B

c

223 DF

11011111

&

B

z

224 Ef)

t 1 1 00000

B

z

Decimal

rtax Binary

Displayed

Character

Kayboard

Character

226 El 111OO001

I

B

'

220

E2 1 1 1 0001

B

<-

227

E3 11100011

I

B

*

235

237

E4

£5

EB

IllOtOOO

E9

11101001

EA 11101010

EB

EC

ED

11101101

1

B

230 EG

11100110

/

B

231 E7

11100111

"

B

e

I

B

-

s

B

D

23B EE

11101110

J

B

F

239 EF

11

1

01 1 1

I

X

240 FO

11110000

r

u

241

FI

1U10O01

-

B

p

242 F2

11110010

1

B

243

F3

111

1O011

T

1

244 F4

11110100

h

B

j

245

F5

F6

11110101

!

B

246

11110110

L. M

247

F7 1 1 1 1 01 1

J

>

248

F8 11111000 J.

<

249

F9

1111 1001

\

L

B-11

Binary

Jtplav*d

K*ytoirri

Character Chwactw

250 FA 11 11010

+

B

K

251 FB 1 1 1 1

or

i

r

H

252 FC ntnoo

A

T

253

FD 1111101

^

a

254 FF. 1111110

k

¥

255 FF

mini

m

c

B-12

APPENDIX C/TECHNICAL

INFORMATION

80C85A

General Description

The

80C85A is a complete 8-bit parallel central processor implemented

in

silicon

gate C-MOS

technology

and

compatible with

8085A,

It

is designed

with

same processing

speed

and

lower

power consumption

compared with 8085A,

thereby

offering

a

high level

of system integration.

The

80C85A uses a

multiplexed address/data

bus.

The

address is split betweer

the 8-bit

address

bus and the 8-bit

data bus.

C-1

:

o

lTi

e2: fit

d

LiZ-

a!

;.-

a:

z:

"^

C3

o=

^=-

-^>:

—

v

!4'k

Figure C-1. Functional Block Diagram

C-2

x,rr

W

5)

Vcc

x,(T

35)

HOLD

FT

OUTfT

38)

HLOA

soorr

80C85A

37]CLK(OUT)

SIDfT

36) RESET IN

trap rr 35)

READY

RSI

©

(T,

33)

IO/M

RST

65

|T

as,

RST

b.5

E

JJ]RD

SJ1R

[TO

5T)

WS

rNTArrr

Dai

f

ADoE

75)50

AD.E

m

Aib

AD-iOI

23

Ah

AOj(T| ]S)Ai3

AD<(76

§Ao

ADlQZ

SI

Am

AD

6

(S

S)Aio

AD,

(T|

23A9

GNDfjO

U]A8

Figure

C-2.

Configuration

of

80C85A

Functional

Description

As

-

A15

(Output,

3-state)

Address

Bus: The

most

significant

8 bits of

the memory

address

or the

8

bits

of

the I/O

address,

3-stated during

Hold

and Halt modes

and

during

RESET.

ADo

-

AD?

(Input/Output,

3-state)

Multiplexed

Address/Data

Bus:

Lower

8 bits of the

memory

address

(or I/O

address)

appear

on the

bus during

the first clock

cycle

(T state)

of

a machine

cycle.

It

then

becomes the

data

bus during the

second

and third

clock

cycles.

ALE

(Output)

Address

Latch

Enable: It

occurs

during the

first clock

state of

a machine

cycle

and

enables

the address

to

get latched into

the on-chip

latch

of

peripherals.

The

falling

edge of ALE is

set

to guarantee

setup and

hold

times for

the

address

information.

The

falling

edge

of

ALE

can also

be used

to strobe

the

status

information.

ALE is

never

3-stated.

So,

Si

and IO/M

Machine

cycle

status:

IO/M

Si

So

States

1

1 Memory

write

Memory read

1 I/O write

I/O read

1

Opcode fetch

IO/M

So

States

1 1 Interrupt

Acknowledge

Halt

.

=

3-state

x x

Hold (high

impedance)

x

x Reset

x

=

unspecified

Si

can

be used

as an

advanced

R/W

status. IO/M,

So and Si

become

valid

at

the

beginning

of

a machine

cycle

and remain

stable

throughout

the cycle.

The

falling

edge of ALE

may

be used

to latch the

state of

these lines.

C-3

RD (Output, 3-state)

_

READ control: A low level on RD indicates the selected

memory

or

I

dev

ce j

to be

read and

that the

Data Bus is

available for the data transfer 3-statec

during

Hold and

Halt

modes

and during RESET.

WR {Output,

3-state)

WRITE control: A low level

on

WR indicates the data on the Data Bus is to be

written into the selected memory or I/O location. Data is set up at the

trailing

edge

of

WR, 3-stated

during

Hold

and Halt modes and

during RESET.

READY

(Input)

If READY

is

high during

a

read or

write

cycle,

it

indicates

that the memory

or

peripheral

is ready to send or receive

data.

If READY

is

low, the

CPU

will wait

an integral number of clock cycles for READY to go high before completing the

read or write

cycle, READY must conform to specified setup

and

hold times,

HOLD (Input)

HOLD

indicates

that another

master

is requesting the use

of

the address and

data

buses.

The

CPU, upon

receiving

the hold request,

will relinquish

the

use

of

the bus as soon as the completion of the current bus transfer. Internal

processing

can continue. The processor can regain the bus only after the HOLD

is removed.

When the HOLD is acknowledged, the Address, Data, RD, WR,

and IO/M lines

are 3-stated.

HLDA

(Output)

HOLD ACKNOWLEDGE:

Indicates that the CPU has received the HOLD

request

and that it will relinquish the bus in the next dock cycle, HLDA

goes

low

after

the Hold request is removed. The CPU takes the bus one half clock

cycle

after HLDA

goes

low.

INTR

(Input)

INTERRUPT REQUEST:

Is

used as a

general purpose interrupt, tt is sampled

only during the next to the last clock

cycle of

an instruction

and

during

Hold and

Halt states. If it is active, t he Program Counter (PC) wilt be inhibited from

incrementing

and

an INTA will be

issued.

During this cycle a RESTART or CALL

instruction

can

be

inserted

to

jump

to

the interrupt service routine.

The INTR is

enabled

and disabled by software. It is disabled by Reset and immediately after

an interrupt

is accepted.

INTA (Output)

INTERRUPT

ACKNOWLEDGE:

Is used

instead of

(and has the same timing as)

RD during the instruction

cycle after an

INTR

is accepted.

RST

5.5,

RST

6.5,

RST

7.5

(input)

RESTART INTERRUPTS:

These

three inputs

have

the

same

timing

as

INTR

except

they cause an internal RESTART to be automatically inserted.

The

priority of these interrupts is ordered as shown in Table C-1 . These

interrupts

have a higher priority than INTR. In addition, they may be individually

masked out

using

the SIM

instruction.

TRAP

(Input)

Trap interrupt

is

a

nonmaskable

RESTART interrupt, (t

is recognized

at

the

same timing as INTR or RST

5.5

-

7.5. It

is

unaffected by

any mask or

Interrupt

Disable.

It has the highest priority of any interrupt. (See Table C-1

.)

C-4

RESET IN (Input)

Sets the Program Counter to zero and resets the Interrupt Enable and

HLDA

flip-flops. The

data

and address

buses

and

the control lines

are 3-staied

dci-c

RESET

and

because

of

the

asynchronous nature of

RESET, the processors

internal

reg

isters and flags may be altered by RESET with unpredictable

result

RESET

IN is a Schmitt-triggered input,

allowing connection

to an R-C

netwc*

for

power-

on

RESET delay. The CPU is held

in

the reset condition

as

long

as

RESET IN

is applied.

RESET

OUT (Output)

Indicates

CPU

is being reset. Can be used as a system reset. The signal is

synchronized

to the processor clock and lasts an

integral number

of clock

periods.

Xi,X2

(Input)

Xi and X2

are connected to

a

crystal

to

drive

the

internal

clock generator.

X-

can also

be

an external clock input from a logic gate. The input frequency

is

divided

by 2 to give the processor's

internal

operating

frequency,

CLK (Output)

Clock

Output for use as a system clock. The period of CLK is twice the

Xs,

X2

input period.

SID

(Input)

Serial

input data

line. The

data on

this line

is loaded

into

accumulator bit

7

whenever a R!M instruction is executed.

SOD (Output)

Serial

output data line. The output SOD is set or reset as specified by the SIM

instruction.

Vcc

+ 5 volt

supply.

GND

Ground Reference.

C-5

ID

"D -a d

t_ <u

<D (U

<a

i;

X)

a. a. a

CO CO

O)

0)

Ere£COE

CO

H

TJ

o

en to 01

a.

c to

—

rz: tZL

CO

X)

~_-

c c C

>>

CD

<D

r: ^ D

H

01

Q.

CD

•a

"5

aj

"5

<D

> > >

™

*

CD

CD 0)

a>

w>

CO

c __ c

_C

-C -C

u>

-t:

(0

CO O)

CO

—

*

c

tr => a: X X X

C-

<"

o

^

K

o

-C

~

°

5

(0 t

X

x

X f

^

*

O

*

o

^: CD

t\J

O

CO

eg

CD

"

.

^

U)

—

S

05

f

£

X3

5

<

>,

o

i—

C\i CO

-*

in

l_

Q.

e

(0

in

<

r-

CO 1-

in

t-

\~

rr

co

«

w

K

rr tx

</)

r-

cn

-

a

£

"a

*

s

o

-J

f

O

0)

Q

I'

-C

-

g

5

<u

o

u

o

-

(/) sz

r

u

c

rn

u

X3

O

C

a

<i)

0)

nC

o

(/I

T3

m

<d

Tl

r

X.

ci)

(/>

o

D)

n

1_

T)

a a>

JJ

g

en

w

u

Cfl

w c

m

0)

J£

o o

i

a

TO

CL

CO

CD CD

o

z

Table

C-1

,

Interrupt Priority,

Restart Address and Sensitivity

C-6

Function

The

80C85A

has

twelve addressable

8-bit

registers. Four of them

can funct-<

only

as two 16-bit register

pairs.

Six others

can

be used interchangeably

as

bit

registers

or a 16-bit

register pairs.

The 80C85A

register

set is as follows:

Mnemonic

Register

Contents

ACC

or A

Accumuiator

8-bits

PC

Program

Counter

16-bit

address

BC, DE, HL

General-Purpose

Register;

data pointer (HL)

8-bit

x

6

or 16-bitsx3

SP

Stack Pointer

16-bit

address

Flags

or

F

Flag Register

5

flag

(8-bit space)

The

80C85A uses a multiplexed

Data Bus. The

address

is split between the

higher

8-bit Address Bus and the

lower

8-bit Address/Data

Bus. During the first

T

state (clock

cycle)

of a machine

cycle

the

low

order address

is

sent out on

the

Address/Data

Bus. These

lower 8-bits

may

be latched externally

by the

Address

Latch Enable signal

(ALE). During the

rest of

the machine

cycle the

data bus

is

used for memory or

I/O

data.

The

80C85A provides RD, WR,

So, Si and IO/M

signals for

bus control. An

Interrupt

Acknowledge

signal (iNTA)

is

also provided. Hold

and

all Interrupts are

synchronized with

the

processor's internal

clock.

The 80C85A

also

provides

Serial

Input

Data (SID)

and

Serial Output

Data

(SOD)

lines

for a simple

serial

interface.

In addition

to these features,

80C85A has three

maskable,

vector interrupt pins

and one

nonmaskable

TRAP interrupt.

Interrupt

and Serial

I/O

The

80C85A has

5

interrupt

inputs;

INTR, RST

5.5,

RST

6.5, RST

7.5, and

TRAP. INTR

is identical in

function

to the 8080A INT.

Each

of the three

RESTART

inputs,

5.5,

6.5,

and

7.5, has

a

programmable

mask.

TRAP

is also a

RESTART

interrupt

but

it is

nonmaskable.

The three

maskable

interrupts

cause the internal

execution of RESTART

(saving

the

program

counter in the

stack and branching

to the

RESTART

address)

if the

interrupts

are enabled and If

the interrupt

mask

is

not

set. The nonmaskable

TRAP

causes the

internal

execution

of

a

RESTART

vector

independent

of the

state

of the interrupt

enable

or masks.

(See

Table

C-1

.)

There

are two different

types of inputs in the

restart

interrupts. RST

5.5

and

RST

6.5 are high level

-sensitive like INTR

(and INT

on the 8080A)

and

are

recognized

with the same timing

as INTR. RST 7.5

is

rising

edge-sensitive.

For RST

7.5,

only a

pulse is required

to set an internal

flip-fiop

which

generates

the internal

interrupt

request. The

RST

7.5 request flip-flop

remains

set until the

request

is serviced.

Then

it is reset

automatically.

This flip-fi op

may also

be

reset

by using the SIM

instruction

or by

issuing

a RESET IN to the

80C85A.

The RST

7.5

internal flip-flop will

be set by a

pulse on

the

RST 7.5 pin even

when the RST

7.5 interrupt

is masked

out,

C-7

The interrupts

are

arranged in a

fixed priority that

determines

which

interrupt

§s

to be

recognized if more

than one

is pending as

follows: TRAP-highest

priority

RST 7.5, RST 6,5,

RST 5.5,

INTR-lowest

priority. This priority

scheme

does

not

take into account

the

priority of a

routine

that was started by a

higher priority

interrupt.

RST 5.5 can interrupt

an

RST 7.5 routine

if

the

interrupts are re-

enabled before the end

of

the RST 7.5

routine.

The TRAP interrupt is useful

for catastrophic events

such as

power failure

or

bus error. The TRAP

input

is

recognized just as

any

other interrupt but

has

the

highest priority.

It is

not affected by any

flag

or

mask. The

TRAP input is both

edge

and

level sensitive. The

TRAP

input must go

high and

remain high until it

is acknowledged, It

will not

be

recognized

again

until it goes low,

then

high

again. This avoids any

false

triggering due to

noise

or logic glitches.

Figure

C-3

illustrates the

TRAP interrupt request

circuitry within the

80C85A. Note

that the

servicing

of any

interrupt

(TRAP,

RST 7.5, RST 6.5,

RST

5.5,

INTR) disables

all

future interrupts (except

TRAPs) until an El

instruction

is executed.

The TRAP interrupt is

special

in that it disables

interrupts, but preserves the

previous interrupt enable

status.

Performing the

first RIM instruction following a

TRAP interrupt

allows you

to determine

whether interrupts were

enabled or

disabled

prior

to

the TRAP.

All subsequent

RIM

instructions

provide current

interrupt enable status.

Performing a RIM

instruction

following INTR or RST 5.5

-

7,5 will provide

current

Interrupt Enable status,

revealing that Interrupts

are

disabled.

The serial I/O

system is also

controlled by

the

RIM and SIM

instructions.

SID

is

read

by

RIM, and

SIM sets the SOD

data.

EXTERNAL

TRAP

INTERRUPT

REQUEST

RESET IN

INSIDE THE

80C85A

TRAP

SCHMITT

TRIGGER

RESET

+5V-

CLK

pi—

S

D

F/F

CLEAR

O

TRAP

INTERRUI

INTERRUPT

REQUEST

TRAP F.F

INTERNAL

TRAP

ACKNOWLEDGE

Figure C-3.

Trap and RESET

IN

C-8

Basic System

Timing

The 80C85A has a

multiplexed

Data Bus. ALE

is

used

as a strobe to

sample

the

lower 8-bits of

address on the Data

Bus.

Figure C-4 shows

an

instructor

fetch,

memory read and I/O write

cycle

(as

would occur

during processing

of

the OUT instruction). Note

that

during the I/O

write and

read cycle that

the

I

port address is copied

on both

the upper and

iower half of the address.

There are seven

possible types

of machine cycles.

Which of these

seven takes

place is defined by

the status of the three

status

lines (IO/M, Si, So)

and

the

three

control

signals (RD, WR, and

INTA). {See Table C-2.)

The

status

line

can

be used as advanced

controls

{for device

selection,

for example), since they

become active at the

Ti

state,

at the outset of

each

machine cycle.

Control

lines RD

and

WR become active later, at

the

time when the

transfer of data is

to take place, so are used as

command

tines,

A machine cycle normally consists

of three

T states, with the

exception of

OPCODE FETCH,

which normally has either four or

six T states {unless WAIT

or HOLD states

are forced

by

the receipt of

READY or

HOLD inputs). Any T

state must

be

one of

ten possible states,

shown in Table C-3,

C-9

o

c

o

< 5

- - - -

*-

o

^

11

~

r. o

-

o

-

,-

w

Ice

o o

*-

o

- -

,-

^

CO

-

o

-

o

- - O

1~

O

to

- -

o

-

o

.- *~

,~

O

12

g

o o o

,-

_

^>

o

O

c

!c

o

(0

o

U.

(D

XJ

O O

o

5

(0 (D

ec

>.

o E

0)

2

0)

£

o E

CD

2

O

•a

CD

oc

O

o

S

o

< z

DC l„

z

"o

0)

)

TJ

CD

o c

J£

o

<

Bus

idle

(Bl);

DAD

ACK.

OF

RST,

TRAP

HALT

Table

C-2. 80C85A Machine Cycle Chart

C-10

o c

o

O

<

"^

o o o o o o o o o

<

z

-

X X X

!1

-

X X X

- - -

CO h-

CO CO

to

<a to

3

CD °3

U)

CO

Q <

O

a <

X X X

X

to

1-CO1-

co to

1-

co i-

CO

(-

<

i

<

X X X X X X X

co CO

£

is

X X X X

o o

co to

CO

to

CO

X X X X

- - -

X

o

X

CD

co

CD

C

'xz

u a

H

1—

<

h- H

1-

H

4

1-

CO

w

u:

1-

t-

< X

t-

a o

X

1~

o

to

T3

CD

Q.

c

o o

</>

c

Q < Q

w

0)

u

>,

o

<U

.E

o J?

nj

o

c

o

V.

a>

co

.£

c

<

(M

-?

T3

l

~~

CD

t

2

en

o

E

c:

*~

P~3-.§

CJ CJ £,

o o

x

o

z:

<

y

I II

O

i-

w

o

CD

d

in

c

8

X

Table C-3. 80C85A

Machine

State Chart

C-11

<

IS

o

uJ

\

*r

U _l

!U

p*

a

i-

<

!^

ls=

-

i/i

Figure

C-4.

80C85A

Basic

System

Timing

C-12

81C55

General Description

The MSM81C55RS/GS is

a

2K

bit static RAM

(256

byte) with

parallel I/O ports

It

uses silicon gate

CMOS technology

and consumes a

standby

current of 100

micro

ampere

maximum while

the chip is not selected.

Featuring a

maximum

access time of 400 ns,

the MSM81C55RS/GS

can be used

in an

80C85A

system without using wait states.

The

parallel I/O consists

of two 8-bit ports

and

one 6-bit port (both

general purpose).

The MSM81C55RS/GS

also

contains

a

14-bit programmable

counter/timer which may be

used for

sequence-wave

generation or terminal

countpulsing.

I0/M

ADo~7<^ZZ|>

CE-

ALE

RD-

WR

RESET

A

256x8

STATIC

RAM

B

PORT

A

TIMER

CLK

—

TIMER 0UT-*-

POR1

C=>

PBo~7

PORT

C

-Vcc

(+ 5

V)

-GND(OV)

Figure C-5.

Functional

Block

Diagram

-*•

pcs[T

-&-

pc«E

-Ha- TIMER

INE

->-

RESETfJ

->•

PCsE

TlMFR

OUTE

-3-

ioAifT

-9-

«E

^=-

rdE

-3-

WR[T!5

-=»

ALE

E

-S-

ADoE

->-

AD.

E

-»

ADi[[I

-^-

ADjfjT

-Ha-

AD«E

-*-

ADsE

-r>-

ADefjI

-5»

AOiE

-95-

6ND[!5

Figure C-6.

Configuration

of

81C55

C-13

Functional Pin

Description

RESET

(input)

A high

level input

to this

pin resets the chip,

placing atl three

I/O ports

in the

input mode,

and

stops timer.

ALE

(Input)

Negative

going edge of the

ALE (Address Latch

Enable)

input latches

ADo 7,

IO/M, and

CE signals into the

respective

latches.

ADo

7 (Input/Output)

Three-state,

bi-directional

address/data

bus. Eight-bit

address

information

on

this

bus

is read into the

internal

address

latch

at the negative

going

edge of the

ALE. Eight

bits of data

can

be read from

or written

to the chip using

this

bus

depending

on

the state of the

WRITE

or READ

input.

CE

(Input)

When

the

CE

input

is high,

both read

and write

operations

to the chip

are

disabled.

IO/M

(Input)

A high

level

input

to

this

pin selects the internal

I/O functions,

and

a low levei

selects

the memory,

RD

(Input)

If this pin in

low,

data from

either

the memory

or ports

is read onto the

ADo 7

lines

depending

on the state

of

the

IO/M

line,

WR

(Input)

If this

is low,

data

on lines ADo

-

7

is written

intoeither the

memory or into

the

selected

port depending

on the state

of

the

IO/M line.

PAo

-

7,

PBo

-

7

(Input/Output)

General-purpose

I/O pins.

Input/output

directions

can be determined

by

programming

the

command/status

(C/S) register.

PCo

-

5

(Input/Output)

Three

pins

are

usable either

as

general-purpose

I/O

pins

or control pins for

the

PA and

PB

ports. When

used as control

pins,

they are

assigned

to the following

functions:

PCO:

A INTR

(port A interrupt)

p

C1:

ABFJport

A

full)

PC2: A

STB (port A

strobe)

PC3: B

INTR

(port B

interrupt)

PC4:

B BF

(

port

B buffer full)

PCS:

B STB

(port

B strobe)

TfMER

IN

(Input)

Input

to the

counter/timer

TIMER

OUT

(Output)

Timer

output. When

the

present

count is reached

during

timer

operation, this

provides

a square-wave

or

pulse output

depending on the

programmed

control

status.

C-14

Function

81C55

has

3 functions as described below.

•

2K bit static RAM

(256

words

x

8

bits)

•

Two 8-bit

I/O

ports (PA

and

PB)

and

a

6-bit

I/O

port

(PC)

•

14-bit

timer counter

The interna!

register

is shown in the figure below, and the I/O addresses are

described in the

table below.

!

C

^>

8-bit In terna!

Data Bus

<"%

<.>X^>

Com-

mand

Status

PC

6 bits

I±Z.

PA

Timer

MSB

Timer

LS8

Boits

a

bits

<^>

Figure C-7. Internal

Register

of

81 C55

A6

i/O Address

Selecting Register

AT

AS A4]A3 A2 A1 AO

X X X X

X

internal

command/status register

X X X X

X

1 Universal

i/O port

A

(PA)

X

X X X X 1 Universal I/O port B

(PB)

X

X X X X 1 1 I/O port C (PC)

X

X X X X 1 Timer

count

lower position S

bits

(LS6)

X X X X X 1 1 Timer

count upoer position

6

bits and

timer

mode

2

bits (MSB)

X : Don't

care.

Table C-4. I/O Address of 81C55

C-15

(1)

Programming

the

Command/Status

(C/S) Register

The

contents

of the command

register

can be written

during

an 10 cycfe

bv

addressing it

with

an I/O address

of xxxxxOOO.

Bit assignments for

the register

are

shown

below:

TMt TM2

IEB

IEA

PC2

PC1

PB

—

^

Timer command-

»

Definition

of PAo- 7

Definition

oiPBo- ?

-"-

Definition of PCo

-

0™

input

1

-

output

00-ALT1

11-ALT2

01

-

ALTS

10-ALT4

See the port

control

assig nment

table.

Port

A interrupt enable

Port

B interrupt enabie

1

-enabled

0- disabled

-

QG-

NOP; Does not afreet

counter

operations.

01

-

STOP

: Stops the timer if

it is running.

NOP if Hie timer

is

not running.

10

-STOP

AFTER TC

: Stops

the timer when

li reaches

TC.

NOP

it

Ihe timer is

not running.

11

-START

:

If the timer

is not running,

loads

the

mode

and the

count length,

and

immediately

starts timer

operation, it

the timer

is

run-

ning,

loads

a new

mode and

the count

length,

and starts timer

operation

imme-

diately

after

TC is

reached.

Figure

C-8. Programming the

Command/Status

Register

ALT1 ALT2

ALT3 ALT4

PCo

Input

port

Output port

A1NTR

AINTB

PC.

Input port

Output port ABF

ABF

PCi

Input port

Output port A STB

A STB

PCi

Input

port Output port

Output port BINTR

PC.

Input

Dort Output port

Output port BBF

PCf

input port

Output port Output port

a

stb

Table C-5. Port Control Assignment

C-16

(2)

Reading the C/S Register

The

I/O

and

timer

status

can

be

accessed by reading the

contents of

the Staxs

register

located at I/O

address xxxxxOOO, The status

word

format is shown

below:

AD7

AD6

ADS AD4

AD3

AD2 AD1 ADO

X™

c

Port A interrupt request

Port

A buffer full

Port

A interrupt

enable

-^

Port

Q

interrupt request

—

- Port B

buffer

full

-^-

Port B

interrupt

enable

-Timer interrupt.

This bit is set high

when

the

timer

reaches TC. and

is reset when the C/S

register is

read or

a

hardware

reset occurs.

Figure C-9. Reading the C/S

Register

(3)

PA and PB Registers

These registers may be used as

either input or output

ports

depending on the

programmed contents of

the C/S register, They may

also

be used either in the

basic

mode or

in the strobe mode,

I/O address of the

PA register: xxxxxOOl

I/O

address of

the PB register: xxxxxCMO

(4)

PC Register

The PC register

may

be used as

an input port, output

port

or

control register

depending

on

the programmed contents

of

the

C/S

register. The I/O

address of

the PC register is xxxxxO1 1

(5)

Timer

The timer is a 14-bit

counter

which

counts

TIMER IN pulses.

The low order byte

of

the

timer register has an I/O address

of

xxxxxlOO, and

the high order byte

of the

register has an I/O address

of

xxxxx101

The

count

length

register (CLR) may be preset with

two bytes of

data. Bits

through

13 are

assigned

to

the count length: bits 14

and 15

specify the timer

output

mode.

A read operation of the CLR

reads

the contents of the

counter

and the pertinent output mode.

The

initial value range which

can

initially

be

loaded into the counter is 2

through

3FFF hex. Bit assignments

to the

timer

counter

and

possible output

modes are shown in

the

following.

C-17

M2 M1 113 T12 T11 T10 T9 T8

ill 1

Output mode

High

order

6

bits

of

count

length

T7

T6

T5 T4 T3 T2 T1 TO

i I

Low

order

byte of count

length

Figure

C-10.

Bit

Assignments

to the Timer Counter

Ma Mi

Outputs a

low-ievel signal

in the

latter half

(Note

1}

of

a

count

period,

1

Outputs

a

low-level signal in the latter half

of

a

count period,

automatically loads the programmed count length, and restarts

counting when the TC value is reached,

1

Outputs a

pulse

when

the TC value is reached.

1 1

Outputs

a

pulse each

time the preset

TC

value

is reached,

automatically loads the programmed count length, and restarts from

the beginning.

Note

1:

When counting

an

asymmetrical value such

as

(9),

a

high level

is

output during the first

period of

five,

and

a low level

is output

during

the second period of four.

Note 2: if an internal counter of the 81C55 receives a reset signal, count

operation

stops

but the counter is not set to

a

specific

initial

value or

output mode. When restarting count operation after reset, the START

command must be executed again through the C/S register,

(6)

Standby Mode

__

The

81C55 is placed in standby mode when the high level at CE input

is

latched during the negative going

edge

of

ALE. All input

ports and

the timer

input should be pulled up or down to either Vcc or GND potential.

When using battery back-up, all ports should be set low or in input port mode.

The timer output should be set low. Otherwise, a buffer should be added to the

timer

output and the battery should be connected to the power supply pins of

the buffer.

By setting

the reset input

to a

high

level, the

standby

mode can

be

selected.

In

this case, the command register is reset, so the ports automatically set to the

input mode and the timer stops.

C-18

82C51A

General

Description

82C51A

is USART (Universal

Synchronous

Asynchronous Receiver Transmits

for serial

data communication developed for the

microcomputer

system.

As a

peripheral

device of the microcomputer

system, 82C51A receives paralle

data from

CPU

and transmits serial data after

conversion. This

device also

receives

serial data from

outside

and transmits parallel data

to CPU after

conversion.

Thus the device

is

used

for

serial

data communication.

82C51A

configures a fully static

circuit using

silicon gate CMOS technology.

Therefore,

it operates on an extremely low

power supply at 100 ^A (max.)

of

standby current

by suspending all the

operations.

82C51A is functionally

compatible

with 8251 A.

D7

a

DATA A

K

BUS /

)

BUFFER

\j

1/

RESET

Cl.K

CD

RD

WR

CS

Dsr--

DTR

CTS

n

READ.'WRITE

CONTROL

LOGIC

\j—

1/

-»c

RTS

*-

MODEM

CONTROL

o

TRANSMIT

BUFFER

c

RECEIVE

BUFFER

IS

Pi

RECEIVE

CONTROL

TRANSMIT

CONTROL

-»

TXRDY

->

TXE

—

TXC

RXO

RyC

SYNDE'F/BD

Figure C-11. Functional Block Diagram

C-19

*-~"

D'E

*

—

O'E

—

RstDfT

NC.[i

gndU

«^>

D«[s

<

—

-*

D

^E

^^

Dsfjf

^^

D:|7

—

TXCfio

_i. WR

EI

>

csfjl

N

-cE

—

c/dO*

->

rdEE

•^-

—

rxrdyE

o

82C5tA

Id.

3j]

Do

13

Vcc

^

N C

^

RXC

13

DTR

H

RTS

II

DSR

13

RESET

Z3JCLK

S| TXD

E]

TXEMPTY

2^

N.C.

i3

CTS

JU

SYNDET/BD

irj

TxRDY

<

*--

~*

^

*-—

—

»

Figure C-12.

Pin Configuration of

82C51

Functional

Pin Description

Do- D?

(Input/Output)

This

is

a

bidirectional data bus which receives

control word

and transmit data

from CPU and sends status word

and received data

to CPU,

RESET (input)

A "High" on this input forces the 82C51A

into "reset

status".

The device waits for the writing of "mode

instruction".

The min.

reset

width is six clock inputs during the

operating status of

CLK.

CLK

(Input)

CLK signal is used to generate an

internal device

timing.

CLK signal

is

independent of RXC or TXC.

How

ever, the frequency of

CLK must be greater than 30 times

the

RXC

and

TXC at Synchronous mode and Asynchronous

"x1" mode, and must be greater

than 5 times at Asynchronous

"x16"

and

"x64" mode.

WR (Input)

This

is

"active

low"

input

terminal which receives a signal for

waiting

transmit

data and control words

from

CPU

into 82C51A.

RD

(Input)

This is

"active

low" input terminal which receives a

signal for

reading

receive

data and status words from

82C51A.

C-20

C/D (Input)

This is an input terminal which

receives

a

signal for

seiecting

data

or commanc

word

and status word when 82C51A is accessed by CPU,

If

C/D

=

low, data

will

be accessed.

If

C/D

=

high, command word or status word will be accessed,

CS

(Input)

This

is "active

low"

input

terminal

which selects the 82C51A at low level when

CPU

accesses.

Note:

The

device

won't be In "standby status" only setting

CS

=

High.

Refer to "Standby Status".

TXD

(Output)

This is an output terminal for transmit

data

from

which

serial-converted data is

sent out.

The device

is

in

"mark

status" (high level) after resetting or during a status

when transmit is

disabled.

it is also

possible to set

the

devicein"break

status" (low level) by a command.

TXRDY

(Output)

This is an

output

terminal

which indicates

that 82C51A is ready to accept

a

transmit

data

character.

But the terminal

is always

at

low

level if CTS

=

high or the device was

set

in

"TX disable status" by

a

command.

Note:

TXRDY

of status word indicates that transmit data

character is

receivable,

regardless of

CTS or command.

If CPU write

a data

character.

TXRDY will be reset by the leading

edge

or

WR

signal.

TXEMPTY

(Output)

This is an output terminal which indicates that 82C51A transmitted all the

characters and had no data character.

In "synchronous mode", the terminal is at high level, if transmit data characters

are no longer left and sync characters are automatically transmitted.

If C

PU

write

a

data character,

TXEMPTY will

be

reset

by the

leading

edge

of

WR signal.

Note:

As

a

transmitter

is

disabled by setting CTS "High" or command, a

data written before disabled will be sent out, then TXD and TXEMPTY will

be "High", Even if a data is written after disable, that data is not sent out

and TXE will be "High".

After

enabled

transmitter, it is

sent out.

TXC

(Input)

This

is

a

clock input

signal which

determines

the

transfer

speed

of transmit

data.

In

"s

ynchronous mode", the

baud

rate

will

be

the same

as

the

frequency of

TXC.

)n "asynchronous

mode",

it

is possible to select baud rate factor

by

mode

instruction. It

can be

1,

1/16

or

1/64 the TXC.

C-21

The falling

edge of

TXC shifts the

serial

data

out of

the

82C51

A.

RXD

(Input)

This is a terminal which receives serial data.

RXRDY (Output)

This

is a terminal which indicates that 82C51A contains a character that is

ready

to READ.

If

CPU

reads a data character, RXRDY will be reset by the leading edge of RD

signal.

Unless CPU

reads a data

character

before next one

character

is received

completely, the

preceding data

will

be

lost.

In

such

a case, an overrun error flag

of status word will be set.

RXC (Input)

This

is a clock input signal which determines the transfer speed

of receive data.

irv^synchronous

mode", the baud rate will be the same as the frequency

of

RXC.

in

"asynchronous mode", it is possible to select baud rate factor

by

mode

instruction.

It can be

1,

1/16, 1/64 the RXC.

SYNDET/BD

(input/Output)

This

is

a terminal which function changes according to mode.

In

"internal

synchronous mode", this terminal is at high level, if sync

characters

are

received

and

synchronized.

If status word is read, the terminal will be reset.

In

"external synchronous

mode", this is an input terminal.

If

"High"

on this input forces, 82C51A starts receiving data character.

In

"asynchronous mode", this is an

output

terminal which

generates

"high level"

output

upon the detection of "break" character, if receiver data contained "low

level"

space between

stop

bits

of two continuous characters. The terminal will

be reset, if RXD

is

at high level.

DSR

(Input)

This is an input port for MODEM interface. The input

status of the terminal

can

be

recognized

by CPU reading status words.

DTR

(Output)

This

is

an output port for MODEM interface. It is possible to set the

status of

DTR by a

command.

CTS

(Input)

This is an input terminal for MODEM

interface

which

is

used for controlling a

transmit

circuit. The terminal controls

data

transmit if the

device

is set in "TX

Enable"

status by a command.

Data is transmittable

if the terminal is at low level,

RTS

(Output)

This

is

an output port for MODEM interface. It is possible to

set

the

status of

RTS by

a

command.

C-22

Function

Outline

82C51A's

functional configuration is programmed

by

the

software.

Operation

between 82C51A and CPU

is executed

by

program

control, Tabte

C-6

shows

the operation between CPU and the

device.

cs C/D RD

WR

1 X

X X

Data

bus 3-state

X 1

1 Data

bus 3-state

1 1

Status

-

CPU

1 1

Control

word

*-

CPU

1

Data

-*

CPU

1

Data

«-

CPU

Table

C-6.

Operation

between

82C51A and

CPU

It is necessary

to execute

a function-setting sequence after

resetting

on

82C51A. Figure

C-13

shows the

function-setting sequence.

If the function

was set, the

device is ready to receive a command,

thus

enabling

the transfer of data

by

setting

a

necessary

command, reading a

status

and

reading/writing

data.

C-23

External reset

Internal reset

v

Write

mode

instruction.

Asynchronous

No

Yes

Write first

sync

character.

Yes

Write second

sync

character.

(End of mode

j

setting

J

Figure

C-13.

Function-Setting

Sequence

(Mode Instruction

Sequence)

There

are two types

of control words.

1. Mode instruction {setting of

function)

2. Command (setting of

operation)

1. Mode Instruction

Mode instruction is used

for setting the function of 82C51A.

Mode instruction

will

be

in "wait

for write" at either internal reset or

externa! reset. That is, the

writing

of

control word after resetting

will

be

recognized as "mode instruction".

Items

to

be

set

by mode instruction

are

as

follows:

•

Synchronous/Asynchronous mode

•

Character hronous mode

•

Character length

•

Parity

bit

•

Baud rate factor (asynchronous

mode)

•

Internal/external

synchronization (synchronous mode)

•

No. of synchronous

characters (synchronous mode)

The bit configuration of mode

instruction is

shown in Figures C-14 and C-15, In

the case of synchronous mode,

it

is

necessary to write one- or two-type sync

characters.

If

sync characters were

written, a function will be set because

the writing

of

sync characters

constitutes part of mode instruction.

C-24

Radio Shack Tandy 200, 26-3861 Technical Reference Manual

Specifications and Main Features

Frequently Asked Questions

User Manual