Radio Shack TRS-80, TRS-80 Model III, 26-1061, 26-1062, 26-1063 Service Manual

•

ervlce

TRS-BO®

MODELm

MICROCOMPUTER

Catalog

Numbers

26-1061/1062/1063

CUSTOM

MANUFACTURED

IN U.S.A.

BY

RADIO

SHACKl!A

DIVISION

OF

/

TANDY

CORPORATION

TABLE

OF CONTENTS

SECTION

NUMBER

II

'"

INTRODUCTION

System Overview

DISASSEMBLY/REASSEMBLY

Disa5Sembly

Reassembly

CPU CIRCUIT BOARD

Technical Description

Video Sync Circuits Processor

RAM

Addrcs.s Decoding Memory Map

10

PORT Description

Video .

Keyboard

Cassette Interface

line

10

Bus Adjustments Model Model

CPU

Module Parts List

..

.................•••••...••.•..

...........................••..

..•...••

.......•.....•.••••..•..

....•.•..............••.

...........••••••••••••....•..

...............•...........•.••..

........••...............

..........•••••••••.........

......•••..•.•••••••..

....................•.........

..................•......

Printer

and

Real Time Clock

•.............................•.

and

Jumper

III

10 Bus Detailed Description

III

PORT Bits

Positions .

................•••.•..

.................••••••.

..............••...

~

•..••••••....•..

.......••••••.

....•......

PAGE

NUMBER

1

3

5

7

9

11

13 13 13 13

14

"

15

16

17

,.

19

21

25

IV

FLOPPY DISK INTERFACE .

Technical Description .

Control and Data Buffering .

Non

·Maskable Interrupt Logic . Drive Select Latch Wait State Generation and WAITIMOUT Logic

Clock Generation Logic .

Disk Bus Selector Logic .

ReadlWrite Data Pulse Shaping Disk Bus

Write Preoompensation and Clock Recovery

Floppy Disk Controller Chip . Adjustments

Floppy Disk Interface

V

VI

RS-232C CIRCUIT

RS-232C Technical Description

Pin Port and Bit Assignments . RS·232C

POWER SUPPLY . . . . . . . . . . . .

Functional Specifications Troubleshooting. Set-Up

Visuiliinspec.:tion Surt-Up

No

Output Perfonnilnce Test Power Supply

Output

·Out

Description .

PC

Board Parts List

Procedures

. . .

and MotorOnLogic .

Logic .

Drives .

and

Jumper

BOARD.

. .

.....................••••.

.........................•.

................••..•..

Component

Options .

PC

Board Parts List , .

. .

.........•••••.

.••••....•..•.

.....•••••.......

.......•••••..••.••••.

......•..••....••.•.

...................••..

..............•••••.•••..

ViIIlues

............•••.

Logic

..••.•.

.,

.3 .3

43

43 44 44 44 44 44 44

45 45

49

53 55

56 57

62

65

67 67 67 67

58 58

69

70

TABLE OF CONTENTS (Cont'd)

SECTION NUMBER

VII

VIII

IX

VIDEO MONITOR .

Functional Specifications .

Se...,ice Adjustments .

ILLUSTRATED PARTS CATALOG

Illustrated

MINI·DISK DRIVE .

General Description

Introduction Important Notice

Physical Description

Functional Interface Connections

Physical Checkout

Mounting Resistor Termination . Flat Ribbon Cable Assembly .

TheoryofOpenrtion .

Introduction .

Organizationofthe

Functional Block Diagram Description .

Indell Pulse . Write Track

Spindle Drive . Positioner Control .

Data Electronics .

Data Recording .

Data Reproduction .

Operation .

Interface Electronics Specifications

Input

SELECT Lines

Drive Motor Enable (MOTORQN) .

Direction and Step Compensated Write Data (CWO) Write

Side Select (SDSE

Output Status .

Index Pulse TRACK OOITAKO-j . Write

Read Data

Maintenance .

Physical Circuit Board Test Points . Option Select .

Input Line Terminations

Pr

...

Cleaning

Alignment

Drive Motor Maintenance .

Carriage

Head Radiel Alignment/CE Alignment . Track

Index Sector Adjustment .

Head

Parts

Protect .

00 Switch : .

Control Lines .

Enable (WG-) .

Protect (WPRT', .

OesaiptionofthePCBoards .

entive Maintenance.._

anet

013

Amplitude/Compliance

..........•...

.................•...

Catalog

Desaiption

the

liP')

(RD-)

the

Head

Adjustment .

Movement Check .

Alignment .

Parts

list

.............•...........

...............••...........

........•••..............

.......•..•............

........•..•.........

........•.•••.........

...........••.•.........

Disk Drive

................•.•......

..........••.•...........

IDS'--DS4-)

L)

.................•.......

............••...........

.......••.•.....

.........••.•.........

Disk Drive .

(DIA-)

(STEP-' .

.....•......•.........

....••.............

.......•••..........

_ _ .

......•......

Oleck

.

..•.....

PAGE

NUMBER

.

73

7S

77

79

8.

91

93 93 93

.3

93 93

94

9.

97 97 97 97 97 97 97 97 97

98

..

101 101 101 101 101

101

101 101 103 103 103 103 103

103

lOS

108

108 108

108

109

110 110

111

TABLE

OF CONTENTS (Cont'dl

FIGURE

NUMBER

SECTION

NUMBER

FiNI

Check . Disk Controller Board Parts List . SalVo Board Parts List (Non-Linear) Servo Board Parts Illustrated Parts Catalog Parts

LIST

list

(linear)

Lin

OF

ILLUSTRATIONS

.......••.

..

.

....•....••..

TiTlE

SECTION1-INTROOUCTION

TAS.aO Model

III

Block Diagram .

PAGE

NUMBER

111 112 118 117

.

119

PAGE

NUMBER

4

1

2

3

4 4

5A

58

5C

5D

5E

5F

5G

5H

5J

5K

1

2 2

3

III

SECTION

CPU

Timing Diagram. . . . . . . . . . . . . . . . . . . . . . . . . . . . . • . • . . . . . . 13

Video Timing Diagram. . . . . . . . . . . . . . . . . . . . . . . . . . . .

10 Bus Timing Diagram

CPU Printed Circuit Board - Component

- CPU CIRCUIT BOARD

..

. . . . . . . . . . . . . . . . . . . . . • • . . . • • • • • . . .

Side.

••

• . . . . . . 16

. . . . • • • . • • . • • • • • • .

..

CPU Printed Circuit Board _ Circuit Side . . . . . • . . . . .

Model

III

CPU Schlml"tic Diagram -

Video and Horizontal Sync

III

Model Model Model

Address

Model Model Model

Cassette Interface

Model

Line Model Model

CPU SChematic Diagram - Processor Section . . . . . • • . . • • • .

III

CPU Schematic Diagram -

111

CPU Schematic De"coding

III

CPU

III

CPU

III

CPU Schematic

Section Schematic Diagram - Video Schematic Diagram - Keyboard

Section.

III

CPU

Schematic Diagram -

Printer and

11/

CPU Schematic Diagram - I/O Bus Section

III

CPU Schematic Diagram -

Real

Time Clock Section... . . . . . . . . . . • • • • • . • . . .

RS·232C Interface and FDC

SECTIONIV-

FOC Board to Floppy Floppy

Model

Did<

Dilik

III

Floppy

flOPPY

CPU

Board Signal

InterfacePCBoard - Component Side InterfacePCBoard - Circuit Side

Disk

Interface

Circuit!>

Di"gram-

............................•....

Diagram-

. . . . . . . . . . . . . . . . . . . . . . . . . . • . . . .

Interface

DISK INTERFACE

. . . . . . . . . . . . . . . . . . . . . . • • .

RAM

Section.

section...

. . . . . . . . . . . • • • .

........••..

Section.

. . . . . .

.......•.•......

Connections.

Description.

. . . . . . . . . • • • • • . . . . . . .

. . . . • • • • • • • • • .

..........••...

...........•••.....

SChematic...

...

....•..•.••....

•••.

.. .. ..

•.

. . 36

..

20 23

24

31 32 33

34

..

35

37

38 39

40

46 47 48 51

LIST OF

ILLUSTRATIONS

(Cant'd)

FIGURE

NUMBER

1

,

3

1

,

3

•

1

,

3

1

,

3

•

5

TITLE

SECTION V

R5-232C Board AS·232CPCBoard RS·232C

til

Model

SECTION VI - POWER SUPPLY

Ten

Set-Up . . . . . . . . . . . . . . . . . . . . . . . . . • • • . . . . . . . . . . . . . .

02

Coll&ctor Waveform . . . . . . . . . . . . . . • . . . • • • . • . • • • • • . 68

02

Bue

Waveform . . . . . . . . . . . . . . . . • • . • • • • . . • . • • . . .

Power Supply 5ct1ematic Diagram

SECTION

Video

Monitor

Deflection Yoke Assembly .

Monitor Assembly Sd1ematic Diagram

Video

SECTION VIII - ILLUSTRATED PARTS CATALOG

Outer

Case

Top Base Plate Assembly

Metal Chassis Assembly... . . . . . . . . . . . . . . . . • . . . . . . . . . . . . .

Disk Drive Assembly . . . . . . . . . . . . . . . . . • . . • . . . . . . . . • . .

- R5-232C CIRCUIT BOARD

to

CPU Board Signal Description

Component

PC

Board - Circuit Side .

RS·232C Schematic Diagram .

VtI-

VIDEO MONITOR

Printed Circuit Board

Assembly.

. . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

. . . . . . . . . . . . . . . . . . . . . . . . . . . • • • • • . . . .

.......••...••.•••.••••...•...........

Side

.......................•...

..•••

, . . . . . . .

...........••..••.•..

.. ..

..

PAGE

NUMBER

..

76

77

78

81 82 83 84

85

5.

60

61

63

67

68 71

1

1A

2

3

•

5 6

7

8 8

10

11

12

13

15

"

16 17

18 18

,.

20

SECTIONIX- FLOPPY DISK DRIVE

Board Component Locations (Logic Board) . . . .... . . . . . . .

PC

Boord Components Locations (servo Boards)

PC

Resistor

Cable Assembly -

Funetional Blode Diagram FM Write Timing

Read Timing

Interface

Logic Board Test Points and

Servo Board "Cat's

Radial Ad;ustmeot Track

Index Sector Timing... . . . . . . . . . . . . . . . . . • . • . • • . . . . • . . . . . 110

Index Upper Arm and Carriage

Illustrated Parts Catalog - Exploded View Mini·Disk Drive Schematic Mini-Disk Drille Schematic (Sheet 2) Servo Board Schematic

Mini·Disk Drive Schematic (new board) . . . . . . . . . . . .

Mini·Disk Drive Schematic (new

Termination.

Recording

Configuration..

Eyes"

tJ0

Stop

Adjustment.

. . . . . . . . . . . . . . . . . . . . . . . • • . • • • . . • . . .

Connector

.............................•..•••.•.•.

Diagram.

Diagram . . . . . . . . . . . . . . . . . . . . . . . . . . .

Comector

Panern... . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

..................•..•••••........•....

Adjustment . • • • • . . . • • • • • • • • . • • • . . • .

. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 110

Pin Removal Chart

. . .... . .... . . . . . . . . . . . . . ..•.••

. . . .... . . .... . . . . . . .•.. . . .... . . . 101

Connector

Locations..

.................••••.............

(Sheet

.....................•..............

boardl

Locations

. . . .... . .... .......•.

11

........••.•••••.•••••.•..

..........••••.............

....•

..............•....

....••.•••••.......

....••.••••••••.

.....•••••••.••.•••....

••••.

,..................

..

94 95

..

96 96 98 98

. 100

100

106

..

. . 107

..

109 109 110

111 118 120 121 122

. . 123

124

LIST OF TABLES

TABLE

NUMBER

1

2

1

2

TITLE

SECTION V - R5-232C CIRCUIT BOARD

BRG

Programming Table .

SECTION

Load Board

Voltage and Ripple Specifications

SECTION IX -

Interface Connector Pin Assignments

Power Connector

Values.

VI-

POWER

. . . . . . .

MINI·DISK

Assignmcots

SUPPLY

............••••..•..•....

....

DAIVE

.............•...

...............•.••.

PAGE

NUMBER

55

58

59

'02 '02

SECTION I

INTRODUCTION

,

SYSTEM OVERVIEW

The Aadio 5tIack TASSO Model

III puter (Modeln.The TAs-80 Model adll8ntilge

Featuresofthe TAS-80 Model

of

the large numberofprograms available.

III

which are common to the TR5-80

• AvailabilityofLevel

•

Full

size typewriter style keyboard

• A 12-inch video

lor

display

LevelIIBASICinROM

• Built·in cassette interface

of

• Character display

• Graphics

under controlofBASIC (128 H x 48

16 linesof64

• UL reoognized construction

In

addition. tne Model

III

has

the

following standard features:

• 12-«.ey numerickeypad for rapid

•

Augged

cabinet housing keyboard. electronics, video display. and power supply

Miaocomputerisan enhanced

IIIissohware

eompatible with

characters

VI

entryofnumbers

venionofAadio 5tIack's popular

the

Modell

§()

include:

thillt

ownenof

TRsaO

Microcom-

either system can take

• Direct drive video monitor for improved resolution

• Internal power supply

• Parallel printer port for

other

several characters,

500

with

features are available when

RAM

internally expandable to 48K bytes, I/O

aoo 1500 baud rates.

Optional peripherals for the increased

The

storage capacity. and a huilt·in R5-232 serial interface for communications and peripheral interface.

Block Diagram shows

USll

with Aadio 5tIack printers

LevelIIBASICisused; features such as: real time clock, upper and lower case

TAS-aO Model

the

various internal components and connectionsofthe Model

III

l)Or\

for peripheral expansion. and cassette interface available

include disk drives (two built·in, two external) with double density for

III

Microcomputer.

3

PRINTER

~

II

LINE

PORT

I/O BUS

, , • I

Z·80 4Kor14K 4K, 16K, 32K,or48K RAM REAL TIME CLOCK UPPER/LOWER CASE VIDEO 500/1500 BAUD CASSETTE INT. KEYBOARD INTERFACE LINE PRINTER INTERFACE I/O

ROM

BUS INTERFACE

CASSETTE

I/O

J~

CH~HJ

POWER

o

SUPPLY

o

AC

D+'

;r:::P~~~==~

I0

~

AC

o:p

POWER

SUPPLY

(optional)

rf1

HJ

~

,---r--L--,

TO

EXTERNAL

DISKS

FLOPPY

DISK

CONTROLLER

(optional)

RS·232

I/O

~

RS'232C

INTERFACE

(optional)

II

o

DISK #0

(optional)

[}

-1

DISK

#1

(optional)

[H

LA

,

ri::1

FIGURE

~

1.

TRS·80 MODEL

~

\",/J

-

I

dygOAE

III

BLOCK

DIAGRAM

a

BRIGHTNESS

CONTRAST

AND

---

-

--------

-

-------------

SECTION II

-

DISASSEMBLYIREASSEMBLY

5

DISASSEMBLY

CASE:

1.

Remove all cables

Position

puter.

easy

accesstothe

from

the

case

of

lengths

screws and note

asideingroups.

2.

Position

and

the

washer from Ihe

3. Very carefully setting it asidetothe careful

4. Remove

nottoexoeed Ihe lengthofthe

$Crews

connectors and remove

CPU BOARD:

1. Remove

all supply cable, if applicable,

hom

the

Compuler

ca~

bottom.

Computer

remove case

from

cable.

connecting

video,

the

RS·232

the

bottom

on

its

bottom.

Notice

Remove

the

their

upright and remuve

topofthe

left

the

back panelofthe

top,

lifting striaghtupand

(if

facing video screenL

chassis shield and the

shield

.••

thc

keyboard,

and cassette cables, and

,md

FDC inter-connect cables).

and

rearofthe

Com·

rear paneltoprovide

the ten

different

positions. Set

types

Ihe:#6

screws

and

them

screw

case.

Be

video cable.

ground

CPU Board {power

R5-232 BOARD (optional):

NOTE: the

1.

2.

The

CPU Board

RS·232 Board.

Be

sure

to

Bo~rd.

R!!move

the

remove

screws connecting

chassis and remove the Board.

MAIN POWER SUPPLY:

I , Remove

on video,

aU

interconnect

the

metal chassis Ixac:ket (power supply cable,

keyboard,

and cassette cables, andIfapplicable, RS·232 and FDC power cable).

2. Remove

bracket

3.

Make sure carefully lift

the

four screws fastening

to

the

case

bottom.

all

inter-eonneeting cables arc removed, then

out

chassis bracket and attached Boards.

must

be removed before removing

all

cables connecting the RS·232

the

PC

Boardtothe

cablestothe

connectors

Boards fastened

and

the

Disk

the

metal chassis

ribbo

....

2.

Remove the five screws fastening

upper right

3.

Remove

screws from

4.

Make sure

corner,

the

small PCB

atop

all

cablestothe

threeonbOltom).

the

metal chassis

nected then remove tt'le spacer

mountstohold

the

mounts

through the

gently pull the CPU Board

FDC BOARD (optional):

NOTE:

The

CPU

Boarr! mustberemovl! before removing

the FDC Board.

1.

Be

sure

to

disconnect

2.

Remove

chass.is and remove

the

screws holding

the

thePCBoard (two

Mount

Bracket and its bracket

CPU Board have been

Board.

the

mounting

(If

your

Board, press

holesinthe

off.l

aU

cablestothe

the

FDC Boardtothe

Board.

.••

discon,

unit uses plastic

the

small

tOOs

PCB

FDC Boord,

metal

two

on

and

the

in

4.

Remove Ihe Bracket (notice where then

DISK DRIVE POWER

1.

Disconnect all cables and wires connectingtothe

the

car.fully

four screws fastening

the

ground

remove

the

power supply,

SUPPLY (optional):

the

Power Supply

tabisfastened),

Power

to

Supply.

2.

Remove Mounting

tened/.

the

four screws fa.tcning

Bracket (notice where

then

carefully remove the Power Supply.

the

Boardtothe

Disk

ground tabisfas·

DISK DRIVES (optional):

1.

To

remove the Disk Driveinthe remove rearofthe

2. Remo¥e which

3,

Disconnect tomofthe

the

ground wire from

the

FOC inter·connect cable

Drive.

the

fOlK

screws and washers

connoct

the

Drivetothe

the

power supply connectOr from

top

boardinthe Disk Drive and also remove

the

rearofthe

top

position,

carefully

connectedtolhe

(twoonealt'l sidel

Disk Mounting Bracket.

the

bot·

Drive.

"Not applicable10all

•

units.

7

4.

To remove the Disk Driveinthe

bottom

position, you

must first remove the Disk Drive Power Supply.

5.

After removing the Powe, Sul)ply, remove the FDC inter·connect

6.

Remove the four screws and washers (twooneach side) whidl connect the Drivetothe

7.

Disconnect the power supply connector from the tomofthe top boardinthe the ground wire from the rear

cable from the rearofthe

Disk

Drive and also remove

of

the Drive.

Drive.

Mounting Bracket.

bot·

3.

Insert a common screwdriver under the suction cup on the high·voltage anode wireonthe sideofthe CRT. the screwdriver10compress the clip holding the wire to the tube and pull

4.

Remove

the

the wire

hee.

ground wire fastened directly to the Video

Board.

5.

Remove which hold

the

upper right and

the

CRTinplace.

I't>wer

reft

nun

and washers

CAUTION

Use

VIDEO

1. Disconnect

MONITOR (CRTI

the

four color

from the CRT yoke.

AND

VIDEO

coded

{Be

sure to note their positions.)

BOARD

wires with spade lugs

2. Disconnect the cOflnectoronthe rearofthe

WARNING

There may be a high voltage anode.

To discharge, connect one

known good ground end connect the

ctIirge

on

Ihe high voltage

endofa wiretoa

other wiretothe bladeofa common screwdriver. Insert the screwdriver blade under the suction to

the clip holding the wiretothe

CRT.

cup

and touch

CRT neck.

endofthe

U dropped,

accident. support the CRT while performing

the

CRT may implode.Toavoid this kind

the

of

6. Remove

the

remaining

l~w,r

right and upper

leh

nun.

and washers and carefully remove the CRT.

7.

Disconnect Ihe

CPU

cable connector from the Video

Board.

8.

Remove Case

the

Top

and carefully

two screws fastening

lift

out

the

Board.

VidllO

Board to the

it

B

REASSEMBLY

RS-232 BOARD (optionol):

1. Install

2. Reconnect

FDC BOARD

1. Install tne

tne

PC

Board using cable, press then fasten

tnePCBoard

with the screws.

all

cablestotne RS·232 Board.

loptionall:

PC

Board

plastic spacer mounts,

u5ing

if

used.

:#6

onto

)(

318" screws.

tnc

plastic spacer mounts

:i;6

)(

3/8"

screws and the

2. Reconnect all cables to the FDC Board.

CPU

BOARD:

1.

Make

sure

good

inwlating

CPU

Board IRev. F boards only) tnen fasten

u~n<;l

#6)(

1/4"

screws.

Reconnect all cablestothe CPU Board {power supply

2.

wa5hef"S

are attachedtothe

cable, video. keyboard, and cassette cables. and cable. RS·232 and FDC inter-eonnect cables!.

If

the

ifappli·

appli·

Board

6. Reconnect the FOC inter·connect cable to Ihe rear the Drive.

DISK DRIVE

,.

Before installing thc Power Supply, be bottom Shieldisill

2. Aeoonnect

3.

Fanen Be

POWER

SUPPLY (optional):

s.ure

Disk

Drivaismountedinplace and the

positononthe

Disk

Mounting Bracket.

all cables and wires10the Power SuppIV.

the

Power Supply with four :?6 x

3/8"

sure the ground tabisfastened backinplace.

that the

screws.

VIDEO MONITOR (CRT) AND VIDEO BOARD;

1. Positron

left andlower rignt ;::10

2. Install the upper right and lower left

tne CRTinthe Case

w<lshers

Top

and install the upper

and nuts.

:::!10

washers and nuts. Be sure to reconnect the ground wire from the CPU

cable.Itwill require two nut5 to fasten

3.

Install the Video Board into

two

#6 x

1/4"

screws.

the

Ctse and fasten with

it.

of

Disk

3.

Attach the small metal chassis brncket with

MAIN

POWER

I.

Fasten the Power Supplytothe metal chassis bracket

SUPPLY:

using four #6

)(

PCB

Mount Bracket (if used)tothe

two

1;6 x

1/4"

screo.\ls.Besure the ground tab

screws.

fastened backinplace.

2. Install the

the case bottom using four #6 x

3.

Reconnect

and cassette cables. and AS·232 and FOC and

chassis bracket (with all Boardsinplace)

1/4"

all

cables (power supply, video, keyboard,

Disk

ribbon cable it necessary).

screws.

pO'Ner

DISK DRIVE (optional);

1. Place the

Disk

Driveinthe

bottom

position and reoon·

nect the ground wire and power supply connector.

2. Fasten the Drive with four flat

wash81'S

3.

Reoonnect the FDC inter<onne<:t cable to the rear

(twooneach side).

#6

x 1/2" screws and four

the Drive.

4. Position

the

second Disk Driveinthe

top

position and

reconnect the ground wire and power supply connector.

5.

Fasten with four screws and washers

(two

on

cables

of

each side).

4.

Connect the ground wire with solder lug Video Board.

5.

Install tne plugonthe rearofthe

6. Innall the four color

is

their a5S0ciated terminals (as determined by a colored

ooded wires with spade lugs

CRT neck.

dotonthe yoke neor each terminal).

in

7. Install the high·voltage anode wireonthe sideofthe CRT.

Use

a screwdrivertocompres.s the clip and insert

it

into the CAT. Press down on the suction cup

secure.

CASE:

all

1. Double'check to be sure

all

rectly and

Boards are properly fastened,

wires are connected cor·

2. Attach the chassis shield (if used) with #6 x screws ltnd reconnect the ground connectors.

3. Carefully

Do

off.

4.

Install the

in

the

5.

Carefully rest the Computeronits rear panel and replace

pillce the

not

hit the CRT neck.Itcould implodeorbreak

#fj

top

rear panelofthe Case.

the ten#8saews;

718" machine head afong front. and two

head

in

remaining positions.

Case

Top

over the

x

3/8"

sneet metal screw and flat washer

five1"sheet metal toward rear, three

back.tothe

Case

Bottom.

1"

machine

to

1/4"

9

SECTION

III

CPU

CIRCUIT

BOARD

11

TECHNICAL

The

techniul circuit board will be broken down inlo nine sections. These ilIre:

1. Processor

2.

RAM

3.

Adress Decoding

4. Video

5.

Video Sync Circuits

descriptionofthe

Model

III

Computer CPU

6. Keyboard

Cilssette Interfaces

7.

8.

Line Printer and

9_

1/0

Bus

This breakdown, which follows

diagrams, will allow

matic

VIDEO SYNC CIRCUITS

The video end polarity requilements adjustment crete increments. The verticol sync pulse VSYNC low is

either50or60Hertl. the signal HSYNC mately 8 psec. The vertical plane adjustml!rlt covers a total of

eight rows andisadjustillbleinincrementsofone {R1. R2, by tions. Both adjustments lire ac<;omplished with wired

PROCESSOR

The MHz. clock (10.1376

sync circuits are required10meet

in

both

and approximately

R4l. The horizonUI plane adjustment increments

two

charac'lers for a

"AND"

CPU

The

gates U22 and U38 {LS266J.

chipisa Z.sO

CPU

Real

Time Clock

the

partitioningofthe

ea'iY

explanation and referencing.

of

the

video monitor.Italo;o

the

horizontal and vertical planesindis·

693J,LSecinduration, The horizontal

is active high

totilll

coverageof16

that

runs at a clock speedof2.02752 clockisderivedbydividing MHz)

by

five. U62 performs this function

rateis15.840Hzand

withadurationofapproxi-

sche-

the

pulse width

allows

is

active

The

frame

late

row

character posi-

the

use

the

basic video

of

DESCRIPTION

and

the

dock

is

non~ymmetrical

cycle. The

and becomes PCLOCK which has a full rise and fall times. keyboard.isORed with poweronreset (R7. provide a System RESET"' signal. The Reset pinonthe is

driven

LS244's (U91, U92), the

control

control lines are combinedinUa9

and

See

U75 cycleorany read operation (1001Memory). Whenever one of

the abled CPU not U104,

ROMs,

dock

signal

POCisrun throughanactive pull-up

The

reset switch. whichislocatedonthe

by

RESET". The MIdress lines are buffered by

data

lines buffered

10 port controls

the

CPU Timing Diagram for exact time relationships.

is

used

to

S>N

ROM's

by

dala

used.

Ul05,

reslJectillcly.

IS

U108 since Ihe ROM's

bus,

BUSRO',

The

Model

U106). They are 64K

by

(RD·,

tch the

being

acceued,

HALT", BUSAK".

III

AAM

The

RAM

consistsofan arrayofuptotwenly-four 16K

chips

dynamic memory address are 8000toBFFF

FFFF.

1\'\/0 memory

direction of

the

by as between RAS". MUX,

and

control lines

addressed at

and U43toU50 are addressed at Cooo

The memory

8T26s (U63, U64). Normally

array. However.ona read cycle U19 switd1es the

the

data

bus.

The·

a 3·terminal regulator (MC7905Cl which takes

its input. See

the

with

4000to7FFF.

dataisinterfacedtothe

transceivers and drives memory

5 volts required by

CPU

Timing Diagram for

CAS·,

with a40percent high

5''1011

swing with

C54.

lines byanLS245

an

lS367

WR·.

data

has three sockets for

damping resinors locatedonall

(RP1,

(U76). The buffered

and US6toform memory

IN·,

OUT·).

bus

buffer during

the

data

bus

bufferisdis·

dala

lines are locatedonthe

and

RFSH'

bit,32K

RP2. RP3). Chips

U25toU32 are addressed

the

t>it

and 16K bil

data

dataisdriven Into

the

RAMsissupplied

the

relationship

U15)

(USO).

INT

the

U710

bus by

dala

-12

duty

fan

to

Z.g()

and

AK·

are

ROMs

U14

at

10

the

onto

volts

___

i .

..-

~

..

_...-

1JUU'.nJ1.J1fUlJ1.iUl/UUl.fiJU1JlIlJ1n.n.nnnnnnIU1IU\.N'\J1J\J1IlIlJl..n.r\.il...

.

'''...,.~~~~~~

..

'..

::x

_o·~

"0"

~

""

.,.._.".....

I I ------=y

---F1

...J

n

a.. ,. ,,

..

.....

"""

~""'.

"

\ I

_----1

FIGURE 1.

CPU

~,

.,~

".:....

\....

TIMING DIAGRAM

..

_

_.

"""",._

.u_._

.

x::::=

I

13

ADDRESS DECODING

The Address

10

pons,

controL Refer to the Memory

devices. The two LSl38 demultiplexors provide the INPUT

and OUTPUT strobes for system10ponsEOto

OUTs and U40 for

U61ina shift register configuration clockedat10.1376 to

give CAS'. Column address for the memory a by LSl39 (USB!. L$32s (U59,

of

RAMs. Note that the first row01RAMsisthe

suitable for 4K

FFI. The

generated by partofthe LS145 (U60I. The combinational logic below U60

Decodlllg p.ovidesaUthe selects for the system

the ROMs, Keyboard, Video,

Vlap

INs.

Memory timing consistsofU37 and

the correct relationship between RAS",

MUX

provides the switch between

on

the

address multiplexors U24 and U42

..

ay. The three CAS signals are generated

Ul07);

RAMs

{jumper

RO:\.1

strobes (RQMA·, ROMB', and ROMeO) are

the

remaining sectionofthe

option

~nd

RAM

for exact locations

Row

one

CAS for each row

U to T, N to P,GGto

LSl39

memory

FF;

U41

for

MHz

MUX.

am,l

address and

only

one

(usa),

and

of

(U75, U73, ROMC' (37E8 and 37E9) which printer

the

16K bit

ac;;cessed

10

port

breakdown

remaining strobes

the

lS145

un, U74,

address. thus ROMCP'isthe actual

ROM.

for a readaseither a memory add.ess /37E81oran

(F81. See thetoPan

of

all

(U60).

U861

deleles two addresses from

The

resultisthat the line printer may be

10

pons

and address

KYBO'

ilnd

VID'

correspond to the line

nrobe

Description

lor

a complete

spac;;e

are also generated by

going to

map. The

MEMORY

HEX

ADDRESS DESCR IPTION DECIMAL SIZE

00

••

1FFF

2.00

2FFF

MAP

ROMA

ROM

OF

MODEL

B

III

3000 ROMC

37FF

37EB Printer Status 37E9

••

38

3BFF

3COO

3FFF

Keyboard

Video

.K

4K

2K·2

2

lK

OK"

1024)

14

4000

7FFF

••

00

BFFF

C."

FFFF

RAM

16K

10

PORT DESCRIPTION

Name:

Port Address: Access: Description:

BIT 7

BIT 6 - OUTPAPER

BIT 5 = UNIT SELECT

BIT4

Name,

Address:

Port Access: Description:

BIT 7

Name:

Pon

Address:

Access: Description:

LPIN"

0F8H

Retld Only

'"

Read Line

BUSY

Pnnter

I-True

0"'False

I-True

0-False

I-True

0=False

= FAULT

'-True

0"'False

LPOUT" OF8H Write Only

Line Printer

thru

BIT 0~ASCII Byte 10bePlinled.

RTCIN" 0ECH

Rl:!ad

Only

Clear Real

Time Clock Interrupt

Output

POrt Status

Data

Pon

N3me: Port Address: Access: Description:

Pon Port QFIH .. Disk Track Regisler Port Port

Name:

Port Address:

Access: Description:

Port 0E8H Port 0E9H

Port 0EAH .. UART Status Register

Port 0EBH

Name: Port Address: Access: Description:

Port 0EBH .. UART Master Reset Pon PortOEAH

Port 0EBH

DISKIN"

0F0Hto0F3H

Read Only

Disk Control Aegisttrs

Read

OFOH""Disk Sl3tus Register

0F2H'"Disk Sector Register 0F3H'"Disk Data Register

RS2321N"

to

0E8H

CilEBH Re3d Only Read UART

'"

Modem Status

co N.A.

'"

UART Receiver Holding Register, Resets D.R.

RS2320Ur

OEBHto0EBH

Only

Write UART Control,

Modem Control; BRG Control

QE9H'"Baud Rale Register

..,

UART Control register and

Modem Control

= UAAT

Transmi"er

Registers

D.1la;

load

Holding Register

BIT 7

Name:

Port Address: Access: Description:

Port Port Pon

Pon

thru

BIT Q

Don't

Care

OISKOUT"

to

0F0H

0F3H

Wrile Only

to

Write

0F0H

• Disk Command Reginer

Disk Control Registers

0FtH0:Disk Track Register 0F2H'"Disk Sector Register 0F3H • Disk

Dau

Regiuer

15

VIDEO

The

Video

~ction

A.

Vidco

B.

Molin

C.

Character generation logic

D.

Wait logic

A.

The

video

U82) which

from the divider chain

LS1S1 multiplexors (U69, U70, U71).

bufferedtothe ortothe

Addressing controlisdetermined

U6B.

RSVID'

B.

The

main oscillator consistsofinverters from U2, cryslal

YI,

and discretes

the

fundamental modeata frequencyof10.1376 This basic frequency comes CLOCKI2.

fed

to

mux

CHAIN signal 1633.6 kHz) provides

with

U52

LATCH SE

Lselects either

(Refertothe

consistsoftwo LS393s

chain

(U

1). This divider counter, counl.

can

be subdivided into four parts;

RAM

wilh associaled addressing and

oscillator and divider chain

RAM

consistsoftwo

gives

1024IIK)

or

the

CPU

data

bus

character

whichISdescribed in paragraph O.

U4 which provides Ihe divide'

the

1118

presents

and

the

generator

Rl,

R5.

andCl.

is

dividedbytwo

The

CLOCK

SHIFT signal, and

Ihe

rateofSHIFT!tovarious

the64characteror32

Video Timing diagram.)

chain,

connectedasone

the

character

horizontal and vertical drive signals

data

buffer

2114

static RAMs

bytesofRAM. Addressing

Z-80 CPU comes from

The

through

logicbyIhe LS273 latch

and

(U20.

COUnl,

an LS245

by

TheoscillalOf runs in

in U3 and be·

CLOCK/2 signals are

chain

the

shift register

i1lso

supplies

character

The

US6) and

Ihe line

(UB

the

video

data (U6]!.

the

$ignal

MHz.

with

the

signal

p<!rts.

MOD·

mode.

main divider

one

LS14

long ripple

and

row

to

the

restofthe video section. The horizontal drive signal

at

(HDRVj runs acters per line;64displayed and 16 blanked. count

IL1toLSI lines per and 150 or

1. C.

The character generation logic U6S)

is

dol patTern making {LS166 . on signals provided cuits. On ASCII to dressofthe charactertobe displayed.

sing informaTion comes

L4)toselect the scan lineorthe charactertobedisplayed. (There are lwelve scan linesineach character block.) On Ihe next LATCH pulse Into

clock.

LATCH, hence

acter qualified by OLYBLANK so

trace, vertical retrace, ilnd

elliulleter displayed,

character

VDRV) runs modulo 22

Hzl depending which jumper

"C",

has

to

hold the ASCII

US21

the

sa-ellO. and

the

byte

the

character

the

shih

The

line

The

15.840 kHz and

runs modulo 12 (i.e., twelve horizontal

block!.

been

selected.

which serializes

by

rising edgeofLATCH the

f.om

Ihe video RAMs. This

gl!Oera;:or

register and

SHIFT clock runs eighl

there

LATCH signal

the

The

data,aROM

up

the

characters, a shift register

the

associaled limtng and control

the

divider chain

ROM

from

the

data

shihed

are eight

the

shift register will shift

resulTsin80

row

counter

(60

Hz).ormodulo

oPtion,

consins

the

S·bit

to form pari

the

diVider chain

from

horllontal

into

that

during horizontal

last four scan linesofeach

"An.ornBw

of a latch (LS273·

which

data

and

oscillato. citlS273 dataispresented

The

other

the

ROMislatched

out

bv

time->

dots

the

shift register

The

(RltoRS

comains

10f

display

stores

olthe

addres-

ell

the

SHIFT

fasler

per char·

out

zeros.

char·

line

the

ad-

than

26

to

is

reo

«...

nfI.r

"':UlIU

UlIU1Jl1Ulr..J1IL'lJUlf

"... , JlJL..r1Jl..-'lJ'"1...n..J'"J""'JL

...

DGI ,

..n....r

Jl

...

rt

J1.J'"""'

......

,.~

t...r...Jl....

'L.J"L

16

....

'_

..

_

....

-

"."'''''''''-~'''-'

FIGURE 2. VIDEO TIMING DIAGRAM

If

V07isa

acter will be displayed which uses LS153 (U54j

LS244 IU531toload that

both

one

U36

and

V06isa zero, 1hen a graphics

the

data

into

the

and

U53

are tri-state devices and

char·

.nd

shift register. Note

that

the

enables for thesedevices(OLYCHAR" and DLYG RAPH·

IC')

are

the

complementsofeach

other.

This means

th<lt either character dataorgrephics data will be loaded into the

shift register depending of courseonthe

and

VD6. The signal ENALTSET and

the64characters

allow characters

to

ENALTSETisa

be displayed from

one.

that

are m<lskedbythe

the

64 standard charactersare dis·

played. When ENALTSET is II zero, 64

<In

ROM

alternate

stateofVD7

LSOO

(U37)

graphics

(U36). When

char·

acters are displayed.

O.

The wait logic forces

BLANK'

signal is not present. This allows video

the

CPU

into a wait >tate if

the

RAM

updates only during horizontal retrace. vertical retrace.

on

the

oonditions

the last

and the blanking

these are

since

will eliminate virtually all

The logic When

consistsofU17.

VID'istrue,

the video RAM, and oombined in U16

it

is

combined with

granted

accesstothe

disabled through

to

VIO"

the

four

scan linesofa character

that

form

BLANK-.

the

"hashing"onthe

U16,

U18. U57,

indicating

the

CPU wants access

PBLANK'isfalse, give

PWAIT'.IfPBLANK' to give

RSVID'

both

U39.

signals are

,which

display.

and

istrue, is then

video AAM. This feature can be

OISWAIT inputtoU39 which

This

Ul.

under software control.

KEYBOARD

The keyboard interface consists

(LOO51

U34 and U35 which feed

addressesAOthrough A7. The Ou1,)utofthe

of

open

collector drivers

theBbyBkey

matrix has

matrix with

the

pullup resistors and CMOS receivers which give reliable key

key

closure sensing even with resistance. The

data busbythe

octal

data

keyboard assembly and the

twenty·pin keyboard cabletothe

all

electronic parts are

requiredonthe

data

from

the

LS240 (USS). The signal

bus driver. The reset switchisalso

the

mountedonthe

PCB

for

the

switches ofupto

CMOS hufferisdriven

KYBD'

three lines required are routed in

reset circuit. Note

CPU

keyboard.

300

ohm

onto

the

strobes

the

mountedonthe

that

Board; none are

the

irIput signalatpin 4 may be compared against. Capacitor

C93 provides

a voltage equaltothe

R46 and CA9 providing fast dischuge. since signal level.

respondingtothe U2

flip-flop will

CAS

will read

Capacitor C93 providesanequivalent AGC action

the

comparator

The

threshold becomes proportionaltothe

comparator

input pulses which are then inverted by

and

fed into

the

clock

thenbeset and will stay set until cleared

OUT·

(equivalenttoOUTSIG in Model II. CAS

the

data

stored inU3and

charge

of

average signal level, with

and

R48 providing a slow

outputs

a

"0"

negative pulses cor-

flip-flop (U3).

outputitat

The

"0"

by

IN'

pin 7ofthe

data bus.

The

500 Baud Write circuitry

cuitry

used in

the

squarewave datil for 1500

out,

Data01H gives 0.8V

the

ModelI.This circuitisalso usedtoprovide

The 1500 Baud uses0'Hand put

is

a 250l1sec pulse white

that

squarewave

2680

Hz.

to

The

1500

detector

using

signal from driving pin

of

U96,

13

will provide a

is

vide this the

which

SOmVofthreshold

comp¥ator

determine

and is also used

variesinfrequency between 1320Hzand

Baud cassette input consists01a zero crossing

U9S.

Diode

1001

is normally high when

50mV

thresholdatpin 11. A57 and R59

is fedtothe whether

to

setaninterrvpt signal U35. ENCASINTF, pin2,enables latch

and

ENCASINTR, pin rupt time.

latch. Only

CASIN·

oneofthe

clears

the STATUS·isusedtoread tell which latch has been set.

is

identicaltothe

BaUd.

Data

out,

and Data 02H gives

02H only. The

the

15Q()

Baud

CRB

is usedtoprevent

U96 negative. The

the

signalisapplied and

and

hysteresis. The

two

74LS74

the

risingorfalling edge is detected

INT·

the

falling edge

12,

enables

the

write cir-

DOH

gives O.4V

O.OV

500

Baud

outputisa

the

output.

output

"0"

flip-flops

using U18 and

inte"upt

rising edge inter·

latches are enabledatanyone

interrupt latches and RDINT·

thedau

The

from

cassette

the

interrupt latch

motor

on relay

OUI.

out·

input

pro·

of

to

is

drivenbyU97.

CASSETTE INTERFACE There are

1500 Baud. The j)l'"incipletothe forms noise. The

wave

rectified

two

sep¥ate

casselle circuits

500

Baud Read circuitryisvery similiar in

Read circuitryonModel

a

two

pole high

two

amplifiers01the

P35S

active filtertofiller

MCI458

active rectifier. Capacitor C94

output

whichisthen led

tol)339

lor

500

I.

The MC1741

out60Hi

(U80) formitfull-

acutosmooth

comparator

Baud and

out

lU96I.

Resistors R48. A49, and ASl provide a fixed threshold O.5Vatpin 5ofU96. This gives a minimum level

with

the

of

which

17

LINE PRINTER AND REAL TIME CLOCK

data

The LS273 (U941latches Ihe and

the

one-shot jU93) provides

status lines are buffered through

of

eight bits face could

Thc

Real

interrupt10lhe CPUifenabled. VDRVisdividedbyIWO U83 (LS74) generatllS an inlcrrupt through LS38

be

can To

clear Ihe inlerrupl

lOBUS

data are bufferedsothllt

be

used rOI any g.enenl purpose

Time Clock circuit provides eitherII30Hzor25Hz

and latched in Ihe other sectionofUS3. This

readbystrobing U84 {LS367J with RDINTSTATUS',

one

mU$l

written10the Line Printer

the

dala

strobe, The printer

the

LS244 (U95). A full

the

Line Printer inter·

Strobe

paralJ.e1

(USB}

RTCIN·.

and

interface.

the

$tatus

ADJUSTMENTS

The jumper positions vary between models. Jumpers should

4K

RAM

16K RAM

al

The CRT positioning jumpers also very between

60Hz models, Jumpers should be installed as dcscrlbed

and

The

below. determinedbythe

monilor

Ihe

The

standard CRT jumper configurations for a60Hz

puter

are:

Vertical and

used.

AND

JUMPER POSITIONS

4K

and 16K

be

installedasdescribed below.

U10T, N10P, GGtoFF

StoT.RtoP,EEtoH

HoriZOf'Ital

factory and dependonIhe frame rate and

Position jumpers are

the

RAM

50Hz

com·

The 10 device comp;:rtibletothe

(U10ll ENEXTIO. The directionisdetermined by and enabled by ENEXTIO. The operation are buffered by Ihe LS367(U103) and enabled also by ENEXTIO. EXlernal10wails and supported tailed10Bus description and timing diagram.

Bus

supportS all Ihe signals necessarytoimplement a

buffers

by

the

10 Bus

Z-SO's

dellainboth

via

10

Structure. The L$245

directions

control lines necessary for 10

US7

and U88. Refer10lhe

and

is

enabled

the

L$244 (Ul021

interrupu

by

are also

de·

Vertical

Horizonlal Position

The aro as follows:

Vertical Frame Rate:

Vertical Position

Frame Rate:

CtoB

Position Adjustment:

o

10

E

K

to

L

J

to

H

Adjustment:

VtoW CCtoBB

standard jumper configurations for a50Hz

to

B

A

Adjustment:

D

10

E

to

L

M

G

to

H

computer

18

Horiwnlal

There norma1ty should be no needtochange these jumper positions, too jumper plug positiontothe

Position Adjustment:

V CCtoBB

however

fertothe

left.Ifthis should occur, change

10W10

right within

to

W

on

some units

X. This moves

the

raster.

the

display may appear

theV10

the

display one

dlaracter

W

The

Mode!

III

10 Bus was designed to allow easy and conve·

nient

interfacingof10 deviccstothe supports compatible

ali the signals necessary

to

the

2-80's10structure.

Addresses:

tports

AGtoA7 output

80H

allow selection

devices.

to

(If

external 10 is enabled.)

I3FFH are reserved lor Sy$lem use.

to

ofupto

MODEL

Modcl Ill.

implement a devicil

That

256tinput

The

is:

and

10 Bus

256

III

10 BUS

For input

port

devices bv writing softwilre. This will enable control

input

signals

deviceisselected the assert.ng EXTIOSEL'low. trilnsceiver

bus be

generatedbvNANOingINand

data

and

lines.

dcvice use, you

to

pan

to

the

10 Bus

allows

the

CPU to read

see

Figure 3

muSI

enable extern

0ECH WIth bit 4onin

the

data

bus addrcss

edg~

connector.

ha~dware

ThIS

for

w II acknowledge

:;witches tile datil bus

the

conlelllSofthe

the

timing.

10

EXTIOSEL·

port

IIddress.

ill

the

user

IIn~s,

ilnd

When

the

by

can

10

Data:

Dgg

to

DB7

cessor

Control

a. IN- -

b.

allow transferof8-bit

data

bus if external 10isenabled.

lines:

2-80 gress. Gated with OUT'

- Z

·80

signal specifying

lORa.

signal specifying

data

onlo

thataninputisin

thatanoutput

progress. Gated with 10RO.

c.

RESET·

d.

10BUSINT- inputtothe

interrupt

- system reset signal. CPU signalinganan

from an 10 Bus deviceif10 Bus interrupts

are enabled.

e.

10BUSWAIT- 10 Bus devices

inputtothe

to

force wait statesonthe

CPU wait line allowing

external 10isenabllKt.

f. EXTIOSEL- -

10 Bus

instruction

g.

M1·and

The address line,

data

to

lORa-

data

are enabled only when

inputtoCPU which switches

bus

transceiver and allows an INPUT

read10Bus

-

line,

and

the

ENEXIO bit in ECissettoa

data.

standardZ-80signals.

control

lines atoc

To enable 10 interrupts. the ENIOBUSINT bit 10PORT

disabled

10BUSINT" line can still readonthe 10PORT

E0

(output

tram

E0.lInput

port)

must be a one. However, even it

generating Interrupts,

port).

the

status

appropriate

the

pro-

is

Z·80

the

andeto

one.

in

CPU

at

the

bitofCPU

Output

in

port

1>0' r device use

that

the el<ternal 10 devices

OECH with bit 4

is

the same as input

mU$t

port

be en"blcdbVwriting

oninthe user software.

deviceinuse

in

the

same

to

fashion.

For either

line

in

devices used in caution. may cause during this

inputoroutput

can

be

usedinthe

10

tne

CPU. Note

the

Model III.

Holding

the

lossofmemory

time. Itisrecommended

linebeheld active

devices.

the

10BUSWAIT' control

normal way 10' synchronizing slow

that

since

the

wait

CPU in a w"it slllte

contents

no

more than 500

dynamic

hne should be used with

since refresh 's inhibited

that

~sec

memories

tal

2mSl'Cormore

the

IOBUs\''VAIT'

with a 25%

afC

duty

cycle.

if

The

Model

jump

the

Usel

routine

When an

III

will

support

lable is

supportedbvthe

,"ust

supplv

bv

writing this addresstolocations

interrupt

occurs

Z·BO

the

address

the

program will be veCtOledtothe

mode

1 interrupts. A

lEVELIIBASIC ROMS

of

his

interrupt

403E,

and

RAM

and

service

4133F.

user supplied address if 10 Bus interruplS have been enabled.

9

To enable 10 Bus interrupts

the

user

must

set bit 3 of Port

0EGH.

See Model o

ElJonattached

The devices"inthat

ModeJ

111

Port Bit assignment for

sheets.

III

CPU

boardisfullv

all

the

disabled under software

device on

&

sohware)

the

10 Bus. certain requirements (both hardware

must

be met.

ports

tiFF.

GEC. and

pfotected

from "foreign 10

10 Bus signals are buffered and

control.

To

attach

and usc an

can

be

10

19

Input or Output Cycles.

....

·.101

~-

O"'T"'.US

w,-

o

...

T

...

SUS

" "

•

-

\

-

IX

1\

\ \ \

"l)J1T

"'DOIIU5

.-

"

/

"

X

,,~

evcu

'"

-

1----

t-----

=r-'C

00'

----

1-----

---

WRIH

CYCLE

Input or Output Cycles with

•

-

........

,

10110-

0 ...T/I,IIU5

-

"

...

n·

-

DAT

....

UI

w,-

fUT'OS(l'

Wait

"

h

X

t----

1----

States.

~

---

----

"

"l)IU"'OOIlUS

~

l.L

.-

~

1--

'.

~

"

~

1"-

,,~

CYCLE

WJlITI

CYCLE

\...

"

---

t--t---

2Q

___

~

..,.DOI;f'l,I

wilhlDMo-

__

"!'lIT_.

FIGURE3.10

BUS

TIMING

DIAGRAMS

MODEL

III

PORT

BITS

N,m,: Port Address:

Access:

Bit

7"

ENINTRO; 0 disables Disk INTRO from

an NMI.

1 enables above.

6

..

Bit

ENDRO;

WANMIMASKREG'

0E4H

WRITE ONLY

iii

disables Disk ORO from generating an

NML

, enables above.

RDNM

1ST

Name:

Port

Address:

Access:

Bit

7 .. Status

Bit

6 .. Status

Bit 5 ..

Name:

Port Accesl:

Bit

Bit 4 .. ENEXTIO;

Bil 3'"ENALTSET;cadisables

Reset'

Address:

7

'"

Undefined

6 .. Undefined

5

'"

DISWAIT; 0 di,ables video waits, 1 enables

1 enables

0E4H

READ ONLY

of

Disk INTRQ:

of

Disk ORO; I " False, 0'"True

StatUi; 1 = False, 0 -

MOD OECH WRITEDNLY

alternate

ATUS·

OUT

tJ

disabills external 10 Bus, 1 enables

video character set.

1"

False, 0'"True

True

alternate

character

gener'ting

set,

Name: Port

Addren:

Access:

NOTE: A

Bil 7 .. Undefined

6

..

Bit

Bit 3..lOBUS tNT

Bit 2 .. RTC INT

Bill'"

BIt 0~CASSETTE

Name: Port Access:

Bit 7 .. Undefined

Bit

RS-232 ERROR INT

5'"

RS·232

4"

RS·232 XMIT INT

CASSETTE

Addrt$s:

6

~

Undefined

5

'"

Undefined

4 .. Undefined

3

'"

Undfined

ROINTSTATUS·

0E0H

READ ONLY

eindicates the device is interrupting.

RCV

CASQUT·

OFFH

WRITE ONLY

INT

(1500

Baud) INT F

Baudl tNT R

Bit 2'"MODSEL; (I enables 64 character

I enables32character

BIt 1

'"'

CAStJlOTQRON; 0 turns cassette

1

turns

cassene

Bit II..Undttfined

motor

mode.

on.

mode,

motor

off,

Bit

2

'"

Undefined

1

..

Cassette

liI

"'Cassent

output

outpull,vel

level

21

Name: Port

Addren:

Access:

WRINTMASKREG·

0E0H

WRJTEONLY

Name: Port

Addleu:

Accen:

DRVSEL' OF4H WRITE ONLY

Bit 7 .. Undefined

Bit

6 = ENERRORINT; 1 enables RS·232

error.

ity

framing

error.ordata

II disable above.

Bit 5 = ENRCVINT;

full

interrupts,

'enables

RS.232

adisables above.

Bit 4 = ENXMITlNT; 1 enables RS.232

register

empty

interrupts.

adisables above.

Bit 3 .. ENIOBUSINT; 1 enables 10 Bus

"disahles

Bit 2 =ENRTC; 1 enables real

"disolbles above.

Bit 1 .. ENCASINTF; 1 enables

rupt,

odisables above.

above.

time

dodo;

1500

Baud falJing edge

interruptsonpar-

overrun

error.

receive

interrupts.

data

transmitter

interrupt,

register

holding

inter·

Bit 7 ..

Bit

Bit 4 = SDSE

FM

'/MFM;

1 stdl!cts

6"

WSGEN; " .. no wait states generated.

1 .. wail states generated.

double

5 = PREOOMP; "

1 ..

wrile

preoompenSillion

L;Iiscle<:ts side aofdiskette.

1 selects side 1

Bit 3..Drive select 4

Bil 2..Olive select

Bit 1 .. Drive select 2

BIt"

.. Drive select 1

0 selects single

dens'

tv .

..nowrite

of

diskette.

:j

density,

prec:ompensalion,

enabled.

Bit

0"

ENCASINTR; 1 enables 1500 Baud rising edge

rupt, o disables above.

Name:

Port

Address:

Access:

Bit 7'"500

Bit

6"

Undefined

Bit

5"

OISWAIT (See Port 0ECH definition)

= ENEXTIO (Sec Port

Bit 4

3"

Bil

Bit 2

Bit 1..CASMOTORON (See

Bit 0 ..

ENALTSET (See Port

'"

MODSEL (See Port

1500

CAS

IN'

0FFH

AEAOQNLY

Baud Cassette bit

Baud

Cuseue

aECH

aeCH

ClECH

definitionI

POI1

(JECH definition)

bit

inler·

definition)

NOTE: Reading Port GFFH interrupts.

22

dears

the

1500

Baud Cassette

(

N

(,J

COMPONENT

FIGURE 4.

SIDE

CPU

PRINTED CIRCUIT BOARD - COMPONENT SIDE

w

o

~

en

'"

!-

::>

u

a:::

u

I

o

a:::

«

o

c:l

!-

::>

u

a:::

'0

w

!-

Z

a:::

Q..

::>

Q..

u

<:t

w

a::: ::>

e"

LL

24

CPU

MODULE PARTS LIST

SYMBOL

Cl C2

47pF, Ceramic Disc

O.lpF,

I

C22 O.l}.lF, SOV. C23

C24

cl

C45 C46 O.lIJ.F, SOV,

\

C53 O.l,uF. SOV, C54 C55 C56 C57 O.1/-lF. SOV, C58 C59 C60 33.uF, C61

4.7pF,

O.lIJF, SOV, Monol ith

4.7pF.

22pF,

O.lJ.1F.

O.l,uF. SOV. Monolithic

4700pF, Ceramic Disc

0.0047,uF, Ceramic Disc

0.1.uF,50V,

DESCRIPTION

SOV,

Monolithic

I

Monolithic

l6V,

Electrolytic, Radial

I

Monolithic

l6V,

Electrolytic,

Monolithic

I

Monolithic

l6V,

Electrolytic,

SOV.

Monolithic

MANUFACTURER'S

PART

CAPACITORS

830-0474

8384104

832-5471

ie

8384104

8381,04

Radial 832-5471

8384104

Radial 832·6221

8384104

8384104 8384104

830-2473

--------

832-6331 8384104

NUMBER

I

RADIO

PART

ACC1Q4QJAP

SHACK

NUMBER

ACC470QJCP

I

ACC1Q4QJAP

ACC4752DAP

ACC104QJAP

ACCJ4QJAPO.l,uF, SOV.

------

ACC104QJAP

-----------

ACC104QJAP

-----------

ACC336QDAP

ACC104QJAP

-----

j

C71

e72 e73 O.l.uF.

J

C79

C80 33pF. Ceramic Disc

C8' C82 O.l,uF. C83 o C84

C85 C86

O.l.uF,

4.7,uF, 16V,

O.l.uF,

O.l,uF.

.1,uF, O.OOl,uF, O.001,uF. Ceramic Disc

O.lJ.1F,

I

SOV,

Monolithic

Electrolytic,

50V.

Monolithic

I I I

50V.

Monolithic

50V.

Monolithic

50V.

Monol

SOV,

Monolithic

Ceramic Disc

SOV,

Monolithic

I I

C90 C91 C92 C93 C94 C95

O.1.uF.

SOV,

Monolithic 200pF. Ceramic Disc O.lf.1F,

SOV,

Monolithic 4700pF. Ceramic Disc O.lf.1F.

Ceramic Disc

O.Ol.uF. Ceramic Disc

ithic

Radial

I

8384104 832·5471

8384104

8384104 830·0334 8384104

8384104 8384104 830·2104 830·2104 8384104

I

8384104

830·1204 8384104 830·2474 8304104 830·3104

I

ACC104QJAP ACC4752DAP ACC104QJAP

ACC104QJAP

ACC330QJCr ACC104QJAP ACCI04QJAP ACC1Q4QJAP

ACC102QJCP ACC1020JCP ACC104QJAP

j

ACCI04QJAP

ACC2010JCP

ACC104QJAP

---------

ACC104QJAP

ACC103QJCP

25

SYMBOL

CPU

MODULE

DESCRIPTION PART NUMBER PART NUMBER

PARTS

LIST

(cont'd)

MANUFACTURER'S RADIO SHACK

O.lpF,

SOY,

C96

j j

CIOl O.lpF, C102 CI03 C'04

C105

CI06 CI07

Cl08 CI09 C1-10 Cl 11

I

CllS C1l6 Cl17 C118 OD22pF, Ceramic Disc C119 CI20 C121 Cl22 C123

C124 OD22pF, Ceramic Disc 830-3224

C12S C126 C127

C128

C129 CI30

I

C136 C137 C138 Not Used

I

C199 Not Used C200 C201 C202

I

C207 C208 C209 10p.F, 16V, Electrolytic, axial C210 C211 C212 C213 C214 C21S C216 e217

10pF, 10pF, Electrolytic, Radial

O.lpF,

O.lpF. O.OlpF, Ceramic Disc 27pF, 220pF,

100pF, l00pF,

0.022pF,

l00pF,

OD22pF. Ceramic Disc 830-3224

OD22pF, Ceramic Disc 830-3224

180pF, 220pF, 27pF, 220pF,

1

OOpF,

lOpF, 16V, Electrolytic, radial OD22p.F, Ceramic Disc

lOOpF,

lOpF,16V, Electrolytic, radial OD22p.F, Ceramic Disc

0.022pF,

220pF,

I

10p.F, 16V, Electrolytic, radial

10p.F. 16V, Electrolytic, axial 10pF, 16V, Electrolytic, radial

10p.F, 16V, Electrolytic, radial

lOpF. 16V, Electrolytic. axial

10pF,

TOp.F,

10pF, 16V, Electrolytic,

10J,tF,

10pF,

OpF, 16V, Electrolytic, radial

1

101.lF,

1OpF,

Monolithic 830-4104

I

SOV,

Monoithic 830-4104 Ac;CIQ40JAP

Electrolytic, Radial 832-6101

832~101

SOV,

Monolithic

SOV,

Monolithic 830-4104 ACC1Q40JAP

Ceramic Disc

SOY,

ZSP, Ceramic

SOV,

Ceramic Disc

SOV,

Ceramic Disc

I

Ceramic Disc

SOV.

Ceramic: Disc

Ceramic Disc Ceramic

Ceramic

Ceramic Disc

SOV.

SOV,

Ceramic Disc

Disc

Ceramic Disc

I

Ceramic Disc

Disc

I

16V, Electrolytic, radial l6V,

Electrolytic, radial

lIxial 16V. Electrolytic, radial 16V, Electrolytic,

16V. Electrolytic, axial l6V.

Electrolytic,

3)(ial

r~ial

8304104

83)·3104

83).Q274 830-1223 8Xl·1104 830·1104 830·3224

I

B:r:l-3224 8:r:l·l104

830-3224

830·1184 830·1223

830.0274 830·1223

830-1104 832·6101 ACC1060DAP 830·3224 830-1104 832-6101 8:xl-3224

I

830-3224 B3O·1223

-----

832·6101 ACC106QOAP 831-6101

832-6101 ACC1060DAP

I I

832-6101 831·6101

831-6101 832-6101 832·6101 ACCI0SQOAP 831-6101 832·6101 831-6101 832-6101 831-6101 832-6101 ACC100QDAP

ACC1040JAP

I

ACC10600AP ACC10600AP

ACCI040JAP

ACC1030JCP

-------

ACC1010JCP ACC1010JCP ACC10l0JCP

---------

-------

ACC101OJO'

--------

-------

ACC470QJCP

---------

--------

ACCOl

:IlQJCP

ACCI060DAP

------

-------~-

--------

---------

------

ACC1060DAP

--------

---------

ACCI060DAP

---------

ACC10000AP

---------

ACC1060DAP

--------

26

CPU

MODULE PARTS LIST (con,'d)

SYMBOL

J3

J4

J5 J6

J7

J8

JP1A

JP18

JP2A

JP28

v,

CRI CR2 CR3

DESCRIPTION

Righi Angle Header

4,pln Header Connector

G·pin Header Cartnector

20

position

20

position,

20

position.

DIP

Strip,

DIP

Strip,

DIP

Strip.8.position

DIP Strip. 8.position

10.1376

lN982

lN4148

Straight connector

straight 8-position 8-position

MHz

Connector

connector

CONNECTORS

CRYSTAL

DIODES

MANUFACTURER'S

PART

NUMBER

851·9091 851·9079 851·9103

851-9086

851-9101

851·9101 851·9105 851·9105 851·9105 851·9105

840-9007

81S.Q982

815-0982

81S.Q148

AAOIOSHACK

PART

NUMBER

AJ6978 AJ6997

AJ6980

AJ6848

AJ6979

AJeg'9

AJ6981

AJ6981 AJ6981

AJ6981

ADX1103

ADX·l103

AOX-1152

I

CR.

Ul U2 U3 U4 U5 U6 U7

I I

U14 U15 U16

U17

U18 Ul. U20 U21 U22 U23

U24

I

IN4t48

INTEGRATED

74LS74, Dual

74LS04,

74L$74, Dual 74LS157. Quad 1-of-2 Data Seleeter 802·0157 AMX3563 74LS93, Binary 74L$10, Tripe 3·jnput

416,RAM

416, RAM

74L$132,Quad 2-input NAND 74LSOO. 74LS74. Dual

74LSOO.Quad 2·input 74LS08. Quad 2-input 74LS393. 74LSll. 74LS246. S02.Q266 74LS221. Dual One·Shot Schmitt Trigger 74LS157. Quad 2-linetol-1ine Data Seleeter{Multiplexer

"0"

Flip-Flop

Hex Inverter

"0"

Flip-Flop 802·0074 AMX3558

{~16l

Quad

2·input

"0"

Flip·Flop 802.Q074

Triple 3·input

input

Counter 802.Q093

NAND

gate

NAND

gate

NAND

gate

AND

gate

AND

gale 802.0011

with

CIRCUITS

I

81S.()148

802.(lO74

802.QOO4

802.Q010 804·1016

I

804·1016 802·0132 AMX3561

S02.Q000

802·0000

802.()QOS S02.Q393

I

AOX·1152

AMX3558

AMX3552

AMX3560 AMX3898 AXX3021

I

AXX3021

All.1X3550 AMX3558 AMX3550 AMX3698 AMX3706 AMX3554

---------

802.Q221

802.Q157

AMX3810

AMX3563

27

CPU

MOOULE PARTS LIST (cont'd)

SYMBOL

U25

U32 U33 U34

U35

U36 U37 U38

U39 U40

U41 U42

U43

I

U50 U51

U52

U53 U54

U55

US6

U57

usa

U59

U60

U6, U62

U63 U64 U65

U66

U67 U68 U69

U70

U71

416,

DESCRIPTION

RAM

MANUFACTURER'S

PART

NUMBER

804·1016

RADIO

PART

SHACK

NUMBER

AXX3021

I

416.

RAM

74LS04,

74LS05,

Open

74lS05, Open Collecter

MCM68A316E.

74LSOO, Quad 74LS266,

with Open Collectcr

74lSOB, Quad 2·input AND gate 802-0008 AMX3698

74lS138,

74LSl38,

7

4lS157.

Data 5electer/Multiplexer

416,

Hex Inverter

Colleeter

Hex Inverter with 802-0005

Quad Exclusive NOR gate 802.Q266

Decoder/De-multiplexer

Oecoder/De-multiplexer

Quad 2·line

RAM

with

Character Generator

2·input

NAND

Outputs

to

l-1inc

gate

I

416,

RAM

MC140508 74LS166,8-bit

Shift Register 74LS244, Line Driver 74LS153, Dual4-line

Data Selecter/Multiplexer 74LS175, Hex/Quad

with

Clear 74LS393 74LS02, 74LS139, Decoder/De-multiplexer

74LS32, Quad 2-input OR gate

74LS145, BCD/Decimal

Decoder/Driller 74LS175, Hex/Quad 74LS90, Decade,

Binary Counter

8126,

Bus

8T26,

Bus

MC14050B

74LS240, Octal Buffer

74LS245 74LS273

74LS157, Quad

Data Selector/Multiplexer 74LS157, Quad

Data Selector/Multiplexer 74LS157, Quad 2-lineto1-line 801.Q157

Data Selector/Multiplexer

Parallelln/Sarial

to

l-line

"0"

Quad

2-input NOR gate 802-0002 AMX3551

"0"

(+12), 802-0090

Transceiver 806.{)026 Transceiver

2-lineto1-I1no

2-lineto1-line 802.Q157

Out

Flip-Flop

804·1016

802.()OO4 a02.QOO5

8044316

802.()OOO

802.Q138

B02.()138

B02.Q157

804·1016

j

804-1016

803..Q050 802{1166

802..Q244 802-1053

802..Q175

802-0393

802..Q139 802-0032 AMX3557

802..Q145

802..Q175

806-0026 B03..Q050

802.{)24O AMX4225

802.Q245

802.Q273

802.Q157

AXX3021

AMX3552

AMX3553

AXX304Q

AMX3550 AMX4660

AMX4583

AMX4583 AMX3563

AXX3021

I

AXX3021 AMX4584

AMX3564

AMX3864 AMX3562

AMX3566

AMX3706

AMX3800

AMX4659

AMX3566

AMX3804

AMX4261 AMX4261 AMX4584

AMX4470 AMX4227 AMX3563

AMX3563

28

CPU

MODULE

PARTS

LIST

(cont'd)

SYMBOL

U72 U73

U74

U75

74LSJO, 74LS27, Triple 3-input NOR

74LSl4.

74LS08,

DESCRIPTION

8~nput

Hex Inverter Quad 2·input 8020004 AMX3552

Quac..l

NAND

2-iu1Al1

U7. 14L$361.Tn·State Hex Buffer U77 U78

U79

ueo

U81 U82 U83

U84

U85 U86

U87 U88

U89 U90 U91

U92 U93

U94 U95 U9. U97

U98 U99

Ul00 74LS174,

U101 Ul02 U103

U104

U105 ROM U106 U107 U108

Z-BO.CPU 74LS74. Dual PositiVI! MC1741, Operational MC1458 MCM2114. RAM MCM2114, RAM 804{)OO4

74LS14. Dual

Positive

74LS367. Tri·State Hex Buffer 802'()361

14lS74. Positive 74LS32.

14lS04,

14L$38,

with

Open

14LS32, 74LS245

74LS244, Line Driver

Not

Used

/4LS273, Octal

74L$244, Line Driver

LM33!

MC75452 805.{)452 AMX3573 74LS174, Hex

74L$244, Line Driver

74LS245 74LS244, Lina Driver 74LS367, Tri-State Hex Buffer

ROM

A, MCM364 B,

ROMC,MCM68A 74LS32,

74L510, Triple 3·input

"D"

Edge

Triggered

"0"

Edge

Triggered

Dual

"0"

Edge

Triggered

Quad

2-input OR

Hex Inverter

Quad

2·ioput

Collector

Quad

2-inpvt OR

"0"

Quad

Hex

Quad

MCM332

Quad

2~nput

Flip·Flop

Amplifier

Flip·Flop

Outpuu

Flip-Flop

"0"

"D"

MANUFACTURER'S

PART NUMBER

gate

AND gate

8020030 8020027

8020008 802<1361

804

8020074

805.0741 AMX4258

805<>458

8040004

8020014

gate

802-0032 AMX3557

802000'

NAND

gate

Buffer

802-0038 AMX4328

8020032

802.()245

802.()244

-------

802'()273 AMX4227

802.()244 AMX3864

805.()339

Flip-Flop 802.{)

802{)244

Flip·Flop 802{)174

802.{)245

802.Q244

802.()367 804·1364

80HJ332

804·03168 AMX4642

OR

gate

NAND

gate

802-0032 AMX3557 B02.()010

7080

174

RADIO SHACK

PART NUMBER

AMX3556 AMX4668

AMX3698 AMX3567

AMX3586 AMX3558

AMX4661

AXX3038 AXX3038 AMX3558

AMX3561 AMX3558

AMX3552

AMX3557 AMX4470 AMX3864 AMX3864

------

AMX4200

AMX3565 AMX3864 AMX3565 AMX447Q AMX3864 AMX3567

AXX3039 AXX3037

AMX3898

Rl R2 R3

R' R5

R.

R7 R8

910

ohm.

4.7K,

%W,

4.7K,

%W,

4.7K, 'l.W. 910 ohm,

4.7K,

%W,

lOOK,

%W,

4.7K,

%W,

5%,

Carbon'film

5%,

Caroon

5%.

Carbon Film

%W,

5%,

5%,Carbon

5%,

Carbon

5%.

Carbon

Carbon Film

Film

Carbon

Film

RESISTORS

820-7191 820-7247 820-7247 820-7247 820-7191

820·7247

820-7410

820-7247

AN0192EEC

AN0247EEC AN0247EEC AN0247EEC AN0192EEC AN0247EEC AN0371EEC AN0247EEC

29

CPU

MODULE PARTS LIST (cont'd)

SYMBOL DESCRIPTION

4.7K,

%W,

R. RIO R11

R12 R'3

R14

R15 750 ohm,

Rl.

R17

R18 22 ohm,

Rl.

R20

R21 7.5K,

R22 R23 7.5K, R24 R25 4.7K, R2.

R27

R28

R29 R30

R31 R32 R33 R34 R35 R36 R37 R38

R39

R40

R41

R42

R43

R44

R45 R4.

R47 R48

R4.

R50

R51 R52

R53

R54 R55

R5. R57

R58

R5.

2.7K,

470

4.7K,

4.7K, 10K.

4.7K,

1.2K,

4.7K, 220K,

4.7K.

220 ohm,

82K,

12K,

4.7K, 75K, 39K, lOOK. 220 ohm, lOOK, 100K, 100K,

lOOK,

4.7K,

4.7K, 150 ohm, 150 ohm,

4.7K, X:W,S%,Cflrbon Film

20K,

4.7K,

4.7K, 10K, 10K, %W,5%,Carbon Film

51K,Y.w,

10K,

4.7K, 620K, 10K,

82K, 6BK. 56K, 56K,

15M. 1K, 15K,

5%, Carboo Film 820·7247 AN0247EEC

%W,

5%, Carbon Film 820-7227

ohm,

%W,

5%, Carbon Film

%W,

5%, Carbon Film 820·7247 AN0247EEC

%oW,

5%,

Carbon Film 820·7247 AN0247EEC

YOW.

5%, Carbon Film

%W,

5%. Carbon Film

%W,

5%,

Carbon Film 820·7247 AN0247EEC

%W,

5%, Cllrbon Film 820·7212 ANOl99EEC

%W,

5%, Carbon Film 820·7022 ANOO78EEC

%oW,

5%,

Carbon Film 820·7247

%W,

5%, Carboo Film 820·7422

Y.,W.

5%. Carbon Film 820-7275

%oW,

5%,

Carbon Film

%W

6%,

Carbon Film

v..W,

5%,

Carbon Film 820-7122

%W,

5%, Carbon Film 820-7247

%W,

5%,

Carbon Film 820-7382

%W,

5%, Carbon Film 820-7212

%W,

5%,

Carbon Film

%W,

5%,

Carbon Film

%W.

5%,

Carbon Film

'-'.W,

5%, Carbon

%W,

5%. Carbon Film

Y.W,

5%, Carbon Film

X:W.

5%, Carbon Film

%W,

5%, Carbon Film

%W,

5'-', Carbon Film

%W,

5%, Carbon Film

%oW,

5%, Carbon %W, %W,

%W,

5%, Carbon Film

%W,

5%, Carbon Film

%W,

5%,

%W,

5%, Carbon Film

%W,

5%. Carbon Film

YOW.

5%.

YOW,

5%,

YOW,

5%,

%W,

5%.

%W,

5%.

%W,

5%,

%W,

5%,

%W,

5%. Carbon Film

%w,

5%,

Carbon Film

Y.W,

5%,

5%. Carbon Film 5%, Carbon Film

Carbofl Film

Carbon Film

Cllrbon Film

Carbon Film Carbon Film carbon Film

Carbon Film

Film

Carbon Film

Film

MANUFACTURER'S RADIO SHACK

PART NUMBER PART NUMBER

AN0224EEC

------

820-7310 820·7175

-------

AN0281EEC

---------

AN0247EEC AN0396EEC

-------

820·7247 AN0247EEC 820·7275

---------

ANQ149EEC AN0247EEC

---------

AN0199EEC 820·7247 AN0247EEC 820·7375

820,7339 820·7410 820·7122 820·7410

820-7410 820·7410 820·7410 820·7247

820·7247 820·7247 820·7115 820-7115 820·7247 820·7320 820·7247 820·7247 820·7310 820-7310 820·7351 820-7310

820·7247 820·7462 820·7310 820·7282 820·7268 820-7356 820·7356 820·7515 820·7210 820·7315

-------

AN0330EEC

AN0371EEC

AN0149EEC

AN0371EEC

AN0247EEC

AN0142EEC

AN0247EEC

---------

AN0247EEC

AN0281EEC AN0281EEC

AN0344EEC

AN0281EEC

AN0247EEC

---------

AN0281 EEe AN027.1EEC

--------

-------

---------

AN0196EEC AN0297EEC

30

CPU

MODULE PARTS LIST (cont'd)

SYMBOL

R60 R61 R62 220 ohm, '4w, 5%, Carbon R63 R64 R65 47 ohm , '4W, 5%, Carbon R66 R67 R68 R69 220 RPl RP2 RP3 RP4 RP5 RP6

Kl

Q1

VRl

150 ohm, 10K,

4.7K, 22K,

30 Fairite Not

27

ohm, Resistor Network

27

ohm, Resistor

27

ohm,

4.7K,

1.5K, Resistor 10K, Resistor Network

1 FormA,5VDC

2N3906 MC7905C

Cable,8-position,3.75" Cable,8-position,8.5"

Jumper

Socket, 40-pin (1)

Socket,24-pin (4)

Socket,20-pin Socket, 18-pin Socket, 16·pin

DESCRIPTION

'4w,

5%, Carbon Film

'4W, 5%, Carbon

'4w,

5%,

Carbon

'4W,

5%,

Carbon Film

ohm,

'4W, 5%, Carbon

Bead

Used

ohm,

'4W, 5%, Carbon Film 820-7122

Network

Resistor Network

Resistor

Plugs

Network Network

(10)

(3) (2) (24)

Film

(1)

Film

RELAY

TRANSISTORS

M

ISCELLANOUS

MANUFACTURER'S

PART

NUMBER

820-7115 820-7310 820-7122 820-7247 820-7322

820-7047

820-7030

841-9014

------

829-0009 829-0009 829-0009 829-3247 829-0015 829-0010

842-9102

810-0906 805-1905

845-9008 845·9108 851-9098 850-9002

850-9001

850-9009 850-9006 850-9003

RADIO

PART

SHACK

NUMBER

AN0142EEC AN0281 AN0149EEC AN0247EEC

--------

AN0099EEC

--------

AR8130

AMX3584 AMX4260

--------

AW2632

--------

AJ6580

AJ6579 AJ6760 AJ6701 AJ6581

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32

FIGURE

58.

MODEL

III

CPU

SCHEMATIC

DIAGRAM

- PROCESSOR SECTION

BIT

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6

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MODEL

III

CPU

SCHEMATIC

DIAGRAM

- RS-232-C

INTERFACE

AND

FDC

INTERFACE

CONNECTORS

SECTION IV

FLOPPY

DISK

INTERFACE

41

TECHNICAL

DESCRIPTION

The TA5-80 Modal optional board which if incorporated inch

floppy disk controller. The Floppy supports both This

flaturl, the

transfer resuhs Model enabled

along with a special software packll!Je,

of

in

an upgrade

III

owner. Write precompensation can be software

or

disabled beginningatany tern software enables write precompensation for greater than twentY-one. The amount sationiscontinously variable from I)nsectorn()(e than

III

Floppy Disk Interface Boardisan

provides a standard five

Disk

Interface Board

single and double density encoding schemes.

al1ow~

Model

Idisk filestothe

to

doubl~

Model

III

synem.

density encoding for

track,

although

the

all

of

write precompen·

This

the

sys·

tracks

500 nsec. The write preoompensationisfactory adjustedto200 nsec. The locked loop oscillator which ity. One (two internal drives and two external). All accomplished by CPU ation, data transfers are synchronizedtothe a walt from the FDC chip. by generating a non-rnaskable interrupt from request insures that error conditions will not hang

the

CONTROL

data

dock. recovery logic iflCOrporates a phase·

achieves stateofthe

to

four drives may be controlledbythe

data

requests.Indouble density

to

the

CPU

and clearing the waitbya data request

The end

of

the

data

transferisindicated

data

transfers are

CPU

art

by forcing

the

outputofthe FDC chip. A hilrdware watchdog timet:

the

wait line

CPU

for a period long enough to destroy

AND

DATA BUFFERING

RAM

reliabl-

interface

oper·

interrupt

contents.

Refer to the Schematic Diagram.

The

Floppy Disk Controller Boardisan

device which utilizes

F4H.

The

decoding logicisimplementedonthe CPU board.

(See

the

Decoding Logic sectionofthe

of

the

Floppy

buffer which

isolates and buffers the required control signals.

Table 1 summarizes

Floppy Controller Board.

is

Board to

a bi-direc1ional.

and from

the

ports

E4H,

FOH,

Disk

Controller Boardisa non.inverting octal

the

port

and bit allocation for the

U2ofthe Floppy Disk Controller

Bobit

transceivef used to buffer

Floppy Controllef Board. data transferiscontrolled by the combinationofcontrol nals DISKIN- and AONMIMASKREG-.Ifeither active (logic lowl. U2isenabled10drive board data bus.Ifboth is

enabled to receive

signals are inactive (logic high). U2

data

from the

CPU

110

port mapped

F1H, F2H, F3H, and

CPU

discussion.) U4

data

The

direction

sig-

sigrlill

data

onto

the

CPU

data bus.

NONMA5KABLE INTERRUPT LOGIC

A dual 07 REG-. The

generate

"0"

"ip-flop (US)isusedtolatch

on

the

rising edgeofthe control signal

outputsofUS

a non-maskable interrupt to

control

data

bits06and

WRNM1MA5-

the

conditions which will

the

CPU. The

NMI

interrupt oonditions are programmed by doing an OUT in·

struction to

pon

E4H

with

the

appropriate bits set.Ifdata

of

to

bit7is request.

FOC

ated

Motor Time

E4H enables troller Boardtodetermine interrupt. Data bit 7 indicates request (0 = Motor Time

status trol signal ADNMIMA$KREGthis

DRIVE SELECT LATCH

$electing a drive prior to a disk

set,anNMI

If

data

<He

disabled.Ifdata bit 6isset, an

by Motor Time

Oul

the

will be generated byanFDC interrupt

bit 7isreset, interrupt

Out.Ifdata

are disabled. AnINinstruction from

CPU

to question

the

true,

1 ,. falsel. Data bit 6 indicates

Out

(0"

true,

1 • false). Data bil 5 indicates the

of

the

front panel reset(0.,

SUItus

onto

the

CPU data bus.

AND

rCQuests

NMI

from the

wiltbegener-

bit 6isreset, interrupts on

the

Floppy Disk Con-

wurceofthe non-maskable

the

statusofFDC interrupt

the

status

true,

1 = false). The con-

when active (logic 0), gates

MOTOR ON LOGIC

I/O

operationisaccom-

port

of

plished by doing an OUT instruction to port F4H with the proper bit set. The following tion

of

the

Drive Select Latch.

DATA BIT

00

01

02 03

04

05

table describes the bit alloca-

FUNCTION

Selects Drive 0 when set Selects Drive 1whcn

set • Selects Drive 2 when set Selects Drive 3 when set Side 0 selected Side 1

selectedifset

Preoom. engaged

Write

when reset,

.....

hen sel,

disabledifreset

06

Generate waitsifset, no weits if reset

MFM

07

-Only

oneofthese bitsshouldbeset per

hex

"D"

A

is

select

flip·flop (U6) latches

and

FM-!MFM bitsonthe

sigtlal IDRVSEL-.A dual

latch

the

Wail

Enable and Precompensation enable bits

Selects

FM

modeifreset

"0"

the rising edgeofIDAVSEL -. also triggers a one·shot (1/2ofU1S) which

Ontothe disk drives. The durationofthe

is

approximately

twO

seconds.

modeifset,

output.

the

drive select biU, side

rising edgeofthe

flip-flop

The

rising edgeofJDAVSEL·

(U1B)isused

producese

MotorOnsignal

The

spindle motors arc not

control

to

on

Motor

designed for continoU$operation, therefore the inactive state of

the

MotorOnsignal

which

dl!~lects

The

MotorOnone-sttotisretriggerable by simply exeQJting

an

OUT instruction to

is

used

to

clear

the

Drive Select Latch,

any drives which were previously selected.

the

Drive Select

latch.

43

WAIT STATE GENERATION ANDWAITIMOUT

As

previously

initiatedbyan

of

Pin 5 invertedby1/6ofU1

it forces

the

wait $late as longasWAIT"islow. Once initiated,

wail

state

mentioned,

outputtothe

U18 willgohigh

andisroutedtothe

the

Z-aO

into a wilit state. The Z.sO will remain in

will remain until

a wait staletothe

Drive Select

after

tnis

lalch

operation.

CPU

oneoffour

conditions arc satis·

lOGIC

CPU can be with06set.

This signal

board where

the

fied. One halfofUIO(afille input NOR gate)isusedtoperform this function.

the

inputstothe

are

active (logic high).

go

will

latch. This

low. This

~!1"1l1,

pin 5) and set

causes WAIT"

INTRa,

the

outputistiedtotne

when

tnc

a"

to

go high and allows

stale_ U20 is a 12-bit binary dog timertoinsure long enoughtodestroy is

clockedbya lMHz signal and is enabledtocount

pinislow (U20 pin 11). A logic highonU20 pin

reset resets

the

output

counter

andisuser!

ouputs.

This watchdog timer logic will limit 1024,uscc. ellen if

or

reQuest

an interrupt request.

thc

CLOCK GENERATION

A 4MHz crystal oscillator

counter

generate

the board. The basic 4MHz oscillator is implemented with invertors (1/3ofU251 and a Quartz crystal U24 is usedtodivKMt a 2MHz 2 using

at

input

watchdog

output

the

at U24 pin6.This

remaining halfofU24toproduce

U24 pina.The 1

of

the

1793 FDC chip and

time

(U20).

ORa,

RESET, andWAITIMOUT

NOR gate. If

outputofthe

anyoneofthese inputs are

NOR gate (U10 pin 6)

clear inputofthe

low, will clear

output

(U1S pin 6). This

counter

thatiIwait

dynamic

U20 pin 15isthe

to

generate

FDC chip

RAM

theaoutput

the

Z-80toexit

which serves as a watch-

condition

will

wntents.

dillideby1024

the

signal WAITIMOUT.

the

duratiunofa wait

hils

to

generate a data

lOGIC

and

a divideby2

clock signals required

and

(Yl).

the

basic 4MHz clcx:kby2toproduce

output

is again divided

a lMHz

MHz

clockisusedtodrive

the

clock inputofthe

condition

the

not

persist

The

counter

when its

divideby4

by

the

One half

output

the

wait

(Ula

wait

FDC

two

by

clock

DISK BUSSELECTOR LOGIC

As mentioned pfllviously,

supportsupto

function

one

buses, drives.

J4isthe

andJlis

la quad 2

of

Inputs from

four

is

implementedbyusing

for

the

edge

tIM!

edge

to1data

the FDC chip. U22 pin 1isthe If

U22 pin 1islow.

wise the internal inputs are selected. This

(labeled Select latch_

EXTSEl"lisderived

If

Drive 2orDrive 3 is selected. U17 pin 1

the

Model

III

Floppy Disk

drives (two internal,

internal drives and

connector

used for

for

two

external). This

two

disk drive interlace

one

for

the

internal drives

the

external drives. U22

selector)isusedtoselect which set

disk drive buses are routed

control pin

the

external inputs arc selected,

for

the

\'I)

data

the

control

from

the

outputsofthe

BOilrd

external

1793

selector.

other·

signal

Drive

will

go

low indicating One halfofU10 (a five when anyofthe

is

NOR

gate

four

IUl0

pin 5)isinverted and is used as timing and ready signal any

drive is selected,

the

selected driveisassumedtobe ready.

READM'RITE DATA PULSE SHAPING

11

Two one--shots (112

insure

that

the

in

450nsec

dlSation.

DISK BUSOUTPUT

High

current

to

used

latch

the

schematic

two

buffers associated with each signal,

and

open

buffer

the

of

read

and

DRIVERS

collector drivers (U21. U9, and

the

output

FDC chiptothe

that

each

the internal drive bus and

ternal bus. No select logicisreQuire<!

to

nals since

the

drive select bits define which drive is active.

WRITE PRECOMPENSATION

lOGIC

The

Write Precompensation and Read Clock Recovery logic

is

of

comj:Kised

(lSS29l,

lSI

is an to

interface

of

Ul1

along with a few passive components. The W01691

device which minimizes

the

1793 FOC chiptoa disk drive. With

ofanexternal VCO, U14,

signal

for

the

1793, while providing an adjustment signal for

the

VCO,tokeep

the

from

drive. Write precompensation control signals are

also provided by

the

WD2143 (U13) clock generator. The Read Clock Recovery

of

tnc

section

ROD", WG.

PO",

PU, both

are low. enable high, a write circuits are

W01691 has five inputs: OOEN", VCO,

and

VFOe"/WF.Italso

and

RClK.

the

operation

disOOrcd

input$.

The Write Precompensation section designed

to

be used with

Write Precompensation

the

and

In

and

signal DOEN" when high indicates this condition.

double

density mode (DOEN"'"01,

lATE

are usedtoselect a phase input

leading edgeofWOIN. The STB line is latched high when

occurs, causing

this

the

that

an external driveisselected.

input

NOR gatel is usedtodetect

drives are selected.

for

the

1793

the

hBiidisaswmedtobe loaded and

The

outputofthis

the

head load

FOC chip. Therefore if

lOGIC

U15 and write

1/2ofU23) are used

data

PlJlses are approximately

Ull

signals from

the

Drive Select

floppy disk drives. Note from

output

the

sign;)1tothe

one

other

setisused for

for these

AND

CLOCK RECOVERY

driv8S has

setisused

output

(WD16911, U13 (WD2143) and

the

RCLK

elltemallogic

W01691

will derive

synchronous

with

the

required

read data

WDl691tointerface directly to

hu

three Outputs:

The

inputs VFOE"!WF and

WG

Clock Recovery logic. When

is in progress

regardlessofthe

the

is

not

W02143tostart

and

the

Clock Recovery

stateofany

of

the

WOl691 was

W02143

clock generator.

used in single density mode

the

signals EARLY

(01

- 04) on

its pulse generation.

the

RClK

when

WG

other

to

are

for ex· sig·

UI4

use

the

is

the

44

02isusedasthe write data pulse

LATE

-'=

OJ.

01isused for the early, and03is

late. The leading edge

tion

of

the next write data pulse. When TG43

= 1, precompemation

WOIN

line will appearonthe WOOUT line.

When VFOE""fwF ood

cuits are enabled. PO""

signals will become active.Ifthe ROo* has made its

transition

go from

in

the

a high impedence state to a logic one, requesting increaseinVCO transition at the end in

the

high impedence state while requesting a de(:reaseinthe ing

edge

of

RDD~

both

PU

and

PO""

of04resets the

is

disabled and any transitionsonthe

WG

are low,

When

the

RoO~

beginningofthe

frequency.Ifthe

of

the

VCO

occursinthe

will

remaininthe high impedence state, indicating that no adjustment quired.Bytying is

created which willbeforced low for a decreaseinVCO

PU

and

PO""

frequency and forced high for uency. To speed up rise times and stabilize the age, a resistordivider using R7, the tri-state results

levelatapproximately

in

a worst case voltage swingofplusorminus 1V,

on

nominal

(EARLY'"

used for the

STB

lineinanticipa·

'"0or

OOEN"

the

Clock Recovery cir·

line goes low,

RCLK window,

ROO~

RCLK window,PUwill

PD~

will

go to a logic zero,

thePUor

PU

line has made it

remain

frequency. When the lead·

centero!the RCLK window,

of

the veo frequency

is

together, an adjustment slynal

an

increaseinVCO

freq·

output

Rl0,

andR9is

lAV.

usedtoadjust

This adjustment

will

volt·

whichisacceptable for the frequency control inputofthe

veo (U141. This signal derived from

and

PO""

will

eventually correct the veo input

the

same frequency multipleasthe FDO" signal. The leading edgeofthe of

the RCLK window, an ideal condition for the

RDO~

signal will then

the

combinationofPU

occurinthe

to

exactly

exaet center

1793

inter-

nal recovery circuits.

an

reo

ADJUSTMENTS

Tne

Data

separator

AND

JUMPER OPTIONS

mustbeadjusted with

the

1793inan

idle condition (no command currentlyinoperation). Adjust

R7

potentiometer for a

R6

adjust

160fU1J.

potentiometer to yield a 2MHz square wave at

l.4V

levelonpin 2ofU14. Then

The Write Precompensation must be adjusted while executing a continous write command one. Adjust at pin 4 value

of

R5

potentiometertoyield 200nsec wide pulses

of

U11. This resultsina write precompensation

200nsec.

There are four jumper optionsonthe

Board. They are designated are referenced should

be

on

the SChematic Diagram. The jumpers

installed as described below.

on

a track

on

thePCBoard silkscreen and

greClter

Floppy

than twenty-

Disk

Controller

JUMPER CONNECTIONS

Ato

B

E

to G

Lto

M

H

to

J

FLOPPY DISK CONTROLLER CHIP

The tions

1793isan

of

a floppy disk formatter/controllerina single chip

MaS

LSI

device which performs the func·

implemetation. The 1793 isfunctionally'identicaltothe 1791 used

on

the ModelIIFOC Printer Interface Board, except that the the appendix section for more informationonthe

data busistrueasopposed to inverted. Refer

F01793.

to

The ModelIITechnical Reference Manual also contains a good presentation cussion on Write Precompensation. The following addresses are assignedtothe

of

the

1791 FOC chip as well as 8 dis·

internal registersofthe 1793

port

FOC chip.

PORT

#

FOH

FlH

F2H

F3H

FUNCTION

Command/Status Register Track Register sector

Register

O<lta

Register

45

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CPU

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FIGURE 1. FDC BOARD TO

CA13L£

CPU

BOARD SIGNAL DESCRIPTION

FLOPPY

CONTROLLER

:BCAl'lD

DISI<

INTERFACE

......

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FIGURE 2. FLOPPY DISK INTERFACEPCBOARD - COMPONENT SIDE

47

2

o

48

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FIGURE 2. FLOPPY

TANDY CORP. ©

'0

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3~...

DISK

INTERFACEPCBOARD-CIRCUIT

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SIDE

SYMBOL

FLOPPY DISK INTERFACEPCBOARD PARTS LIST

MANUFACTURER'S RADIO SHACK

DESCRIPTION

CAPACITORS

PART NUMBER

C' C2

C3 C4

C5 C6 C7 C8

C9 C10 Cll C12 C13 C14 C15 C16 C17

C'8 C19

J2

J3

O.l,uF, 50V, monolithic, radial O.l,uF, 50V, mOl1olithic, O,l,uF, 50V, monolithic, radial O.l,uF, 50V, monolithic, radial O.l,uF,

50V,

monolithic, radial

O,l,uF,

50V,

monolithic,

75pF,

50V,

ceramic disc

33jlF, 16V, electrolytic, radial

100pF,

50V,

ceramic disc 830·1104

O.l,uF,

50V,

monolithic,

0.47jlF,16V, O.1,uF, O.l,uF,

100pF, 50V, ceramic disc 830-1104 O.ljlF, 470pF, 50V, ceramic disc

10,uF,

10,uF,16V,eleetrolytiC,radial 832-6101 ACC1060DAP

0.01,uF,16V,ceramicdisc 830-3104

20

pos.

4 pin right angle

mylar 835-4471

50V,

monolilhic,

50V,

monolithic,

50V,

monolithic,

16V, electrolytic, radial 832-6101

right

angle

header

radiotl

radial

radial radial

radial 838-4104

CONNECTORS

838-4104 838-4104 8384104 838-4104 838-4104 838-4104

830.()754 839-6331

838-4104 ACC104QJAP

838-4104 ACC1040JAP 838-4104

830-1474 ACC471GJCP

851-9078 851·9079

ACC1040JAP ACC1040JAP ACC1040JAP ACC1040JAP ACC104QJAP ACC104QJAP

---------~

----------

ACC1010JCP

------~---

ACC104QJAP ACC101QJCP

ACC1Q4QJAP

ACC106QDAP

ACC103QJCP

----------

AJ69n

Y1

CR'

U1 U2 U3

U' U5

U6 U7 U8 U9

U10 Ull

U12 U13

4 MHz

MZ4682

7416. Hex Inverter/Buffer 74LS245 74LSOO, 74LS244, Octal Buffer 74LS74, Dual

74lS174, W01793 74lS38, 7416, Hex Inverter/Buffer 74lS260, W01691 MC140733, WD2143-{)1

NAND

Quad

NAND

Dual NOR

AND

U1. 74LS629. VCO U15

74lS123,

Mono Multivibrator

CRYSTAL

840·9010 AMX2804

DIODES

815{)682

INTEGRATED CIRCUITS

800-D016

802iJ245

gate

"D"

Flip·Flop

"0"

Flip-Flop

Buffer 802{)()38

gate

802.0000 802iJ244 AMX3864 802{)()74

802-Q174 AMX3565 850-9002 AXX3041

800.Q016

802.Q260 850·9009 AMX4471 803-0073 850·9006

802.Q629

802.Q123

ADX1518

-----

AMX3550

AMX3558

----------

-----~----

AMX4472 AMX4663

AMX3803

49

FLOPPY OISK INTERFACEPCBOARO

PARTS

LIST

SYMBOL

U16

U17

U

18 U19 U20 U21 U22 U23 U2.

U2'

Rl R2 R3

R'

R. R7

R8

R9 RlO Rll R12

R13

Rl' R15 Rl. R17 R18 R19 R20

MANUFACTURER'S

DESCRIPTION

INTEGRATED CIRCUITS (cont'd)

74LS367.

74LS02,

74lS74,

74lS368,

MC14040B,

7416,

74LS157, Quad Multiplexer 802-0157

74lS123,

74lS74,

74LS04,

2.2K,1/4W,5% 150ohm,

150

2.2K, 10K, Trim Pot 827-9310 AP7167

50K,

1

OOK,

10K,

47K, 47K,

10K, 1!4W, 10K,

47

ohm,

270K,1/4W,5%

150 ohm, 10 pin resistor network 10K, 1/4W,

910ohm, 910

2.2K, 1!4W,

22K,

Hex

Buffer

NAND gale

Dual

"0"

Flip-Flop

Hex Inverter/Buffer

Binary

Counter

Hex Inverter/Buffar 800-0016

Mono Multiplexer a02{)123

Dual

"0"

Flip-Flop

Hex Inverter

RESISTORS

1!4W,

5%

ohm,

6 pin resistor netWork 829.0012

1!4W,

5%

Trim Pot

Trim

Pot 827-9410

T!4W,

5%

1/4W,

5%

1/4W,

5% 5%

1/4W,

5%

1/4W,

5%

1/4W,

5%

ohm, 1!4W,

1!4W,

5%

PART

NUMBER

802.()367 AMX3567

8020002

802.()O74

B02.()368

803.Q04Q

802.0074

802.QOO4

820-7222 AN0216EEC

820-7115

820-7222 AN0216EEC

827-9350

820-7310 820-7347 AN0340EEC 820-7347 AN0340EEC 820-7310 AN0281EEC

820-7310

820-7047 820-7427

8290013

820-7310 820-7191 AN0192EEC 820-7191 AN0192EEC 820-7222 820-7322

RADIO

PART

SHACK

NUMBER

AMX3551 AMX3558

AMX3568

AMX4666

----------

AMX3563 AMX3803

AMX3558

AMX3552

AN0142EEC

ARX0241

AP7168

---------

AN0281

AN0281 AN0099EEC-

---------

ARX0242

AN0281EEC

AN0216EEC

----------

EEC

50

MISCELLANEOUS

Socket, 18 pin 850-9006 Socket, 20 pin 850·9009 Socket,40

FOe FOC Board,

pin 850-9002

Board, complete assembly

without

major chips

AJ6701 AJ6760

AJ6580

AXX0510

AXX0509

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NOTES:

1. All

capacitor all resistor values wise

2.

On

some

resistor resistor.

values

stated.

boards,R5may

and

R21 may

areinmicro-farads

areinohms

unless

appear

as a

other-

as a 1K

750

ohm

and

FIGURE

3 MODEL III Fl..OPPY

DISK

INT~RFA

I;

H~MATIG

51

SECTION V

RS-232C

CIRCUIT BOARD

53

RS-232C TECHNICAL DESCRIPTION

The RS-232C supports asynchronous serial transmissions and COflforms

to

the

EIA RS-232C standards at

interface Asyndlrooous of serial

For per-forms these functions, refer sheets clock rates

Baud rate generator(BR194111. This circuit

5.0688

programmed information received from the two 50 complete list.

TRANSMIT

NIBBLE LOADED BAUD RATE

(Pli.

con'o'llrting

data

stream including

a more detailed descriptionofhow

and

application notes.

that

MHz supplied

data

bus and divides

clocks.

Baudto19200 Baud. See

The

BRG PROGRAMMING TABLE

OR

RECEIVE

option

the

board for

The heartofthe

Receivertrransmittef.Itperforms

parallel

the

TRl602

by

rates available

the

Model

III

the

input·

boardisthe

byte

date from

start,

stop,

to

The

needs are suppliedbythe

the

CPU board and

the

bolsic

from

the

l6X

the

and

this

the

TRl602

transmit and reoeive

the

clock ratetoprovide

the

BRG go from

BRG table for tlte

CLOCK FREQUENCY

paritY bits.

computer

output

TRl602

the

CPUtoa

LSI

circuit

data

takes

CPU

over

job

the the

SUPPa

SETCOM

ATED

BY

GH

lH

2H

3H 4H 5H 6H

7H 6H 9H AH BH CH

OH

EH

FH

50 0.8 kHz 75

110 1.76 kHz

1345

150

300 600

1200 19.2 kHz

1600

2Q00

2400

3600 4800 7200

9600

19,200

1.2 kHz

2.1523kHz

2.4 kHz

4.8 kHz

9.6

kHz.

28.8 kHz

32.081 kHz

38.4 kHz

57.6

kHz

76.8

kl-lz

115.2 kHz

113.6

316.8

kHz

YO'

,

..

,

..

YO' YO'

,

..

,

..

,

..

,

..

,

..

,

..

,

..

,

..

,

..

YO' YO'

55

Thc RS-232C boardisa port mapped device and used

areEBto

on both

PORT

E8

EA

E9

input and

EB.

output.

INI

UT

'

Modem

UART status

status

Not Usad

followingisa descriptionofeach port

OUTPUT

Master

Reset, enables

UART control registor

1000

UART control register load and modem control

Baud rate reyister load

enable bit

the

ports

The following listisa pinout descriptionofthe DB-25

nector

(Pl).

PIN#

1

2

3

4

5 6

7

8

20

22

PGND (Protective Ground)

TD

(Transmit Data)

RD

(Receive Data)

RTS (Request

ers '(Clear

DSR (Data Set Ready) SGND (Signal Ground) CD

(Carrier Detect)

DTR (Data Terminal Ready)

RI

(Ring Indicate)

SIGNAL

To

Send)

con·

ES

Interrupts are supported

the Interrupt mask register

lUg) which allows has occurred. Interrupts can be generatedonreceiver register full, transmitter register

errors - parity, framing.

urnUIllofCPU UART. The interrupt interrupt status register Port description their

The Model the Model I RS-232 Interrupts are supported, there are no figuring versing the function DCtoDC provided by the internal power supply. Other differences include three additional interface the BRG. face provided that the software does not configure problem by directly programming the desired configuration of

the disk operating system to configure TRS·aO RS·232C Interface hardware manual has a good discussion examples (Catalog Number 26·1145).

Receiver

register

bit

positions.

the

converter b not required since +12V and -12V are

All

is

compataule with the Model

the

of

the AS·232C standard and specific programming

Holding

on

the

CPUtosee which kindofinterrupt

or

overheadintransferring datatoor

ma~

registerisportE0(write) and the

is

port E0 (rcild). Refertothe

fOI"

a full breakdownofall interrupts and

III

RS·232C boardisfunctionally identical

bOClrd

with the following exceptions:

intcrface, thereisno COMn-ERM switch for re-

of

pins 2 and 3onthe

Model I software written

interface. The programmer can get around this

or

Transmitter Holding register

the

RS-232C

(Ul0)

empty,

data overun. This allowsilmin-

outputs

II

the

by using

option

and the Status register

and

S€nse

switches for

and no crystal for

forthe

I R5-232C option board,

use

the

sense switches

BRG

the

SETCDM command

the

ooijrd by

data

anyoneofthe

from the

10

con·

D8·25,

and UART for

and

the

RS·232 inter·

interface. The

to

56

PORT

PORT E8H OUTPUT: MASTER RESET

INPUT: MODEM STATUS REGISTER

An

outputtothis

load enable bit.

port

(and

data),

The

following table details

performs a master resettothe

AND

BIT

ASSIGNMENTS

UART

the

bit definitions for an input from port

and

enables

the

control register

EBH.

DATA BIT

07

06

OS

D4

03

02

01

00

PORT E9H

OUTPUT: BAUD RATE LOAD

INPUT: NOT USED

An

outputtothis

and transmit Baud rate

outputtothis

mit

Baud rate.

PORT EAH OUTPUT: UART AND MODEM CONTROL

INPUT: UART STATUS

port

loads

the

as

outlined in

determines

Clear Data Set Ready, Pin 6 Carrier Detect. Pin 8

Ring Indicator, Pin2208-25 Not Used Not Used Not Used

Receiver

Baud rate

the

generator

the

receiver Baud

FUNCTION

To

Send, Pin 5

Input.

BRG Programming Table. The low

rate.

08·25

08-25

UART Pin20oB-25

with

a code which correspondstothe

while

the

high

order

desired receive

order

nibbleofthe

nibble determines tne trans-

data

An

outputtothis

~

11.

E8H

(02

UART Control register. The tables below summarize

enabled and disabled.

The UART Control registerisfive bits

.

00).

PORT EAH OUTPUT

port

loads

the

Three morc modem

DATA BIT

07

06

OS

D'

03

02

01

00

UART Control register if

mnlrol

BlTSWITH UART CONTROL REGISTER ENABLED

bits were addedbyallowing softwaretoenableordisable

Even Parity Enable. 1-=even. Q""odd Word Length Select 1 Word Length Stop'

Bit Select. 1 =

Parity Inhibit, 1 - disable parity

IJ

'"

Break

Data Terminal Ready, Pin

Request To Send, Pin 4 OB-25

disable

wid!'!

the

Select 2

transmit

the

enable bit for this functionisset (01 port

(07

.

03)

leaving three bits for modem control

bit allocations

FUNCTION

two

stop

data

20

with

the

bits. G -

Icontinous space}

08-25

one

UART Control register

stop

bit

the

57

PORT

EAH

OUTPUT BITS

WITH

UAAT CONTROL REGISTER DISABLED

DATA

BIT

07

06

OS

04

03 02

01

""

OATA81TS

07

06

OS

04

03 02

01

OIl

FUNCTION

Not Used Not Used secondary unassigned, Pin 18 Secondary Transmit Data, Secondary Request To Send, Break"=di$3b1e Data Terminal Ready, Pin20OB·25 ReQUest

PORT

Data Received, Transmitter Holding register

Overrun error,

Framing error,

Parity error, Not

Not Used Not Used

To Send, Pin 4 OB-25

EAH

INPUT BITS

Used

Tran!ifTlit

1 • condition true

1"

condition true

1"

condition

1.

condition true

Pin1408-25

Data (continous space)

FUNCTION

08-25

Pin1908·25

empty,

true

,.

condition true

PORT E8H OUTPUT: TRANSMITTER HOLDING REGISTER

INPUT: RECEIVER HOLDING REGISTER

An output

as

soon8Sthe until last word

the data

to

this port loads the UART Transmitter Holding register with a wordtobe transmitted,

last word loadedinthe

the

Transmitter Holding register

received from the UART received data holding register_This register should

received bit

(port

EAH)istrue.

58

holding registeristransmitted. This register should neverbeloaded

empty

bit (port EAH)istrue.

An input from this

port

not

be read until

reads the

HE.

-Z~2-C

.D¢

DI

D2

-/2 V

D3

r4

bezl5

I'%

-5v

liMb

RS2320UT-JI'

P.S232

D5

.DG

D7

IN

~

tlC207

SIG

CLOCKI2.

SPARE

RESET-lt

SPARE

INTJf

Art>

AI

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Git

I

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INTERFACE

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RESET-it

WHINT

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SPAFIE

INT""

MASK

"R((3*

\ /

\'

1'IS-232-

INTEP.FACE

C

BOARD

FIGURE1.RS·232 BOARD TO

~~

CABLE

CPU

BOARD SIGNAL DESCRIPTION

\ /

CPU

\/--

BOARD

59

60

FIGURE

2. RS-232CPCBOARD

- COMPONENT SIDE

o

1111111

11I1I1I1111I

o

a

i

o

I

"-

11

o

&"-..-

•

...

o

•

~---

..

--

-

•

FIGURE2.RS·232CPCBOARD-CIRCUIT

SiDE

61

RS·232CPCBOARD

PARTS LIST

SYMBOL DESCRIPTION

Cl C2

C3

C4

CS C6 C7

C8

C9

PI

P2

P3

Ul U2 U3

lOJlF, 16V, radial (optional)

10pF,

16V,

radial (optional)

O.lpf.

SOV,

monolithic,

O.lp.F,

SOV.

mOOlolithic, radial

O,lJJ.F,

50V,

monolithic,

O.lJJ.F,

50V,

monolithic, radial

0.1,l.1F,

50V,

monolithic, radial 10,l.lF,16V,rCldial 10,l.lF,16V,radial

OB-25 Connector

20

pos,

right angle

4

pos.

right

angle

BRl941·L,

TRl602B,

74LS244,~aIB~

Dual

UART

Baud

C

U. 74L$367. Hex Buffer US U6

U7 U8

U. Ul0 74LS174,Quad Ull MC1489, U12 U13

Ul'

U15

U16 MC148B,

74LS367, Hex Buffer 74LS174,Quad 7404, Hex Inverter 74LS139, Dual Decoder

74LS368. Hex Buffer

MCI488. 74

LS27

, NOR 74LS3B, MC1489,

Quad Quad

NAND

Quad Quad

"0"

Flip-Flop

"0"

Flip·Flop Line Driver Line Driver

gate

8uffer Line Driver Line Driller

CAPACITORS

radial

CONNECTORS

INTEGRATED CIRCUITS

MANUFACTURER'S

PART NUMBER PART NUMBER

832~101

8384104 8384104

8384104 8384104 838-4104 ACC104QJAP

832~101

A32-6101

851-9030

851-9078 851·9079

804·6941

804-5602

802.0244 AMX3864

802.0367 AMX3567

802.{)367

802.0174

-----

802.{)139

802.Q368

802.Q174 AMX3565

805.Q189

805.Q188

802-0027

802.o03B AMX4328

805.0189

805.0188 AMX3867

RADIO SHACK

ACC106QOAP

ACC1060DAP ACC104QJAP ACC104QJAP ACC104QJAP ACC104QJAP

ACC106QDAP ACC1060DAP

-----

-------

AJ6977

AMX3921 AMX3B65

AMX3567 AMX3565 AMX3655 AMX3800 AMX3568

AMX3868 AMX3867

---------

AMX3868

62

R1

R2

R3

R'

4.7K, 1/4W,

4.7K, 1/4W,5%(optionaH 62K,

4.7K,

Cable, Socket,18pin Socket, 40 pin

5%

1/4W,6%(optional! 1/4W,

5%

20

pes..4.5",

flat 845·9020

RESISTORS

MISCELLANEOUS

820-7247 820·7247

---

820-7247

850·9006 850-9002 AJ6580

AN0247EEC AN0247EEC

-------

AN0247EEC

AW2631

AJ6701

SECTION

VI

POWER SUPPLY

65

FUNCTIONAL SPECIFICATIONS

The

power

supply

switching power supply, The

directlytothe

through a locking 2.pin

1

Pin 2

Outputs are taken from (SK-2, SK-3,and

Pin 1 ·12V Pin 2 +12V Pin 3 Common Pin 4 +5V

In

theory,

and chops it at transformedtothe

low

voltage regulation and

The power supply module can withstand maximum

the

voltage isolated DC. Feedback loops are provided for

ratings:

Vin (AC continuousl -95to Short Circuit,

tor

the

TRs.80

printedcirwitboardismounted

case.

Une

inputtothe

PCB

wetet

line

- Neutral

line-Live

locking 4-pin

SK-4).

power supply rectifies

20

kHz. The chopped

required

any

output

overcUrfent

output

- indefinite

protection.

135VAC@60Hz

Model

header

voltages and rectified

IIIisa40wan,

power supplyismade

(SK-ll.

PCB

socket headers

the

AC

DC

voltageisthen

the

linetoDC

to

following

2.

0,

140V Vilriilble Transformer (Variac) -

U5ed

to

vary input votUgiI. Recommend

1.4 KVA rating minimum.

3.

Voltmeter Neededtomeasure

to

200

ages

4.

Oscilloscope-

Need

5.

Load Board with Connectors See Table 1 for valuesofloads required. The the

table for safe Load Poweristhe minimum power

ratings for

Ohmmeter

6.

SET·UP PROCEDURE

Set-tJP as input

voltage and -the

Which

is output The

ctleek

points within power supply

with

DVM

the

VAC. Re<:ommetld

X10

and

the

U"oowninFigure1.You will wanttomonitor

the+5output,

the

monitoring

other

ac

volt

..

ges

to

50 vacand

two

Xl00

probes.

load resistors used.

output

oscilloscope using SOmv/div sensitivity.

the

outputs.

voltageofthe

with

DVMs.

+5

output

See

textofsection

AI50

10

Amp,

AC

volt-

digital multimeters,

entry

regulated bus,

monitor

can also be used

III

tile +5

for

on

the

to

ten

TROUBLESHOOTING

Section 1

EQU IPMENT FOR TEST SET-UP

1.

Isolation Transformer (minimumofSOOVA

.....

CAUTION

Dangerously high voltages are presentinthis power supply.

the

doing transformer. The keep

the

otfatthe

peak charging capacitors

the

peakoftheACwaveform.

at

For

the safetyofthe

testing, please use an isolation

500VA

AC

waveform from being clipped

peaks. These power supplies have

....

ratingisneeded

and

draw

rating)-

indivkiual

to

full power

............

•

-

FIGURE1.TEST SET·UP

SeetiOll

VISUAL INSPECTION

Check power supply for damaged components. Visually check fuse resistor,ifany question

II

che<:k

with

any

ohmmeter.

broken, burned,

:I==;l

'"r-,

•

....

'''''

or

obviou~y

67

.<

TABLE1.LOAD

BOARD

VALUES

OtJTPUT

"

."

-12 NONE

MIN

LOAD

O.45A

O.3A

LOAOR

11.l1ohm

"'.hm

OPEN

LOAD

START·UP

Load power

wpply

with minimum load

as

specified

Table 1. Briny powerupslowly with Variable Transformer while monitoring +5 should

nart

with approximately

should regulate'

output

with scope and DVM. Supply

40.60

VAC applied and

when 95 VACisreadled.Ifoutput

has reached +5 volts,doa performance test as showninSection IV.Ifthere

S.ction

NO

OUTPUT

is00output

III

refertosection III.

SAFE

POWER

5W 5W

0

E.

in

MAX

LOAD

2.5A

2.02A

O.lA

LOADR

20hm

24.6ohm 120

ohm

LOAD

SAFE

POWER

25W

"'"

'W

Check02Waveforms Using X100 probe waveform. The collector

large capacitors C5 and

ing,

correct waveformisshowninFigure 2.Ifthisisnot prescnt, the

check for shorted junctionon02.If0 K check

base

waveform.

on

heatsinkof02,

of02is

CG.

Transistor should be $Witdl-

check collector

the pin closest to the

Baseof02ispinoftransistor nearen

the edgeofPCB. The correct waYeformisshown

Figure

3.Ifthis waveformisnot

and

01,

'and secondary components and L3.IfllInyofthe or

inductors

open.

replaa! them.

semiconductors are found shorted

pr~t,

03,

check

08,

l2.01,

09,

in

010

A. Check Fusable Resistor

If

fusable resistorisblown replace

power until

B.

Preliminary CheckonMajor Primary Components Check diode bridge

catch diode

ponent

C.

Primary Check on Major secondary Components. Using

put,.with rectifiers check crowbar

O. Check for B+

Set

power

to

endofRIO nearest

check for B+

With input

120 if

necessary, check R2,

C5

and C6.

cause

of

failureisfound.

(BRl),

(03)

for shorted junctions.Ifany com·

is

found shorted, replace.

ohmmeter from

output

or

loads disconnected. check

capacitors.

SCA

(SC

Rll

supply and attach X100

OBl.

on

end

at

95 VAC, this point should

140

VOC.IfthisIsnot

power transistor (T21, and

output

commontoeach

If

+5

outputisshorted also

and zener (Z

scope

Slowly

of

R9 nearest mounting hole.

tum

correct, check

02,

and

finally

but

do

for

1).

probe ground

up

power

be

input

capacitors

not apply

out·

shorted

and

between

SRI

and

FIGURE

1.0

5 Jbec{OIV

Input

same a above.

2.

VIDIV

and

50

V-,>tv

5 JbeC/D1V

I"put

Load'

Q2

COLLECTOR WAVEFORM

Load.

FIGURE3.02

BASE WAVEFORM

_ 120VAC

-

+5.

2A

+12@lA

·12@O.lA

68

Section

PERFORMANCE TEST

IV

Eachofthese test conditions shouldbeset-up and noted

be within

T5'

1

2

3

4 128VAC

5 95VAC

OUTPUT

.,

."

the

limits specifiedinTable

Input +5 Load

95VAC 128VAC 120VAC

TABLE2.VOLTAGE

MIN

4.75V 5.25V

11.40V 12.60V

- 11.00V 15,oOV

2.

+12 Load

Mox M"

M"

Min Min

AND

RIPPLE SPECIFICATION

MAX

M" M"

M~

Min Min

NO

·12 Load

LOAD

l50mV 150mV p.p

M" M"

Min Min

Min

RIPPLE

•

50mV

to

p.p p.p

• Applies to resistive load conditions.

only.

Not under system operating

69

POWER SUPPLY COMPONENT

VALUES

CAPACITORS

Cl

-

2200pF,

C2-

C3 - 2200pF. 250V

C4

C5-

C6 -

C7 -

C8-

O.Q1JlF,lKV

- O.22pF,

47~F,250V

47pF.

220pF,

4700pF,lKV

250VAC

250

250V

lOV

V

C9-O.OlpF,lKV

Cl0

- O.22pF, lODV

ell

- 1000

ell

- 1000j.lF,25V

e12

- 1000pF,

C13 -

l000pF,25V

C14 - 330pF,

C15 - 2200J.lF,

Gt6

- 330/.lF,

e17

- 470j.lF,

Gta

- O.022pF.

C19

- O.22J,lF.

e2l

- O.1f,lF,

CHOKES

L1

-

TF

L2 - 328

l3

- 328 - 00100010

L4

-

TF·

L5

-

TF·

25V

l6V

l6v

25V

sov

l00V

250VAC

- 202000010

- 00100030

20100010

10100370

L6 - 328 - 00100060

AC

INTEGRATED

let

-

Tl43TCLP

RESISTORS

RT-47

R2

- 150K, 1/2W

R3-

RS

R7-3.30hm,1/2W

R12-

R13 R14 - 8.2 ohm. 1/4W R15 - 560 ohm, 1!4W R16 R17

R20 R21 R22 - 2.7K,

R24 -

TRANSFORMERS

tK,1/4W

R4 -

not

- 82

R6-

27ohm,1/4W

R8-

10ohm,1/4W

A9-27

RlO -

0.15

Rl1-

270

B2ohm,

270

56

-56

AlB

- 12K, 1/4W

A19 - 12 ohm, 1/4W

470

- 4.7K, 1/4W

A23 - 6BK, 1/4W

220ohm,

A25 - 2 ohm,

CIRCUIT

ohm,

1W

used

ohm,

1/4W

ohm,

2W

ohm,

1/2W

ohm,

1/2W

1!4W

ohm, 1/2W

ohm, 1/4W

t/4W

lW

2W

(fuse resistor)

70

DIODES

01 02~RGP 03-RGP 04-RG3B

05

0607 08 09 010 OBl-W06 SeRl Zl

RGP

-

RG3B

-

RGP

-

lN4606

-

lN4606

- 1N4606

- C122F

-

5.6V,lW

lOA 100 10J

15B

T1

-

TF·

4491

T2-

TRANSISTORS

Ql Q2

03

TF·4441

- PE80S0B

- 25C2502

- PE8550B

DBl

L~~]]'"

1

C2'

:J

C2-{)t

+

L4

I,

,

---_.--0

+12V

N~mn

?o---------

N

tJC3

+IC5

..

_--------0

+5V

R2

I ,

R3

D1

"

,

"

,

"

,

"

"-

"

,

'--

"

U

k""I

•••

. .

'"

.J_

I.

C

'6

_

• T I

_

C19 :

OCOM

----O-12V

R2,

,j

I

Cl0

__

Tl_\

j

I

""-I

...

FIGURE 4.

POWER

SUPPLY SCHEMATIC

DIAGRAM

----

~~J

.

.-.1

SECTION

VII

VIDEO

MONITOR

73

FUNCTIONAL

The

video

for

displayofalphanumeric

designed

power

consumption

arate

video,

SPECIFICATIONS

monitorisa 12-inch solid

for

a 12-volt

and

vertical drive

dot

DC

power

of12watts.

TTL

state

monitor

characters. The

input

with

The

monitor

level

inputs.

SPECIFICATIONS

designed

monitor

an

average

accepts

is

sep·

Cathode

Ray

Tube:

Enviroment:

Power

Input:

TTL

Level

Input Signals:

Video Response:

Scanning

Frequency:

Horizontal Retrace:

Vertical Retrace:

12"

diagonal,

900deflection

integral implosion

Operating Humidity: Operating

+12

4 volts ±

Horizontal:4to Vertical:

Video:

Bandwidth: Pulse rise

Horizontal:

Vertical:

10.5,usec

850,usec

Temperature:

95% non-condensingat410Fto1040F

Altitude:

VDCat1

amp

1.5

volts

100to1400J,lSec, negative going

positive

15 MHz, 3 dB

time

less

15.600

50/60

maximum

protection.

10,000

nominal

25J,Lsec,

white

than

Hz ±

Hz

angle, 4 x 5

41°Fto131°F

ft.

(3046

positive going

30nsec

500

Hz

aspect

(50Cto550C)

metersl

maximum

ratio,P4phosphor,

ambient

(5°Cto40°C)

75

-..I

C)

n 1 I 2 I 3

t--

I ,

14

I 5 r

.,.,

C5

C

::1J

m

-'

<

o

m

o

$

o

2

-l

o

::1J

"tl

::1J

2

-l

m

o

("')

::1J

("')

C

-l

to

o

»

::1J

o

SERVICE ADJUSTMENTS

WIDTH

NOTE: Measurements should Measurements with kine (CRT) attached will require the ground transistor failures

FOCUS

Adjust focus control F524 (Figure 1, Zone 2-A) for overall focus.

VERTICAL SIZE

Adjust

produce vertical scan

HORIZONTAL LINEARITY

Loosen deflection yoke clamp and slide linearity sleeve wardorbackward to equalize character spacingonleft side oftomatch character spacingonright sideofscreen (See

Figure 2 for locationoflinearity sleeve).

strap from kine be connected to chassis to prevent

in

the eventofkine arcing.

vertiC<lI

size control

of

be made using 12.0

R6t7

(Figure1,Zone 3-B) to

approximately 6 inches.

VDC

input.

best

for·

Note: Check Adjust width control to produce horizontal scan imately 8 inches.

CENTERING

Adjust centering rings display

HORIZONTAL HOLD

Horizontal Hold

horizontal oscillator coil (Figure 1. Zone

horizontal linearity priortowidth adjustment.

on

deflection yoke assemblytocenter

on

screen

toptobottom

is

accomplished by adjustment

and left to right.

4·0).

01

approx-

of

the

KINE

YOKE

CE.NTERING

MAGNETS

Ulrl~~

__

L1NEARITY

SLEEVE

FIGURE2.DEFLECTION·

YOKE

ASSEMBLY

77

2

r

A

'!IDEO INPUT

B

-

+18V

QI-F]

c

Q601

SYNC

AMP

C603

7!JJV

[9A]

ll

.

1000

~~04

R704

3900

+18V

[jl-f]

o

R602

470

E

I

F

GND

NC

~G_N_O-++-+-~

6~--+-+-+-1f-""'-f-{

+12V

G

10

C702

-.1I0V

R703*

(,.5Me

270

I

-

R501 1500

R607

220K

R502 4700

C503

.033

R608

82K

C606

220pF

15V

R611 lOOK

R610 6800

lo.lIV

8

..-..=-1------,

n021

-.J

R123

1500 112W

I

-

C519 +

3~6'~

C520

C518

l)lF 150V

BOOST

-

--

R301

lOOK

6

--

TO

PIN 4

EDGE

BOARD

[I-G

4

5

-

L302

C301

.1

22pH R306

R302

680

220K

TO

+80V

BOOST

[8-G]

CONNECTOR

J

7

-C;-;;J

Dlf--

-=

1kVE304

-

E602

L

470

R629

Q502

HORIZ. DRIVER

+

80V

9.Z/IV

C507

.033

(8·GJ

R625

l80K

R624 16K 1/2W

R622

120

R510

47K

R508

2200

""

1/1;»------'

HORIZ

OSC.

(HOLD)

R511 330

R514

R616

3.9

C608 47pF

R506

C506

5.61l

C609

.I

10K

R507 1500

20V

608

+

F

R615

10K

+

R614

15K

504

.018

220

C611 3300

L502

HORIZONTAL DRIVER

TRANSFORMER

I

-

DO

NOT

MEASURE,

CR504

DAMPER

C513

1 kV

R516

lMEG

.

01

.

lW

R518

470K

1/2

W

9

-

C527

,01

1 kV

R524

2.5

FOCUS

~

-

E505

MEG.

__

10

C525

1°'i°1f-°

__

VIOl

R

1

523

MEG.

~~

E501

__

11

I. RESISTOR VALU6S

2.CAPllCITOR VALUES GREATER THtlN

3. VOLTAGES MEtlSURED

4. ALL RESISTORS 1/4

THIS PRODUCT CONTAINS CRITICAL ELECTRICAL PROTECTION. SEE PAGE 6 OF SERVICE DATA SPECIFIED REPLACEMENT PARTS. VOLTAGE IS 12.0kV FOR A VERY DIM PICTURE AND MUST NOT CONDITIONS. THIS INSTRUMENT CONTAINS NO HIGH VOLTAGE ADJUSTMENT. SEE PAGE DATA

SCHEMATIC NOTES:

AREINOHMS,

THOSE

1.0

AND

WISE DESIGN4\TED.

"VOLTOHMYST".NOSIGNAL APPLIED AND SHOULD

WITHIN

+INDICATES

..

lit-

..

if!-

]RELATESTOZONINGONPERIMETEROFDRAWING.

[

LESS liREIN)lFD.

~20%.

GROUND

INDICATES

5'%

IN DICATES 2 % TOLERANCE.

...

EXCEED

FOR

TOLERANCE.

INDICATES I % TOLERANCE.

PARTS

16.0kV

OTHER SERVICE ADJUSTMENTS

---,

I

-l

;~~~c~C

I

I I

I

12

~'1000.

1.0

liRE IN

U~LESS

WITH

RESPECT

WATT,

UNLESS OTHERWISE INDICATED.

.•

ESSENTIAL

UNDER

..1-

TO-=USIN:; A

X·RADIATION

MECHANICAL

FOR

\X·RADIATION

NOMINAL

2ND ANODE

ANY

OPERATING

5 OF THIS SERVICE

OTHEf'-

o.

~OLO

AND FOR

I

78

I

H

L

----

-

---

--

FIGURE 3.

---

VIDEO

--

MONITOR ASSE!VlBLV SCHEMATIC

E502

E801

---

DIAGRAM

--

-

_=.J

-

SECTION VIII

ILLUSTRATED PARTS CATALOG

79

M

o

....

......

o

....

<D

o

....

>-

..J

In

:2

w

CI) CI)

«

w

CI)

«

u

a:

w

~

:::>

o

....

w

a:

:>

Q

u.

8

....

M

o

....

g

....

81

82

>

-J

::;:

'"

w

<n <n

«

w

~

-J

'"-

W

<n

«

'"

M

w

c:

::l

52

lL

83

00

...

141

•

."~

135,136,

137

~134

FIGURE 4.

METAL

CHASSIS

ASSEMBLY

III

W

::>

"

£!

...

85

ILLUSTRATED

PARTS CATALOG

PARTS LIST

FIGURE 1. OUTER CASE ASSEMBLY

ITEM

NUMBER

101

102

103

104

105 '06

107

lOB

ITEM

NUMBER

111

112

113 Washer.

114 Nut, 115 117 Case

MANUFACTURER'S

DESCRIPTION

Case Feet

Screw, #4 x

Screw, #8 x Screw, #8 x Power 9N.tch Screw.

Washer.

Power Cord 8709138 AW2540

Video Board Assembly

Screw,#6x

Video Display, CRT 8492002 AXX80TO

Tab,

ground. Top

3/8",

1",

PH, machine

3/4",

#13

x 318". sheet metal

#i3.

flat

DESCRIPTION

1/4".

#10,

flat 8589038 AHD8548

hex,

#10-24

CAT 8529020 AHC0329

plastitEl 8569102

sheet metal

FIGURE2.CASE

plastite

TOP

PART NUMBER PART NUMBER

8590088

8569084 8569083

6480030

8569088

8589017 AHDB514

ASSEMBLY

MANUFACTURER'S

PART

NUMBER

8492002 8569077

8579021 AHD7180

8719104

RADIO

PART

SHACK

AF0297

--------

AHD2308 AH01620

AS0693

AH01621

SHACK

NUMBER

AXXB010 AH0161S

AZ5689

FIGURE3.BASE PLATE ASSEMBLY

ITEM

NUMBER

116

120

121 123

12'

125 126

·127

128 Metal Chassis Not Stocked Not Stocked

12.

·132

"33

·items

NOTE:

mony

DESCRIPTION

Screw, #6 x Knob, Thumbwheel Video Control Bracket Ubel, Koyboard,65-key

Screw,#6x

Keyboard, Bezel 8719101 AZ5688

Keyboard Header, right angle

Mylar Shield

Power Supply, main

utex,16404.o8

F SCrew, #6 x

Fane)! Tinnerman

not

appearonearlier version units.

RAM

Ground

dip

1/4",

plastite

sile,

16K 8789261 AHC0321

1/2",

plastite

3/8"

Clip 8182-.6H)4

MANUFACTURER'S

PART NUMBER PART NUMBER

8569077 8719112

8729040

8790511 AXX0205 8569079

8519107 8539015

8790021 AXX6005 8559022 8569108

8559029

RADIO SHACK

AHD1618

AK4298

ART3081

AHD1619

AJ6909

------

AHCOO75

------

AHC0782

86

ILLUSTRATED

PARTS LIST (Cont'd)

PARTS CATALOG

FIGURE

ITEM

NUMBER

·134

'3'

·,36 '137

138

"39

140

141

NOTE;Ifyour computerisearlier the Rev. F, the following hardware maybeused

on your

unit

insteadofthe starred ('0' items.

DESCRIPTION

Chassis CPU

Insulating Screw, Connector Bracket

Ground Bracket 8729055

R5-232 80ard FDC Board Assembly

PCB

Clip, RICHCa, LCBS·20R

Fastex,l6404.Q8

Clip, RICHCa, LCBS4R

Fastex, 16402.Q4

Shield

Board Assembly 8858006 AXXQ507

Washers

#6 x

5/8",

Screw, #6 x

Washer,#6,star 8589043

Nut, #S 8579014 AHD7168

Mount

Screw,

Bracket

#6

1/4"

Assembly

x

1/4",

PPH

planite

4.METAL

CHASSIS ASSEMBLY

MANUFACTURER'S

PART

NUMBER

Not

Stocked

8539013 AHC0787 B569013 8729039 ART3082

8569098

----

885802.

729042 8569077 8559017 8559022 8559018 8559020

RADIO

PART

Not

-------

-----~

-------

AXX0511 AXX0510

ART3080 AHD1618

AHCOO70 AHCOO75 AHCOO71 AHCOO73

SHACK

NUMBER

Stocked

FIGURE 5.

ITEM

NUMBER DESCRIPTION

POWl!(

14'

14. 147 Disk Mounting Bracket,

14.

'"

Supply

RF Shield 8729041 ART3085

Disk Mounting Bracl<et, right 8719105 ART3086 Disk Drive

Disk.

left

DISK

DRIVE

ASSEMBLY

MANUFACTURER'S

PART

NUMBER

8790021

8719106

8790112

RADIO

PART

AXX6005

ART3083

AXX5019

SHACK

NUMBER

81

ILLUSTRATED

PARTS

MISCELLANEOUS

PARTS CATALOG

LIST

(Cont'd)

DESCRIPTION

Cable Clamp Cable Mount Cable Tie, Ground Ttlb, Ground Tab, Keyboard (O.l Ground Tab,

AC Ctl$$cttc CRT

DC DC

Ground Harness, Disk

Ground Harness, Keyboard Ground Harness, Ground Harness, Secondary Disk Kevboard/CPU, shielded

4"

CPU

KeYUaord

Power Hilrness

I/O Internal

Wire

Harness Pwer Harness, Disk Pow.r Harness,

Main

30)

(0.171)

MANUFACTURER'S

PART NUMBER

8729054 8559028 8559027 8529024 8529026 8519062

CABLES

8709151 8709156 8709153 8709155 8709178 8709204 8709194 8709161 8709195 8709182

RADIO SHACK

PART NUMBER

AHC0358

AW2214

AW2531 AW2538

AW2356

AW2532 AW2537

AW2591

aa

THIS PAGE WAS

LEFT

INTENTIONALLY

BLANK.

THIS PAGE WAS

LEFT

INTENTIONALLY

BLANK.

SECTION

IX

MINI

DISK

DRIVE

91

PART

1

GENERAL

A INTRODUCTION

The

Disk Driveisa

ateen

dom These applications typically. are intelligefl1 terminal lers, micro"'Computers, munications systems, error

and

point-of·sale terminals.

cording and reading digital

techniques.

redesigned

A

Servo cirQ.litry will

and Boards usedinthe disk driven. A schematicofthis new Board

lists.

Catalog Number26·11

B PHYSICAL DESCRIPTION

The

electronic: compoflt'f)ts are the Logic Board and located aboye Ihe chassis

are connceted dlrectlvtothat

nals may be versionoftne Vl!fSlon the

Disk Drive version the

Disk Driveoninternal of

the

external

data

isattne

please refertothe

mountedinoneoftwo

Non ·Iioear Servo Boardismountedtothe

lioear

Drive -

unin.

"MINI"

entry.

IMPORTANT NOTICE

logic

PC Board

endofthis section, For

Disk Memory de$igned

storage, and retrieval applications.

word

proceuing logging, micro-pHlgram 10il(ling The

data

using FM, MFMorM2FM

which

soon

be replillcing

systems,

Disk Oriveiscapable

contaim

the

Theory

TRS-BOMini Disk !*rvice Manual,

flJ/X.

mountedontwo

the

Servo Board. and

the

Board and

on

internal and eJCternal units.

Servo Boardismountedtothe

the

typeofDIsk Drive.

units

same as the

The

Logic Board

Power lind Interface sig·

BOillrd.

The

ways, dependingonthe

and

mounted10the

non·llnear

for

con~rol

data

of

both

Logic

two

separilte

and Parts

PC Boards:

Servo Board

The

older

rear of

The

newer

bottom

Boards _

ran·

com-

rear

on

DESCRIPTION

servo is

loaded

the front latchisclosed.

A ell!Ctronics

reo

is

of

track. a

'·uack is (he write electronics is

appliedtothe lion. a 0.Ot3·inch (0.33 mml (nO'llinal!

corded.l

Data recovery electrorliCs IIlclude a low·level read amp ifiar, differentlator, No

The

o INTERFACE CONNECTIONS

controlledDCmotor.Inoperation.

into

f.ontact with lht! rt!cording medium whenevt!r

4·phase

inserted

dilta decoding facIlities are providedInthe basic Drive.

stepper

This positioner

lioear movement. When a write,protcetcd d,skette

into

Drive isalso supplied with the folloWlrlg sensor systems;

1. A track: Carriage

2.

The transistorlispositioned so hole index can dex sector holesina hard sectored

3,

The electronics

to

the

motorlband

position Ihe magnetic head over the desired

employs

the

Drive. the wrile-protect scnsor disables

of

the Drive

interface. (When perfonnrng a write

lero

cronmg

00

SWItch

assemblyispositionedatTrack

index sensor (an LED light source and a

is

detected,

$Cnsor

usedisa high reKllution device which

distinguish holes placed close together. i.e.,

write·protect

whenever a

diskette.

assembly and its associated

a one·step

detector

which senses when

a dIQital signalisgenerated.

sensor disables the Disk Drive

write·protect

the magnetic head

ro:at,ontocau$C

and

an appropriate s gnal

data

trackisre-

and digitizing circuits.

the eJ0.

that

whenanindex

diskette.

tabisapplied

oper"

Headl

photo·

The

·n·

The

~indle

tachometer.

tachometer control erase head assemblyispositioned by me"ns of a stepper mOlor. split

C FUNCTIONAL DESCRIPTION

The

Disk Driveisfully self·contained. It consists01a spindle drive system. a head posi tioning system, and read/write/crase system.

When the front latct\ is

insenionofa 5.25 inch (133.4 mm) standard

disketteispositionedinplace by plastic guides.

latch

and a back

Closing which centers and clamps the The drive

is

bell driven by a

The

servo control circuit, pulleys and

thespecdof

band llnd a pulley.

opened,

stop.

the

front laten activate'S the cone/clamp system

hubisdrivenata

DC

mOlor with an integral

the spindle.

accessisprovided

diskettetothe

constant

speedof300

The

diskette.

the

read/write/

10'

the

The

the

front

drive

hub.

rpm

by a

S,gnal

connections

a user·supplied

Drive

uses a Radio Shack

of

Both connector nectaris;}

on

The signal

twisted pair

Power

18

Harnen,

these

(Jl)atthe

four ,pln

the

top

reorofthe Drive.

connector

type

1.

Maximum lengthof10

2.

22

- 24 gauge

ncetor

connections

AWG

cable. Internal Drives use the Disk

Radio Shack Part Number AW2532.

for the extern,,1 Disk Drive are mooe

34·pin

connectors

to be used.

11,,1

ribbon

connector.

mate directly with

reor of

connector

harnen

with the following characteristics:

conductor

for external Drives should be made with

Part Number AW2535,

the

Drive,

(J21onthe

should beofthe

feet

(3M).

compatible

The internal

thePCBoard

TheDCpower

Logic PC Board

flat ribbon

with the con-

DC

via

con·

or

Powel

93

Radio Shack TRS-80, TRS-80 Model III, 26-1061, 26-1062, 26-1063 Service Manual

Specifications and Main Features

Frequently Asked Questions

User Manual

LIST OF TABLES