Rabbit 6000 User Manual

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Rabbit® 6000 Microprocessor

User’s Manual

90001108_J

Rabbit 6000 Microprocessor User’s Manual

Part Number 90001108 • Printed in U.S.A.

Digi International reserves the right to make changes and

improvements to its products without providing notice.

Trademarks

Rabbit and Dynamic C are registered trademarks of Digi International Inc.

Rabbit 6000 is a trademark of Digi International Inc.

The latest revision of this manual is available on the Digi Web site, http://www.digi.com/support/.

1. The Rabbit 6000 Processor

1.1 Introduction ....................................................8

1.2 Features ..........................................................9

1.3 Block Diagram .............................................11

1.4 Basic Specifications .....................................12

1.5 Comparing Rabbit Microprocessors.............13

2. Clocks

2.1 Overview ......................................................16

2.1.1 Block Diagram .....................................17

2.1.2 Registers ..............................................17

2.2 Dependencies ...............................................18

2.2.1 I/O Pins ................................................18

2.2.2 Other Registers ....................................19

2.3 Operation......................................................20

2.3.1 Main Clock ..........................................20

2.3.2 Main PLL .............................................21

2.3.3 Spectrum Spreader ...............................22

2.3.4 Clock Doubler .....................................24

2.3.5 32 kHz Clock .......................................26

2.4 Register Descriptions ...................................28

3. Reset and Bootstrap

3.1 Overview ......................................................35

3.1.1 Block Diagram .....................................36

3.1.2 Registers ..............................................36

3.2 Dependencies ...............................................37

3.2.1 I/O Pins ................................................37

3.2.2 Clocks ..................................................37

3.2.3 Other Registers ....................................37

3.2.4 Interrupts ..............................................37

3.3 Operation......................................................38

3.3.1 Asynchronous Serial Bootstrap ...........40

3.3.2 Serial Flash Bootstrap ..........................40

3.3.3 Parallel Bootstrap ................................41

3.4 Register Descriptions ...................................41

4. System Management

4.1 Overview ......................................................42

4.1.1 Block Diagram .....................................43

4.1.2 Registers ..............................................44

4.2 Dependencies ...............................................45

4.2.1 I/O Pins ................................................45

4.2.2 Clocks ..................................................45

4.2.3 Interrupts ..............................................45

4.3 Operation......................................................46

4.3.1 Periodic Interrupt .................................46

4.3.2 Real-Time Clock .................................46

4.3.3 Watchdog Timer ..................................47

4.3.4 Secondary Watchdog Timer ................47

4.3.5 CPU Clock Cycle Counter .................. 47

4.4 Register Descriptions ...................................48

5. Memory Management

5.1 Overview......................................................54

5.1.1 Block Diagram .................................... 57

5.1.2 Registers ..............................................58

5.2 Dependencies ............................................... 60

5.2.1 I/O Pins ................................................ 60

5.2.2 Clocks ..................................................60

5.2.3 Interrupts .............................................60

5.3 Operation...................................................... 61

5.3.1 Internal RAM ......................................61

5.3.2 Memory Management Unit (MMU) ... 61

5.3.3 Memory Bank Operation ..................... 62

5.3.4 Memory Modes ...................................64

5.3.5 Separate Instruction and Data Space ... 66

5.3.6 Memory Protection ..............................67

5.3.7 Stack Protection ..................................67

5.4 Register Descriptions ...................................68

6. Interrupts

6.1 Overview......................................................83

6.2 Operation...................................................... 84

6.3 Interrupt Tables ............................................84

7. External Interrupts

7.1 Overview......................................................87

7.2 Block Diagram .............................................88

7.2.1 Registers .............................................89

7.3 Dependencies ............................................... 90

7.3.1 I/O Pins ................................................ 90

7.3.2 Clocks ..................................................90

7.3.3 Interrupts .............................................90

7.4 Operation...................................................... 91

7.4.1 Example ISR .......................................91

7.5 Register Descriptions ...................................92

8. Parallel Port A

8.1 Overview......................................................94

8.1.1 Block Diagram .................................... 95

8.1.2 Registers ..............................................95

8.2 Dependencies ............................................... 96

8.2.1 I/O Pins ................................................ 96

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8.2.2 Clocks ..................................................96

8.2.3 Other Registers ....................................96

8.2.4 Interrupts .............................................96

8.3 Operation......................................................97

8.4 Register Descriptions ...................................98

9. Parallel Port B

9.1 Overview ....................................................100

9.1.1 Block Diagram ..................................101

9.1.2 Registers ............................................102

9.2 Dependencies .............................................102

9.2.1 I/O Pins ..............................................102

9.2.2 Clocks ................................................102

9.2.3 Other Registers ..................................102

9.2.4 Interrupts ...........................................102

9.3 Operation....................................................103

9.4 Register Descriptions .................................104

10. Parallel Port C

10.1 Overview ..................................................106

10.1.1 Block Diagram ................................107

10.1.2 Registers ..........................................108

10.2 Dependencies ...........................................108

10.2.1 I/O Pins ............................................108

10.2.2 Clocks ..............................................108

10.2.3 Other Registers ................................108

10.2.4 Interrupts .........................................108

10.3 Operation..................................................109

10.4 Register Descriptions ...............................110

11. Parallel Port D

11.1 Overview ..................................................113

11.1.1 Block Diagram ................................115

11.1.2 Registers ..........................................116

11.2 Dependencies ...........................................117

11.2.1 I/O Pins ............................................117

11.2.2 Clocks ..............................................117

11.2.3 Other Registers ................................117

11.2.4 Interrupts .........................................117

11.3 Operation..................................................118

11.4 Register Descriptions ...............................119

12. Parallel Port E

12.1 Overview ..................................................125

12.1.1 Block Diagram ................................127

12.1.2 Registers ..........................................128

12.2 Dependencies ...........................................129

12.2.1 I/O Pins ............................................129

12.2.2 Clocks ..............................................129

12.2.3 Other Registers ................................129

12.2.4 Interrupts .........................................129

12.3 Operation..................................................130

12.4 Register Descriptions ...............................131

13. Parallel Port F

13.1 Overview ..................................................136

13.1.1 Block Diagram ................................138

13.1.2 Registers .......................................... 139

13.2 Dependencies ........................................... 139

13.2.1 I/O Pins ............................................ 139

13.2.2 Clocks ..............................................139

13.2.3 Other Registers ................................ 139

13.2.4 Interrupts .........................................140

13.3 Operation..................................................140

13.4 Register Descriptions............................... 141

14. Parallel Port G

14.1 Overview..................................................145

14.1.1 Block Diagram ................................146

14.1.2 Registers .......................................... 147

14.2 Dependencies ........................................... 147

14.2.1 I/O Pins ............................................ 147

14.2.2 Clocks ..............................................147

14.2.3 Other Registers ................................ 147

14.2.4 Interrupts .........................................148

14.3 Operation..................................................148

14.4 Register Descriptions............................... 149

15. Parallel Port H

15.1 Overview..................................................153

15.1.1 Block Diagram ................................154

15.1.2 Registers .......................................... 155

15.2 Dependencies ........................................... 156

15.2.1 I/O Pins ............................................ 156

15.2.2 Clocks ..............................................156

15.2.3 Other Registers ................................ 156

15.2.4 Interrupts .........................................156

15.3 Operation..................................................157

15.4 Register Descriptions............................... 158

16. Timer A

16.1 Overview..................................................161

16.1.1 Block Diagram ................................163

16.1.2 Registers .......................................... 164

16.2 Dependencies ........................................... 165

16.2.1 I/O Pins ............................................ 165

16.2.2 Clocks ..............................................165

16.2.3 Other Registers ................................ 165

16.2.4 Interrupts .........................................165

16.3 Operation..................................................166

16.3.1 Handling Interrupts .........................166

16.3.2 Example ISR ................................... 166

16.4 Register Descriptions............................... 167

17. Timer B

17.1 Overview..................................................169

17.1.1 Block Diagram ................................170

17.1.2 Registers .......................................... 171

17.2 Dependencies ........................................... 171

17.2.1 I/O Pins ............................................ 171

17.2.2 Clocks ..............................................171

17.2.3 Other Registers ................................ 171

17.2.4 Interrupts .........................................172

17.3 Operation..................................................172

17.3.1 Handling Interrupts .........................172

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17.3.2 Example ISR ....................................172

17.4 Register Descriptions ...............................173

18. Timer C

18.1 Overview ..................................................176

18.1.1 Block Diagram ................................177

18.1.2 Registers ..........................................178

18.2 Dependencies ...........................................179

18.2.1 I/O Pins ............................................179

18.2.2 Clocks ..............................................179

18.2.3 Other Registers ................................179

18.2.4 Interrupts .........................................179

18.3 Operation..................................................180

18.3.1 Handling Interrupts ..........................180

18.3.2 Example ISR ....................................180

18.4 Register Descriptions ...............................181

19. Serial Ports A – D

19.1 Overview ..................................................184

19.1.1 Block Diagram ................................186

19.1.2 Registers ..........................................187

19.2 Dependencies ...........................................188

19.2.1 I/O Pins ............................................188

19.2.2 Clocks ..............................................188

19.2.3 Other Registers ................................189

19.2.4 Interrupts .........................................189

19.3 Operation..................................................190

19.3.1 Asynchronous Mode ........................190

19.3.2 Clocked Serial Mode .......................191

19.4 Register Descriptions ...............................193

20. Serial Ports E – F

20.1 Overview ..................................................200

20.1.1 Block Diagram ................................201

20.1.2 Registers ..........................................202

20.2 Dependencies ...........................................203

20.2.1 I/O Pins ............................................203

20.2.2 Clocks ..............................................203

20.2.3 Other Registers ................................203

20.2.4 Interrupts .........................................204

20.3 Operation..................................................205

20.3.1 Asynchronous Mode ........................205

20.3.2 HDLC Mode ....................................205

20.3.3 More on Clock Synchronization and

Data Encoding ...........................................206

20.4 Register Descriptions ...............................210

21. Slave Port

21.1 Overview ..................................................216

21.1.1 Block Diagram ................................217

21.1.2 Registers ..........................................217

21.2 Dependencies ...........................................218

21.2.1 I/O Pins ............................................218

21.2.2 Clocks ..............................................218

21.2.3 Interrupts .........................................218

21.3 Operation..................................................219

21.3.1 Master Setup ....................................220

21.3.2 Slave Setup ......................................220

21.3.3 Master/Slave Communication ......... 221

21.3.4 Slave/Master Communication ......... 221

21.3.5 Handling Interrupts .........................221

21.3.6 Example ISR ................................... 221

21.3.7 Other Configurations ....................... 222

21.3.8 Timing Diagrams ............................ 223

21.4 Register Descriptions............................... 225

22. Wi-Fi Analog Components

22.1 Overview..................................................227

22.2 Block Diagram.........................................230

22.2.1 Registers .......................................... 231

22.3 Dependencies ........................................... 231

22.3.1 I/O Pins ............................................ 231

22.3.2 Clocks ..............................................231

22.4 Operation..................................................232

22.4.1 Fast A/D Converter ......................... 232

22.4.2 Fast D/A Converter ......................... 232

22.4.3 Slow A/D Converter ........................ 232

22.5 Sample Circuits........................................233

22.6 Register Descriptions............................... 235

23. Analog/Digital Converter

23.1 Overview..................................................240

23.2 Block Diagram.........................................241

23.2.1 Registers .......................................... 241

23.3 Dependencies ........................................... 242

23.3.1 I/O Pins ............................................ 242

23.3.2 Clocks ..............................................242

23.4 Operation..................................................243

23.4.1 Single Reading ................................ 243

23.4.2 Continuous Read ............................. 243

23.4.3 Handling Interrupts .........................243

23.5 Sample Circuit ......................................... 244

23.6 Register Descriptions............................... 245

24. DMA Channels

24.1 Overview..................................................249

24.1.1 Block Diagram ................................252

24.1.2 Registers .......................................... 253

24.2 Dependencies ........................................... 255

24.2.1 I/O Pins ............................................ 255

24.2.2 Clocks ..............................................255

24.2.3 Other Registers ................................ 255

24.2.4 Interrupts .........................................255

24.3 Operation..................................................256

24.3.1 Handling Interrupts .........................257

24.3.2 Example ISR ................................... 257

24.3.3 DMA Priority with the Processor .... 258

24.3.4 DMA Channel Priority .................... 259

24.3.5 Buffer Descriptor Modes ................. 260

24.3.6 DMA with Peripherals .................... 263

24.4 Register Descriptions............................... 264

25. 10/100Base-T Ethernet

25.1 Overview..................................................285

25.1.1 Block Diagram ................................287

25.1.2 Registers .......................................... 288

25.2 Dependencies ........................................... 290

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25.2.1 I/O Pins ............................................290

25.2.2 Clocks ..............................................290

25.2.3 Other Registers ................................290

25.2.4 Interrupts .........................................291

25.3 Operation..................................................291

25.3.1 Setup ................................................291

25.3.2 Transmit ...........................................292

25.3.3 Receive ............................................292

25.3.4 Handling Interrupts ..........................293

25.3.5 Multicast Addressing .......................294

25.4 Register Descriptions ...............................295

29.1.2 Registers .......................................... 335

29.2 Dependencies ........................................... 336

29.2.1 I/O Pins ............................................ 336

29.2.2 Clocks ..............................................336

29.2.3 Other Registers ................................ 336

29.2.4 Interrupts .........................................336

29.3 Operation..................................................337

29.3.1 Handling Interrupts .........................337

29.3.2 Example ISR ................................... 337

29.4 Register Descriptions............................... 338

26. 802.11a/b/g Wireless

26.1 Overview ..................................................309

26.1.1 Block Diagram ................................310

26.1.2 Registers ..........................................311

26.2 Dependencies ...........................................313

26.2.1 I/O Pins ............................................313

26.3 Clocks.......................................................314

26.3.1 Other Registers ................................315

26.3.2 Interrupts .........................................316

26.4 Operation..................................................316

27. USB Host

27.1 Overview ..................................................317

27.1.1 Block Diagram ................................317

27.1.2 Registers ..........................................318

27.2 Dependencies ...........................................318

27.2.1 I/O Pins ............................................318

27.2.2 Clocks ..............................................318

27.2.3 Other Registers ................................319

27.2.4 Interrupts .........................................319

27.3 Operation..................................................320

27.3.1 32-bit Interface ................................320

27.3.2 Setup ................................................320

27.3.3 Transmit and Receive ......................320

27.3.4 Handling Interrupts ..........................320

27.4 Register Descriptions ...............................321

28. Input Capture

28.1 Overview ..................................................322

28.1.1 Block Diagram ................................323

28.1.2 Registers ..........................................324

28.2 Dependencies ...........................................325

28.2.1 I/O Pins ............................................325

28.2.2 Clocks ..............................................325

28.2.3 Other Registers ................................325

28.2.4 Interrupts .........................................325

28.3 Operation..................................................326

28.3.1 Input-Capture Channel ....................326

28.3.2 Handling Interrupts ..........................326

28.3.3 Example ISR ....................................326

28.3.4 Capture Mode ..................................327

28.3.5 Count Mode .....................................327

28.4 Register Descriptions ...............................328

29. Quadrature Decoder

29.1 Overview ..................................................333

29.1.1 Block Diagram ................................335

30. Pulse Width Modulator

30.1 Overview..................................................340

30.1.1 Block Diagram ................................343

30.1.2 Registers .......................................... 343

30.2 Dependencies ........................................... 344

30.2.1 I/O Pins ............................................ 344

30.2.2 Clocks ..............................................344

30.2.3 Other Registers ................................ 344

30.2.4 Interrupts .........................................344

30.3 Operation..................................................345

30.3.1 Handling Interrupts .........................345

30.3.2 Example ISR ................................... 345

30.4 Register Descriptions............................... 346

31. External I/O Control

31.1 Overview..................................................348

31.1.1 External I/O Bus ..............................348

31.1.2 I/O Strobes ......................................349

31.1.3 I/O Handshake .................................350

31.1.4 Block Diagram ................................351

31.1.5 Registers .......................................... 352

31.2 Dependencies ........................................... 353

31.2.1 I/O Pins ............................................ 353

31.2.2 Clocks ..............................................353

31.2.3 Other Registers ................................ 353

31.2.4 Interrupts .........................................353

31.3 Operation..................................................354

31.3.1 External I/O Bus ..............................354

31.3.2 I/O Strobes ......................................354

31.3.3 I/O Handshake .................................354

31.4 Register Descriptions............................... 355

32. Breakpoints

32.1 Overview..................................................360

32.1.1 Block Diagram ................................361

32.1.2 Registers .......................................... 362

32.2 Dependencies ........................................... 363

32.2.1 I/O Pins ............................................ 363

32.2.2 Clocks ..............................................363

32.2.3 Other Registers ................................ 363

32.2.4 Interrupts .........................................363

32.3 Operation..................................................363

32.3.1 Handling Interrupts .........................363

32.3.2 Example ISR ................................... 364

32.4 Register Descriptions............................... 365

33. Flexible Interface Modules

33.1 Overview..................................................368

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33.2 Block Diagram .........................................369

33.2.1 Registers ..........................................370

33.3 Dependencies ...........................................371

33.3.1 I/O Pins ............................................371

33.3.2 Clocks ..............................................371

33.3.3 Other Registers ................................371

33.3.4 Interrupts .........................................371

33.4 Operation..................................................372

33.4.1 Handling Interrupts ..........................372

33.5 Register Descriptions ...............................374

37.3.2 Memory Writes ...............................419

37.3.3 External I/O Reads .......................... 422

37.3.4 External I/O Writes ......................... 422

37.4 Clock Speeds............................................425

37.4.1 Recommended Clock/Memory

Configurations .......................................... 425

37.5 Power and Current Consumption............. 427

37.5.1 Sleepy Mode Current Consumption 427

37.5.2 Battery-Backed Clock Current

Consumption ............................................. 428

34. Error Check and Correction

34.1 Overview ..................................................383

34.1.1 Block Diagram ................................384

34.1.2 Registers ..........................................384

34.2 Dependencies ...........................................385

34.2.1 I/O Pins ............................................385

34.2.2 Clocks ..............................................385

34.2.3 Other Registers ................................385

34.3 Operation..................................................385

34.3.1 ECC .................................................385

34.3.2 CRC .................................................385

34.4 Register Descriptions ...............................386

35. I2C Peripheral (Serial Port G)

35.1 Overview ..................................................389

35.1.1 Block Diagram ................................390

35.1.2 Registers ..........................................391

35.2 Dependencies ...........................................392

35.2.1 I/O Pins ............................................392

35.2.2 Clocks ..............................................392

35.2.3 Other Registers ................................392

35.2.4 Interrupts .........................................392

35.3 Operation..................................................393

35.3.1 32-bit Interface ................................393

35.3.2 Interrupts .........................................393

35.3.3 Master Mode, Data Write ................393

35.3.4 Master Mode, Data Read .................394

35.3.5 Slave Mode, Data Write .................. 394

35.3.6 Slave Mode, Data Read ...................394

35.4 Register Descriptions ...............................395

38. Package Specifications and Pinout

38.1 Ball Grid Array Packages ........................ 429

38.1.1 Pinout 17mm × 17mm BGA 292 ....429

38.1.2 Pinout 15mm × 15mm BGA 233 ....430

38.1.3 Mechanical Dimensions and Land

Pattern .......................................................431

38.2 Rabbit Pin Descriptions ...........................434

Appendix A. Parallel Port Pins with

Alternate Functions

A.1 Alternate Parallel Port Pin Outputs........... 441

A.2 Alternate Parallel Port Pin Inputs.............. 444

36. Low-Power Operation

36.1 Overview ..................................................403

36.1.1 Registers ..........................................404

36.2 Operation..................................................405

36.2.1 Unused Pins .....................................405

36.2.2 Unused Peripherals ..........................405

36.2.3 Clock Rates ......................................405

36.2.4 Short Chip Selects ...........................407

36.2.5 Self-Timed Chip Selects ..................412

36.3 Register Descriptions ...............................413

37. Specifications

37.1 Preliminary DC Characteristics................416

37.2 AC Characteristics ...................................418

37.3 External Memory Access Times ..............419

37.3.1 Memory Reads ................................419

Rabbit 6000 User’s Manual digi.com 7

1. THE RABBIT 6000 PROCESSOR

1.1 Introduction

Rabbit Semiconductor was formed expressly to design a better microprocessor for use in small- and medium-scale, single-board computers. The first microprocessors were the Rabbit 2000, Rabbit 3000, Rab- bit 4000, and the Rabbit 5000. The latest microprocessor is the Rabbit 6000. Rabbit microprocessor designers have had years of experience using Z80, Z180, and HD64180 microprocessors in small singleboard computers. The Rabbit microprocessors share a similar architecture and a high degree of compatibility with these microprocessors, but represent a vast improvement.

The Rabbit 6000 is a high-performance microprocessor with low electromagnetic interference (EMI), and is designed specifically for embedded control, communications, and network connectivity. Extensive integrated features and glueless architecture facilitate rapid hardware design, while a C-friendly instruction set promotes efficient development of even the most complex applications.

The Rabbit 6000 is the second Rabbit microprocessor to have a full 16-bit internal bus architecture, providing significant performance improvements when used with external 16-bit memory devices. It also has the ability to support both 8-bit and 16-bit external memory devices.

The Rabbit 6000 is also the fastest microprocessor from Rabbit, now a Digi International brand, running at up to 200 MHz, with compact code and support for up to 16 MB of memory. Operating with a 1.2 V core and 3.3 V I/O, the Rabbit 6000 boasts 16 channels of DMA, six serial ports with IrDA, 64+ digital I/O,

quadrature decoder, PWM outputs, I tures a battery-backable real-time clock, glueless memory and I/O interfacing, and ultra-low power modes. Four levels of interrupt priority allow fast response to real-time events. Its compact instruction set and high clock speeds give the Rabbit 6000 exceptionally fast math, logic, and I/O performance.

C port, and pulse capture and measurement capabilities. It also fea-

The Rabbit 6000 contains 1MB of internal high-speed 16-bit RAM, which can be used for both code and data. It also contains 32 KB of battery-backable 16-bit SRAM (also high speed) for applications where data retention is critical. It is capable of booting off of a standard serial flash, so a microcontroller application with no external parallel memory is possible.

The Rabbit 6000 provides two options for network connectivity — a full 10/100Base-T Ethernet MAC and PHY built into the device, and a wireless 802.11a/b/g MAC compatible with several standard Wi-Fi transceivers. Both network interfaces can be active at the same time. The Rabbit 6000 also contains a USB 2.0compatible full-speed USB host MAC and PHY.

The Rabbit 6000 also features two “flexible interface modules,” or FIMs. These two modules can be loaded with customized designs to support a variety of interfaces, including serial ports and CAN-bus interfaces.

Rabbit 6000 User’s Manual digi.com 8

1.2 Features

The Rabbit 6000 contains an internal phase-locked loop (PLL) that is fully controlled by software and provides up to a 200 MHz clock from a 25 MHz input. Other clock options are available as well, including the clock doubler and divider features present in earlier Rabbit devices.

The Rabbit 6000 has several powerful design features that practically eliminate EMI problems, which is essential for OEMs who need to pass CE and regulatory radio-frequency emissions tests. The amplitude of any electromagnetic radiation is reduced by the internal spectrum spreader, by gated clocks (which prevent unnecessary clocking of unused registers), and by separate power planes for the processor core and I/O pins (which reduce noise crosstalk). An external I/O bus can be used by designers to enable separate buses for I/O and memory, or to limit loading the memory bus to reduce EMI and ground bounce problems when interfacing external peripherals to the processor. The external I/O bus accomplishes this by duplicating the Rabbit's data bus on Parallel Port A, and uses Parallel Port B to provide the processor's six or eight least significant address lines for interfacing with external peripherals.

The high-performance instruction set offers both greater efficiency and execution speed of compiler-generated C code. Instructions include numerous single-byte opcodes that execute in two clock cycles, 16-bit and

32-bit loads and stores, 16-bit and 32-bit logical and arithmetic operations, 16 × 16 multiply (executes in 12 clocks), long jumps and returns for accessing a full 16 MB of memory, and one-byte prefixes to turn memory-access instructions into internal and external I/O instructions. Hardware-supported breakpoints ease debugging by trapping on code execution or data reads and writes.

The Rabbit 6000 requires no external memory driver or interface logic. Its 24-bit address bus, 8-bit or 16bit data bus, three chip-select lines, two output-enable lines, and two write-enable lines can be interfaced directly with up to six memory devices. Up to 1 MB of code memory and 15 MB of data memory can be accessed directly via the Dynamic C development software. The Rabbit 6000 also contains 1 MB of internal high-speed 16-bit RAM and 32 KB of battery-backed SRAM, which can be used instead of or in addition to any external memory devices.

A built-in slave port allows the Rabbit 6000 to be used as master or slave in multi-processor systems, permitting separate tasks to be assigned to dedicated processors. An 8-line data port and five control signals simplify the exchange of data between devices. A remote cold boot enables startup and programming via a serial port, a slave port, or from a standard external serial flash device.

The Rabbit 6000 features eight 8-bit parallel ports, yielding a total of 64 digital I/O. Six CMOS-compatible serial ports are available. All six are configurable as asynchronous (including output pulses in IrDA format), while four are configurable as clocked serial (SPI) and two are configurable as SDLC/HDLC. The various internal peripherals share the parallel port’s I/O pins. Drive strength, slew rate, and pullup/pulldown resistors can be controlled on all of the parallel ports.

The Rabbit 6000 also offers many specialized peripherals. Two input-capture channels each have a 16-bit counter, clocked by the output of an internal timer, that can be used to capture and measure pulses. These measurements can be extended to a variety of functions such as measuring pulse widths or for baud-rate auto detection. Two Quadrature Decoder channels each have two inputs, as well as an 8-bit or 10-bit up/ down counter. Each Quadrature Decoder channel provides a direct interface to quadrature encoder units. Four independent pulse-width modulator (PWM) outputs, each based on a 1024-pulse frame, are driven by the output of a programmable internal timer. The PWM outputs can be filtered to create a 10-bit D/A converter or they can be used directly to drive devices such as motors or solenoids. The Rabbit 6000 has eight

Rabbit 6000 User’s Manual digi.com 9

external interrupt vectors, two of which can each multiplex inputs from up to three external pins. A new

addition to the Rabbit 6000 is a fully featured I

C port capable of up to 400 kbits/s and 10-bit addressing.

The Rabbit 6000 has three timer systems. Timer A consists of twelve 8-bit counters, each of which has a programmed time constant. Six of them can be cascaded from the primary Timer A counter. Timer B contains a 10-bit counter, two match registers, and two step registers. An interrupt can be generated or an output pin can be updated when the counter reaches a match value, and the match value can then be incremented automatically by the step value. Timer C is a 16-bit counter that counts up to a programmable limit. It contains eight match registers so that up to four PWM (both synchronous and variable-phase) or quadrature signals for motor-control applications can be created.

The Rabbit 6000 also provides support for protected operating systems. Support for two levels of operation, known as system and user modes, allow application-critical code to operate in safety while user code is prevented from inadvertently disturbing the setup of the processor. Memory blocks as small as 4 KB can be write-protected against accidental writes by user code, and stack over/underflows can be trapped by high-priority interrupts.

Security features are also available in the Rabbit 6000. New instructions were added to the existing encryption support to increase encryption algorithm speeds dramatically, and 32 bytes of battery-backed RAM can store an encryption key away from prying eyes.

The Rabbit 6000 supports sixteen channels of DMA access to internal or external memory, internal I/O addresses, and the external I/O bus. Directing a DMA channel to or from an internal peripheral such as a serial port or the Ethernet port automatically connects DMA enable signals. Burst size, priority, and guaranteed cycles for the processor are all under program control. DMA operations to/from the internal memory and peripherals can operate simultaneously with code fetches, so no performance hit occurs. When accessing external memory, DMA operations will alternate between DMA and code fetches as in previous Rabbit designs.

The Rabbit 6000 contains an 802.11a/b/g wireless MAC peripheral, also designed to operate with the DMA peripheral. It includes support for all standard Wi-Fi features, including infrastructure and ad-hoc modes. The high-speed internal A/D converter and D/A converter and clocked-serial control port provide a generic interface to several common Wi-Fi transceivers. A low-speed A/D converter is also available to monitor the transmit signal strength if desired. The two A/D converters and single D/A converter are available for customer use when the Wi-Fi peripheral is disabled.

The Rabbit 6000 also contains a full-featured 10/100Base-T Ethernet MAC peripheral and PHY. Designed to operate with the DMA peripheral, the Ethernet peripheral is fully compliant with the 802.3 Ethernet standard, including support for auto-negotiation, link detection, multicast filtering, and broadcast addresses.

The Rabbit 6000 provides an Open Host Controller Interface (OHCI) USB device MAC and PHY. Fully supported by the DMA peripheral, the MAC and PHY are USB 2.0 compliant, full-speed (12 Mbit/s) devices.

Another new feature of the Rabbit 6000 is a 12-bit, 8-channel A/D converter. This A/D converter can run at up to 1 megasample per second, based on either the internal clock or an external clock input. The A/D converter is muxed across eight channels which can be sampled individually or continuously across all channels.

Rabbit 6000 User’s Manual digi.com 10

1.3 Block Diagram

Figure 1.1 Rabbit 6000 Block Diagram

Rabbit 6000 User’s Manual digi.com 11

1.4 Basic Specifications

Two versions of the Rabbit 6000 are available—the standard 292-ball BGA and a smaller 233-ball BGA for specialty Wi-Fi applications. The larger package is intended for most Rabbit applications; the smaller package has no address or data bus, and is intended for particular applications. If you need further information, please contact your Rabbit sales representative.

Table 1-1. Rabbit 6000 Specifications and Features

Package 292-ball BGA 233-ball BGA

Package Size

Operating Voltage

Operating Current (typ)

Operating Temp.

Maximum Clock Speed

Digital I/O

Network Interfaces

Serial Ports

Baud Rate

C Ports

Address Bus

Data Bus

Timers

17 mm × 17 mm × 1.3 mm 15 mm × 15 mm × 1.3 mm

1.2 V DC core, 3.3 V DC I/O ring

372 A/MHz @ 1.2 V/3.3 V, 25-200 MHz

(Wi-Fi and Ethernet disabled)

-40°C to +85°C

200 MHz

64+ (arranged in eight 8-bit ports)

10/100Base-T

802.11b/g Wi-Fi

6 CMOS-compatible 2 CMOS-compatible

Clock speed/8 max. asynchronous

24-bit None

8/16-bit None

Twelve 8-bit, one 10-bit with 2 match registers,

and one 16-bit with 8 match registers

Real-Time Clock

RTC Oscillator Circuitry

Watchdog Timer/Supervisor

Clock Modes

Power-Down Modes

External I/O Bus

A/D Converters

D/A Converters

* Limitations on the use of the 1MB internal RAM are present when running in lower CPU frequency or

sleepy modes. See Section 5.3.1, “Internal RAM”.

Rabbit 6000 User’s Manual digi.com 12

8 data, 8 address lines No

10-bit, 2 synchronous channels, up to 40 megasamples/s

10-bit, single channel, up to 1 megasamples/s

12-bit, eight multiplexed channels, up to 1 megasamples/s

10-bit, 2 synchronous channels, up to 80 megasamples/s

Yes, battery-backable

External

Ye s

1×, 2×, /2, /3, /4, /6, /8

Sleepy (32 kHz)

Ultra-Sleepy (16, 8, 4, 2 kHz)

1.5 Comparing Rabbit Microprocessors

The Rabbit 2000, Rabbit 3000, Rabbit 4000, Rabbit 5000, and Rabbit 6000 features are compared below.

Feature Rabbit 6000 Rabbit 5000 Rabbit 4000 Rabbit 3000 Rabbit 2000

Maximum Clock Speed, industrial

Maximum Clock Speed, commercial

Maximum Crystal Frequency Main Oscillator (may be increased internally up to maximum clock speed)

32.768 kHz Crystal Oscillator

200 MHz 100 MHz 60 MHz 55.5 MHz 30 MHz

200 MHz 100 MHz 60 MHz 58.8 MHz 30 MHz

24–42 MHz

(crystal)

20–200 MHz

100 MHz 60 MHz 30 MHz 30 MHz

(ext. clock)

External External External External Internal

Operating Voltage, core 1.2 V ± 10% 1.8 V ± 10% 1.8 V ± 10%

Operation Voltage, I/O

1.2 V ± 10%

3.3 V ± 10%

1.8 V ± 10%

3.3 V ± 10%

1.8 V ± 10%

3.3 V ± 10%

3.3 V ± 10% 5.0 V ± 10%

Maximum I/O Input Voltage 3.6 V 3.6 V 3.6 V 5.5 V 5.5 V

Current Consumption (32kHz – 200MHz)

0.37 mA/MHz @ 1.2 V/3.3 V

(Wi-Fi and

Ethernet

disabled)

0.57 mA/MHz @ 1.8 V/3.3 V

(Wi-Fi and

Ethernet

disabled)

0.35 mA/MHz

@ 3.3 V

2 mA/MHz

@ 3.3 V

4 mA/MHz

@ 5 V

Number of Package Pins 292/233 289/196 128 128 100

Size of Package, LQFP/

× 16 × 1.5 mm16 × 16 × 1.5 mm24 × 18 × 3

PQFP

N/A

Spacing Between Package Pins

Size of Package, BGA (mm) 17

Spacing Between Package Pins

× 17 ×

1.3 15 × 15 × 1.4 10 × 10 × 1.2 10 × 10 × 1.2

0.8 mm 0.8 mm 0.8 mm 0.8 mm

0.4 mm

(16 mils)

0.4 mm

(16 mils)

Separate Power and Ground for I/O Buffers

Ye s Ye s Ye s Ye s N o

(EMI reduction)

Clock Spectrum Spreader Yes Yes Yes Yes

Phase-Locked Loop

Clock Modes

Yes , u p t o

200MHz

1×, 2×, /2, /3,

/4, /6, /8

No No No No

1×, 2×, /2, /3,

/4, /6, /8

1×, 2×, /2, /3,

/4, /6, /8

1x, 2x, /2, /3

/4, /6, /8

0.65 mm (26 mils)

N/A

Rabbit 2000B/C

1x, 2x, /4, /8

Rabbit 6000 User’s Manual digi.com 13

Feature Rabbit 6000 Rabbit 5000 Rabbit 4000 Rabbit 3000 Rabbit 2000

Powerdown Modes, sleepy 32 kHz 32 kHz 32 kHz 32 kHz

32 kHz

Powerdown Modes, ultra sleepy

Low-Power Memory Control

16, 8, 4, 2 kHz

Short and

Self-Timed

Chip Selects

16, 8, 4, 2 kHz 16, 8, 4, 2 kHz 16, 8, 4, 2 kHz

Short and

Self-Timed

Chip Selects

Short and

Self-Timed

Chip Selects

Short and

Self-Timed

Chip Selects

None

Extended Memory Timing for High-Frequency

Ye s Ye s Ye s Ye s N o

Operation

Address Bus Size 24 bits 20–24 bits 20–24 bits 20 bits 20 bits

External Data Bus Size 8/16 bits 8/16 bits 8/16 bits 8 bits 8 bits

Internal Data Bus Size 16 bits 16 bits 8 bits 8 bits 8 bits

Internal RAM

1 MB + 32KB

battery-backed

128KB None None None

Number of 8-bit I/O Ports86575

External I/O Data/Address Bus

Ye s Ye s Ye s Ye s N on e

Number of Serial Ports66664

DMA Channels 16 8 8 None None

Serial Ports Capable of SPI/Clocked Serial

Serial Ports Capable of SDLC/HDLC

4 (A, B, C, D) 4 (A, B, C, D) 4 (A, B, C, D) 4 (A, B, C, D) 2 (A, B)

2 (E, F) 2 (E, F) 2 (E, F) 2 (E, F) None

Asynch Serial Ports With Support for

6666None

IrDA Communication

Serial Ports with Support for SDLC/HDLC IrDA

2 (E,F) 2 (E,F) 2 (E,F) 2 (E,F) None

Communication

Serial Ports with 4-Byte FIFO

Maximum Asynchronous Baud Rate

Hardware I

C Ports

Ethernet Port

6 2 (E,F) 2 (E,F) 2 (E,F) None

Clock speed/8 Clock Speed/8 Clock Speed/8 Clock Speed/8

1 None None None None

10/100Base-T

with PHY

10/100Base-T

(MAC only)

10Base-T

(partial PHY)

None None

Clock Speed/32

Wi-Fi (802.11a/b/g) Yes Yes No No No

USB (2.0 compatible) Full-speed host No No No No

PWM Outputs 4444None

Rabbit 6000 User’s Manual digi.com 14

Feature Rabbit 6000 Rabbit 5000 Rabbit 4000 Rabbit 3000 Rabbit 2000

Va r ia b l e -P h a se PWM Outputs (PPM)

4 4 4 None None

Input Capture Units 2222None

External Interrupts/Vectors 22/8 6/2 6/2 4/2 4/2

Quadrature Decoders 2 channels 2 channels 2 channels 2 channels None

Flexible Interface Modules 2 None None None None

Hardware Breakpoints 7 7 7 None None

User A/D Converter Channels

A/D Converter Channels (Wi-Fi disabled)

D/A Converter Channels (Wi-Fi disabled)

* Limitations on the use of the 1MB internal RAM are present when running in lower CPU frequency or

sleepy modes. See Section 5.3.1, “Internal RAM”.

8 None None None None

3 3 None None None

2 2 None None None

Rabbit 6000 User’s Manual digi.com 15

2. CLOCKS

2.1 Overview

The Rabbit 6000 supports up to five separate clocks at once—the main clock, the 32 kHz clock, the 20 MHz Wi-Fi clock, the 25 MHz Ethernet clock, and the 48 MHz USB clock. The main clock is used to drive the processor clock and the peripheral clock inside the processor. The 32 kHz clock is used to drive the asynchronous serial bootstrap, the real-time clock, the periodic interrupt, and the watchdog timers.

The 32 kHz clock input requires an external clock signal; the remaining clock inputs have internal oscillators that can be driven with just an external crystal. If desired, each of the remaining clock inputs can also be used with an external clock as well, bypassing the internal oscillator.

The Ethernet peripheral can be driven from the main clock instead of the PHY clock input, removing the need for separate main and Ethernet clocks. When this feature is enabled, the main clock must be 25 MHz for proper Ethernet operation.

The main clock can be fed into a phase-locked loop (PLL), generating CPU and peripheral clocks in the range of 150–200 MHz, depending on the input clock and PLL settings. This clock can be further adjusted by the clock divider if desired. Dividers exist for most peripherals to scale their clocks over a wide range of frequencies.

The Rabbit 6000 has a spectrum spreader on the main clock that shortens and lengthens clock cycles. This has the net effect of reducing the peak energy of clock harmonics by spreading the spectral energy into nearby frequencies, which reduces EMI and facilitates government-mandated EMI testing. Gated clocks are used whenever possible to avoid clocking unused portions of the processor, and separate power-supply pins for the core and I/O ring further reduce EMI from the Rabbit 6000. Note that the spectrum spreader is not usable at main clock frequencies above 115 MHz because of the short period.

The main clock can be doubled or divided by 2, 4, 6, or 8 to reduce EMI and power consumption. The 32 kHz clock (which can be divided by 2, 4, 8, or 16) can be used instead of the main clock to generate processor and peripheral clocks as low as 2 kHz for significant power savings. Note that dividing the 32 kHz clock only affects the processor and peripheral clocks; the full 32 kHz signal is still provided to the realtime clock and watchdog timer peripherals that use it directly. The periodic interrupt is disabled automatically since there is not enough time to process it when it is running off the 32 kHz clock. Also, note that the internal RAM content will not be maintained at CPU frequencies below 12MHz.

There is also a 25 MHz Ethernet oscillator that connects directly to the Ethernet PHY if you are using the Ethernet option, but want a different main clock frequency. See Chapter 25 for more details on the Ethernet clock.

The Wi-Fi peripheral requires a 20 MHz clock input, which goes to a dedicated PLL to produce the required clocks for the 802.11a/b/g peripheral. The USB peripheral requires a 48 MHz clock for proper operation.

Rabbit 6000 User’s Manual digi.com 16

2.1.1 Block Diagram

2.1.2 Registers

Global Control/Status Register GCSR 0x0000 R/W 11000000

Global Clock Modulator 0 Register GCM0R 0x000A W 00000000

Global Clock Modulation 1 Register GCM1R 0x000B W 00000000

Global Clock Double Register GCDR 0x000F R/W 00000000

Master System Configuration Register MSCR 0x0434 R/W 00000000

Master System Status Register MSSR 0x0435 R/W 00000x00

Rabbit 6000 User’s Manual digi.com 17

2.2 Dependencies

2.2.1 I/O Pins

The main, Wi-Fi, Ethernet, and USB clocks contain a bypassable internal oscillator, so either a crystal or an external clock input can be used. The selection of a crystal or an external signal for the main oscillator is determined by the state of the CFG pins on startup, and by the Master System Status Register (MSSR). The Ethernet clock source (main clock or PHY oscillator) is selected in the Master System Configuration Register (MSCR). Table 2-1 lists the pins assigned to each clock and how they are controlled.

Table 2-1. Clock Pin Assignments

Clock Frequency Crystal Pins

External Clock

Signal Pins

Crystal/External

Clock Selection by

24 –42 MHz

Main Clock

(crystal)

20–200 MHz

(external

CLK_HSI

CLK_HSO

CFG pins

(see chapter 3)

clock)

W-Fi Clock 20 MHz

Ethernet Clock 25 MHz

USB Clock 48 MHz

XTL_20MI

XTL_20MO

XTL_25MI

XTL_25MO

XTL_48MI

XTL_48MO

XTL_20MO MSSR

XTL_25MO —

XTL_48MO MSSR

32 kHz Clock 32 kHz — CLK_32K —

The 32 kHz clock input is on the CLK_32K pin. There is an internal Schmitt trigger on this pin to reduce sensitivity to noise.

The peripheral clock or peripheral clock divided by 2 may be optionally output on the CLK pin by enabling it via bits 7–6 in GOCR.

Rabbit 6000 User’s Manual digi.com 18

2.2.2 Other Registers

GOCR Used to set up the CLK output pin.

Used to:

MSCR

- select clock input or PLL output for CPU clock

- select main clock or external 25 MHz clock for Ethernet

- select CPU clock or PLL output for Flexible Interface Modules

MSSR

Used to select crystal or external oscillator for Wi-Fi and USB clocks, and read main and Wi-Fi PLL status.

GCM0R, GCM1R Used to select the main PLL loop and pre-divider values.

GCDR Used to enable the main PLL.

ENPR Used to enable the Wi-Fi PLL (automatic when Wi-Fi is enabled).

Rabbit 6000 User’s Manual digi.com 19

2.3 Operation

2.3.1 Main Clock

The main clock is based on the main oscillator output, which in turn is driven by the CLK_HSI and CLK_HSO pins. This output serves as the input for the main PLL, which can be programmed for various frequencies or bypassed completely. There is an option for the resulting output to then be sent through the spectrum spreader and then the clock doubler, which are described later. This resulting clock is the main clock.

Different main clock modes may be selected via the GCSR, as shown in Table 2-2. Note that one GCSR setting slows the processor clock while the peripheral clock operates at full speed; this allows some power reduction while keeping settings like serial baud rates and the PWM at their desired values.

Table 2-2. Clock Modes

GCSR Setting Processor Clock Peripheral Clock

xxx010xx Main clock Main clock

xxx011xx Main clock / 2 Main clock / 2

xxx110xx Main clock / 4 Main clock / 4

xxx111xx Main clock / 6 Main clock / 6

xxx000xx Main clock / 8 Main clock / 8 (default on startup)

xxx001xx Main clock / 8 Main clock

xxx100xx 32 kHz clock (possibly divided)

32 kHz clock (possibly divided);

xxx101xx

When the 32 kHz clock is enabled in GCSR, it can be further divided by 2, 4, 8, or 16 to generate even lower frequencies by enabling those modes in bits 0–2 of GPSCR. See Table 2-6 for more details.

main clock disabled via CLKIEN output signal

32 kHz clock (possibly divided via GPSCR)

Rabbit 6000 User’s Manual digi.com 20

2.3.2 Main PLL

The main PLL is optimally tuned for a 25 MHz clock input and to produce a 400 MHz output, which can be fed directly to the Flexible Interface Modules (FIMs), and is divided by two to 200 MHz for processor and peripheral operation. Note that the main PLL can be bypassed if lower frequencies are desired.

The main PLL is enabled in GCDR, but is not selected as the main clock until enabled in MSCR. If the 32 kHz clock is present, then the switchover to the PLL output for the main clock will not occur until 200 µs after the bit is enabled in MSCR to allow the PLL output to stabilize. The status of the main PLL (stable output or not) can be read in bit 0 of MSSR.

The main PLL input clock is restricted to 20–200 MHz, and the output frequency range is limited to 300– 400 MHz. There are further restrictions on the internal frequency

The main PLL divider values are located in GCM0R and GCM1R. These should be set to a nonzero value before enabling the PLL. Some suggested PLL settings are described in Table 2-3, chosen to match other clock requirements in the design to allow clock sharing. If other PLL settings are desired, please contact your sales representative at Digi International.

Table 2-3. Suggested PLL Modes

Input Clock

Main Clock

(max)

FIM Clock

(max)

GCM0R

Setting

GCM1R

Setting

20 MHz 150 MHz 300 MHz xxx10000 xxxx0001

20 MHz 200 MHz 400 MHz xxx10100 xxxx0001

25 MHz 150 MHz 300 MHz xxx01100 xxxx0001

25 MHz 200 MHz 400 MHz xxx10000 xxxx0001

48 MHz 156 MHz 312 MHz xxx01101 xxxx0010

48 MHz 192 MHz 384 MHz xxx10000 xxxx0010

Note that if the PLL is enabled, restrictions may exist for the use of the spectrum spreader and clock doubler. The following sections provide more details.

Rabbit 6000 User’s Manual digi.com 21

2.3.3 Spectrum Spreader

When enabled, the spectrum spreader stretches and compresses the main clock in a complex pattern that spreads the energy of the clock harmonics over a wider range of frequencies. Note that the spectrum spreader cannot operate at frequencies above 115 MHz as it uses up too much of the available clock period, so care must be exercised when using the main PLL.

Figure 2.1 Effects of Spectrum Spreader

There are three settings that correspond to normal and strong spreading in the 0–50 MHz and >50 MHz main clock range. Each setting will affect the clock cycle differently; the maximum cycle shortening (at

1.8 V and 25°C) is shown in Table 2-4 below.

Table 2-4. Spectrum Spreader Settings

0–50 MHz 50 - 150 MHz

— Normal 01xxxxxx

GCM0R

Value

Description

Normal spreading of frequencies over 50 MHz

Max. Cycle Shortening

2.3 ns

Normal spreading of frequencies

Normal Strong 00xxxxxx

up to 50 MHz; strong spreading of

3 ns

frequencies over 50 MHz

Strong spreading of frequencies up

Strong — 10xxxxxx

to 50 MHz; normal spreading of

4.5 ns

frequencies over 50 MHz

Rabbit 6000 User’s Manual digi.com 22

The spectrum spreader either stretches or shrinks the low plateau of the clock by a maximum of 3 ns for the

10050 200150 250

350

300

Normal Spreading

Strong Spreading

Frequency (MHz)

Harmonics (dB)

normal spreading and up to 4.5 ns for the strong spreading. If the clock doubler is used, this will cause an additional asymmetry between alternate clock cycles.

Both normal and strong modes reduce clock harmonics by approximately 15 dB for frequencies above 100 MHz; for lower frequencies the strong setting has a greater effect in reducing the peak spectral strength as shown in Figure 2.2.

Figure 2.2 Peak Spectral Amplitude Reduction by Spectrum Spreader

Two registers control the clock spectrum spreader. These registers must be loaded in a specific manner with proper time delays. GCM0R is only read by the spectrum spreader at the moment when the spectrum spreader is enabled by setting bit 7 of GCM1R. If bit 7 of GCM1R is cleared (when disabling the spectrum spreader), there is up to a 500-clock delay before the spectrum spreader is actually disabled. The proper procedure is to clear GCM1R, wait for 500 clocks, set GCM0R, and then enable the spreader by writing a 1 to bit 7 of GCM1R.

The spectrum spreader is applied to the main clock before the clock doubler, so if both are enabled there will be additional asymmetry between alternate clock cycles.If the clock doubler is used, the spectrum spreader affects every other cycle and reduces the clock high time. If the doubler is not used, then the spreader affects every clock cycle, and the clock low time is reduced.

Rabbit 6000 User’s Manual digi.com 23

2.3.4 Clock Doubler

The clock doubler allows a lower frequency crystal to be used for the main oscillator and to provide an added range over which the clock frequency can be adjusted. The clock doubler is controlled via the Global Clock Double Register (GCDR).

The clock doubler uses an on-chip delay circuit that must be programmed by the user at startup if there is a need to double the clock. Table 2-5 lists the recommended delays in GCDR for various oscillator or crystal frequencies.

Table 2-5. Recommended Delays Set In GCDR for Clock Doubler

Recommended GCDR Value Frequency Range

0x0F 7.3728 MHz

0x0B 7.3728–11.0592 MHz

0x09 11.0592–16.5888 MHz

0x06 16.5888–20.2752 MHz

0x03 20.2752–52.8384 MHz

0x01 52.8384–77.4144 MHz

0x00 >77.4144 MHz

Rabbit 6000 User’s Manual digi.com 24

When the clock doubler is used and there is no subsequent division of the clock, the output clock will be asymmetric, as shown in Figure 2.3.

Figure 2.3 Effect of Clock Doubler

The doubled-clock low time is subject to wide (50%) variation since it depends on process parameters, temperature, and voltage. The times given above are for a core supply voltage of 1.8 V and a temperature of 25°C. The values increase or decrease by 1% for each 5°C increase or decrease in temperature. The doubled clock is created by xor’ing the delayed and inverted clock with itself. If the original clock does not have a 50-50 duty cycle, then alternate clocks will have a slightly different length. Since the duty cycle of the built-in oscillator can be as asymmetric as 52%/48%, the clock generated by the clock doubler will exhibit up to a 4% variation in period on alternate clocks. The memory access time is not affected because the memory bus cycle is 2 clocks long and includes both a long and a short clock, resulting in no net change due to asymmetry. However, if an odd number of wait states is used, then the memory access time will be affected slightly.

Rabbit 6000 User’s Manual digi.com 25

The maximum allowed clock speed must be reduced slightly if the clock is supplied via the clock doubler. The only signals clocked on the falling edge of the clock are the memory and I/O write pulses, and the early option memory output enable. See Chapter 5 for more information on the early output enable and write enable options.

The power consumption is proportional to the clock frequency, and for this reason power can be reduced by slowing the clock when less computing activity is taking place. The clock doubler provides a convenient method of temporarily speeding up or slowing down the clock as part of a power management scheme.

2.3.5 32 kHz Clock

The 32.768 kHz clock is used to drive the asynchronous serial bootstrap, the real-time clock, the periodic interrupt, and the watchdog timers; see Section 4.3 for detailed descriptions of these features. If these features are not used in a design, the use of the 32 kHz clock is optional.

A self-contained external oscillator is the recommended oscillator circuit for the Rabbit 6000, but a tunable oscillator circuit such as the one shown below may be used. The values of resistors and capacitors may need to be adjusted for various frequencies and crystal load capacitances. Rabbit’s Technical Note TN235,

External 32.768 kHz Oscillator Circuits, is available on the Rabbit Web site and goes into this circuit

in detail.

Figure 2.4 Basic 32.768 kHz Oscillator Circuit

Rabbit 6000 User’s Manual digi.com 26

The 32.768 kHz circuit consumes microampere-level currents and has a very high impedance, making it susceptible to noise, moisture, and environmental contaminants. It is strongly recommended to conformally coat this circuit to limit the effects of humidity and dust on the oscillation frequency. Details about this requirement are available in Technical Note TN303, “Conformal Coating”, from the Rabbit Web site. The need for a conformal coating can be avoided by using a single external clock chip.

The 32.768 kHz oscillator is slow to start oscillating after power-on. The startup delay may be as much as 5 seconds. For this reason, a wait loop in the BIOS waits until this oscillator is oscillating regularly before continuing the startup procedure. If the clock is battery-backed, there will be no startup delay since the oscillator is already oscillating. Crystals with low series resistance (R < 35 k) will start faster.

The 32 kHz oscillator can be used to drive the processor and the peripheral clock to provide significant power savings in “ultra-sleepy” modes. The 32 kHz oscillator can be divided by 2, 4, 8, or 16 to provide clock speeds as low as 2.048 kHz, although there are limitations on use of the 1MB internal RAM at those low clock speeds (See Section 5.3.1, “Internal RAM”). Special self-timed chip selects are available to keep the memory devices enabled for as short a time as possible when an ultra-sleepy mode is enabled; see Chapter 36 for more details on reducing power consumption.

Table 2-6. Ultra-Sleepy Clock Modes

GPSCR

Setting

Processor and

Peripheral Clock

xxxxx000 32.768 kHz

xxxxx100 16.384 kHz

xxxxx101 8.192 kHz

xxxxx110 4.096 kHz

xxxxx111 2.048 kHz

When the 32 kHz clock is enabled as the CPU clock, the periodic interrupt is disabled automatically. The real-time clock and watchdog timers keep running, and use the full 32 kHz clock speed even when the processor and peripheral clocks use a divider on the 32 kHz clock.

Rabbit 6000 User’s Manual digi.com 27

2.4 Register Descriptions

Global Control/Status Register (GCSR) (Address = 0x0000)

Bit(s) Value Description

7:5 000 No reset or watchdog timer timeout since the last read.

(rd-only) 010

110

111

(write)

0 No effect on the Periodic interrupt.

1 Force a Periodic interrupt to be pending.

4:2 000

001

010

011

100

The watchdog timer timed out. These bits will be cleared by reading the register.

Hardware reset occurred. These bits will be cleared by reading the register.

Power-on reset occurred. These bits will be cleared by reading the register.

Processor clock from the main clock, divided by 8. Peripheral clock from the main clock, divided by 8.

Processor clock from the main clock, divided by 8. Peripheral clock from the main clock.

Processor clock from the main clock. Peripheral clock from the main clock.

Processor clock from the main clock, divided by 2. Peripheral clock from the main clock, divided by 2.

Processor clock from the 32 kHz clock, optionally divided via GPSCR. Peripheral clock from the 32 kHz clock, optionally divided via GPSCR.

Processor clock from the 32 kHz clock, optionally divided via GPSCR.

101

Peripheral clock from the 32 kHz clock, optionally divided via GPSCR. The main clock is disabled.

110

111

Processor clock from the main clock, divided by 4. Peripheral clock from the main clock, divided by 4.

Processor clock from the main clock, divided by 6. Peripheral clock from the main clock, divided by 6.

1:0 00 Periodic interrupts are disabled.

01 Periodic interrupts use Interrupt Priority 1.

10 Periodic interrupts use Interrupt Priority 2.

11 Periodic interrupts use Interrupt Priority 3.

Rabbit 6000 User’s Manual digi.com 28

Global Clock Modulator 0 Register (GCM0R) (Address = 0x000A)

Bit(s) Value Description

7:6 00

Clock dither in 1 ns steps, from 0 ns to 26 ns. Do not modify while the dither function is enabled.

01 Clock dither in 0.5 ns steps, from 0 ns to 13 ns.

10 Clock dither in 2 ns steps, from 0 ns to 52 ns.

11 This bit combination is reserved and must not be used.

5:4 These bits are reserved and should be written with zeros.

System PLL loop divider value. All zeros is not a valid value for the PLL loop divider. The PLL output frequency is the input frequency divided by

4:0

the value of the PLL pre-divider, and multiplied by the value of the PLL loop divider. Neither divider value should not be modified while the PLL is supplying the clock to the system.

Global Clock Modulator 1 Register (GCM1R) (Address = 0x000B)

Bit(s) Value Description

Disable the clock dither function. The disable does not take effect until the dither pattern has returned to the 0 ns base delay value.

1 Enable the clock dither function.

6:5 These bits are reserved and should be written with zeros.

System PLL pre-divider value. All zeros is not a valid value for the PLL

3:0

pre-divider. Neither divider value should not be modified while the PLL is supplying the clock to the system.

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Global Clock Double Register (GCDR) (Address = 0x000F)

Bit(s) Value Description

7 0 Disable system PLL.

Enable system PLL. Setting this bit does not select the system PLL as the clock source.

6:5 These bits are reserved and should always be written with zeros.

4:0 00000 The clock doubler circuit is disabled.

00001 9 nS nominal Low time.

00010 10.5 nS nominal Low time.

00011 12 nS nominal Low time.

00100 13.5 nS nominal Low time.

00101 15 nS nominal Low time.

00110 16.5 nS nominal Low time.

00111 18 nS nominal Low time.

01000 19.5 nS nominal Low time.

01001 21 ns nominal Low time.

01010 22.5 ns nominal Low time.

01011 24 ns nominal Low time.

01100 25.5 ns nominal Low time.

01101 27 ns nominal Low time.

01110 28.5 ns nominal Low time.

01111 30 ns nominal Low time.

10001 4.5 nS nominal Low time.

10010 6 nS nominal Low time.

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Global Output Control Register (GOCR) (Address = 0x000E)

Bit(s) Value Description

7:6 00 CLK pin is driven with peripheral clock.

01 CLK pin is driven with peripheral clock divided by 2.

10 CLK pin is low.

11 CLK pin is high.

5:4 00 STATUS pin is active (low) during a first opcode byte fetch.

01 STATUS pin is active (low) during an interrupt acknowledge.

10 STATUS pin is low.

11 STATUS pin is high.

3:2 00 /WDTOUT pin functions normally.

01 Enable /WDTOUT for test mode. Reserved for internal use only.

10 /WDTOUT pin is low (1 cycle min, 2 cycles max, of 32 kHz).

11 This bit combination is reserved and should not be used.

1:0 00 /BUFEN pin is active (low) during external I/O cycles.

01 /BUFEN pin is active (low) during data memory accesses.

10 /BUFEN pin is low.

11 /BUFEN pin is high.

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Master System Configuration Register (MSCR) (Address = 0x0434)

Bit(s) Value Description

7 0 CPU clock direct from oscillator.

CPU clock from system PLL output (divided by two). Response to this

setting may be delayed until the PLL output is stable (roughly 200 µs after enabling the system PLL, uses 32 kHz clock to generate delay).

6 This bit is reserved and should be written as zero.

5 0 Clock on-chip 10/100 PHY from system oscillator.

Enable embedded oscillator in the internal 10-100 PHY. If using this

option, the oscillator must be enabled at least 500 ns before the PHY is enabled in ENPR. This delay must be created in software.

4 0 No reset of the internal 10/100 PHY. Reads always return zero.

(Write-

only)

Reset the internal 10/100 PHY hardware. This command must not be issued until at least 600 ms after the internal PHY has been enabled in ENPR. This delay must be created in software.

3:2 00 FIMB clock is disabled.

01 FIMB clock is identical to the CPU clock.

10 This bit combination is reserved and should not be used.

FIMB clock from system PLL output. Response to this setting may be

delayed until the PLL output is stable (roughly 200 us after enabling the system PLL, uses 32 kHz clock to generate delay).

1:0 00 FIMA clock is disabled.

01 FIMA clock is identical to the CPU clock.

10 This bit combination is reserved and should not be used.

FIMA clock from system PLL output. Response to this setting may be

delayed until the PLL output is stable (roughly 200 µs after enabling the system PLL, uses 32 kHz clock to generate delay).

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Master System Status Register (MSSR) (Address = 0x0435)

Bit(s) Value Description

7:6 These bits are reserved and should be written with zeros.

5 0 Direct Wi-Fi clock input.

1 Enable Wi-Fi crystal oscillator.

4 0 Direct USB clock input.

1 Enable USB crystal oscillator.

3 0 Normal operation.

(Read-

only)

1 Small package address and data bus option enabled (TEST = 0xF or 0xC).

2 0 Large package.

(Read-

only)

1 Small package.

1 0 Wi-Fi PLL not enabled or output not stable.

(Read-

only)

1 Wi-Fi PLL is enabled, with stable output.

0 0 System PLL not enabled or output not stable.

(Read-

only)

1 System PLL is enabled, with stable output.

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Enable Network Port Register (ENPR) (Address = 0x0430)

Bit(s) Value Description

7 0 Disable Network Port C (the Wi-Fi port).

1 Enable Network Port C (the Wi-Fi port).

6 0 Disable Network Port B (the 10/100Base-T Ethernet port).

1 Enable Network Port B (the 10/100Base-T Ethernet port).

5 0 Disable Network Port D (the USB port).

1 Enable Network Port D (the USB port).

Internal 10/100 PHY. This bit is ignored unless bit 6 of this register is also set, at which point the internal PHY is powered up.

1 External 10/100 PHY.

3:2 00 Network Port D interrupts are disabled.

01 Network Port D interrupts use Interrupt Priority 1.

10 Network Port D interrupts use Interrupt Priority 2.

11 Network Port D interrupts use Interrupt Priority 3.

1:0 00 Network Port C interrupts are disabled.

01 Network Port C interrupts use Interrupt Priority 1.

10 Network Port C interrupts use Interrupt Priority 2.

11 Network Port C interrupts use Interrupt Priority 3.

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3. RESET AND BOOTSTRAP

3.1 Overview

The Rabbit 6000’s /RESET pin initializes everything in the processor except for the real-time clock registers, the contents of the battery-backed onchip-encryption RAM and the 32K battery-backed SRAM. If a write cycle is in progress, it waits until the write cycle is completed to avoid potential memory corruption.

After reset, the Rabbit 6000 checks the state of the SMODE and SYSCFG pins. Depending on the state of the SMODE pins, it either begins normal operation by fetching instruction bytes from memory bank zero, which is mapped to either /CS0 or /CS3 depending on the state of the SYSCFG pin, or it enters a special bootstrap mode where it fetches bytes from either Serial Port A or the slave port. In this mode, bytes can be written to internal registers to set up the Rabbit 6000 for a particular configuration, or to memory to load a program. The processor can begin normal operation once the bootstrap operation is completed.

Rabbit 6000 User’s Manual digi.com 35

3.1.1 Block Diagram

3.1.2 Registers

Slave Port Control Register SPCR 0x0024 R/W 0xx00000

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3.2 Dependencies

3.2.1 I/O Pins

SMODE0, SMODE1 — When the Rabbit 6000 is first powered up or when it is reset, the state of the SMODE0 and SMODE1 pins controls its operation.

SYSCFG — When the Rabbit 6000 is first powered up or when it is reset, the state of this pin controls whether memory bank zero is mapped to /CS0 or the internal SRAM (/CS3).

/RESET — Pulling the /RESET pin low will initialize everything in the Rabbit 6000 except for the realtime clock registers, the 32K battery-backed RAM and the onchip-encryption RAM.

/CS1 — During reset the impedance of the /CS1 pin is high, and all other memory and I/O control signals are held high. The special behavior of /CS1 allows an external RAM to be powered by the same source as the VBATIO pin (which powers /CS1). In this case, a pullup resistor is required on /CS1 to keep the RAM deselected during powerdown.

RESOUT — The RESOUT pin, which is powered by the backup battery, is high during reset and powerdown as long as VBAT and VBATIO are present, but low at all other times, and can be used to control an external power switch to disconnect VDDIO from VBATIO when the main power source is removed.

3.2.2 Clocks

The processor requires a 32 kHz clock input to generate the 2400 bps internal clock required for asynchronous serial bootstrap, which is used when booting via Dynamic C and the Rabbit Field Utility. No 32 kHz clock is required for either clocked serial or slave port bootstrap.

When the processor comes out of reset, the CPU clock and peripheral clocks are both in divide-by-8 mode.

3.2.3 Other Registers

SPCR

Enable/disable processor monitoring of SMODE pins; read current state of SMODE pins.

3.2.4 Interrupts

There are no interrupts associated with reset or bootstrap.

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3.3 Operation

Pulling the /RESET pin low will initialize everything in the Rabbit 6000 except for the real-time clock registers, the 32K battery-backed RAM and the onchip-encryption RAM. The reset of the Rabbit 6000 is delayed until any write cycles in progress are completed; the reset takes effect as soon as no write cycles are occurring. The reset sequence requires a minimum of 128 cycles of the main clock to complete in either case.

During reset, the impedance of the /CS1 pin is high and all other memory and I/O control signals are held high. The special behavior of /CS1 allows an external RAM to be powered by the same source as the VBATIO pin (which powers /CS1). In this case, a pullup resistor is required on /CS1 to keep the RAM deselected during powerdown. The RESOUT pin, which is powered by the backup battery, is high during reset and powerdown as long as VBAT and VBATIO are present, but low at all other times, and can be used to control an external power switch to disconnect VDDIO from VBATIO when the main power source is removed.

Table 3-1 lists the condition of the processor after reset takes place. The state of all registers after reset is provided in the chapter describing the specific peripheral.

Table 3-1. Rabbit 6000 Condition After Reset

Function Operation After Reset

CPU Clock, Peripheral Clock

Clock Doubler, Clock Dither

Memory Bank 0 Control Register

Memory Advanced Control Register

Divide-by-8 mode

Disabled

/CS0, /OE0, write-protected,

4 wait states

8-bit interface

CPU Registers: PC, SP, IIR, EIR,

0x0000

HTR

Interrupt Priority (IP Register)

0xFF (Priority 3)

Watchdog Timer Enabled (2 seconds)

Secondary Watchdog Timer

Disabled

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The processor checks the SMODE and SYSCFG pins after the /RESET signal is inactive. Table 3-2 summarizes what happens.

Table 3-2. SMODE Pin Settings

SMODE Pins [1,0] SYSCFG Operation

No bootstrap; code is fetched from address 0x0000

00 0

on /CS0, /OE0.The internal SRAM is enabled as a 16-bit memory device.

No bootstrap; code is fetched from address 0x0000

00 1

on /CS3, /OE0. The internal SRAM is enabled as a 16-bit memory device.

01 x Bootstrap from the slave port.

10 x Bootstrap from Serial Port A, serial flash mode.

11 x Bootstrap from Serial Port A, asynchronous mode.

If both SMODE pins are zero, the Rabbit 6000 begins fetching instructions from the memory device mapped into memory bank 0. When SYSCFG is low, memory bank 0 is set to /CS0 and /OE0. If SYSCFG is high, memory bank 0 is set to /CS3 and /OE0. In both cases, the internal SRAM is selected in 16-bit mode. If a 16-bit memory is used in memory bank 0, the first section of code must immediately select the 16-bit bus mode. Chapter 5 provides a short sample program to do this.

If either of the SMODE pins is high, the processor will enter the bootstrap mode and accept triplets from Serial Port A, the serial flash bootstrap port, or the slave port, depending on the SMODE pin selection. It is good practice to place pulldown resistors on the SMODE pins to ensure the proper operation of your design.

In the bootstrap mode, the processor inhibits the normal memory fetch, and instead fetches instructions from a small internal boot ROM. This program reads triplets of three bytes from the selected peripheral. The first byte is the most-significant byte of a 16-bit address, the second byte is the least-significant byte of the address, and the third byte is the data to be written. If the uppermost bit of the address is 1, then the address is assumed to be an internal register address instead of a memory address, and the data are written to the appropriate register instead. For example, a triplet of (0x04, 0x34, 0x5A) will write 0x5A to logical memory address 0x0434, while a triplet of (0x80, 0x34, 0x5A) will write 0x5A to processor register 0x34. Processor registers with addresses above 0xFF are not accessible in the bootstrap mode.

The boot ROM program waits for data to be available; each byte received automatically resets the watchdog timer with a 2-second timeout. Bytes must be received quickly enough to prevent timeout (or the watchdog must be disabled).

The device checks the state of the SMODE pins each time it jumps back to the start of the ROM program and responds according to the current state. In addition, by setting bit 7 of the Slave Port Control Register (SPCR) high, the processor can be told to ignore the state of the SMODE pins and continue normal operation.

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Note that the processor can be told to re-enter bootstrap mode at any time by setting bit 7 of SPCR low; once this occurs and the least significant four bits of the current PC address are zero, the processor will sample the state of the SMODE pins and respond accordingly. This feature allows in-line downloading from the selected bootstrap port; once the download is complete, bit 7 of SPCR can be set high and the processor will continue operating from where it left off.

As a security feature, any attempt to enter the bootstrap mode from either the SMODE pins or by writing to bit 7 of the SPCR will erase the data stored in the onchip-encryption RAM. This prevents loading a small program in memory to read out the data.

3.3.1 Asynchronous Serial Bootstrap

When the asynchronous serial bootstrap mode is selected by the SMODE pins, the Rabbit 6000 will begin accepting triplets at 2400 bps on Serial Port A. The baud rate is generated from the 32 kHz clock input, so a 32 kHz clock is required for this mode.

3.3.2 Serial Flash Bootstrap

When the serial flash bootstrap mode is selected by the SMODE pins, the Rabbit 6000 will enable the SPI serial flash bootstrap port on pins PD4, PD5, PD6, and PB0; the pins’ functionality is listed in Table 3-3 below. Note that these pins can be used for Serial Port B in normal operation, so the serial flash may be accessed with that serial port during normal operation.

Table 3-3. Serial Flash Bootstrap Pin Functions

Pin SPI Signal Operation

PD4 MOSI Rabbit data transmit (to serial flash)

PD5 MISO Rabbit data receive (from serial flash)

PD6 CS Chip select (to serial flash)

PB0 SCK Serial clock (output to serial flash)

The Rabbit 6000 divides the main clock by 64 to provide the SPI clock for the serial flash bootstrap. Once this mode is entered, the Rabbit 6000 will send the byte sequence “0x03 0x00 0x00 0x00”, which is an industry-standard command that enables continuous read mode starting at serial flash address 0x0. Figure 3.1 provides a sample timing diagram. The Rabbit 6000 will then read triplets out of the serial flash until the bootstrap mode is exited.

Figure 3.1 SPI Timing Diagram for Serial Flash Bootstrap Mode

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3.3.3 Parallel Bootstrap

When the parallel bootstrap mode is selected by the SMODE pins, the Rabbit 6000 will enable the parallel slave port interface on Parallel Ports A and B, and will wait for triplets to be sent to that interface. See Chapter 21 for more details on the operation of the slave port.

3.4 Register Descriptions

Slave Port Control Register (SPCR) (Address = 0x0024)

Bit(s) Value Description

7 0 Program fetch as a function of the SMODE pins.

1 Ignore the SMODE pins program fetch function.

6:5 Read These bits report the state of the SMODE pins.

Write These bits are ignored and should be written with zero.

4:2 000 Disable the slave port. Parallel Port A is a byte-wide input port.

001 Disable the slave port. Parallel Port A is a byte-wide output port.

010 Enable the slave port, with /SCS from Parallel Port E bit 7.

011

Enable the external I/O bus. Parallel Port A is used for the data bus and Parallel Port B[7:2] is used for the address bus.

100 This bit combination is reserved and should not be used.

101 This bit combination is reserved and should not be used.

110 Enable the slave port, with /SCS from Parallel Port B bit 6.

111

Enable the external I/O bus. Parallel Port A is used for the data bus and Parallel Port B[7:0] is used for the address bus.

1:0 00 Slave port interrupts are disabled.

01 Slave port interrupts use Interrupt Priority 1.

10 Slave port interrupts use Interrupt Priority 2.

11 Slave port interrupts use Interrupt Priority 3.

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4. SYSTEM MANAGEMENT

4.1 Overview

There are a number of basic system peripherals in the Rabbit 6000 processor, some of which are covered in later chapters. The peripherals covered in this chapter are the periodic interrupt, the real-time clock, the watchdog timers, the battery-backed onchip-encryption RAM, and some of the miscellaneous output pins and their control and processor registers that provide the processor ID and revision numbers.

The periodic interrupt, when enabled, is generated every 16 clocks of the 32 kHz clock (every 488 µs, or

2.048 kHz). This interrupt can be used to perform periodic tasks.

The real-time clock (RTC) consists of a 48-bit counter that is clocked by the 32 kHz clock. It is powered by the VBAT pin, and so can be battery-backed. The value in the counter is not affected by reset, and can only be set to zero by writing to the RTC control register. The 48-bit width provides a 272-year span before rollover occurs.

There are two watchdog timers in the Rabbit 6000, both clocked by the 32 kHz clock. The main watchdog timer can be set to time out from 250 ms to 2 seconds, and resets the processor if not reloaded within that time. Its purpose is to restart the processor when it detects that a program gets stuck or disabled.

The secondary watchdog timer can time out from 30.5 µs up to 7.8 ms, and generates a Priority 3 secondary watchdog interrupt when it is not reset within that time. The primary use for the secondary watchdog is to act as a safety net for the periodic interrupt — if the secondary watchdog is reloaded in the periodic interrupt, it will count down to zero if the periodic interrupt stops occurring. In addition, it can be used as a periodic interrupt on its own.

The battery-backed onchip-encryption RAM consists of 32 bytes of memory that are powered by the VBAT pin (note that this RAM is separate from the battery-backed 32 KB SRAM). Their values are not affected by a reset, but are erased if the state of the SMODE pins changes. These 32 bytes are intended for storing sensitive data (such as an encryption key) somewhere other than an external memory device. The “tamper-protection” erase feature erases these bytes if an attempt is made to load a program into the onchip RAM to read out the bytes.

A feature new to the Rabbit 6000 is a 14-bit CPU clock cycle counter. This counter counts the number of CPU cycles that occur during one 32 kHz clock period. This is useful for determining the frequency of the main CPU oscillator which can be used in baud rate calculations as well as other CPU clock dependant features.

The following other registers are also described in this chapter.

• Global Output Control Register (GOCR), which controls the behavior of the CLK, STATUS, /WDT,

and /BUFEN pins

• Global CPU Register (GCPU), which holds the identification number of the processor.

• Global Revision Register (GREV), which hold the revision number of the processor.

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4.1.1 Block Diagram

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4.1.2 Registers

Global Control/Status Register GCSR 0x0000 R/W 11000000

Real-Time Clock Control Register RTCCR 0x0001 W 00000000

Real-Time Clock Byte 0 Register RTC0R 0x0002 R/W xxxxxxxx

Real-Time Clock Byte 1 Register RTC1R 0x0003 R xxxxxxxx

Real-Time Clock Byte 2 Register RTC2R 0x0004 R xxxxxxxx

Real-Time Clock Byte 3 Register RTC3R 0x0005 R xxxxxxxx

Real-Time Clock Byte 4 Register RTC4R 0x0006 R xxxxxxxx

Real-Time Clock Byte 5 Register RTC5R 0x0007 R xxxxxxxx

Watchdog Timer Control Register WDTCR 0x0008 W 00000000

Watchdog Timer Test Register WDTTR 0x0009 W 00000000

Secondary Watchdog Timer Register SWDTR 0x000C W 11111111

Global Output Control Register GOCR 0x000E R/W 00000000

Global ROM Configuration Register GROM 0x002C R 0xx00000

Global RAM Configuration Register GRAM 0x002D R 0xx00000

Global CPU Configuration Register GCPU 0x002E R 0xx00010

Global Revision Register GREV 0x002F R 0xx00000

Battery-Backed Onchip-Encryption RAM Bytes 00–1F

Master System Configuration Register MSCR 0x0434 R/W 00000000

Master System Status Register MSSR 0x0435 R/W 00000x00

VRAM00–

VRAM1F

0x0600–

0x061F

R/W xxxxxxxx

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4.2 Dependencies

4.2.1 I/O Pins

The CLK, STATUS, /WDTOUT, and /BUFEN pins are controlled by GOCR. Each of these pins can be used as general-purpose outputs by driving them high or low.

• The CLK pin can output the peripheral clock, the peripheral clock divided by two, or be driven high or

low.

• The STATUS pin can be active low during the first byte of each opcode fetch, active low during an

interrupt acknowledge, or driven high or low.

• The /WDTOUT pin can be active low whenever the watchdog timer resets the device or driven low.

• The /BUFEN pin can be active low during external I/O cycles, active low during data memory cycles,

or driven high or low.

The values in the battery-backed onchip-encryption RAM bytes are cleared if the signal on the SMODE pins changes state.

4.2.2 Clocks

The periodic interrupt, real-time clock, watchdog timer, and secondary watchdog timer require the 32 kHz clock.

4.2.3 Interrupts

The periodic interrupt is enabled in GCSR, and will occur every 488 µs. It is cleared by reading GCSR. It can operate at Priority 1, 2, or 3.

The secondary watchdog interrupt will occur whenever the secondary watchdog is enabled and allowed to count down to zero. It is cleared by restarting the secondary watchdog by writing 0x5F to WDTCR or writing a new timeout value to SWDTR. The secondary watchdog interrupt always occurs at Priority 3.

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4.3 Operation

4.3.1 Periodic Interrupt

The following steps explain how a periodic interrupt is used.

1. Write the vector to the interrupt service routine to the internal interrupt table.

2. Enable the periodic interrupt by writing to GCSR.

3. The interrupt request is cleared by reading from GCSR.

A sample interrupt handler is shown below.

periodic_isr:: push af ioi ld a, (GCSR) ; clear the interrupt request and get status

; handle any periodic tasks here

pop af ipres ret

4.3.2 Real-Time Clock

The real-time clock consists of six 8-bit registers that together comprise a 48-bit value. The real-time clock is not synchronized to the read operation, so the least-significant byte should be read twice and checked for matching values; if the two reads do not match, then the real-time clock may have been updating during the read and should be read again.

Writing to RTC0R latches the current real-time clock value into the RTCxR holding registers, so the following sequence should be used to read the real-time clock.

1. Write any value to RTC0R and then read back a value from RTC0R.

2. Write a value to RTC0R again, and again read back a value from RTC0R.

3. If the two values do not match, repeat Step 2 until the last two readings are identical.

4. At this point, registers RTC1R through RTC6R can also be read and used.

Note that the periodic interrupt and the real-time clock are clocked by the same edge of the 32 kHz clock; if read from the periodic interrupt, the count is guaranteed to be stable and only needs to be read once (assuming it occurs within one clock of the 32 kHz clock).

The real-time clock can be reset by writing the sequence 0x40 – 0x80 to RTCCR. It can be reset and left in the byte increment mode by writing 0x40 – 0xC0 to RTCCR and then writing bytes repeatedly to RTCCR to increment the appropriate bytes of the real-time clock. The byte increment mode is disabled by writing 0x00 to RTCCR.

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4.3.3 Watchdog Timer

The watchdog timer is enabled on reset with a 2-second timeout. Unless specific data are written to WDTCR before that time expires, the processor will be reset. The watchdog timer can be disabled by writing a sequence of two bytes to WDTTR as described in the register description.

Table 4-1. Watchdog Timer Settings

WDTCR Value Effect

0x5A Restart watchdog timer with 2-second timeout.

0x57 Restart watchdog timer with 1-second timeout.

0x59 Restart watchdog timer with 500-millisecond timeout.

0x53 Restart watchdog timer with 250-millisecond timeout.

0x5F Restart the secondary watchdog timer.

The watchdog timer also contains a special test mode that speeds up the timeout period by clocking it with the peripheral clock instead of the 32 kHz clock. This mode can be enabled by writing to WDTTR.

4.3.4 Secondary Watchdog Timer

The secondary watchdog timer is disabled on reset. The following steps explain how to use the secondary watchdog timer.

1. Write the vector to the interrupt service routine to the internal interrupt table.

2. Write the desired timeout period to SWDTR. This also enables the secondary watchdog timer.

3. Restart the secondary watchdog timer by either writing the timeout period to SWDTR or writing 0x5F to WDTCR.

If the secondary watchdog timer counts down to zero, a Priority 3 secondary watchdog interrupt will occur. This interrupt request is cleared by writing a new timeout value to SWDTR. A sample interrupt handler is shown below.

secwd_isr:: push af

; determine why the interrupt occurred and take appropriate action

ld a, 0x40 ; timeout period of 0x40/32kHz = 1.95ms ioi ld (SWDTR), a ; clear the interrupt request

pop af ipres ret

4.3.5 CPU Clock Cycle Counter

This counter counts the number of CPU cycles that occur during one 32 kHz clock period. The least significant 8 bits of this 14-bit counter are accessed by reading WDTCR, and the upper 6 bits are accessed by reading WDTTR. This value is updated continually, so be careful to not change the main clock frequency between reading the two registers.

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4.4 Register Descriptions