QUICK LOGIC QL12x16B-0CG84M, QL16x24B-0CF160M, QL16x24B-0CG144M, QL16x24B-1CF160M, QL16x24B-1CG144M Datasheet
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8-7
Military 5.0V pASIC 1 Family - Very-High-Speed CMOS FPGA
Military 5.0V pASIC 1 Family
Rev B
Military 5.0V pASIC 1 Family
Device Highlights
Very High Speed
■ ViaLink“ metal-to-metal programmable technol-
ogy, allows counter speeds over 150 MHz and
logic cell delays of under 2 ns at 5V, and over 80
MHz at 3.3V operation.
High Usable Density
■ Up to a 24-by-32 array of 768 logic cells provides
22,000 usable PLD gates in 208-pin PQFP and
208-pin CQFP packages.
PCI-Output Drive
■ Fully PCI 2.1 compliant input/output capability.
(including drive current)
Features
■ Total of 180 I/O pins
■ -172 Bidirectional Input/Output pins
■ -6 Dedicated Input/High-Drive pins
■ -2 Clock/Dedicated input pins with fanout-
independent, low-skew clock networks
■ -PCI 2.1 Compliant I/Os
■ Input + logic cell + output delays under 6 ns
■ Chip-to-chip operating frequencies up to 110 MHz
■ Internal state machine frequencies up to 150 MHz
■ Clock skew < 0.5 ns
■ Input hysteresis provides high noise immunity
■ Built-in scan path permits 100% factory testing of
logic and I/O cells and functional testing with Automatic Test Vector Generation (ATVG) software
after programming
■ 208 pin PQFP pin for pin compatible with the
208 CQFP
■ 0.65µ CMOS process with ViaLink programming
technology
TABLE 1: Selector Table
D
EVICE HIGHLIGHTS
F
EATURES
Device
ASIC
Gates
PLD
Gates
Package
Max
I/O
Qualification
Level
SMD
5962-
QL8x12B 1,000 2,000 68CPGA 64 M
QL12x16B 2,000 4,000 84CPGA 76 M, /883 96836
144CPGA 122 M, /883 95599QL16x24B 4,000 7,000
160 CQFP 122 M, /883 95599
208CQFP 180 M, /883 96837QL24x32B 8,000 14,000
208PQFP 180 M
M = Military Temperature (-55 to +125 degrees C)
/883 = MIL-STD-883 qualified
8 Preliminary
8-8
Military 5.0V pASIC 1 Family
Product Summary
The pASIC 1 Family is a very-high-speed CMOS
user-programmable ASIC devices. The 768 logic cell
field-programmable gate array (FPGA) features
22,000 usable PLD gates of high-performance general-purpose logic in a 208-pin PQFP and CQFP
package.
Low-impedance, metal-to-metal, ViaLink interconnect technology provides nonvolatile custom logic
capable of operating above 150 MHz. Logic cell
delays under 2 ns, combined with input delays of
under 1.5 ns and output delays under 3 ns, permit
high-density programmable devices to be used with
today’s fastest microprocessors and DSPs.
Designs can be entered using QuickLogic’s QuickWorks Toolkit or most popular third-party CAE tools.
QuickWorks combines Verilog/VHDL design entry
and simulation tools with device-specific place &
route and programming software. Ample on-chip
routing channels allow fast, fully automatic place and
route of designs using up to 100% of the logic and I/
O cells, while maintaining fixed pin-outs.
Pinout Diagram 68-Pin CPGA
TABLE 2: CPGA 68 Function/Connector Pin Table
P
RODUCT SUMMARY
P
INOUT DIAGRAM
68-PIN CPGA
PIN FUNC PIN FUNC PIN FUNC PIN FUNC
B10IOB2IOK2IOK10IO
A10 IO B1 IO L2 IO K11 IO
B9 IO C2 IO K3 IO J 10 IO
A9 IO C1 IO L3 IO J11 IO
B8 IO D2 IO K4 IO H10 IO
A8 IO D1 IO L4 IO H11 IO
B7 I/(SCLK) E2 IO K5 I/(SI) G 10 IO
A7 I/CLK/(SM) E1 IO L5 I/CLK G11 IO
B6 VCC F2 GND K6 VCC F10 GND
A6 I F1 IO L6 I F11 IO
B5 I G2 IO K7 I/(SO) E10 IO
A5 IO G1 IO L7 IO E11 IO
B4 IO H2 IO K8 IO D10 IO
A4 IO H1 IO L8 IO D11 IO
B3 IO J2 IO K9 IO C10 IO
A3 IO J1 IO L9 IO C11 IO
A2 IO K1 IO L10 IO B11 IO
8-9
Military 5.0V pASIC 1 Family
Pinout Diagram 84-pin CPGA
TABLE 3: CPGA 84 Function/Connector Pin Table
P
INOUT DIAGRAM
84-PIN CPGA
PIN FUNC PIN FUNC PIN FUNC PIN FUNC
B10IOB2IOK2IOK10IO
B9 IO C2 IO K3 IO J10 IO
A10 IO B1 IO L2 IO K11 IO
A9 IO C1 IO L3 IO J11 IO
B8 IO D2 IO K4 IO H10 IO
A8 IO D1 IO L4 IO H11 IO
A7 IO E1 IO L5 IO G11 IO
C7 GND E3 GND J5 GND G9 GND
A6 IO E2 IO L6 IO G10 IO
B7 I/(SCLK) F1 IO K5 I/(SI) F11 IO
C6 I/CLK/(SM) F2 IO J6 I/CLK F10 IO
B6 I(P) F3 IO K6 I F9 IO
B5 I G1 IO K7 I/(SO) E11 IO
C5 VCC G3 VCC J7 VCC E9 VCC
A5 IO G2 IO L7 IO E10 IO
A4 IO H1 IO L8 IO D11 IO
B4 IO H2 IO K8 IO D10 IO
A3 IO J1 IO L9 IO C11 IO
A2 IO K1 IO L10 IO B11 IO
B3 IO J2 IO K9 IO C10 IO
A1 IO L1 IO L11 IO A11 IO
10 Preliminary
8-10
Military 5.0V pASIC 1 Family
Pinout Diagram 144-pin CPGA
TABLE 4: CPGA 144 Function/Connector Table
(Cont’d on next page)
P
INOUT DIAGRAM
144-PIN CPGA
PIN FUNC PIN FUNC PIN FUNC PIN FUNC
A2 IO B15 IO R14 IO P1 IO
B3 IO C14 IO P13 IO N2 IO
C4 IO D13 IO N12 IO M3 IO
A3 IO C15 IO R13 IO N1 IO
B4 IO D14 IO P12 IO M2 IO
A4 IO E13 VCC R12 IO L3 VCC
C3 VCC D15 IO N13 VCC M1 IO
B5 IO E14 IO P11 IO L2 IO
A5 IO E15 IO R11 IO L1 IO
C6 IO F13 IO N10 IO K3 IO
B6 IO F14 IO P10 IO K2 IO
A6 IO F15 IO R10 IO K1 IO
A7 IO G15 IO R9 IO J1 IO
B7 IO C13 GND P9 IO N3 GND
C5 GND G14 IO N11 GND J2 IO
A8IOH15IOR8IOH1IO
B8 I/(SCLK) H14 IO P8 I/(SI) H2 IO
C8 I/CLK/(SM) G13 GND N8 I/CLK J3 GND
C7 VCC H13 IO N9 VCC H3 IO
A9 I/(P) J15 IO R7 I G1 IO
B9 I J14 IO P7 I/(SO) G2 IO
C11 VCC J13 VCC N5 VCC G3 VCC
A10 IO K15 IO R6 IO F1 IO
A11 IO L15 IO R5 IO E1 IO
B10 IO K14 IO P6 IO F2 IO
8-11
Military 5.0V pASIC 1 Family
CPGA 144 Function/Connector Table (Cont’d)
A12 IO M15 IO R4 IO D1 IO
B11 IO L14 IO P5 IO E2 IO
C10 IO K13 IO N6 IO F3 IO
A13 IO N15 IO R3 IO C1 IO
C9 GND L13 GND N7 GND E3 GND
B12 IO M14 IO P4 IO D2 IO
A14 IO P15 IO R2 IO B1 IO
B13 IO N14 IO P3 IO C2 IO
C12 IO M13 IO N4 IO D3 IO
A15 IO R15 IO R1 IO A1 IO
B14 IO P14 nc P2 IO B2 nc
P
INOUT DIAGRAM
160-PIN CPGA
QL16x24B-1CF160M
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