QUICK LOGIC QL82SD-4PT280C, QL82SD-4PT280I, QL82SD-4PT280M, QL82SD-5PB516C, QL82SD-5PB516M Datasheet

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Preliminary

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Device Highlights

LVDS SERDES Basic Features

• 10 High Speed Bus LVDS Serial Links—

bandwidth up to 5 Gbps

• Eight Independent Bus LVDS serial

transceivers with operating speeds to 632 Mbps per channel

• Two Independent Bus LVDS clock serial

transceivers with operating speeds to 400 MHz per channel

• Integrated clock and data recovery (CDR)

with no external analog components required

• CDR bypass for applications with external

clock source

• Programmable serial to parallel

configuration

• 10-bit data width—with

• clock recovery

• 4-bit, 7-bit and 8-bit data widths—

with external clock

• 1-bit asynchronous level conversion

• Fast Lock and Random (auto) Lock capable

• Lock signal feedback

• I/O support for LVTTL, LVCMOS, PCI,

GTL+, SSTL2, SSTL3, LVDS, LVPECL

• Low Power/Independent power-down

mode for each SERDES channel

• IEEE1149.1 JTAG Support &

boundary scan

• Operation over PCB or backplane traces, or

across twisted pair cabling up to 25 m

• Point-to-Point, Multi-Point, and Multi-Drop

Support

• Pre-Emphasis Control on each LVDS

Channel Link

Extended Features

The following can be implemented into the programmable logic:

• UTOPIA Level 2, 16-bit wide System

interface (up to 50 MHz) with parity support for ATM applications

• UTOPIA Level 3 compatible 8-bit wide

system Interface (up to 100 MHz) with parity support for ATM applications

• CSIX-L1 32-bit switch fabric interface (up to

100 MHz)

• Supports Generic 8,16,32-bit

microprocessor bus interface for configuration, control and status monitoring

• Supports Generic 32, 64-bit peripheral bus

interface for bridging functions

Flexible Programmable Logic

• 2,016 Programmable Logic Cells

• 536 K System Gates

• Muxed architecture; non-volatile technology

• Completely customizable for any digital

application

Dual Port SRAM Blocks

• 36 Dual Port SRAM Blocks

• Configurable array sizes (by 2, 4, 9, 18)

• < 3 ns access times, FIFO capable of over

300 MHz

• Configurable as RAM or FIFO

QL82SD Device Data Sheet

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QL82SD Device Data Sheet Rev C

Preliminary

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Programmable I/O

• Up to 252 Programmable I/O pins

• High performance Enhanced I/O (EIO): Less than 3 ns Tco

• Programmable Slew Rate Control

• Programmable I/O Standards

• LVTTL, LVCMOS, PCI, GTL+, SSTL2, and SSTL3, LVDS, LVPECL

• Four Independent I/O Banks

• Three Register Configuration: Input, Output, OE

Embedded Computational Unit (ECU) Blocks

• Integrated multiply, add, and accumulate function

• 18 distributed MAC blocks

• 8 × 8 multiply (sign & unsigned)

• 16-bit carry add

Advanced Clock Network

• Nine Global Clock Networks consisting of:

• one dedicated

• eight programmable

• Eight I/O (high drive) networks: two I/Os per bank

• Ten Quad-Net Networks—five per quadrant

Figure 1: QL82SD Device Block Diagram

Table 1: QL82SD Device Table

Customer Part #

SERDES

Data

LV DS

Clocks

SRAM

Blocks

Logic

Cells

ECU

Blocks

Programmable I/O

QL82SD-PQ208 4 2 36 2016 18 75

QL82SD-PT280 8 2 36 2016 18 121

QL82SD-PS484 8 2 36 2016 18 209

QL82SD-PB516 8 2 36 2016 18 252

RAM Blocks

Embedded Computational Units (ECUs)

RAM Blocks

IO Block IO Block

IO Block

2016 Logic Cells

CLKB

CH7

CH6

CH5

CH4

CH3

CH2

CH1

CH0

CLKA

LVDS/SERDES IO Block

IO Block

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QL82SD Device Data Sheet Rev C

Preliminary

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General Description

LVDS SERDES Transmitter and Receiver

A QuickSD LVDS SERDES device in serializer mode takes a parallel data bus and a separate clock and converts them into a serial data stream. In deserializer mode, it takes a serial data stream and converts it to a configurable bit wide parallel data bus and separate clock. The reduced number of I/O board traces and cable connectors saves on cost and significantly simplifies design. Skew and timing issues are significantly reduced and performance is enhanced.

Figure 2 and Figure 3 illustrate the block diagrams of the QuickSD device

transmitter and receiver.

Figure 2: LVDS SERDES Transmitter Block Diagram

Figure 3: LVDS SERDES Receiver Block Diagram

RL = 2 7

Ω

- 100ΩVo +

Vo -

IL = 8-12 mA

Do +

Do -

300k

/E nabl e

Parallel to Serial

.

txd [9:0]

TTL_Din

Din +

Din -

300k W

VCM = 0.2 V - 2.2 V

Serial to Parallel

.

FPGA

rxd [9:0]

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QL82SD Device Data Sheet Rev C

Preliminary

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LVDS SERDES Applications

The QuickSD device is designed to address the need for high-speed serial communications. It maintains the features of standard discrete SERDES devices, but integrates these features with customizable logic to allow for the highest degree of flexibility, performance, and integration at the lowest cost. The QuickSD device is designed to support both transmit and receive requirements in a single chip. The device can support multiple channels in a variety of modes (with or without clock recovery,) a variety of translation widths (1:1 to 1:10), as well as a range of frequencies. These capabilities make this device ideal in applications where the performance is critical and customization is required.

The QuickSD device targets three applications: on-board, board-to-board (via common backplane), and box-to-box (via common cable).

Software Support

The turnkey QuickWorks package from QuickLogic provides the most complete ESP and FPGA software solution from design entry to logic synthesis, to place and route, and to simulation. The package provides a solution for designers who use third-party tools from Cadence, Mentor, OrCAD, Synopsys, Viewlogic, Veribest and other third-party tools for design entry, synthesis, or simulation. A power calculator is also provided for SERDES power consumption.

To speed up the QuickSD design process, QuickLogic includes a SERDES Wizard in its QuickWorks package. This wizard simplifies the process of configuring the multi-channel SERDES core into each of its modes. For details on the SERDES Wizard, please refer to "The QL82SD Quickstart Design Guide". To find this guide go to the QuickSD device documentation Web page at

http://www.quicklogic.com/home.asp?PageID=315&sMenuID=199#Order.

Process Data

QuickSD is fabricated on a 0.25 µ, five-layer metal CMOS process. The core voltage is

2.5 Volt V

CC

supply and 3.3 V tolerant I/O with the addition of 3.3 Volt V

CCIO

. QuickSD is

available in commercial and industrial temperature grades.

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QL82SD Device Data Sheet Rev C

Preliminary

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Ordering Information

Maximum Ratings and Operating Range

Table 2: Absolute Maximum Electrical Ratings

VCC Voltage -0.3 V to 4 V

Bus LVDS Driver

Output Voltage

-0.3 V to +2.8 V

LVCMOS/LVTTL

Input Voltage

-0.3 V to (V

CC

+ 0.3 V)

Bus LVDS Output Short

Circuit Duration

10 mS

LVCMOS/LVTTL

Output Voltage

-0.3 V to (V

CC

+ 0.3 V) ESD Rating HBM 2 kV

Bus LVDS Receiver

Input Voltage

-0.3 V to +2.8 V

Table 3: Absolute Maximum Thermal Ratings

Junction Temperature +150°C

Lead Temperature

(Soldering, 4 seconds)

+260°C

Storage Temperature -65°C to +150°C

Thermal and Power

Dissipation

Characteristics

See the following table

Table 4: Thermal and Power Dissipation Characteristics

Package 0ja (*C/W vs. Airflow 0jc (*C/W)

Estimated Maximum

Power Dissipation (W)

0.0 0.5 1.0 2.0

PQ208 26.0 24.5 23.0 22.0 11.0 1.65

QL 82SD - 4 PB516 C

QuickLogic device

QuickSD device part number

Speed Grade

4 = Quick 5 = Fast 6 = Faste r 7 = Faste st

Package Code

PQ208 = 208-pin FPBGA PT280 = 280-pin BGA (1.0mm)

PS484 = 484-pin BGA (1.0mm)

PB516 = 516-pin BGA (1.27mm)

Operating Range

C = Commercial

I = Industrial

M = Military

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QL82SD Device Data Sheet Rev C

Preliminary

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Electrical Specifications - LVDS SERDES

LVDS SERDES Transceiver Capability (Speed)

General Test Conditions

All tests are done for the 484-pin BGA package (1.00 mm pitch). The tests are set up so that an LVDS SERDES channel of a QL82SD transmits, and the other LVDS SERDES channel of the same device (or another QL82SD device) receives. All results are given as worst cases over commercial temperature, VCC, and process, with PLLVCC = 2.5 V unless otherwise specified.

If the QL82SD device is used only for transmit or receive, but not both simultaneously, the performance can be significantly better, and, in many cases, exceeds 1 Gb/s per channel.

NOTE:

All data are in Mb/s. Low/High frequencey refers to internal SERDES PLL lock

range (see

Table 29 on page 31 for more information).

PT280 18.5 17.0 15.5 14.0 7.0 2.24

PS484 28.0 26.0 25.0 23.0 9.0 2.42

PB516 20.0 19.0 17.5 16.0 7.0 2.51

Table 5: Operating Ranges

Symbol Parameter Industrial Commercial Unit

Min Max Min Max

Vcc Supply Voltage 2.3 2.7 2.3 2.7 V

Vccio I/O Input Tolerance Voltage 2.3 3.6 2.3 3.6 V

T

A

Ambient Temperature -40 85 0 70 °C

K Delay Factor

-4 Speed Grade 0.43 2.16 0.47 2.11 n/a

-5 Speed Grade 0.43 1.80 0.46 1.76 n/a

-6 Speed Grade 0.43 1.26 0.46 1.23 n/a

-7 Speed Grade 0.43 1.14 0.46 1.11 n/a

Table 4: Thermal and Power Dissipation Characteristics

Package 0ja (*C/W vs. Airflow 0jc (*C/W)

Estimated Maximum

Power Dissipation (W)

0.0 0.5 1.0 2.0

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QL82SD Device Data Sheet Rev C

Preliminary

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Cable - Normal Operation

NOTE:

Test Conditions: Up to 3-meter Category 5 Cable without any compensation.

Cable - High Speed Operation

NOTE:

Test Conditions: Up to 9" Category 5 Cable, and reference design in the programmable fabric portion of the device for internal skew compensation for channel link modes.

Backplane - Normal Operation

NOTE:

Test Conditions: Up to 18" point-to-point backplane without any compensation.

Table 6: Cable - Normal

Low Frequency High Frequency

Modes Min Max Min Max

10:1 Mode Not Available 250 350

8:1 112 360 224 368

7:1 112 322 224 364

4:1 112 348 224 304

Table 7: Cable - High Speed Operation

Low Frequency High Frequency

Modes Min Max Min Max

10:1 Mode Not Available 250 350

8:1 112 480 224 552

7:1 112 462 224 504

4:1 112 456 224 500

Table 8: Backplane - Normal Operation

Low Frequency High Frequency

Modes Min Max Min Max

10:1 Mode Not Available 250 350

8:1 112 320 224 376

7:1 112 315 224 385

4:1 112 384 224 384

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QL82SD Device Data Sheet Rev C

Preliminary

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Backplane - High Speed Operation

NOTE:

Test Conditions: Up to 18" point-to-point backplane, and reference design in the programmable fabric portion of the device for internal skew compensation for channel link modes.

1:1 Mode (Asynchronous Level Conversion)

Up to 9" cable: 0 to 500 Mbps

Up to 18" point-to-point backplane: 0 to 700 Mbps

All numbers are for LVDS channel performance only, and do not include the programmable fabric’s ability to support high data rates.

Table 9: Backplane - High Speed Operation

Low Frequency High Frequency

Modes Min Max Min Max

10:1 Mode Not Available 250 350

8:1 112 632 224 632

7:1 112 630 224 630

4:1 112 628 224 628

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QL82SD Device Data Sheet Rev C

Preliminary

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Bus LVDS DC Specifications

Over the operating range, RxVcc = 3.0 V to 3.6 V.

NOTE:

Apply to pad_ChX_p/n, pad_ClkX_p/n

Figure 4: Output Differential Voltage

Table 10: Serializer / Transmitter

Symbol Parameter Conditions Min Typ Max Units

V

OD

Output Differential Voltage,

pad_ChX_p - Pad_ChX_n

Figure 4 Figure 5

R

L

= 27Ω

240 325 420 mV

V

OS

Offset Voltage 0.90 1.10 1.30 V

I

OS

Output Short Circuit Current

D

O

= 0 V,

D

IN

+ H,

EN + OE + V

CC

20 25 35 mA

I

OZ

Tri-State Output Current

DO = 0 V/VCC,

EN = 0

-25 ±10 25 µA

I

OX

Power-Off Output Current

V

CC

- 0 V,

D

O

= 0 V/V

CC

-25 ±10 25 µA

Table 11: Deserializer / Receiver

Symbol Parameter Conditions Min Typ Max Units

V

TH

Differential Threshold High Voltage

Figure 6

V

CM

= 1.1 V

n/a 35 50 mV

V

TL

Differential Threshold Low Voltage -50 -35 n/a mV

I

IN

Input Current

V

IN

= 0 V,

V

CC

= 0 V / 3.6 V

-25±825µA

VIN = 2.4 V,

V

CC

= 0 V / 3.6 V

-25 ±8 25 µA

D out +

D out -

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QL82SD Device Data Sheet Rev C

Preliminary

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Figure 5: Output Differential Voltage for Different Loads

Figure 6: Differential Threshold Voltages

82SD BLVDS output Vod vs Iod

0.00

0.10

0.20

0.30

0.40

0.50

0.60

0.70

0.80

0.90

1.00

8 9 10 11 12 13

Iod ( m A )

Vod ( v )

100

Ω

60

Ω

27

Ω

40

Ω

80

Ω

VCM

VTH/ VTL

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QL82SD Device Data Sheet Rev C

Preliminary

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Supply Current per Channel

NOTE:

More accurate supply current/power consumption numbers specific to your application should be calculated using the power calculator supplied with QuickLogic’s QuickWorks software package.

Table 12: Serializer / Transmitter

Symbol Parameter Conditions Min Typ Max Units

I

CCT

Serializer Supply Current CL =10 pF

Figure 7 1:1 Mode Figure 7 mA

Figure 8 4:1 Mode Figure 8 mA

Figure 9 7:1 Mode Figure 9 mA

Figure 12 8:1 Mode Figure 12 mA

Figure 11

10:1 Mode

Data/Clock

Figure 11 mA

I

CCTX

Serializer Supply Current

Powerdown

EN = 0 1 10 µA

Table 13: Deserializer / Receiver

Symbol Parameter Conditions Min Typ Max Units

I

CCR

Serializer Supply Current CL = 10 pF

Figure 13 1:1 Mode Figure 13 mA

Figure 14 4:1 Mode Figure 14 mA

Figure 15 7:1 Mode Figure 15 mA

Figure 13 8:1 Mode Figure 13 mA

Figure 14

10:1 Mode

Data/Clock

Figure 14 mA

I

CCRX

Serializer Supply Current

Powerdown

EN = 0 1 10 µA

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QL82SD Device Data Sheet Rev C

Preliminary

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Figure 7: Data/Clock Channel, 1:1 Transmit Mode

Figure 8: Data/Clock Channel, 4:1 Transmit Mode

Figure 9: Data/Clock Channel, 7:1 Transmit Mode

Figure 10: Data/Clock Channel, 8:1 Transmit Mode

Figure 11: Data/Clock Channel,10:1 Transmit Mode

Figure 12: Data/Clock Channel, 1:1 Receive Mode

S

upply Current at VccTx = 2.5

V

ICCT (mA)

Clock Frequency(MHz)

0

9

10

11

12

13

0 100 200 300 400 500 600 700

Rt=100ohm

Rt= 27ohm

Supply Current at VccTx = 2.5 V

ICCT (mA)

Clock Frequency(MHz)

10

15

20

20 40 60 80 100 120 140 160

Rt=100ohm Rt= 27ohm

Supply Current at VccTx = 2.5V

ICCT (mA)

Clock Frequency(MHz)

10

10 30 50 70 90

Rt=100ohm

Rt= 27ohm

15

20

25

Supply Current at VccTx = 2.5 V

ICCT (mA)

10

20 40 60

15

20

25

Rt=100ohm

Rt= 27ohm

Clock Frequency(MHz)

Supply Current at VCCRX = 3.3 V V

CC

= 2.5 V

ICCR (mA)

Clock Frequency (MHz)

2

0 100 200 300 400 500 600 700

4

6

8

10

12

14

16

18

20

S

upply Current at VccTx = 2.5

V

ICCT (mA)

Clock Frequency(MHz)

10

10 30 50 70

Rt=100ohm

Rt= 27ohm

15

20

25

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QL82SD Device Data Sheet Rev C

Preliminary

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Figure 13: Data/Clock Channel, 4:1 Receive Mode

Figure 14: Data/Clock Channel, 7:1 Receive Mode

Figure 15: Data/Clock Channel, 8:1 Receive Mode

Figure 16: Data/Clock Channel, 10:1 Receive Mode

ICCR (mA)

Clock Frequency (MHz)

5

20 40 60 80 100 120 140 160

15

20

25

Supply Current at V

CCRX

= 3.3 V, V

CC

= 2.5 V

10

ICCR (mA)

Clock Frequency (MHz)

S

upply Current at VCCRX = 3.3 V, V

CC

= 2.5 V

0 10 30 50 70 90

20

10

5

15

ICCR (mA)

Clock Frequency (MHz)

10 20 30 40 50 60 70 80 90

5

S

upply Current at

VCCR

X

= 3.3 V,

V

CC

= 2.5

V

20

15

10

0

ICCR (mA)

Clock Frequency (MHz)

S

upply Current at

VCCR

X

= 3.3 V,

V

CC

= 2.5

V

0

10

15

20

5

20 25 30 35 40 45 50 55 60 70

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QL82SD Device Data Sheet Rev C

Preliminary

14

SERDES Timing Requirements

NOTE:

Both Table 14 and Tabl e 15 refer to CDR (10:1) Mode for ChX_txclk and Channel Link (8:1, 7:1, 4:1) Mode for ClkX_txclk

Figure 17: Serializer Transmit Clock / Deserializer Reference Clock Transition Times

Table 14: Serializer / Transmitter Transmit Clock

Symbol Parameter Conditions Min Ty p Max Units

t

TCP

Transmit Clock Period

Mode

Dependent

n/a T n/a nS

t

TDC

Transmit Clock Duty Cycle 45 50 55 %

t

CLKT

Transmit Clock Input Transition Time Figure 17 1 n/a n/a V/nS

t

JIT

Transmit Clock Input Jitter n/a n/a 150.0

pS

(RMS)

Table 15: Deserializer / Receiver Transmit Clock

Symbol Parameter Conditions Min Ty p Max Units

t

RFCP

Reference Clock Period

Mode

Dependent

n/a T n/a nS

t

RFDC

Reference Clock Duty Cycle 40 50 60 %

t

RFCP/tTCP

Ratio of Reference Clock to

Transmit Clock

0.4 0.5 0.6 n/a

t

RFTT

Reference Clock Transition Time Figure 17 1 n/a n/a V/nS

90%

10%

txclk

tclkT/tRFTT tclkT/tRFTT

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QL82SD Device Data Sheet Rev C

Preliminary

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SERDES Switching Characteristics - Serializer/Transmitter]

Table 16: Serializer/Transmitter Switching Characteristics

CDR (10:1) Mode

Symbol Parameter Conditions Min Typ Max Units

t

HZD

pad_ChX_p/n High to Tri-State Delay

Figure 18

1.9 2.2 2.5 nS

t

LZD

pad_ChX_p/n Low to Tri-State Delay 1.9 2.0 2.2 nS

t

ZHD

pad_ChX_p/n Tri-State to High Delay 1.9 2.4 3.0 nS

t

ZLD

pad_ChX_p/n Tri-State to Low Delay 2.0 2.3 2.8 nS

t

DIS

ChX_txd[9:0] Setup to ChX_txclk

Figure 19

2.6 3.2 nS

t

DIH

ChX_txd[9:0] Hold from ChX_txclk 2.1 2.7 nS

t

PLD

Serializer PLL Lock Time Figure 20 90 uS

Channel Link (8:1, 7:1, 4:1) Mode

Symbol Parameter Conditions Min Typ Max Units

t

HZD

pad_ChX_p/n High to Tri-State Delay

Figure 18

1.9 2.2 2.5 nS

t

LZD

pad_ChX_p/n Low to Tri-State Delay 1.9 2.0 2.2 nS

t

ZHD

pad_ChX_p/n Tri-State to High Delay 1.9 2.4 3.0 nS

t

ZLD

pad_ChX_p/n Tri-State to Low Delay 2.0 2.3 2.8 nS

t

DIS

ChX_txd[N-1:0] Setup to ChX_txclk

Figure 21

2.6 3.2 nS

t

DIH

ChX_txd[N-1:0] Hold from ChX_txclk 2.1 2.7 nS

t

SD

Serializer Delay 1.7 nS

t

SCP

Serial Transmit Clock Period T/mode nS

t

TXD[N-1]

Transmitter Output Pulse Position for

Bit [N-1]

[N-1] x t

SCP

+ 1.1 [N-1] x t

SCP

+ 1.5 nS

t

PLD

Serializer PLL Lock Time Figure 20 90 uS

Asynchronous Level Conversion (1:1) Mode

t

HZD

pad_ChX_p/n High to Tri-State Delay

Figure 18

1.9 2.2 2.5 nS

t

LZD

pad_ChX_p/n Low to Tri-State Delay 1.9 2.0 2.2 nS

t

ZHD

pad_ChX_p/n Tri-State to High Delay 1.9 2.4 3.0 nS

t

ZLD

pad_ChX_p/n Tri-State to Low Delay 2.0 2.3 2.8 nS

t

ASD

Asynchronous Serializer Delay -

Data Channel

Figure 22

1.8 nS

t

ASC

Asynchronous Serializer Delay -

Channel Clock

1.7 nS

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QL82SD Device Data Sheet Rev C

Preliminary

16

Figure 18: Serializer Delays to Tri-State

Figure 19: 10:1 Mode Serializer Transmit with Embedded Clock

Figure 20: Serializer PLL Times

3V

0V

V

0H

0L

EN

Pad_p/n

t

LZD

t

HZD

t

ZHD

t

ZLD

50%

1.1V

50%

1.5V1.5V

1.1V

Ch0_txclk

Ch0_txd[9:0]

A

B

C

D

E

DIS

DIH

t

F

Pad_Ch0_p/n

t

ZHD

or

t

ZLD

0.8V

t

HZD

or

t

LZD

TRI-STATE

Output Active

TRI-STATE

txclk

Pad_p/n

ENABLE

2.0V

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QL82SD Device Data Sheet Rev C

Preliminary

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Figure 21: Channel Link Mode Serializer Transmit (Using 8:1 Mode as Example)

Figure 22: 1:1 Mode Asynchronous Level Conversion Mode Serializer Delays

[bit3][bit2][bit1][bit0][bit7][bit6][bit5][bit4]

Pad_ClkX _p/n

Pad_ ChX _p/n

TXD

[4]

[5]

[6]

[7]

[0]

ChX _txd [7:0]

ChX_txclk

Note: [N-1]

physical

positi ons wrt

Pad_ClkX_p/n while Pad_ChX_p/n bit[n] bit positions wrt

ChX

_txd [7:0].

tt

t

TXD

t

TXD

t

TXD

t

TXD

t

TXD

t

DIS

DIH

SD

denotes

refers to

bit

logical

Ch0_txd [0]

Pad_Ch0_p/n

ClkA_txclk

Pad_ClkA_p/n

t

ASD

t

ASC

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QL82SD Device Data Sheet Rev C

Preliminary

18

SERDES Switching Characteristics - Deserializer/Receiver

a. These values include the delay resulting from application of internal compensation for data/clock skew.

Table 17: Deserializer / Receiver Switch Characteristics

CDR (10:1) Mode

Symbol Parameter Conditions Min Typ Max Units

t

RCP

ChX_rxclk Period 28.5 T 40.0 nS

t

RDC

ChX_rxclk Duty Cycle 45 50 55 %

t

DD

Deserializer Delay

Figure 23

2

× t

RCP

+ 1.5 2 × t

RCP

+ 2.5 2 × t

RCP

+ 3.5 nS

t

RXPD

ChX_rxclk to ChX_rxd[9..0] 1.5 2.5 3.5 nS

t

DSR1

Deserializer PLL Lock Time

from powered-down state

Figure 24: 25 MHz

Figure 24: 50 MHz

5 8

uS uS

t

DSR2

Deserializer PLL Lock Time from SYNCPAT

Figure : 25 MHz

Figure : 50 MHz

1

0.75

uS uS

t

DJIT

Pad_ChX_p/n Jitter

25 MHz 50 MHz

±350 ±200

pS pS

Channel Link (8:1, 7:1, 4:1) Mode

Symbol Parameter Conditions Min Typ Max Units

t

RCP

ChX_rxclk Period T nS

t

RDC

ChX_rxclk Duty Cycle 45 50 55 %

t

DD

Deserializer Delay

Figure 26

2

× t

RCP

+ 1.5 2 × t

RCP

+ 2.5 2 × t

RCP

+ 3.5 nS

t

RXPD

ChX_rxclk to ChX_rxd[N-1..0] 1.5 2.5 3.5 nS

t

RXDS

Pad_ChX_p/n Setup to Strobe Position 150 200 pS

t

RXDH

Pad_ChX_p/n Hold to Strobe Position 150 200 pS

t

SCD

Pad_ClkX_p/n to Serial Clock Delay

a

0.6 0.8 1 nS

t

SCP

Serial Clock Period T/mode nS

t

RXD[N-1]

Receiver Input Strobe Position for Bit [N-1] [N-1]

× t

SCP

+ 1.1 [N-1] × t

SCP

+ 2.4 nS

t

DSR1

Deserializer PLL Lock Time from

powered-down state

Figure 24: 25 MHz

Figure 24: 50 MHz

5 8

uS uS

t

DJIT

Pad_ChX_p/n Jitter

25 MHz 50 MHz

±300 ±150

pS pS

Asynchronous Level Conversion (1:1) Mode

t

ADD

Asynchronous Deserializer Delay -

Data Channel

Figure 27

1.7 nS

t

ADC

Asynchronous Serializer Delay -

Channel Clock

a

0.6 0.8 1 nS

LVDS Link

Frequency

Compression

Mode

-1

Mode Dependent

LVDS Link

Frequency

Compression

Mode

-1

Mode Dependent