QUICK LOGIC QL80FC-PB456C, QL80FC-PB456I, QL80FC-PQ208C, QL80FC-PQ208I Datasheet

1

QuickLogic QL80FC Programmable Fibre Channel ENDEC

QL80FC - QuickFC

TM

Rev A

QL80FC - QuickFC

Features

■ ANSI Fibre Channel (FC) compatibility

■ Data rates up to 2.5 Gb/s supported

■ 2.5Gb/s Simplex (200 MByte/s) or Duplex

(400 MByte/s) Mode

■ Compatible with standard SERDES components

■ 32 bit synchronous FIFO system interface

■ Tx and Rx internal FIFO for system applications

without external FIFOs

■ Selectable 20-bit/10-bit encoded transmission

character interface to SERDES

■ 8b/10b Encoding/Decoding

■ CRC Calculation and checking per FC standard

■ Fibre Channel Loss of Synchronization (LOS) state

machine

■ Support for arbitrated loops

■ IntraFrame idles support for proprietary links

■ “Raw” data path for the injection of encoding and

CRC errors into the bitsteam for use in testing link
error handling functions

■ 3.3V operating voltage

■ 3.3V CMOS I/O, 5.0V CMOS tolerant inputs

■ 208 PQFP and 456 PBGA packages available

Extended Features

Extended features that can be designed into the user
customizable logic:

■ Fibre Channel Link Control State Machine (LCSM)

■ RRDY credit management for link flow control

■ Microprocessor interface to configure various link

modes

■ BIST functions support link bit error rate

measurements

F

EATURES

E

XTENDED FEATURES

Dual Port SRAM

■ 22 blocks (total of 25,344 bits) of dual-port RAM

■ Configurable as RAM, ROM or FIFO

■ Can be configured as two internal FIFOs of up to

352 x 36 in size

■ Configurable RAM array sizes (by 2, 4, 9, 18)

■ <5ns access times, 160+Mhz FIFOs

High Speed Customizable Logic

■ Up to 269 customizable I/O pins

■ 751 Logic cells

■ 300 MHz 16-bit counters, 400 MHz Data paths

■ Mux-Based architecture; non-volatile technology

■ Completely customizable for any digital application

Fibre Channel Block Diagram

D

UAL PORT

SRAM

H

IGH SPEED CUSTOMIZABLE LOGIC

RAM Blocks

22 Blocks (25K bits)

IO Pins

Fibre Channel ENDEC

Customizable

Logic Cells

IO Pins

Transmit

Receive

10 bit/20 bit 10 bit/20 bit

IO Pins

2Preliminary

2

QL80FC - QuickFC

TM

FIGURE 1. System Level Diagram

General Description

The QL80FC device in the QuickLogic QuickFC ESP
(Embedded Standard Product) family provides a com­pletely integrated configurable Fibre Channel
Encoder/Decoder interface solution combined with
customizable logic. This device provides a means to
receive and transmit high-speed serial data and
implement a Fibre Channel Link interface or any
proprietary high-speed serial link.

The chip is divided into two main portions, an
embedded design and a customizable design. The
embedded design contains the built in functionality of
Fibre Channel's FC-1 and FC-2 layers, which the sys­tem designer uses as a standard product. This portion
can not be modified. As such, all functionality and
timing requirements have been verified in hardware
and are guaranteed.

The customizable portion consists of user customiz­able system gates, and interfaces directly to the
embedded portion of the chip. These gates may be
programmed to implement glue logic to other bus
standards such as PCI or SCSI. They can also be pro­grammed with Fibre Channel Upper Layer Protocols.
Of course, the designer may choose to modify Upper
Layer Protocols for customization. In this way, the

QuickLogic QL80FC provides the embedded systems
designer with an easy to use and cost effective solu­tion for embedded serial applications.

Fibre Channel Application

The QL80FC ENDEC is a high performance
encoder/decoder designed for use in conjunction
with Gb/s SERDES transmitter/receiver chips. These
chips, when combined with internal FIFO buffer
memory, can be used to build a complete serial link.
Optional, external FIFOs can be used in place of the
available internal FIFOs to extend buffering to sizes
beyond 352 words.

The embedded ENDEC is a full duplex design with an
encoder section for transmission and a decoder sec­tion for reception. The transmitter/encoder section
accepts a 4-byte user data word, encodes each byte
into a 10-bit transmission character and outputs
transmission characters to the SERDES transmitter.
This equals two 10-bit characters per clock (one 10­bit character per clock in 10-bit mode). The receiver/
decoder section accepts two 10-bit transmission char-

System

Bus

(Optional)

Transmit

FIFO

(Optional)

Recei ve

FIFO

FIFO Control

User Customizabl e

Logic

Embedded

Fibre Channel

ENDEC

QL80FC Programmable ENDEC Chip

Bridge Logic
For Dat a Path

Transmit/

Recei ve

SERDES

2.5 Gb/s Serial
Data Ove r
Copper or

Optical Cable

Internal

Transmit

FIFO

Internal
Receive

FIFO

Micro- Process or

Or

System Bus

Interface

G

ENERAL DESCRIPTION

F

IBRE CHANNEL APPLICATIONS

3

QL80FC - QuickFC

TM

acters from the SERDES receiver (one 10-bit charac­ter in 10-bit mode), decodes them, and outputs a 4­byte user data word.

The QL80FC has a system interface that emulates a
synchronous FIFO for ease of use. FIFOs allow maxi­mum sustained performance of 400 MB/s running a
full duplex link. Their function is to handle the asyn­chronous interface between the bus data rate and the
different serial data rates, and handle phase and fre­quency differences inherent in serial links. Internal
FIFOs of 352 x 36 or external FIFOs can be used to
expand the buffering to accommodate multiple
frames.

The QL80FC includes the hardware necessary for
packetized data protection. Framing functions are
provided via Fibre Channel compliant command
words (ordered sets) for Start of Frame and End of
Frame. CRC generation and data frame verification
protect the Fibre Channel frame header and data
field when these framing functions are used.

The device provides a microprocessor interface that
allows the user to manage the serial link. Signals are
also provided to decode serial link error conditions
and differentiate between data and commands. The
QL80FC implements link synchronization with the

SERDES chip through the Loss of Synchronization
State Machine (LOS) as required by the ANSI FC-PH
specification. The LOS manages receiver word syn­chronization with the RxComDet (comma detect) sig­nal.

The QL80FC is a versatile part that allows the system
designer to create proprietary or Fibre Channel com­pliant serial links by taking advantage of some, or all,
of the Fiber Channel compliant features. It has a
number of useful features for system designers of
proprietary links. One such feature is the ability to
send intraframe IDLEs. These characters are auto­matically sent if the FIFO is empty, but they do not
affect the CRC. In this mode the QL80FC allows
simple interfacing to systems where the flow of data
may be interrupted.

Embedded Design Functional Description

The embedded FC-1 and FC-2 layers are divided into
two functional groupings: the Transmit data path and
the Receive data path. A functional diagram for the
Transmit path is included in Figure 2.

FIGURE 2. Customizable ENDEC Chip Functional Block Diagram - Transmit and LCSM Data Paths

E

MBEDDED DESIGN

F

UNCTIONAL DESCRIPTION

CRC Generation

8b/10b Encoder

User Program mable

Logic

TxData[31:0]

Embedded Fibre Channel ENDEC

Registers

TxCrcEn

Registers

TxRawEn

TxOut[19:0]

TxClk125_inTxClk125_out

TxClk63

/2

TxRst

To receive data path

TxKChar

Async_rst

TenbMode

Registers

TxRData[39:32]

Async_rst

TenbMode

TxIF IdleEn

(only [9:0] used

in 10b mode)

TxClk63 Sync

Reset Circuit

Clk_rst

Clk_rst

To receive data path

4Preliminary

4

QL80FC - QuickFC

TM

Transmit Data Path

When the transmit data path is in standard operation
(TxRawEn not asserted) the chip will latch an un­encoded, Fibre Channel, 32-bit word on inputs
TxData[31:0]. This data then passes on to the 8b/
10b encoder, which creates a 40-bit encoded Fibre
Channel word. The encoder will encode the most sig­nificant character as a command character if the
TxKChar input line is asserted. This word is regis­tered and passed to the SERDES in 20-bit chunks (10
bit chunks if 10 bit mode is enabled) on the TxOut
signal lines.

Asserting the TxCrcEn signal enables the CRC Gen­eration block. This block will automatically detect the
SOF ordered set and begin CRC generation using the
ANSI specified CRC polynomial. It will continue until
an EOF or any other FC ordered set is encountered
(unless TxIFIdleEn is asserted, then the IDLE ordered
set will be ignored by the CRC generator). It then
inserts the CRC value into the data path for transmis­sion to the SERDES.

The TxRawEn signal enables the raw transmit data
path when asserted. In this mode, the 8 bits of TxR­Data is concatenated onto the 32 bits of the TxData
signal to create a 40-bit wide data path. The CRC
generation and 8b/10b encoder blocks are bypassed
and the “raw” data latched at the inputs is passed
directly to the output registers that drive the SER­DES. This mode is useful for testing the error han­dling capabilities of the serial link by providing the
systems designer a way to intentionally introduce
errors into the serial bit stream.

The TxIFIdleEn (Intra-Frame Idle Enable) input
enables the use of Fibre Channel IDLE words within
a Frame. When this signal is asserted, IDLE words
present within a data frame will not affect the value

generated by the CRC block. This feature is useful in
custom FC designs where it is desired to suspend the
transmission of a frame for a period of time and then
resume later.

The use of external FIFOs is optional. There is
enough RAM on the ENDEC chip to be configured
into two 352 x 36 FIFOs. If FIFOs of this size are all
that is required, external FIFOs would not be needed.
Synchronous read and writes directly from the system
bus without a FIFO is also possible.

Two clock signals are supplied to the customizable
logic on high speed, low skew clock networks:
TxClk125 and TxClk63. TxClk125 is a clock run­ning at a maximum speed of 125 MHz, and repre­sents the “full speed” of the Oscillator being used to
clock the transmit data path. The input that drives
this signal is also used to clock the SERDES chip.
The TxClk63 clock signal operates at half the speed
of the TxClk125 clock. You will most likely want to
use the TxClk63 signal to clock your FIFOs and cus­tomizable logic. Of course, these signals can be
routed off-chip through the customizable I/O.

The Async_rst pin accepts an asynchronous, active
high reset signal. Circuitry takes this signal and syn­chronizes it with the TxClk63 clock. This synchro­nous reset signal, TxRst, is used to set or clear flip­flops in the transmit data path. It is made available to
the user programmable logic for the same purpose
on a high speed, low skew network

The Clk_rst input stops the TxClk63 clock when this
signal is asserted. This signal was added primarily to
facilitate simulation. Clk_rst may be permanently
grounded in hardware.

T

RANSMIT DATA PATH

5

QL80FC - QuickFC

TM

FIGURE 3. .Customizable ENDEC Chip Functional Block Diagram - Receive Data Path

Receive Data Path

Receive Data Path

The receive data path receives encoded data from an
on-board SERDES, decodes it and passes the result­ing data to the customizable section of the chip. A
functional block diagram of the receive data path is
shown in Figure 3.

The RxClk125 signal latches 20 bits (10 bits when
10-bit mode is enabled) of data from the SERDES
into the RxIn input registers on the positive edge of
the clock. The RxClk125 signal is made available to
the customizable section. RxClk125 is divided by two
and made available to the customizable section on
the RxClk63 signal line. Both clocks use a high
speed, low skew clock network. Again you will most
likely want to use the RxClk63 signal to clock all reg­isters and FIFOs in the receive data path. Registers
using RxClk125 and RxClk63 should be sensitive to
the rising edge of these clocks.

Once the data on the RxIn signal lines is latched into
the input registers, the data is passed on to the 8b/
10b decoder. Under standard operation, (input RxRa-

wEn is low), the data is decoded into 4, 8-bit charac­ters and the resulting Fibre Channel word is placed
on the RxData[31:0] output signals. RxRData is not
used under normal operation. If the decoder detects a
Fibre Channel comma character in the most signifi­cant character of the word, the RxKChar signal line
will be asserted.

When the RxCrcEn signal is asserted the CRC check­ing logic will function. The CRC logic will automati­cally detect a SOF word and begin performing CRC
division on the next word in the data stream using the
ANSI specified CRC polynomial for Fibre Channel.
When an EOF word or any other FC ordered set is
detected (unless RxIFIdleEn is asserted, then the IDLE
ordered set will be ignored by the CRC checker) the
CRC will assert the RxCrcRdy signal for one cycle of
the RxClk63 clock. If the remainder for the division is
zero, the RxCrcOK signal line will also be asserted
during this same cycle.

User Programmable

Logic

Embedded Fibre Channel ENDEC

RxClk125_inRxClk125_ out

RxClk63

/2

8b/10b Decoder

Loss Of Sync

State Machine

CRC Checking

Ordered Set
Recogn ition

Registers

RxIn[19:0]

RxComDet

RxLOSync

RxLOSIdx[3:0]

RxData[31:0]

Registers

RxRawEn

RxKChar

RxCrcOK

RxCrcRdy

(SOF, ID LE, EOF . . . )RxSgpBus[14:0]

From transmit data path

Async_rst

RxCrcEn

(only [9:0] used

in 10b mode)

Registers

RxRData[39:32]

TenbMode

RxInvWord

RxIF IdleEn

RxClk63 Sync

Reset Circuit

RxRst

Clk_rst

From transmit

data path

R

ECEIVE DATA PATH

6Preliminary

6

QL80FC - QuickFC

TM

When the RxRawEn signal is asserted the “raw” data
path will be enabled for the receive circuit. With the
“raw” data path enabled, the data received from the
SERDES does not pass through the 8b/10b decoder
or the CRC checking blocks. Instead it is routed
directly to the output registers and is made available
to the customizable section of the chip on signal lines
RxRData and RxData. This mode is useful for testing
the serial link.

The Loss of Synchronization State machine is
responsible for achieving character synchronization
on the data being sent from the SERDES. When the
Rst signal is asserted, the LOSSM goes to the “loss of
synchronization” state. In this state the RxLOSync
signal will be asserted. After the reception of three
valid command characters, the state machine will
proceed to the “synchronization acquired” state and
the RxLOSync signal is de-asserted. After the recep­tion of 4 successive invalid characters the state
machine will return to the “Loss of Synchronization”
state. The value on the RxLOSIdx bus indicates the
state of LOSSM.

The ordered set recognition block detects Fibre
Channel ordered sets and asserts one signal line in

the RxSgpBus bus corresponding to the ordered set
detected. All 15 Fibre Channel ordered set types are
detected including SOF, EOF and IDLE. There is a list
of ordered sets detected by the ordered set recogni­tion circuitry in Table 1.

There are two signals used to indicate that a word
having a decoding error of some kind is present on
the RxData outputs. When RxInvChar is asserted a
word with an invalid 10-bit representation is present
on the RxData signal lines. RxRDErr indicates an
invalid running disparity was detected on the cur­rently available RxData word.

The Async_rst pin accepts an asynchronous, active
high reset signal. Circuitry takes this signal and syn­chronizes it with the RxClk63 clock. This synchro­nous reset signal, RxRst, is used to set or clear flip­flops in the receive data path. It is made available to
the user programmable logic for the same purpose
on a high speed, low skew network.

The Clk_rst input stops the RxClk63 clock when this
signal is asserted. This signal was added primarily to
facilitate simulation. Clk_rst may be permanently
grounded in hardware.

7

QL80FC - QuickFC

TM

Table of Recognized Ordered Sets

TABLE 1. Table of Recognized Ordered Sets

* Only recognized when RxIFIdleEn is asserted

R

ECOGNIZED ORDERED SETS

Beginning

RD

Identifier Ordered Set Code Hex

Equivalent

RxSgpBus Signal

Line Asserted

- SOFc1 K28.5 D21.5 D23.0 D23.0 BC B5 17 17 [0]

- SOFi1 K28.5 D21.5 D23.2 D23.2 BC B5 57 57 [0]

- SOFn1 K28.5 D21.5 D23.1 D23.1 BC B5 37 37 [0]

- SOFi2 K28.5 D21.5 D21.2 D21.1 BC B5 55 55 [0]

- SOFn2 K28.5 D21.5 D21.1 D21.1 BC B5 35 35 [0]

- SOFi3 K28.5 D21.5 D22.2 D22.2 BC B5 56 56 [0]

- SOFn3 K28.5 D21.5 D22.1 D22.1 BC B5 36 36 [0]

- SOFf K28.5 D21.5 D24.2 D24.2 BC B5 58 58 [0]

- EOFt K28.5 D21.4 D21.3 D21.3 BC 95 75 75 [1]

+ EOFt K28.5 D21.5 D21.3 D21.3 BC B5 75 75 [1]

- EOFdt K28.5 D21.4 D21.4 D21.4 BC 95 95 95 [1]

+ EOFdt K28.5 D21.5 D21.4 D21.4 BC B5 95 95 [1]

- EOFa K28.5 D21.4 D21.7 D21.7 BC 95 F5 F5 [1]

+ EOFa K28.5 D21.5 D21.7 D21.7 BC B5 F5 F5 [1]

- EOFn K28.5 D21.4 D21.6 D21.6 BC 95 D5 D5 [1]

+ EOFn K28.5 D21.5 D21.6 D21.6 BC B5 D5 D5 [1]

- EOFdti K28.5 D10.4 D21.4 D21.4 BC 8A 95 95 [1]

+ EOFdti K28.5 D10.5 D21.4 D21.4 BC AA 95 95 [1]

- EOFni K28.5 D10.4 D21.6 D21.6 BC 8A D5 D5 [1]

+ EOFni K28.5 D10.5 D21.6 D21.6 BC AA D5 D5 [1]

- IDLE K28.5 D21.4 D21.5 D21.5 BC 95 B5 B5 [2]

+ IDLE* K28.5 D21.5 D21.5 D21.5 BC B5 B5 B5 [2]

- R_RDY K28.5 D21.4 D10.2 D10.2 BC 95 4A 4A [3]

- OLS K28.5 K21.1 D10.4 D21.2 BC 35 8A 55 [4]

- NOS K28.5 D21.2 D31.5 D5.2 BC 55 BF 45 [5]

- LR K28.5 D9.2 D31.5 D9.2 BC 49 BF 49 [6]

- LRR K28.5 D21.1 D31.5 D9.2 BC 35 BF 49 [7]

- ARBx K28.5 D20.4 AL_PA AL_PA BC 4A xx xx [8]

- ARB(F0) K28.4 D20.4 D16.7 D16.7 BC 4A F0 F0 [8]

- OPNyx K28.5 D17.4 AL_PD AL_PS BC 91 yy xx [9]

- OPNyy K28.5 D17.4 AL_PD AL_PD BC 91 yy yy [9]

- OPNfr K28.5 D17.4 D31.7 D31.7 BC 91 FF FF [9]

- OPNyr K28.5 D17.4 AL_PD D31.7 BC 91 yy FF [9]

- CLS K28.5 D5.4 D21.5 D21.5 BC 85 B5 B5 [10]

- MRKtx K28.5 D31.2 MK_TP AL_PS BC 5F tt xx [11]

- LIP(F7,F7) K28.5 D21.0 D23.7 D23.7 BC 15 F7 F7 [12]

- LIP(F8,F7) K28.5 D21.0 D24.7 D23.7 BC 15 F8 F7 [12]

- LIP(F7,x) K28.5 D21.0 D23.7 AL_PS BC 15 F7 xx [12]

- LIP(F8,x) K28.5 D21.0 D24.7 AL_PS BC 15 F8 xx [12]

- LIP(y,x) K28.5 D21.0 AL_PD AL_PS BC 15 yy xx [12]

- LPEyx K28.5 D5.0 AL_PD AL_PS BC 05 yy xx [13]

- LPEfx K28.5 D5.0 D31.7 AL_PS BC 05 FF xx [13]

- LPByx K28.5 D9.0 AL_PD AL_PS BC 09 yy xx [14]