QuickLogic QL7180 DSP DATA SHEET

QL7180 DSP Data Sheet

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Combining Embedded DSP Blocks, Performance, Density

and Embedded RAM

1.0 Device Highlights

Clock Network

• 9 global clock networks

• 1 dedicated, 8 programmable

• 16 I/O (high drive) networks:

2 banks per I/O

• 20 Quad-net networks: 5 per quadrant

Programmable I/O

• High performance enhanced I/O:

less than 3 ns Tco

• Programmable slew rate control

• Programmable I/O standards

• LVTTL, LVCMOS, PCI, GTL+, SSTL2,

and SSTL3

• 8 independent I/O banks

• 3 register configuration: Input, Output, OE

Parameterized IP

• Free parameterized IP administered with a

DSP Wizard

• Supports multiple and hierarchical IP

instantiations

High Speed Customizable Logic

• 0.25u, 5 layer metal CMOS process

• 2.5 V Vcc, 2.5 / 3.3 V drive capable I/O

• 512 programmable I/O

• 4,032 Logic Cells

• 660,000 max system gates

• Muxed based architecture,

non-volatile technology

• Completely customizable for any

digital applications

Dual Port SRAM

• 36 blocks of dual-port SRAM

• 2,304 bit dual port high performance

SRAM Blocks

• Total of 82,900 bits

• RAM / ROM / FIFO Wizard for automatic

configuration

• Configurable and cascadable

• Array sizes of 2, 4, 9, and 18

• < 3 ns access times, 300+ MHz FIFO

Applications

• Signal processing operators

• Signal processing functions

• Networking / communications for VoIP

• Speech / voice processing

• Channel coding

QL7180 QuickDSPTM Data Sheet Rev B

Figure 1: Embedded QuickDSP Block Diagram

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QL7180 DSP Data Sheet

2.0 AC Characteristics at Vcc = 2.5V, TA=25° C (K=1.00)

The AC Specifications, Logic Cell diagrams and waveforms are provided below.

Figure 2: QuickDSP Logic Cell

Table 1: Logic Cells

Symbol Parameter

Logic Cells 1

tPD Combinatorial delay: time taken by the combinatorial circuit to output 0.257

tSU

tCLK

tCWHI Clock High Time: the length of time that the clock stays high 0.46

tCWLO Clock Low Time: the length of time that the clock stays low 0.46

tSET

tRESET

tSW

tRW

Setup time: the amount of time the synchronous input of the flip flop must be stable before the active clock edge

Hold time: the amount of time the synchronous input of the flip flop must be stable after the

thl

active block edge Clock to out delay: the amount of time the synchronous input of the flip flop must be stable

after the active block edge

Set Delay: amount of time between when the flip flop is ”set” (high) and when Q is consequent “set” (high)

Reset Delay: amount of time between when the flip flop is ”reset” (low) and when Q is consequent “reset” (low)

Set Width: length of time that the SET signal remains high (low if active low)

Reset Width: length of time that the RESET signal remains high (low if active low)

Propagation

delay (ns)

0.22

0.255

0.18

0.09

0.3

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Figure 3: Logic Cell Flip Flop

QL7180 DSP Data Sheet

Figure 4: Logic Cell Flip Flop Timings - First Waveform

Figure 5: Logic Cell Flip Flop Timings - Second Waveform

QL7180 QuickDSPTM Data Sheet Rev B

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QL7180 DSP Data Sheet

Figure 6: QuickDSP Global Clock Structure

Table 2: QuickDSP Clock Performance

Macro

I/O

Skew

Symbol Parameter Propagation delay (ns)

Input Register Cell Only

tGCKP Global clock pin delay

GCKB Global clock buffer delay

Clock Performance

Global Dedicated

1.51 ns 1.59 ns

2.06 ns 1.73 ns

0.55 ns 0.14 ns

Table 3: QuickDSP Input Register Cell

Figure 7: Global Clock Structure Schematic

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Figure 8: QuickRAM Module

Table 4: RAM Cell Synchrono us Write Timing

QL7180 DSP Data Sheet

Symbol Parameter

Propagation

delay (ns)

RAM Cell Synchronous Write Timing 1

TSWA

THWA

TSWD

THWD

TSWE

THWE

TWCRD

WA Setup Time to WCLK: the amount of time the WRITE ADDRESS

must be stable before the active edge of the WRITE CLOCK

WA Hold Time to WCLK: the amount of time the WRITE ADDRESS must

be stable after the active edge of the WRITE CLOCK

WD Setup Time to WCLK: the amount of time the WRITE DA TA must be

stable before the active edge of the WRITE CLOCK

WD Hold Time to WCLK: the amount of time the WRITE DATA must be

stable after the active edge of the WRITE CLOCK

WE Setup Time to WCLK: the amount of time the WRITE ENABLE must

be stable before the active edge of the WRITE CLOCK

WE Hold Time to WCLK: the amount of time the WRITE ENABLE must

be stable after the active edge of the WRITE CLOCK

WCLK to RD (WA=RA) [5]: the amount of time between the active

WRITE CLOCK edge and the time when the data is available at RD

0.675

0.654

0.623

4.38

QL7180 QuickDSPTM Data Sheet Rev B

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QL7180 DSP Data Sheet

Figure 9: RAM Cell Synchronous Write Timing

Table 5: RAM Cell Synchronous & Asynchronous Read Timing

Symbol Parameter

Propagation

delay (ns)

RAM Cell Synchronous Read Timing 1

TSRA

THRA

TSRE

THRE

TRCRD

RA Setup Time to RCLK: the amount of time the READ ADDRESS must

be stable before the active edge of the READ CLOCK

RA Hold Time to RCLK: the amount of time the READ ADDRESS must

be stable after the active edge of the READ CLOCK

RE Setup Time to RCLK: the amount of time the READ ENABLE must

be stable before the active edge of the READ CLOCK

RE Hold Time to RCLK: the amount of time the READ ENABLE must be

stable after the active edge of the READ CLOCK

RCLK to RD [5]: the amount of time between the active READ CLOCK

edge and the time when the data is available at RD

0.686

0.243

4.38

RAM Cell Synchronous Read Timing

RPDRD

RA to RD [5]: amount of time between when the READ ADDRESS is

input and when the DATA is output

2.06

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QL7180 DSP Data Sheet

Figure 10: RAM Cell Synchronous & Asynchronous Read Timing

QL7180 QuickDSPTM Data Sheet Rev B

Figure 11: QuickDSP Cell I/O

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QL7180 DSP Data Sheet

Figure 12: QuickDSP Input Register Cell

Table 6: Input Register Cell

Symbol Parameter

Input Register Cell Only 1

tISU

tIH

tICLK

tIRST

tIESU

tIEH

Input register setup time: the amount of time the synchronous input of the flip flop must be stable before the active clock edge

Input register hold time: the amount of time the synchronous input of the flip flop must be stable after the active clock edge

Input register clock to Q: the amount of time taken by the flip flop to output after the active clock edge

Input register reset delay: amount of time between when the flip flop is “reset”(low) and when Q is consequently “reset” (low)

Input register clock enable setup time: the amount of time “enable” must be stable before the active clock edge

Input register clock enable time: the amount of time “enable” must be stable after the active clock edge

Propagation

delay (ns)

3.12

1.08

0.99

0.37

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