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© 2002 QuickLogic Corporation
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QL6325-E Eclipse-E Data Sheet Rev A
Preliminary
26
Table 22: Dedicated Pin Descriptions
Pin Function Description
GCLK Global clock network driver
Low skew global clock. This pin provides access to a dedicated,
distributed network capable of driving the CLOCK, SET, RESET,
F1, and A2 inputs to the Logic Cell, READ, and WRITE CLOCKS,
Read and Write Enables of the Embedded RAM Blocks, CLOCK
of the ECUs, and Output Enables of the I/Os.
I/O(A) Input/Output pin
The I/O pin is a bi-directional pin, configurable to either an inputonly, output-only, or bi-directional pin. The A inside the
parenthesis means that the I/O is located in Bank A. If an I/O is
not used, SpDE (QuickWorks Tool) provides the option of tying
that pin to GND, V
CC,
or TriState during programming.
V
CC
Power supply pin Connect to 2.5 V supply
V
CCIO
(A) Input voltage tolerance pin
This pin provides the flexibility to interface the device with either a
3.3 V , 2.5 V , or 1.8 V device. The A inside the parenthesis means
that V
CCIO
is located in BANK A. Every I/O pin in Bank A will be
tolerant of V
CCIO
input signals and will output V
CCIO
level signals.
This pin must be connected to either 3.3 V, 2.5 V, or 1.8 V.
GND Ground pin Connect to ground
PLLIN PLL clock input Clock input for PLL
DEDCLK Dedicated clock pin
Low skew global clock. This pin provides access to a dedicated,
distributed clock network capable of driving the CLOCK inputs of
all sequential elements of the device (e.g. RAM, Flip Flops).
GNDPLL Ground pin for PLL Connect to GND
INREF(A) Differential reference voltage
The INREF is the reference voltage pin for GTL+, SSTL2, and
STTL3 standards. Follow the recommendations provided in
Table 19
for the appropriate standard. The A inside the
parenthesis means that INREF is located in BANK A. This pin
should be tied to GND if not needed.
PLLOUT PLL output pin Dedicated PLL output pin; otherwise, may be left unconnected
IOCTRL(A) Highdrive input
This pin provides fast RESET , SET, CLOCK, and ENABLE access
to the I/O cell flip-flops, providing fast clock-to-out and fast I/O
response times. This pin can also double as a high-drive pin to the
internal logic cells. The A inside the parenthesis means that
IOCTRL is located in Bank A. There is an internal pulldown
resistor to Ground on this pin. This pin should be tied to Ground if
it is not used. For backwards compatibility with Eclipse, it can be
tied to Vcc or Ground. If tied to Vcc, it will draw no more than
20 µA per IOCTRL pin due to the pulldown resistor.
(Sheet 1 of 2)