QUICK LOGIC QL6325-5PT280M, QL6325-6PS484C, QL6325-6PS484I, QL6325-6PS484M, QL6325-6PS516C Datasheet

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Device Highlights

Flexible Programmable Logic

• .25

µ

m, Five layer metal CMOS Process

• 2.5 V V

CC

, 2.5 V/3.3 V Drive Capable I/O

• 1,536 Logic Cells

• 320,640 Max System Gates

• Up to 313 I/O Pins

Embedded Dual Port SRAM

• Twenty four 2,304-bit Dual Port High

Performance SRAM Blocks

• 55,300 RAM Bits

• RAM/ROM/FIFO Wizard for Automatic

Configuration

• Configurable and Cascadable

Programmable I/O

• High performance Enhanced I/O (EIO):

Less than 3 ns Tco

• Programmable Slew Rate Control

• Programmable I/O Standards:

• LVTTL, LVCMOS, PCI, GTL+, SSTL2,

and SSTL3

• Eight Independent I/O Banks

• Three Register Configurations: Input,

Output, and Output Enable

Advanced Clock Network

• Nine Global Clock Networks:

• One Dedicated

• Eight Programmable

• 20 Quad-Net Networks: Five per Quadrant

• 16 I/O Controls: Two per I/O Bank

Figure 1: Eclipse Block Diagram

Memory - Dual Port RAM

High Speed Logic Cells

321K Gates

Memory - Dual Port RAM

Combining Performance, Density, and Embedded RAM

QL6325 Eclipse Data Sheet

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QL6325 Eclipse Data Sheet Rev C

Electrical Specifications

AC Characteristic s a t VCC = 2.5 V, TA = 25° C (K = 0.74)

The AC Specifications are provided from Table 1 to Table 10. Logic Cell diagrams and waveforms are provided from

Figure 2 to Figure 15.

Figure 2: Eclipse Logic Cell

Table 1: Logic Cells

Symbol Parameter Value (ns)

Logic Cells Min Max

t

PD

Combinatorial Delay of the longest path: time taken by the combinatorial circuit to output

- 0.257

t

SU

Setup time: time the synchronous input of the flip flop must be stable before the active clock edge

0.22 -

t

HL

Hold time: time the synchronous input of the flip flop must be stable after the active clock edge

0 -

t

CO

Clock-to-out delay: the amount of time taken by the flip flop to output after the active clock edge.

- 0.255

t

CWHI

Clock High Time: required minimum time the clock stays high 0.46 -

t

CWLO

Clock Low Time: required minimum time that the clock stays low 0.46 -

t

SET

Set Delay: time between when the flip flop is ”set” (high) and when the output is consequently “set” (high)

- 0.18

t

RESET

Reset Delay: time between when the flip flop is ”reset” (low) and when the output is consequently “reset” (low)

- 0.09

t

SW

Set Width: time that the SET signal remains high/low 0.3 -

t

RW

Reset Width: time that the RESET signal remains high/low 0.3 -

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QL6325 Eclipse Data Sheet Rev C

Figure 3: Logic Cell Flip Flop

Figure 4: Logic Cell Flip Flop Timings - First Waveform

Figure 5: Logic Cell Flip Flop Timings - Second Waveform

SET

D

CLK

RESET

Q

SET

RESET

Q

CLK

t

CWHI

(min)

t

CWLO

(min)

t

RESET

t

RW

t

SET

t

SW

CLK

D

Q

t

SU

t

HL

t

CO

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QL6325 Eclipse Data Sheet Rev C

Figure 6: Eclipse Global Clock Structure

Figure 7: Global Clock Structure Schematic

Table 2: Eclipse Clock Performance

Clock Parameters Clock Performance

Global Dedicated

Logic Cells (Internal) Clock signal generated internally 1.51 ns (max) 1.59 ns (max)

I/O’s (External) Clock signal generated externally 2.06 ns (max) 1.73 ns (max)

Table 3: Eclipse Global Clock Performance

Clock Segment Parameter Value (ns)

Min Max

t

PGCK

Global clock pin delay to quad net - 1.34

t

BGCK

Global clock buffer delay (quad net to flip flop)

- 0.56

Quad net

Programmable Clock

External Clock

Global Clock Buffer

Global Clock

t

PGCK

t

BGCK

Clock Select

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QL6325 Eclipse Data Sheet Rev C

Figure 8: RAM Module

Table 4: RAM Cell Synchronous Write Timing

Symbol Parameter Value (ns)

RAM Cell Synchronous Write Timing Min Max

t

SWA

WA setup time to WCLK: time the WRITE ADDRESS must be stable before the active edge of the WRITE CLOCK

0.675 -

t

HWA

WA hold time to WCLK: time the WRITE ADDRESS must be stable after the active edge of the WRITE CLOCK

0 -

t

SWD

WD setup time to WCLK: time the WRITE DATA must be stable before the active edge of the WRITE CLOCK

0.654 -

t

HWD

WD hold time to WCLK: time the WRITE DATA must be stable after the active edge of the WRITE CLOCK

0 -

t

SWE

WE setup time to WCLK: time the WRITE ENABLE must be stable before the active edge of the WRITE CLOCK

0.623 -

t

HWE

WE hold time to WCLK: time the WRITE ENABLE must be stable after the active edge of the WRITE CLOCK

0 -

t

WCRD

WCLK to RD (WA = RA): time between the active WRITE CLOCK edge and the time when the data is available at RD

- 4.38

WA

WD

WE

WCLK

RE

RCLK

RA

RD

RAM Module

[9:0]

[17:0]

[9:0]

[17:0]

ASYNCRD

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QL6325 Eclipse Data Sheet Rev C

Figure 9: RAM Cell Synchronous Write Timing

Table 5: RAM Cell Synchronous & Asynchronous Read Timing

Symbol Parameter Value (ns)

RAM Cell Synchronous Read Timing Min Max

t

SRA

RA setup time to RCLK: time the READ ADDRESS must be stable before the active edge of the READ CLOCK

0.686 -

t

HRA

RA hold time to RCLK: time the READ ADDRESS must be stable after the active edge of the READ CLOCK

0 -

t

SRE

RE setup time to WCLK: time the READ ENABLE must be stable before the active edge of the READ CLOCK

0.243 -

t

HRE

RE hold time to WCLK: time the READ ENABLE must be stable after the active edge of the READ CLOCK

0 -

t

RCRD

RCLK to RD: time between the active READ CLOCK edge and the time when the data is available at RD

- 4.38

RAM Cell Asynchronous Read Timing

r

PDRD

RA to RD: time between when the READ ADDRESS is input and when the DATA is output

- 2.06

t

SWA

t

SWD

t

SWE

t

HWA

t

HWD

t

HWE

t

old data

new data

WCLK

WA

WD

WE

RD

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QL6325 Eclipse Data Sheet Rev C

Figure 10: RAM Cell Synchronous & Asynchronous Read Timing

Figure 11: Eclipse Cell I/O

t

SRA

t

HRA

RCLK

RA

t

SRE

t

HRE

t

RCRD

old data

new data

RE

RD

r

PDRD

E

R

Q

D

R

Q

E

R

Q

D

+

-

PAD

OUTPUT ENABL E

REGISTER

OUTPUT

REGISTER

INPUT

REGISTER

D

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QL6325 Eclipse Data Sheet Rev C

Figure 12: Eclipse Input Register Cell

Table 6: Input Register Cell

Symbol Parameter Value (ns)

Input Register Cell Only Min Max

t

ISU

Input register setup time: time the synchronous input of the flip-flop must be stable before the active clock edge

3.12 -

t

IHL

Input register hold time: time the synchronous input of the flip-flop must be stable after the active clock edge

0 -

t

ICO

Input register clock to out: time taken by the flip-flop to output after the active clock edge

- 1.08

t

IRST

Input register reset delay: time between when the flip-flop is “reset”(low) and when the output is consequently “reset” (low)

- 0.99

t

IESU

Input register clock enable setup time: time “enable” must be stable before the active clock edge

0.37 -

t

IEH

Input register clock enable hold time: time “enable” must be stable after the active clock edge

0 -

PAD

t

IN

, t

INI

t

ICLK

t

ISU

t

SID

+

-

Q

E

D

R

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QL6325 Eclipse Data Sheet Rev C

Figure 13: Eclipse Input Register Cell Timing

Table 7: Standard Input Delays

Symbol Parameter Value (ns)

Standard Input Delays To get the total input delay add this delay to tISU Min Max

t

SID

(LVTTL) LVTTL input delay: Low Voltage TTL for 3.3 V applications - 0.34

t

SID

(LVCMOS2)

LVCMOS2 input delay: Low Voltage CMOS for 2.5 V and lower applications

- 0.42

t

SID

(GTL+) GTL+ input delay: Gunning Transceiver Logic - 0.68

t

SID

(SSTL3) SSTL3 input delay: Stub Series Terminated Logic for 3.3 V - 0.55

t

SID

(SSTL2) SSTL2 input delay: Stub Series Terminated Logic for 2.5 V - 0.61

R

CLK

D

Q

t

ISU

t

IHL

t

ICO

t

IESU

t

IEH

t

IRST

E

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QL6325 Eclipse Data Sheet Rev C

Figure 14: Eclipse Output Register Cell

Table 8: Eclipse Output Register Cell

Symbol Parameter Value (ns)

Output Register Cell Only Min Max

t

OUTLH

Output Delay low to high (90% of H) - 0.40

t

OUTHL

Output Delay high to low (10% of L) - 0.55

t

PZH

Output Delay tri-state to high (90% of H) - 2.94

t

PZL

Output Delay tri-state to low (10% of L) - 2.34

t

PHZ

Output Delay high to tri-State - 3.07

t

PLZ

Output Delay low to tri-State - 2.53

t

COP

Clock to out delay (does not include clock tree delays) -

3.15 (fast slew)

10.2 (slow slew)

PAD

OUTPUT

REGISTER

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QL6325 Eclipse Data Sheet Rev C

Figure 15: Eclipse Output Register Cell Timing

Table 9: Output Slew Rates @ V

CCIO

= 3.3 V

Fast Slew Slow Slew

Rising Edge 2.8 V/ns 1.0 V/ns

Falling Edge 2.86 V/ns 1.0 V/ns

Table 10: Output Slew Rates @ V

CCIO

= 2.5 V

Fast Slew Slow Slew

Rising Edge 1.7 V/ns 0.6 V/ns

Falling Edge 1.9 V/ns 0.6 V/ns

L

H

L

H

t

OUTLH

t

OUTHL

L

H Z

t

PZH

L

H

Z

t

PZL

L

H

Z

t

PLZ

L

H

Z

t

PHZ

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QL6325 Eclipse Data Sheet Rev C

DC Characteristics

The DC Specifications are provided in Table 11 through Table 13.

Table 11: Absolute Maximum Ratings

Parameter Value Parameter Value

VCC Vol tage

-0.5 V to 3.6 V

DC Input Current

±20 mA

V

CCIO

Voltage

-0.5 V to 4.6 V

ESD Pad Protection

±2000 V

INREF Voltag e

2.7 V

Leaded Package

Storage Temperature

-65° C to + 150° C

Input Voltage

-0.5 V to V

CCIO

+0.5 V

Laminate Package (BGA)

Storage Temperature

-55° C to + 125° C

Latch-up Immunity

±100 mA

Table 12: Operating Range

Symbol Parameter Military Industrial Commercial Unit

Min Max Min Max Min Max

V

CC

Supply Voltage 2.3 2.7 2.3 2.7 2.3 2.7 V

V

CCIO

I/O Input Tolerance Voltage 2.3 3.6 2.3 3.6 2.3 3.6 V

TA Ambient Temperature -55 -40 85 0 70 °C

TC Case Temperature - 125 - - - - °C

K Delay Factor

-4 Speed Grade 0.42 2.3 0.43 2.16 0.47 2.11 n/a

-5 Speed Grade 0.42 1.92 0.43 1.80 0.46 1.76 n/a

-6 Speed Grade 0.42 1.35 0.43 1.26 0.46 1.23 n/a

-7 Speed Grade 0.42 1.27 0.43 1.19 0.46 1.16 n/a

Table 13: DC Characteristics

Symbol Parameter Conditions Min Max Units

I

I or I/O Input Leakage Current VI = V

CCIO

or GND -10 10 µA

I

OZ

3-State Output Leakage Current VI = V

CCIO

or GND -10 10 µA

C

I

Input Capacitance

a

a. Capacitance is sample tested only. Clock pins are 12 pF maximum.

--8pF

I

OS

Output Short Circuit Current

b

b. Only one output at a time. Duration should not exceed 30 seconds.

Vo = GND

V

o

= V

CC

-15 40

-180 210

mA mA

I

CC

D.C. Supply Current

c

c. For -4/-5/-6/-7 commercial grade devices only. Maximum ICC is 3 mA for -0 commercial

grade and all industrial grade devices, and 5 mA for all military grade devices.

V

I,Vo

= V

CCIO

or GND 0.50 (typ) 2 mA

I

CCIO

D.C. Supply Current on V

CCIO

- 0 2 mA

I

CCIO

(DIF)

D.C. Supply Current on V

CCIO

for Differential I/O

---mA

I

REF

D.C. Supply Current on INREF - -10 10 µA

I

PD

Pad Pull-down (programmable) V

CCIO

= 3.6 V - 150 µA