QUICK LOGIC QL5032-33APB256C, QL5032-33APB256I, QL5032-33APQ208I Datasheet

33 MHz/32-bit PCI Master/Target with Embedded Programmable Logic and dual Port SRAM

QL5032 - QuickPCI

last updated 12/2/99

Rev B

Device Highlights

High Performance PCI Controller

■ 32-bit / 33 MHz PCI Master/Target

■ Zero-wait state PCI Master provides 132 MB/s transfer rates

■ Programmable back-end interface to optional local processor

■ Independent PCI bus (33 MHz) and local bus

(up to 160 MHz) clocks

■ Fully customizable PCI Configuration Space

■ Configurable FIFOs with depths up to 256

■ Reference design with driver code (Win 95/98/Win 2000/

NT4.0) available

■ PCI v2.2 compliant

■ Supports Type 0 Configuration Cycles in Target mode

■ 3.3V, 5V Tolerant PCI signaling supports Universal

PCI Adapter designs

■ 3.3V CMOS in 208-pin PQFP and 256-pin PBGA

■ Supports endian conversions

■ Unlimited/Continuous Burst Transfers Supported

Extendable PCI Functionality

■ Support for Configuration Space from 0x40 to 0x3FF

■ Multi-Function, Expanded Capabilities, & Expansion ROM capa-

ble

■ Power management, Compact PCI, hot-swap/hot-plug

compatible

■ PCI v2.2 Power Management Spec compatible

■ PCI v2.2 Vital Product Data (VPD) configuration support

■ Programmable Interrupt Generator

■ I

O support with local processor

■ Mailbox register support

Programmable Logic

■ 37K system gates / 390 Logic Cells

■ 16,128 RAM bits, up to 154 I/O pins

■ 250 MHz 16-bit counters, 275 MHz Datapaths, 160 MHz FIFOs

■ All back-end interface and glue-logic can be implemented on chip

■ 7 64-deep FIFOs or 3 128-deep FIFOs or a single 256-deep

FIFO or a combination that requires 14 or less QuickLogic RAM Modules

■ (3) 32-bit busses interface between the PCI Controller and the

Programmable Logic

FIGURE 1. QL5032 Diagram

Architecture Overview

The QL5032 device in the QuickLogic QuickPCI ESP (Embedded Standard Product) family provides a complete and customizable PCI interface solution combined with 37,000 system gates of programmable logic. This device eliminates any need for the designer to worry about PCI bus compliance, yet allows for the maximum 32-bit PCI bus bandwidth (132 MB/s).

The programmable logic portion of the device contains 390 QuickLogic Logic Cells, and 14 QuickLogic Dual-Port RAM Blocks. These configurable RAM blocks can be configured in many width/depth combinations. They can also be combined with logic cells to form FIFOs, or be initialized via Serial EEPROM on power-up and used as ROMs.

The QL5032 device meets PCI 2.2 electrical and timing specifications and has been fully hardwaretested. This device also supports the Win’98 and PC’98 standards. The QL5032 device features 3.3volt operation with multi-volt compatible I/Os. Thus it can easily operate in 3-volt systems and is fully compatible with 3.3V,5V or Universal PCI card development.

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EVICE HIGHLIGHTS

RCHITECTURE OVERVIEW

2 Preliminary

QL5032 - QuickPCI

PCI Controller

The PCI Controller is a 32-bit/33 MHz PCI 2.2 Compliant Master/Target Controller. It is capable of infinite length Master Write and Read transactions at zero wait state (132 MBytes/second). The Master will never insert wait states during transfers, so data should be supplied or received by FIFOs, which can be configured in the programmable region of the device. The Master Controller will most often be operated by a DMA Controller in the programmable region of the device. A DMA Controller reference design is available. The Target interface offers full PCI Configuration Space and flexible target addressing. Any number of 32-bit BARs may be configured, as either memory or I/O space. All required and options PCI 2.2 Configuration Space registers can be implemented within the programmable region of the device. A reference design of a Target Configuration and Addressing module is provided.

The interface ports are divided into a set of ports for master transactions and a set for target transactions. The Master DMA controller and Target Configuration Space and Address Decoding are done in the programmable logic region of the device. Since these functions are not timing critical, leaving these elements in the programmable region allows the greatest degree of flexibility to the designer. Reference DMA controller, Configuration Space, and Address Decoding blocks are included so that the design cycle can be minimized.

Configuration Space and Address

Decode

The configuration space is completely customizable in the programmable region of the device. PCI address and command decoding is performed by logic in the programmable section of the device. This allows support for any size of memory or I/O space for back-end logic. It also allows the user to implement any subset of the PCI commands supported by the QL5032. QuickLogic provides a reference Address Register/Counter and Command Decode block.

DMA Master/Target Control

The customizable DMA controller included with the QuickWorks design software contains the following features:

■ Configurable DMA count size for reads and writes

(up to 30-bits)

■ Configurable DMA burst size for PCI (including

unlimited/continuous burst)

■ Programmable Arbitration between DMA Read &

Write transactions

■ DMA Registers may be mapped to any area of

Target Memory Space

- Read Address (32-bit register)

- Write Address (32-bit register)

- Read Length (16-bit register) / Write Length (16-bit register)

- Control and Status (32-bit register, includes 8 bit Burst Length)

■ DMA Registers are available to the local design or

the PCI bus

■ Programmable Interrupt Control to signal end of

transfer or other event

Configurable FIFOs

FIFOs may be created with the Ram/FIFO wizard in the QuickWorks tools. The figure below shows the graphical interface used to create these FIFOs. FIFOs may be designed up to 256 deep. With 14 RAM cells available in the QL5032, that allows for up to 7 FIFOs at 64 deep (36 wide), 3 FIFOs at 128 deep (36 wide), or 1 FIFO at 256 deep (36 wide).

FIGURE 2. Graphical Interface to create FIFO

PCI C

ONTROLLER

DMA MASTER/TARGET CONTROL

ONFIGURATION SPACE

AND

DDRESS DECODE

ONFIGURABLE

FIFO

QL5032 - QuickPCI

PCI Interface Symbol

The figure below shows the interface symbol you would use in your schematic design in order to attach the local interface programmable logic design to the PCI core. If you were designing with a top-level Verilog or VHDL file, then you would use a structural instantiation of this PCI32 block, instead of a graphical symbol.

FIGURE 3. PCI Interface Symbol

Master

Target

PCI Pads

PCI Signals

PCI32

Cfg_CmdReg6 Cfg_CmdReg8

Cfg_LatCnt[7:0]

Cfg_RdData[31:0]

CLK

GNTN

IDSEL

Mst_Burst_Req Mst_LatCntEn

Mst_One_Read

Mst_RdAd[31:0] Mst_RdCmd[1:0]

Mst_RdMode

Mst_Two_Reads

Mst_WrAd[31:0]

Mst_WrData[31:0] Mst_WrData_Valid

Mst_WrMode

RSTN

Usr_Interrupt Usr_MstRdAd_Sel

Usr_MstWrAd_Sel

Usr_RdData[31:0]

Usr_RdDecode

Usr_Rdy

Usr_Select Usr_Stop

Usr_WrDecode

AD[31:0]

CBEN[3:0]

DEVSELN

FRAMEN

IRDYN

PAR

PERRN

STOPN

TRDYN

Cfg_MstPERR_Det

Cfg_PERR_Det

Cfg_SERR_Sig

Cfg_Write

INTAN

Mst_IRDYN

Mst_Last_Cycle

Mst_RdBurst_Done

Mst_RdData[31:0]

Mst_RdData_Valid

Mst_REQN

Mst_Tabort_Det

Mst_TTO_Det

Mst_WrBurst_Done

Mst_WrData_Rdy

Mst_Xfer_D1

PCI_clock

PCI_DEVSELN_D1

PCI_FRAMEN_D1

PCI_IDSEL_D1

PCI_IRDYN_D1

PCI_reset

PCI_STOPN_D1

PCI_TRDYN_D1

REQN

SERRN

Usr_Addr_WrData[31:0]

Usr_Adr_Inc

Usr_Adr_Valid

Usr_CBE[3:0]

Usr_Devsel

Usr_Last_Cycle_D1

Usr_STOPN

Usr_TRDYN

Usr_Write

Usr_WrReq

PCI Interface Symbol

4 Preliminary

QL5032 - QuickPCI

PCI Master Interface

The internal signals used to interface with the PCI controller in the QL5032 are listed below, along with a description of each signal. The direction of the signal indicates if it is an input provided by the local interface (i) or

an output provided by the PCI controller (o). Signals that end with the character ‘N’ should be considered activelow (for example, Mst_IRDYN

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Mst_WrAd[31:0] I Address for master DMA writes. This address must be treated as valid from the

beginning of a DMA burst write until the DMA write operation is complete. It must be incremented (by 4) each time data is transferred on the PCI bus, since only DWORD (4 byte) transfers are supported.

Mst_RdAd[31:0] I Address for master DMA reads. This address must be treated as valid from the

beginning of a DMA burst read until the DMA read operation is complete. It must be incremented (by 4) each time data is transferred on the PCI bus, since only DWORD (4 byte) transfers are supported.

Mst_WrMode I DMA state machine in “write” mode. This must be asserted at the b eginning of a

Master Transfer, and must be held until th e Master Transfer completed (Mst_WrBurst_Done).

Mst_RdMode I DMA state machine in “read” mode. This must be asserted at the beginning of a

Master Transfer, and must be held until th e Master Transfer completed (Mst_RdBurst_Done).

Mst_Burst_Req I Request use of the PCI bus. This signal should be held from when the DMA

controller is ready to provide the first data, until the transfer is complete (Mst_WrBurst Done or Mst_RdBurst_Done).

Mst_One_Read I This signals to the PCI core that one data transfer remains in the burst. This sign al

must be asserted when only one DWORD remains to be transferred on the PCI bus.

Mst_Two_Reads I Two or less data transfers remain in the burst. This signal must be asserted when two

or less DWORDs remain to be transferred on the PCI bus. Mst_WrData[31:0] I Data for master DMA writes (to PCI bus). Mst_WrData_Valid I Data valid on Mst_WrData[31:0]. Mst_WrData_Rdy O Data receive acknowledge for Mst_WrData[31:0]. This serves as a POP control for a

FIFO which provides data to the PCI core. Mst_WrBurst_Done O Master write pipeline is empty, which indicates that the Write burst transaction is

completed. Mst_RdData[31:0] O Data for master DMA reads (from PCI bus). Mst_RdData_Valid O Data valid on Mst_RdData[31:0]. This serves as a PUSH control for a F I FO that

receives data from the PCI core. Mst_RdBurst_Done O Master read pipeline is empty, which indicates that Read burst transaction is

completed. Mst_RdCmd[1:0] I Type of PCI read command to be used for DMA reads:

00 or 01 = Memory Read

10 = Memory Read Line

11 = Memory Read Multiple Mst_LatCntEn I Enable Latency Counter. Set to 0 to ignore the Latency Timer in the PCI configuration

space (offset 0Ch). For full PCI complian ce, this port should be always set to 1. Mst_Xfer_D1 O Data was transferred on the previous PCI clock. Useful for updating DMA transfer

counts on DMA Read operations. Mst_Last_Cycle O Active during the last data transfer of a PCI master transaction. Mst_REQN O The PCI REQN signal generated by this device as PCI master. Not usually used in the

back-end design. Mst_IRDYN O The PCI IRDYN signal generated by this device as PCI master. Not usually used in

the back-end design. Mst_Tabort_Det O Target abort detected during master transaction. This is normally an error condition to

be handled in the DMA controller. Mst_TTO_Det O Target timeout detected (no response from target). This is normally an error condition

to be handled in the DMA controller.

PCI Master Interface

QL5032 - QuickPCI

PCI Target Interface

Usr_Addr_WrData[31:0] O Target address and data from target writes. During all target

accesses, the address will be presented on Usr_Addr_WrData[31:0] and simultaneously, Usr_Adr_Valid will be active. During target write transactions, this po r t will present write data to the PCI configuration space or user logic.

Usr_CBE[3:0] O PCI command and byte enables. During target accesses, the PCI

command will be presented on Usr_CBE[3:0] and simultaneously, Usr_Adr_Valid will be active. During target read or write transactions, this port will present acti ve-low byte-enables to the PCI configuration space or user logic.

Usr_Adr_Valid O Indicates the beginning of a PCI transaction, and that a target

address is valid on Usr_Addr_WrData[31:0] and the PCI command is valid on Usr_CBE[3:0]. When this signal is active, the target address must be latched and decoded to determine if this

address belongs to the device’s memory space. Also, the PCI command must be decoded to determine the type of PCI transaction. On subsequent clocks of a target access, this signal will be low, indicating that data (not an address) is present on Usr_Addr_WrData[31:0].

Usr_Adr_Inc O Indicates that the target address should be incremented, because

the previous data transfer has completed. During burst target accesses, the target address is only presented to the back-end logic at the beginning of the transaction (when Usr_Adr_Valid is active), and must therefore be latched and incremented (by 4) for subsequent data transfers.

Usr_WrReq O This signal will be active for the duration of a target write

transaction, and may be used by back-end logic to turn on outputenables for transmitting the data off-chip.

Usr_RdDecode I Active when a “user read” command has been decoded from the

Usr_CBE[3:0] bus. This command may be mapped from any of the PCI “read” commands, such as Memory Read, Memory Read Line, Memory Read Multiple, I/O Read, etc.

Usr_WrDecode I Active when a “user write” command has been decoded from the

Usr_CBE[3:0] bus. This command may be mapped from any of the PCI “write” commands, such as Memory Write or I/O Write.

Usr_Select I The address on Usr_Addr_WrData[31:0] has been decoded and

determined to be within the address space of the device. Usr_Addr_WrData[31:0] must be compared to each of the valid Base Address Registers in the PCI configuration space. Also, this signal must be gated by the Memory Access Enable or I/O Access Enable registers in the PCI configuration space (Command Register bits 1 or 0 at offset 04h).

Usr_Write O Write enable for data on Usr_Addr_WrData[31:0] during PCI

writes.

Cfg_Write O Write enable for data on Usr_Addr_WrData[31:0] during PCI

configuration write transactions.

Cfg_RdData[31:0] I Data from the PCI configuration registers, required to be presented

during PCI configuration read s.

Usr_RdData[31:0] I Data from the back-end user logic (and/or DMA configuration

registers), required to be presented during PCI reads.

PCI Target Interface

6 Preliminary

QL5032 - QuickPCI

PCI Target Interface (Continued)

Cfg_RdData[31:0] I Data from the PCI configuration registers, required to be presented during PCI

configuration reads.

Usr_RdData[31:0] I Data from the back-end user logic (and/or DMA configuration registers),

required to be presented during PCI reads. Cfg_CmdReg8 Cfg_CmdReg6

I Bits 6 and 8 from the Command Register in the PCI configuration space (offset

04h). Cfg_LatCnt[7:0] I 8-bit value of the Latency Timer in the PCI configuration space (offset 0Ch). Usr_MstRdAd_Sel I Used when a target read operation should return the value set on the

Mst_RdAd[31:0] pins. This select pin saves on logic which would otherwise

need to be used to multiplex Mst_Rd Ad[31:0] into the Usr_RdData[31:0] bus.

When this signal is asserted, the data on Usr_RdData[31:0] is ignored. Usr_MstWrAd_Sel I Used when a target read operation should return the value set on the

Mst_WrAd[31:0] pins. This select pin saves on logic which would otherwise

need to be used to multiplex Mst_WrAd[31 :0] into the Usr_RdData[31:0] bus.

When this signal is asserted, the data on Usr_RdData[31:0] is ignored. Cfg_PERR_Det O Parity error detected on the PCI bus. When this signal is active, bit 15 of the

Status Register must be set in the PCI configuration space (offset 04h). Cfg_SERR_Sig O System error asserted on the PCI bus. When this signal is active, the Signalled

System Error bit, bit 14 of the Status Register, must be set in t he PCI

configuration space (offset 04h). Cfg_MstPERR_Det O Data parity error detected on the PCI bus by the master. When this signal is

active, bit 8 of the Status Register must be set in the PCI configuration space

(offset 04h). Usr_TRDYN O Copy of the TRDYN signal as driven by the PCI target interface. Usr_STOPN O Copy of the STOPN signal as driven by the PCI target interface. Usr_Devsel O Inverted copy of the DEVSELN signal as driven by the PCI target interface. Usr_Last_Cycle_D1 O Last transfer in a PCI transaction is occurring. Usr_Rdy I Used to delay (add wait states to) a PCI transaction when the back end needs

additional time. Subject to PCI latency restrictions. Usr_Stop I Used to prematurely stop a PCI target access on the next PCI clock. Usr_Interrupt I Used to signal an interrupt on the PCI bus.

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